Read for memory cells with threshold switch selector

Abstract

Techniques for reading a memory cell having a threshold switch selector are disclosed. The sense amplifier may have a set of capacitors that may be used to exchange charge with a sense node connected to a selected word line. A capacitor may be used to draw excess charge from or provide charge to the sense node. The control circuit drives a current to the selected word line to charge the selected word line to turn on the threshold switch selector of the selected memory cell. When or shortly after the threshold switch selector is turned on, the capacitor may be connected to the selected word line. The capacitor may draw over charge away to prevent a snapback current from flowing through the memory cell, thereby preventing misreads. The capacitor may reduce read latency by accelerating the rate of voltage change on the word line.

Description

Background Art

[0001] Memory is widely used in various electronic devices, such as cellular phones, digital cameras, personal digital assistants, medical electronics, mobile computing devices, non-mobile computing devices, and data servers. Memory may include non-volatile memory or volatile memory. Non-volatile memory allows information to be stored and retained even when the non-volatile memory is not connected to a power source (e.g., a battery). Non-volatile memory can be rendered non-volatile for at least a limited time by adding a battery back to the power source external to the memory chip.

[0002] The memory cells may reside in a cross-point memory array. In a memory array having a cross-point type architecture, one set of conductive lines extends across the surface of the substrate, and another set of conductive lines is formed over the previous set of conductive lines, extending in an orthogonal direction relative to the initial layer. The memory cells are located at the cross-point junction of the two sets of conductive lines.

[0003] A programmable resistance memory cell is formed of a material having a programmable resistance. In a binary approach, a programmable resistance memory cell can be programmed to one of two resistance states: a high resistance state (HRS) and a low resistance state (LRS). In some approaches, more than two resistance states can be used. One type of programmable resistance memory cell is a magnetoresistive random access memory (MRAM) cell. An MRAM cell uses magnetization to represent the stored data, as opposed to some other memory technologies that use electron charge (DRAM) or voltage (SRAM) to store data. Data bits are written to an MRAM cell by changing the magnetization direction of a magnetic element ("free layer") within the MRAM cell, and bits are read by measuring the resistance of the MRAM cell, which changes with the magnetization direction.

[0004] In a cross-point memory array, each memory cell may include a threshold switch selector in series with a material having a programmable resistance. The threshold switch selector has a high resistance (in an off or non-conductive state) until it is biased to a voltage higher than its threshold voltage (Vt) or a current higher than its threshold current (It), and until its voltage bias drops below Vhold ("Voffset") or the current drops below the holding current Ihold. After exceeding Vt and when exceeding Vhold across the threshold switch selector, the threshold switch selector has a relatively low resistance (in an on or conductive state). The threshold switch selector remains on until its current drops below the holding current Ihold, or the voltage drops below the holding voltage Vhold. When this occurs, the threshold switch selector returns to the off (higher) resistance state. In order to read the memory cell, the threshold switch selector is activated by turning on before determining the resistance state of the memory cell. An example of a threshold switch selector is a bidirectional threshold switch (OTS). Other examples of threshold switch selectors include, but are not limited to, volatile conductive bridges (VCBs), metal-insulator-metal (MIMs), or other materials that provide a highly non-linear dependence of current on select voltage.

[0005] In a forced current technique for reading programmable resistance memory cells in a cross-point array, current is driven to a memory cell that is address-selected for reading in one direction ("a selected memory cell"). The address-selected conductor in the Y direction is actively driven to an opposite direction power supply; for example, a forced voltage is applied. The current will charge the voltage on the selected memory cell until the threshold switch selector is turned on. Next, the voltage on the selected cell is sensed as the read current is driven through the programmable resistance memory element of the selected memory cell.

[0006] One technique for reading a programmable resistance memory cell may be referred to as a global reference read. A global reference read is sometimes referred to as a midpoint read or a midpoint reference read. A global reference read may use a reference voltage between a lower resistance state (LRS) and a higher resistance state (HRS). Here, LRS and HRS refer to the voltage that appears on the cell in response to a read current. For example, a midpoint reference may be a reference voltage that is in the middle of two voltages corresponding to sensing a cell with LRS or HRS. In a forced current method, the state of the memory cell is determined based on whether the sensed voltage Vsense is above or below a midpoint reference voltage VREF.

[0007] Another technique for reading programmable resistance memory cells is generally referred to as destructive self-referenced reading (SRR). In SRR, a reference is generated based on the sensing cell itself, rather than using a midpoint reference independent of the cell state. In a destructive SRR, it is possible to change (e.g., destroy) the state of the memory cell due to the write operation of the SRR. An SRR technique includes a first read (Read1), a destructive write to a known state (e.g., a high resistance state HRS), and a second read (Read2). The results of the two reads are compared to determine the original state of the cell. A technique for the first read is to apply a read current in the memory cell, thereby generating a voltage having a magnitude representing the resistance of the memory cell on the cell. The voltage is stored and can be adjusted (e.g., raised or lowered by 150mv) to compare with the voltage sample from the second read. The voltage adjustment can be approximately half of the signal difference on the MRAM of each state. For example, if the MRAM low resistance state (LRS) is 25 kiloohms, the high resistance state is 50 kiloohms, and the read current is 15 ua, the difference in state change is 375 mV, so an adjustment of about 180 mV can be made from the Read1 storage voltage of the SRR. The determination of the original state of the memory cell depends on the difference between the first adjusted read voltage and the second read voltage. For example, if the first sampled voltage of Read1 from the SRR is raised and written to the HRS, then if the cell is initially in the HRS, the second sampled voltage from Read2 should be approximately the same as Read1 and therefore lower than the first raised voltage. However, if the cell is initially in the LRS, the second sampled voltage from Read2 should be higher than the raised voltage from Read1 because the higher Read2 voltage is caused by writing the bit from the low resistance LRS to the HRS.

[0008] For both midpoint reads during SRR, signals, voltages and currents are applied to conductive lines such as word lines and / or bit lines. The time for completing the read will depend on the time it takes for the voltage on the word lines and / or bit lines to reach a stable voltage.

[0009] Memory elements, such as but not limited to MRAM and OTS elements, may have their state changed unintentionally due to current flowing through the memory element during a read operation. Turning on a threshold HRS switch selector may result in a snapback current through the memory element, which may potentially change the state of the MRAM memory element before the memory element is sensed. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Like numbered elements refer to common parts in different figures.

[0011] Figure 1 is a block diagram of one embodiment of a non-volatile memory system connected to a host.

[0012] Figure 2 is a block diagram of one embodiment of a memory die.

[0013] Figure 3 is a block diagram of one embodiment of an integrated memory component including a control die and a memory structure die.

[0014] Figure 4A One embodiment of a portion of a memory array forming a cross point architecture is depicted in oblique view.

[0015] Figure 4B and Figure 4C They presented Figure 4A Side and top views of the junction structure in .

[0016] Figure 4D One embodiment of a portion of a two-level memory array forming a cross-point architecture is depicted in oblique view.

[0017] Figure 5 An embodiment of the structure of an MRAM memory cell is shown, where, for example, a selected cell is driven by a current source for reading or writing.

[0018] Fig. 6A and Figure 6B An embodiment for incorporating a threshold switch selector into an MRAM memory array having a cross-point architecture is shown.

[0019] Figure 7 An implementation of a memory array having a cross-point architecture accessed using a forced current method is depicted.

[0020] Figure 8 is a diagram of one embodiment of a system for reading a memory cell having a threshold switch selector.

[0021] Fig. 9 is a flow chart of one embodiment of a process for reading a programmable resistance memory cell in a cross point array.

[0022] Fig.10 The voltages on the bit line and word line during reading of a memory cell with a threshold switch selector are shown.

[0023] Fig.11 is a schematic diagram of one embodiment of a read path connected to a sense amplifier.

[0024] Fig.12 is a schematic diagram of one implementation of a sense amplifier.

[0025] Fig.13is a table indicating the timing of signals in the sense amplifier for an implementation of a global reference read, where capacitor C1 is used as a snapback discharge capacitor.

[0026] Fig.14A and Fig. 14B Further details of timing signals during an implementation of a global reference read are depicted.

[0027] Fig.15 is a table indicating the timing of signals in a sense amplifier for an implementation of an SRR, where capacitor C1 is used as a snapback discharge capacitor.

[0028] Fig.16 is a table indicating the timing of signals in the sense amplifier for an implementation of the SRR where capacitor C4 is used as a write reset charging capacitor.

[0029] Fig.17A and Fig. 17B Further details of the timing signals during implementation of the SRR are depicted.

[0030] Fig.18 is a flow chart of one embodiment of a process for controlling a capacitor during an SRR to accelerate charging of a word line during a destructive write phase.

[0031] Fig.19 is a flow chart of one embodiment of a process for controlling a capacitor during SRR to accelerate the discharge of a word line after a destructive write phase.

[0032] Fig. 20 is a table indicating the timing of signals in the sense amplifier for an implementation of the write-back phase of the SRR.

[0033] Fig.21 is a flow chart of one embodiment of a process for controlling a capacitor to speed up charging of a word line during the write-back phase of an SRR. DETAILED DESCRIPTION

[0034] The present invention discloses a technology for a memory system and method for reading a memory cell having a threshold switch selector. In one embodiment, a capacitor is used to exchange charge with a sensing node connected to a selected conductive line, which is then connected to a selected memory cell. For example, a capacitor can be used to pull excess charge from a sensing node to accelerate the rate at which the voltage drops on a selected word line in order to reduce a read delay. In one embodiment, a capacitor can be used to provide charge to accelerate the rate at which the voltage rises on a selected word line in order to reduce a read delay. In one embodiment, a capacitor absorbs charge that would otherwise flow through a selected memory cell after a snapback of a threshold switch selector, thereby preventing the state of the memory cell from flipping. Therefore, misreading is prevented.

[0035] In some embodiments, the sense amplifier has a group of capacitors that can be used to exchange charge with a sensing node connected to a selected word line. The control circuit drives a current to the selected word line to charge the selected word line to turn on the threshold switch selector of the selected memory cell. In one embodiment, when the threshold switch selector is turned on or shortly thereafter, the capacitor is connected to the selected word line. Turning on the threshold switch selector may potentially cause a snapback current to flow through the memory cell unexpectedly. If a significant snapback current will flow through the memory cell, the state of the memory cell may change, thereby causing a misread. The capacitor can absorb excess charge to thereby prevent such snapback current from flowing through the memory cell, thereby preventing misreading. In addition, the capacitor can reduce the time it takes to stabilize the word line voltage at a stable voltage (Vfinal) for sensing the state of the memory cell. Therefore, the read latency is reduced. In one embodiment, a capacitor is used in a global reference read to exchange charge with a sensing node connected to a selected word line. In one embodiment, a capacitor is used in an SRR to exchange charge with a sensing node connected to a selected word line.

[0036] The set of capacitors may be used at different times in the SRR. The capacitors may be used to speed up the rate at which the voltage on the selected word line increases for a destructive write of the SRR. The capacitors may be used to speed up the rate at which the voltage on the selected word line decreases after a destructive write of the SRR. The capacitors may be used to speed up the rate at which the voltage on the selected word line increases and / or decreases during the write-back phase of the SRR, in which the original state of the memory cell is restored.

[0037] In one embodiment, a memory system is used to read programmable resistance memory cells residing in a cross-point memory array. In a memory array having a cross-point architecture, a set of conductive lines extends across the surface of a substrate, and another set of conductive lines is formed above the previous set of conductive lines, extending above the substrate in a direction perpendicular to the previous set of conductive lines. The memory cell is located at the intersection of the two sets of conductive lines. The cross-point memory array is sometimes referred to as a cross-stripe memory array. In one embodiment, each memory cell has a magnetoresistive memory element connected in series with an OTS, which magnetoresistive memory element may be referred to as an MRAM memory cell. However, the cross-point memory array may have other types of memory cells. For example, the cross-point memory array may have memory cells of other technologies such as ReRam, PCM (phase change memory), and FeRAM. In addition, the threshold switch selector does not have to be an OTS.

[0038] In some embodiments, the programmable resistance memory cell has a magnetoresistive random access memory (MRAM) element. As used herein, the magnetization direction is the direction in which the magnetic moment is oriented relative to a reference direction set by another element of the MRAM (the "reference layer"). In some embodiments, the low resistance is referred to as a parallel or P state or LRS, and the high resistance is referred to as an anti-parallel or AP state or HRS. MRAM can use the spin transfer torque effect to change the magnetization direction from the P state to the AP state and vice versa, which typically requires a bipolar (bidirectional write) operation to write. However, the SRR of the programmable resistance memory cell disclosed herein is not limited to memory cells having MRAM elements or OTS elements.

[0039] Figure 1 is a block diagram of one embodiment of a non-volatile memory system (or more simply referred to as a "memory system") 100 connected to a host system 120. The memory system 100 can implement the techniques presented herein for a system for reading a memory cell having a threshold switch selector. In one embodiment, the memory cell has a programmable resistance memory element (e.g., an MRAM element) in series with a threshold switch selector (such as an OTS). Many types of memory systems can be used with the techniques presented herein. Example memory systems include dual in-line memory modules (DIMMs), solid-state drives ("SSDs"), memory cards, and embedded memory devices; however, other types of memory systems can also be used.

[0040] Figure 1The memory system 100 includes a memory controller 102, a memory 104 for storing data, and a local memory 140 (e.g., MRAM, ReRAM, DRAM). The local memory 140 may be non-volatile and retain data after power failure. The local memory 140 may be volatile and cannot retain data after power failure. In one embodiment, the local memory 140 is an MRAM. In one embodiment, the local memory MRAM does not need to retain data after power failure. However, the local memory MRAM can retain data after power failure. In one embodiment, the memory controller 102 and / or the local memory controller 164 provide access to the programmable resistance memory cells in the local memory 140. For example, the memory controller 102 may provide access to the cross-point array of the MRAM cells in the local memory 140. In another embodiment, the memory controller 102 or the interface 126 or both are eliminated, and the memory package is directly connected to the host 120 via a bus such as DDRn. Alternatively, they are connected to the host memory management unit (MMU). In another case, the memory controller 102 or a portion thereof is moved onto the memory 104 to connect the memory 104 directly to the host, such as by providing parity bits, ECC, and wear leveling on the memory 104, along with a DDRn interface to / from the host or MMU. The term "memory system" as used throughout this document is not limited to the memory system 100. For example, the local memory 140 or the combination of the local memory 140 and the local memory controller 164 may be considered a memory system. Likewise, the host memory 124 or the combination of the host processor 122 and the host memory 124 is considered a memory system.

[0041] Figure 1The components of the memory system 100 depicted in the figure are electronic circuits. The memory controller 102 has a host interface 152, a processor 156, an ECC engine 158, a memory interface 160, a local memory controller 164, a refresh logic 172, and a wear leveling 174. The host interface 152 is connected to the host 120 and communicates with it. The host interface 152 is also connected to the network on chip (NOC) 154. NOC is a communication subsystem on an integrated circuit. NOC can span synchronous and asynchronous clock domains, or use non-clocked asynchronous logic. NOC technology applies network theory and methods to on-chip communication, and brings significant improvements compared to conventional bus and cross switch interconnections. Compared with other designs, NOC improves the scalability of the system on chip (SoC) and the power efficiency of complex SoCs. The wires and links of the NOC are shared by many signals. Since all links in the NOC can run simultaneously on different data packets, a high degree of parallelism is achieved. Therefore, as the complexity of integrated subsystems continues to increase, NOC provides enhanced performance (such as throughput) and scalability compared to previous communication architectures (e.g., dedicated point-to-point signal lines, shared buses, or segmented buses with bridges). In other embodiments, NOC 154 can be replaced by a bus. Processor 156, ECC engine 158, memory interface 160, local memory controller 164, refresh logic 172, and wear leveling 174 are connected to NOC 154 and communicate with it. Local memory controller 164 is used to operate local high-speed memory 140 (e.g., MRAM) and communicate with it. In other embodiments, local high-speed memory 140 can be DRAM, SRAM, or another type of volatile memory.

[0042] The ECC engine 158 performs error correction services. For example, the ECC engine 158 performs data encoding and decoding of parity bits provided on or off memory as part of a codeword for error correction of data retrieved from the memory 140 or 104. In one embodiment, the ECC engine 158 is an electronic circuit programmed by software. For example, the ECC engine 158 can be a programmable processor. In other embodiments, the ECC engine 158 is a custom dedicated hardware circuit without any software. In one embodiment, the functions of the ECC engine 158 are implemented by the processor 156. In one embodiment, the local memory 140 has an ECC engine with or without a wear leveling engine. In one embodiment, the memory 104 has an ECC engine with or without a wear leveling engine.

[0043] The processor 156 performs various controller memory operations, such as programming, erasing, reading, and memory management processes including wear leveling. A separate wear leveling 174 is depicted, but the wear leveling 174 can be implemented by the processor 156. In addition, refresh logic 172 is depicted, but refresh can also be implemented by the processor 156. In one embodiment, the processor 156 is programmed by firmware. In other embodiments, the processor 156 is a customized dedicated hardware circuit without any software. The processor 156 also implements a conversion module, either as a software / firmware process or as a dedicated hardware circuit. In many systems, non-volatile memory is addressed internally to the storage system using physical addresses associated with one or more memory dies. However, the host system will use logical addresses to address various memory locations. This enables the host to assign data to consecutive logical addresses while the storage system is idle to store data between locations of one or more memory dies as desired. To implement such a system, the memory controller 102 (e.g., a conversion module) performs address conversion between the logical addresses used by the host and the physical addresses used by the memory dies. One exemplary implementation is to maintain a table (i.e., the L2P table described above) that identifies the current conversion between logical addresses and physical addresses. An entry in the L2P table may include an identification of a logical address and a corresponding physical address. Although logical address to physical address tables (or L2P tables) include the word "table", they do not have to be tables in the literal sense. Instead, the logical address to physical address tables (or L2P tables) may be any type of data structure. In some examples, the memory space of the storage system is so large that the local memory 140 cannot hold all L2P tables. In this case, the entire set of L2P tables is stored in the memory 104, and a subset of the L2P tables is cached (L2P cache) in the local high-speed memory 140.

[0044] The memory interface 160 communicates with the non-volatile memory 104. In one embodiment, the non-volatile memory 104 includes programmable resistance memory cells in a cross-point array. In one embodiment, the memory interface provides a switch mode interface. Other interfaces may also be used. In some exemplary implementations, the memory interface 160 (or another portion of the controller 102) implements a scheduler and buffer for transmitting data to one or more memory dies and receiving data from one or more memory dies.

[0045] In one embodiment, the local memory 140 has an ECC engine. The local memory 140 can be used to help perform other functions, such as wear leveling. Further details of on-chip memory maintenance are described in U.S. Patents 10,545,692, entitled "Memory Maintenance Operations During Refresh Window," and 10,885,991, entitled "Data Rewrite During Refresh Window," both of which are hereby incorporated by reference in their entirety. In one embodiment, the local memory 140 is synchronous. In one embodiment, the local memory 140 is asynchronous.

[0046] In one embodiment, memory 104 includes a plurality of memory packages. Each memory package includes one or more memory dies. Therefore, memory controller 102 is connected to one or more memory dies. In one embodiment, memory packages may include multiple types of memory, such as storage class memory (SCM) based on programmable resistive random access memory (such as ReRAM, MRAM, FeRAM, or RRAM), or phase change memory (PCM). In one embodiment, memory controller 102 provides access to memory cells in a cross-point array in memory package 104.

[0047] The memory controller 102 communicates with the host system 120 via an interface 152 that implements a protocol such as Compute Express Link (CXL). Alternatively, such a controller may be eliminated and the memory package may be placed directly on a host bus (e.g., DDRn or CXL). To work with the memory system 100, the host system 120 includes a host processor 122, a host memory 124, and an interface 126 connected along a bus 128. The host memory 124 is the physical memory of the host and may be a DRAM, SRAM, ReRAM, MRAM, non-volatile memory, or another type of storage device. In one embodiment, the host memory 124 includes a cross-point array of programmable resistance memory cells, wherein each memory cell includes a programmable resistance memory element and a threshold switch selector connected in series with the programmable resistance memory element.

[0048] The host system 120 is external and separate from the memory system 100. In one embodiment, the memory system 100 is embedded in the host system 120. The host memory 124 may be referred to as a memory system herein. The combination of the host processor 122 and the host memory 124 may be referred to as a memory system herein. In one embodiment, such a host memory may be a cross-point memory using MRAM.

[0049] Figure 2 is a block diagram depicting an example of a memory die 292 that can implement the techniques described herein. In one embodiment, the memory die 292 is included in the local memory 140, and in an embodiment, the memory die 292 is included in the memory 104. In one embodiment, the memory die 292 is included in the host memory 124. The memory die 292 includes a memory structure 202, which may include any memory cell described below. The memory structure 202 may include one or more memory arrays. The array terminal lines of the memory structure 202 include one or more various word line layers organized into rows, and one or more various bit line layers organized into columns. However, other orientations may also be implemented, including, for example, a diagonal pattern to save space. The memory die 292 includes a row control circuit 220, the output 208 of which is connected to the corresponding word line of the memory structure 202. The row control circuit 220 receives a set of M row address signals and one or more various control signals from the system control logic circuit 260, and may generally include circuits such as a row decoder 222, a row driver 224, and a block selection circuit 226 for both read operations and write operations. The row control circuit 220 may also include read / write circuits. In one embodiment, the row decoding and control circuit 220 has sense amplifiers 228, each of which includes circuitry for sensing the condition (e.g., voltage) of a word line of the memory structure 202. In one embodiment, the condition or bit state of a memory cell in the cross-point array is determined by sensing the word line voltage, comparing the accessed memory cell voltage to a reference voltage directly through the sense amplifier. Or less directly by first accessing the memory cell and storing a read voltage generated by forcing a read current through the cell and adjusting it up or down by 150 mV (or half of the voltage difference resulting from changing bit states), then writing the cell to the AP state, and again accessing the memory cell with the read current and comparing the resulting voltage to the stored voltage adjusted by, for example, 150 mV (or half of the voltage difference resulting from 2 different bit states). The memory die 292 also includes column decoding and control circuitry 210, whose input / output 206 is connected to corresponding bit lines of the memory structure 202. Although only a single block is shown for the memory structure 202, the memory die may include multiple arrays or "strips" that can be accessed individually. The column control circuitry 210 receives a set of N column address signals and one or more various control signals from the system control logic 260, and may generally include circuits such as a column decoder 212, a column decoder and driver 214, a block select circuit 216, and read / write circuits and I / O multiplexers.

[0050] System control logic 260 receives data and commands from a host system, and provides output data and status to the host system. In other embodiments, system control logic 260 receives data and commands from a separate controller circuit, and provides output data to the controller circuit, wherein the controller circuit communicates with the host system. Such a controller system can implement interfaces such as DDR, DIMM, CXL, PCIe, etc. In another embodiment, these data and commands are sent and received directly from the memory package to the host without a separate controller, and any controller required is in each tube core or in the tube core added to the multi-chip memory package. In some embodiments, system control logic 260 may include a state machine 262 for providing die-level control of memory operations. In one embodiment, state machine 262 can be programmed by software. In other embodiments, state machine 262 does not use software and is fully implemented in hardware (e.g., electronic circuit). In another embodiment, state machine 262 is replaced by a microcontroller or a microprocessor. The system control logic 260 may also include a power control module 264 that controls the power, current source current, and voltage supplied to the rows and columns of the memory structure 202 during memory operation, and may include a charge pump and regulator circuit for generating a regulated voltage, and an on / off control for the selection of each of the word lines and bit lines by the memory cell. In some embodiments, the power control 264 includes one or more current sources. (Multiple) current sources can be used to provide read and / or write currents. The system control logic 260 includes a storage device 266 that can be used to store parameters for operating the memory structure 202. The system control logic 260 also includes refresh logic 272 and wear leveling logic 274. Such system control logic can be commanded by the host 120 or the memory controller 102 to the refresh logic 272, which can load the row and column addresses (pointers) stored on the chip that can be incremented after refreshing. Only such address bits can be selected (to refresh OTS). Alternatively, such addresses may be read, corrected by manipulation via the ECC engine 269, and then stored in a "spare" location that is also incremented (so all codewords are periodically read, corrected, and relocated throughout the chip under the control of the wear leveling logic 274) to actually perform wear leveling so each bit is used more evenly across the chip. Such operations may be more directly controlled by a host of external controllers such as a PCIe or DDRn controller located separately from the memory chip or located on the memory die.

[0051] Commands and data are transmitted between the memory controller 102 and the memory die 292 via a memory controller interface 268 (also referred to as a "communication interface"). Such an interface may be, for example, PCIe, CXL, DDRn. The memory controller interface 268 is an electrical interface for communicating with the memory controller 102. Examples of the memory controller interface 268 also include a switching mode interface. Other I / O interfaces may also be used. For example, the memory controller interface 268 may implement a switching mode interface that is connected to the switching mode interface of the memory interface 228 / 258 of the memory controller 102. In one embodiment, the memory controller interface 268 includes a set of input and / or output (I / O) pins connected to the controller 102. In another embodiment, the interface is a JEDEC standard DDRn or LPDDRn, such as DDR5 or LPDDR5, or a subset thereof with smaller pages and / or relaxed timing.

[0052] The system control logic 260 in the controller located on the memory tube die in the memory package can include an error correction code (ECC) engine 269. The ECC engine 269 can be referred to as an ECC engine on the tube die because it is on the same semiconductor tube die as the memory unit. That is, the ECC engine 269 on the tube die can be used to encode the data and parity check bits to be stored in the memory structure 202, and decode and correct the decoded data. The encoded data can be referred to as a code word or an ECC code word in this article. The ECC engine 269 can be used to perform a decoding algorithm and to perform error correction. Therefore, the ECC engine 269 can decode the ECC code word. In one embodiment, the ECC engine 269 can decode data more quickly by directly decoding without iteration. Having an ECC engine 269 on the same tube die as the memory unit allows faster decoding. The ECC engine 269 can use a variety of decoding algorithms, including but not limited to Reed Solomon, Bose-Chaudhuri-Hocquenghem (BCH) and low-density parity check (LDPC).

[0053] In some embodiments, all elements of memory die 292, including system control logic 260, may be formed as part of a single die. In other embodiments, some or all of system control logic 260 may be formed on a different die; for example, an external controller chip.

[0054] In one embodiment, the memory structure 202 includes a three-dimensional memory array of nonvolatile or volatile memory cells, wherein multiple memory levels are formed over a single substrate, such as a wafer. The memory structure may include any type of nonvolatile or volatile memory integrally formed in one or more physical levels of memory cells having active regions disposed over a silicon or silicon-on-insulator (or other type) substrate. In another embodiment, the memory structure 202 includes a two-dimensional memory array of nonvolatile memory cells.

[0055] The exact type of memory array architecture or memory cell included in the memory structure 202 is not limited to the above examples. Many different types of memory array architectures or memory technologies can be used to form the memory structure 202. No specific non-volatile memory technology is required to implement the new claimed new embodiments proposed herein. Other examples of suitable technologies for the memory cells of the memory structure 202 include ReRAM memory (resistive random access memory), magnetoresistive memory (e.g., MRAM, spin transfer torque MRAM, spin orbit torque MRAM), FeRAM, phase change memory (e.g., PCM), etc. Examples of suitable technologies for the memory cell architecture of the memory structure 202 include two-dimensional arrays, three-dimensional arrays, cross-point arrays, stacked two-dimensional arrays, vertical bit line arrays, etc.

[0056] An example of a ReRAM or MRAM cross-point memory includes a programmable resistive switch element in series with an OTS selector, which is arranged in a cross-point array accessed by an X line and a Y line (e.g., a word line and a bit line). In another embodiment, the cross-point is a PCM in series with an OTS selector. In another embodiment, the memory cell may include a conductive bridge memory element. The conductive bridge memory element may also be referred to as a programmable metallization unit. Based on the physical relocation of ions within a solid electrolyte, the conductive bridge memory element may be used as a state-changing element. In some cases, the conductive bridge memory element may include two solid metal electrodes, one of which is relatively inert (e.g., tungsten) and the other is electrochemically active (e.g., silver or copper), with a thin film of a solid electrolyte between the two electrodes. As the temperature increases, the mobility of the ions also increases, which causes the programming threshold of the conductive bridge memory cell to decrease. Therefore, the conductive bridge memory element may have a wide range of programming thresholds over the entire temperature range.

[0057] Magnetoresistive random access memory (MRAM) uses magnetic storage elements to store data. These elements are formed by two ferromagnetic layers separated by a thin insulating layer, each of which can maintain magnetization. For field-controlled MRAM, one of the two layers is a permanent magnet set to a specific polarity; the magnetization of the other layer can be changed by applying an external field to the storage memory. Other types of MRAM cells are possible. The memory device can be built from a grid of MRAM cells or as a SOT magnetoresistive memory. MRAM-based memory implementations are discussed in more detail below.

[0058] Phase change memory (PCM) takes advantage of the unique properties of chalcogenide glass. One embodiment uses GeTe-Sb2Te3 superlattice to achieve non-thermal phase change by changing the coordination state of germanium atoms using only laser pulses (or light pulses from another source). The memory cell is programmed by a current pulse that can change the coordination of the PCM material or switch between an amorphous state and a crystalline state. Note that the use of "pulse" in this document does not require a square pulse, but includes (continuous or discontinuous) vibrations or pulse trains of sound, current, voltage light or other waves. And the current imposed for writing can be, for example, driven quickly to a peak value and then linearly ramped down at, for example, a 500ns edge rate. Such peak current force may be limited by partition voltage compliance, which varies with the position of the memory cell along the word line or bit line. In one embodiment, the phase change memory cell has a phase change memory element connected in series with a threshold switch selector (such as OTS).

[0059] Those of ordinary skill in the art will recognize that the technology described herein is not limited to a single particular memory structure, memory configuration, or material composition, but encompasses many related memory structures within the spirit and scope of the technology as described herein and as understood by those of ordinary skill in the art.

[0060] You can Figure 2The elements of the memory die 292 are grouped into two parts: the memory structure 202 and the peripheral circuits, including all other elements. An important characteristic of the memory circuit is its capacity, which can be increased by increasing the area of ​​the memory die 292 reserved for the memory structure 202; however, this will reduce the area of ​​the memory die available for peripheral circuits or increase the cost associated with the chip area. This can impose quite severe restrictions on these peripheral elements. For example, the need to fit the sense amplifier circuits within the available area can be a significant limitation on the sense amplifier design architecture. With respect to the system control logic 260, the reduction in available area may limit the available functions that can be implemented on the chip. Therefore, in the design of the memory die 292, a basic trade-off needs to be made between the amount of dedicated area for the memory structure 202 and the amount of dedicated area for the peripheral circuits. This trade-off may result in more IR drops due to the use of larger xy memory arrays between the driver circuits on the word lines and bit lines, which in turn may benefit more from the use of voltage limits and the partitioning of voltage compliance by the memory cell locations along the word lines and bit lines.

[0061] Another area where the memory structure 202 and the peripheral circuits often conflict is in the processing involved in forming these areas, as these areas often involve different processing technologies and the trade-offs when implementing different technologies on a single die. For example, elements such as sense amplifier circuits, charge pumps, logic elements in state machines, and other peripheral circuits in the system control logic 260 often use PMOS devices. In some cases, the memory structure will be based on CMOS devices. The processing operations used to manufacture CMOS dies will differ in many ways from processing operations optimized only for NMOS technology.

[0062] To improve these limitations, the following implementations can Figure 2 The components are separated into separately formed tube dies, and then these tube dies are bonded together. Figure 3An integrated memory component 270 is depicted having a memory structure die 280 and a control die 290. The memory structure 202 is formed on the memory structure die 280, and some or all of the peripheral circuit elements, including one or more control circuits, are formed on the control die 290. For example, the memory structure die 280 may be formed only of memory elements, such as an array of memory cells of an MRAM memory, a PCM memory, a ReRAM memory, or other memory type. Some or all of the peripheral circuits, even including elements such as decoders, current sources, and sense amplifiers, may then be moved to the control die. This allows each die in the semiconductor die to be optimized individually according to its technology. This provides more room for peripheral elements, and additional capabilities that may not be easily incorporated if the peripheral elements are confined to the edge of the same die that houses the memory cell array can now be incorporated. The two dies can then be bonded together in a bonded multi-die integrated memory component, with the array on one die connected to the peripheral elements on the other die. For example, although the following description will focus on an integrated memory assembly with one memory die and one control die, other embodiments may use additional dies, such as two memory dies and one control die.

[0063] and Figure 2 Like the memory die 292, Figure 3 The memory structure die 280 in the embodiment of the present invention includes the memory structure 202, which may include multiple independently accessible arrays or "strips". The system control logic 260, the row control circuit 220, and the column control circuit 210 are located in the control die 290. In some embodiments, all or a portion of the column control circuit 210 and all or a portion of the row control circuit 220 are located on the memory structure die 280. In some embodiments, a portion of the circuits in the system control logic 260 are located on the memory structure die 280.

[0064] Figure 3Column control circuitry 210 on control die 290 is shown coupled to memory structure 202 on memory structure die 280 via electrical path 293. For example, electrical path 293 may provide electrical connections between column decoder 212, column driver circuitry 214, block selector 216, and bit lines of memory structure 202. Electrical paths may extend from column control circuitry 210 in control die 290 through pads on control die 290 that are bonded to corresponding pads of memory structure die 280 that are connected to bit lines of memory structure 202. Each bit line of memory structure 202 may have a corresponding electrical path in electrical path 293 connected to column control circuitry 210, including a pair of bond pads. Similarly, row control circuitry 220, including row decoder 222, row driver 224, block selector 226, and sense amplifier 228, is coupled to memory structure 202 via electrical path 294. Each of the electrical paths 294 may correspond to, for example, a word line. Additional electrical paths may also be provided between the control die 290 and the memory structure die 280.

[0065] For the purposes of this document, the phrase "control circuitry" may include one or more of the following: memory controller 102, local memory controller 164, processor 156, system control logic 260, column control circuit 210, row control circuit 220, host processor 122, microcontroller, state machine and / or other control circuitry, or other similar circuitry for controlling non-volatile memory. The control circuitry may include only hardware or a combination of hardware and software (including firmware). For example, a controller programmed by firmware to perform the functions described herein is an example of a control circuit. The control circuitry may include a processor, an FPGA, an ASIC, an integrated circuit, or other types of circuits. Such control circuitry may include a driver, such as a direct driver that connects a node via a fully-conducting transistor (gate to power supply) driven to a fixed voltage (such as a power supply). Such a control circuit may include a current source driver.

[0066] For purposes of this document, the term “device” may include, but is not limited to, one or more of the following: memory system 100, local memory 140, local memory controller 164 and / or a combination of memory controller 102 and local memory 140, memory package 104, memory die 292, integrated memory component 270 and / or control die 290.

[0067] In the following discussion, Figure 2 and Figure 3The memory structure 202 will be discussed in the context of a cross-point architecture. In a cross-point architecture, a first set of conductors or lines (such as word lines) extend in a first direction relative to an underlying substrate, and a second set of conductors or lines (such as bit lines) extend in a second direction relative to the underlying substrate. Memory cells are located at the intersection of the word lines and the bit lines. The memory cells at these intersections can be formed according to any of a variety of techniques, including those described above. The following discussion will focus primarily on an implementation of a cross-point architecture based on the use of MRAM memory cells, wherein each MRAM memory cell is connected in series with a threshold switch selector (such as a bidirectional threshold switch (OTS)) to include a selectable memory bit. However, the implementation is not limited to a cross-point architecture in which current is provided to each MRAM cell having a magnetic memory element in a series OTS selector.

[0068] Figure 4A One embodiment of a portion of a memory array 402 forming a cross-point architecture is depicted in an oblique view. Figure 4A The memory array 402 is Figure 2 or Figure 3 2, wherein the memory die 292 or the memory structure die 280 may include a plurality of such memory arrays 402. The memory array 402 may be included in the local memory 140 or the host memory 124. The bit lines BL1-BL5 are arranged along a first direction (shown as extending into the page) relative to an underlying substrate (not shown) of the die, and the word lines WL1-WL5 are arranged along a second direction perpendicular to the first direction or along a diagonal line to provide a junction for interconnecting memory cells between WL and BL. Figure 4A is an example of a horizontal cross-point structure, wherein word lines WL1-WL5 and BL1-BL5 all extend in a horizontal direction relative to the substrate, and memory cells (two of which are indicated at 401) are oriented so that current (such as I cell In a memory array having additional layers of memory cells, such as described below with respect to Figure 4D As discussed, there will be corresponding additional layers of bit lines and word lines. For example, one pattern would be from the bottom layer: WL, memory cell, BL, memory cell, WL, WL, memory cell, BL memory cell, WL.

[0069] like Figure 4AAs depicted in , the memory array 402 includes a plurality of memory cells 401. The memory cell 401 may include a rewritable memory element, such as may be implemented using ReRAM, MRAM, PCM, or other materials having programmable resistance. The memory cell 401 may be referred to herein as a programmable resistance memory cell. One type of programmable resistance memory cell is called an MRAM cell, which is a memory cell that includes an MRAM memory element. The memory cell 401 may also include a threshold switch selector as an additional series element within the memory cell 401, such as may be implemented using a bidirectional threshold switch (OTS), a volatile conductive bridge (VCB), a metal-insulator-metal (MIM), or other materials that provide a highly nonlinear dependence of current or resistance on a varying selection voltage. The following discussion will focus on memory cells consisting of MRAM memory elements combined in series with bidirectional threshold switch elements, but much of the discussion may be more generally applicable. The current in the memory cells of the first memory level is shown as arrow I cell Upward flow is indicated, but current can flow in either direction to read or write the memory cell bit state, as discussed in more detail below.

[0070] Figure 4B and Figure 4C They presented Figure 4A Side and top views of the junction structure in . Figure 4B The side view shows a bottom line or word line WL1 and a plurality of top lines or bit lines BL1-BL n An MRAM memory cell 401 is located at the intersection between each top and bottom line, but PCM, ReRAM, FeRAM or other technologies may be used as memory elements. Figure 4C Is to show M bottom lines WL1-WL M and N top lines BL1-BL NA top view of the intersection structure of FIG. In a binary embodiment, the MRAM cell at each intersection can be programmed to one of two resistance states, a high resistance state and a low resistance state. More details on embodiments of MRAM memory cell designs and their reading techniques are given below. In some embodiments, groups of these wires are arranged continuously as "strips", and such strips can be paired adjacently in the word line (WL) direction and orthogonally in the bit line direction to form modules. Such modules can be composed of 2×2 strips to form a four-strip combination, where the WL driver between the strips is "center-driven" between the strips, where the WL runs continuously on the transistor driver at the approximate center of the line. Similarly, the BL driver can be located between pairs of strips paired in the BL direction, thereby being driven by the center, whereby the transistor driver and its area are shared between a pair of strips. Copper or other types of low-resistance through-holes can decode the transistor driver / selection and connect it to the WL or BL. In addition to the memory elements in the memory cell between the WL and the BL, a series selection element such as an OTS may also be included.

[0071] Figure 4A The cross-point array of FIG. 1 shows an embodiment with one layer of word lines and bit lines, where the MRAM or other memory technology for the memory cells is located at the intersection of the two sets of conductive lines. To increase the storage density of the memory die, multiple layers of such memory cells and conductive lines can be formed. The dual layer example in FIG. Figure 4D Shown in.

[0072] Figure 4D One embodiment of a portion of a two-level memory array forming a cross-point architecture is depicted in oblique view. Figure 4A Like in Figure 4D The first layer 418 memory cells 401 of the memory array 403 are shown, which are connected to the first layer word lines WL above. 1,1 -WL 1,4 The memory array 403 may be included in the intersection of the bit lines BL1-BL5. Figure 2 or Figure 3 The second layer 420 memory cells are formed above the bit lines BL1-BL5 and between these bit lines and the second set of word lines WL 2,1 -WL 2,4 In practice, the BL is shared. In an alternative, the second layer may include another BL layer above the BL shown and below the 2nd WL layer. Figure 4D Two layers 418 and 420 of memory cells are shown, but the structure can be extended upward in a similar pattern through additional alternating layers of word lines and bit lines. Depending on the embodiment, Figure 4DThe word lines and bit lines of the array can be biased for a read operation or a programming operation so that the current in each layer flows from the word line layer to the bit line layer or circulates in the opposite direction. For a given operation, the two layers can be constructed to have current in the same direction in each layer, or to have current in opposite directions by selection of the driver in the positive or negative direction. The memory cells can be placed in the first and second layers in the same orientation, so that they can be read or written using current in opposite directions by layer. Or when placed between the BL and WL in the second layer, the memory cells are placed in an inverted or flipped direction (so that current in the same direction can be used, such as for reading or writing memory cells in the first layer).

[0073] The use of a cross point architecture allows for arrays with a small footprint, and several such arrays can be formed on a single die. The memory cells formed at each cross point can be resistive memory cells, where the data value is encoded as different resistance levels, such as two levels with MRAM, or two or more levels for other memory element technologies such as PCM. Depending on the implementation, the memory cells can be binary valued, have a low resistance state or a high resistance state, or be multi-level cells (MLCs), which can have additional resistance intermediate between the low resistance state and the high resistance state. The cross point arrays described herein can be used for Figure 2 Memory die 292, Figure 1 The local storage 140 and / or Figure 1 124 in a host memory 124, or for any other configuration in which additional memory is useful. The resistive type memory cells may be formed according to many of the above mentioned technologies, such as ReRAM, PCM, FeRAM, or MRAM. The following discussion is primarily presented in the context of a memory array using a cross point architecture with binary valued MRAM memory cells, but much of the discussion is more generally applicable to other memory elements in memory cells within a cross point array or other configurations apparent to those skilled in the art.

[0074] Figure 5 The structure of an embodiment of an MRAM cell is shown. The MRAM cell can be used as, for example FIG. 4A to FIG. 4D4. The programmable resistive memory cell 401 in FIG. The MRAM cell includes a bottom electrode 501, a spacer layer 512, a threshold switch selector 502, a spacer layer 514, a pair of magnetic layers (reference layer 503 and free layer 507) separated by a separation layer or tunneling layer (in this example, magnesium oxide (MgO)) 505, and then a top electrode 511 separated from the free layer 507 by a spacer layer 509. The spacer layer 509 can include a MgO capping layer in contact with the free layer 507. The spacer layer 509 can also include additional metal layers. In another embodiment, the position of the reference layer 503 and the position of the free layer 507 are swapped, where the reference layer 503 is above the MgO 505 and the free layer 507 is below the MgO 505. In another embodiment, the position of the threshold switch selector 502 is between the free layer 507 and the top electrode 511.

[0075] In some embodiments, the bottom electrode 501 is a word line, and the top electrode 511 is a bit line. In other embodiments, the bottom electrode 501 is a bit line, and the top electrode 511 is a word line. The state of the memory cell is based on the relative orientation of the magnetization of the reference layer 503 and the free layer 507: if the two layers are magnetized in the same direction, the memory cell will be in a parallel (P) low resistance state (LRS); and if they have opposite orientations, the memory cell will be in an anti-parallel (AP) high resistance state (HRS). MLC embodiments will include additional intermediate states. The orientation of the reference layer 503 is fixed, and Figure 5 The reference layer 503 is also referred to as a fixed layer or a pinned layer. The reference layer 503 may be composed of multiple ferromagnetic layers coupled in an antiferromagnetic manner in a structure generally referred to as a synthetic antiferromagnet or SAF for short.

[0076] Data is written to the MRAM memory cell by programming the free layer 507 to have the same orientation or the opposite orientation as the reference layer 503. The MRAM memory cell array can be placed in an initial or erased state by setting all MRAM memory cells to a low resistance state in which all free layers of the MRAM memory cells have the same magnetic field orientation as their reference layers. Each of the memory cells is then selectively programmed (also referred to as "written") by reversing the magnetic field to be opposite to the magnetic field of the reference layer 503 and placing the free layer 507 of the memory cell in a high resistance state. The reference layer 503 is formed so that it will maintain its orientation when programming the free layer 507. The reference layer 503 may have a more complex design including a synthetic antiferromagnetic layer and additional reference layers. For simplicity, the drawings and discussion omit these additional layers and focus only on the fixed magnetic layer that is primarily responsible for the tunneling magnetoresistance in the cell.

[0077] The threshold switch selector 502 has a high resistance (in an off or non-conductive state) until it is biased to a voltage above its threshold voltage or a current above its threshold current, and until its voltage bias drops below Vhold ("Voffset") or the current drops below Ihold. After exceeding Vt and when Vhold across the switch selector is exceeded, the switch selector has a low resistance (in an on or conductive state). The threshold switch selector remains on until its current drops below the holding current Ihold, or the voltage drops below the holding voltage Vhold. When this occurs, the threshold switch selector returns to the off (higher) resistance state. Therefore, to program the memory cell at the intersection, a voltage sufficient to turn on the associated threshold switch selector and set or reset the memory cell is applied; and to read the memory cell, the threshold switch selector is similarly activated by turning on before determining the resistance state of the memory cell. One set of examples of threshold switch selectors is the bidirectional threshold switch material of a bidirectional threshold switch (OTS). Exemplary threshold switch materials include Ge-Se, Ge-Se-N, Ge-Se-As, Ge-Se-Sb-N, Ge58Se42, GeTe6, Si-Te, Zn-Te, C-Te, B-Te, Ge-As-Te-Si-N, Ge-As-Se-Te-Si and Ge-Se-As-Te, wherein the atomic percentage of each element ranges from a few percent to over 90%. In one embodiment, the threshold switch selector is a two-terminal device. The threshold switch selector 502 may also include an additional conductive layer at the interface with the reference layer 503. For example, a spacer layer 514 is depicted between the switch selector 502 and the reference layer 503. The spacer layer 514 at the interface with the reference layer 503 may be a single conductive layer or be composed of multiple conductive layers. The threshold switch selector 502 may also include an additional conductive layer at the interface with the bottom electrode 501. For example, a spacer layer 512 is depicted between the switch selector 502 and the reference layer 503. The spacer layer 512 at the interface with the bottom electrode 501 can be a single conductive layer or composed of multiple conductive layers. Examples of conductive layers adjacent to the OTS include carbon, carbon nitride, carbon silicide, carbon tungsten, titanium, titanium nitride, tungsten, tungsten nitride, tantalum, tantalum nitride, and others. The threshold voltage switch has a threshold voltage (Vt) above which the resistance of the device changes substantially from insulating or quasi-insulating to conductive.

[0078] In one embodiment, a current forcing method is used to access an MRAM cell. The current forcing method can be used to read or write an MRAM cell. In the current forcing method, a current driver drives an access current (e.g., I read or I write) through the bottom electrode 501. The current will be provided by a transistor or resistor based current source. In one embodiment, the current driver can be part of a row driver circuit (e.g., array driver 224) for address selection of the electrode 501. However, alternatively, the current driver can be part of a column driver circuit (e.g., driver circuit 214) for address selection of the electrode 501. A voltage (e.g., V select ). In this article, the term “read current” (I read ) and “write current” (I write ) will be used in conjunction with an access current driven through the MRAM cell (or other programmable resistor cell). The write current can change the state of the MRAM cell. For example, for a cell with a critical dimension (CD) of about 20 nanometers and a RA of 10Ωμm 2 For an MRAM cell, a write current of about 30uA for 50ns can be used to switch the MRAM state from the P state to the AP state. If a limited time (such as <20ns) is applied, the read current may be about half of the write current. A write current flowing through the MRAM cell in one direction will cause the AP state MRAM cell to change from the AP state to the P state. A write current flowing through the MRAM cell in another direction (such as in the read direction) will cause the P state MRAM cell to change from the P state to the AP state. In general, until the cell state is determined or the voltage level associated with the memory cell state is captured and stored, the read current will preferably be set low enough and the read duration will be short enough to avoid changing the state of the MRAM cell from the P state to the AP state or from the AP state to the P state during the read. Typically, the write current required to switch the MRAM state from the P state to the AP state is greater in absolute magnitude than the write current required to switch the MRAM state from the AP state to the P state. The current magnitude can be adjusted accordingly by the write direction or the current used for P to AP (if a single magnitude is used).

[0079] In some embodiments, a read current may be applied in the P2AP direction or alternatively in the AP2P direction. In some embodiments, the MRAM cell is read by performing an SRR (self-referenced read). In one embodiment, the SRR has a first read (Read1 in the P2AP direction), a first write (Write 1 to the AP state), and a second read (Read2 in the P2AP direction). The original state of the cell may then be restored by a second write (Write_back to the P state for bits that were originally in the P state). Or in another embodiment, the SRR read current and write current are reversed; for example, when the second layer is addressed by a memory cell of the same orientation as in the first layer.

[0080] In one embodiment, the voltage level of the memory cell due to Read1 in the P2AP direction is sensed and stored, for example, on a capacitor; or converted to a digital bit by an analog-to-digital converter and the bit stored in the memory, such as in an SRAM, until used in Read2. The state stored on the capacitor can be adjusted by forcing a voltage on one terminal of the capacitor connected to the storage capacitor, for example, positive or negative 150mv. Alternatively, the level of digital storage can be adjusted by digitally adding or subtracting 150mV to the storage bit. The 150mV can be adjusted to depend on the typical bit resistance. For example, if the low resistance state of the bit is 25K ohms and the high resistance state is 50K, the difference is 25K. For example, if the read current is 15ua, the voltage difference between the states is 25K×15ua=375mV, making the selection of 150mv acceptable, but perhaps suggesting that 187mV is more optimal.

[0081] Although the preceding description describes a read in the P2AP direction and a destructive write to the AP state (writing back to the P state after the SRR), in an alternative embodiment, the first SRR has a first read (Read1 in the AP2P direction), a destructive write to the P state (Write 1), and a second read in the AP2P direction (Read2).

[0082] In one embodiment, the MRAM cell is read by applying, for example, about 0V to the top electrode 511 (by turning on a transistor connected between 511 and a power source) while driving, for example, 15 microamperes (μA) of current through the bottom electrode 501. The read current may flow from the bottom electrode 501 to the top electrode 511. Note that the read may be Read1 or Read2 in the P2AP direction. P2AP means that the current flows in the direction of writing a bit from P to AP or from AP to AP. In some embodiments, data is written to the MRAM cell using a bipolar write operation. In one embodiment, the MRAM cell is written from the AP state to the P state by applying, for example, 3V to the top electrode 511 while driving, for example, a write current of -30μA through the bottom electrode 501. The write current will flow from the top electrode 511 to the bottom electrode 501. In one embodiment, the MRAM cell is written from the P state to the AP state by applying, for example, 0V to the top electrode 511 while driving, for example, 30μA of current through the bottom electrode 501. The write current will flow from electrode 501 to electrode 511 .

[0083] As Figure 5As an alternative to the method in , a select voltage may be applied to the bottom electrode 501, and an access current applied through the top electrode 511. In one such embodiment, the MRAM cell is read by applying, for example, 3V to the bottom electrode 501 while driving, for example, a read current of -15 μA through the top electrode 511. The read current may flow from the bottom electrode 501 to the top electrode 511.

[0084] In one embodiment, the MRAM cell is written from the AP state to the P state by applying, for example, -3V to the bottom electrode 501 while driving, for example, a 30μA write current through the top electrode 511. The electron current will flow from the bottom electrode 501 to the top electrode 511. In one embodiment, the MRAM cell is written from the P state to the AP state by applying, for example, 0V to the bottom electrode 501 while driving, for example, -30μA current through the top electrode 511. The electron current will flow from the top electrode 511 to the bottom electrode 501. In this discussion, it should also be understood that the direction of the current polarity used to switch the magnetization of the bit to the P or AP state can vary based on the reference layer design and the position of the reference layer relative to the free layer.

[0085] Some biasing techniques may result in a voltage across unselected memory cells of the array that can induce current in the unselected memory cells. Although this wasteful power consumption can be mitigated to some extent by designing the memory cells to have relatively high resistance levels for both the high resistance state and the low resistance state when WL or NL is not selected by the address, this overhead leakage will still result in increased current and power consumption as well as impose additional design constraints on the design of the memory cells and array. One approach to addressing this undesirable current leakage is to place a selector element in series with each MRAM or other resistive (e.g., ReRAM, PCM) memory cell. For example, in FIG. 4A to FIG. 4DIn, a selection transistor can be placed in series with each resistive memory cell element, so that the memory cell 401 is now a composite structure of a selection transistor and a programmable resistor. Such an architecture may be referred to as 1T1R. However, the use of a selection transistor requires the introduction of additional control lines and cell regions in order to be able to turn on the corresponding transistor of the selected memory cell. In addition, transistors are generally not scaled in the same manner as the resistive memory element write current, so that as the memory array moves to a smaller size, the use of a transistor-based selector may be a limiting factor, for example, in reducing costs. An alternative method for selecting a transistor is to use a threshold switch selector (e.g., threshold switch selector 502) connected in series with a programmable resistive element. The two-terminal threshold switch selector is able to turn on the corresponding selection transistor of the selected memory cell without the aforementioned additional control lines and additional cell regions. In some embodiments, the memory system performs a read as disclosed herein to read a memory cell having a two-terminal threshold switch selector connected in series with a programmable resistive memory element.

[0086] Fig. 6A and Figure 6B An embodiment for incorporating a threshold switch selector into an MRAM memory array having a cross-point architecture is shown. Fig. 6A and Figure 6B The example of FIG. 1 shows two MRAM cells (layer 1 cell, layer 2 cell) in a two-layer cross-point array, such as Figure 4D As shown, however, it is shown in a side view. Fig. 6A As depicted, keeping the orientation of the MRAM layers the same in both Tier 1 cells and Tier 2 cells allows the fabrication process to be the same for each layer. While 6B has inverted memory cells, this allows the drive circuits to work the same; for example, BL goes low for each layer to read P2AP. Fig. 6A and Figure 6B The first conductive line word line 1 600 at the bottom, the first conductive line word line 2 620 at the top, and the second conductive line bit line 610 in the middle are shown. In these figures, for ease of presentation, all of these lines are shown as extending from left to right across the page, but in a cross-point array, they would be more accurately represented as Figure 4D , wherein the word line or first conductive line or wire extends in a direction parallel to the surface of the underlying substrate, and the bit line or second conductive line or wire extends in a second direction parallel to the surface of the substrate, the second direction being substantially orthogonal to the first direction. The MRAM memory cell is also shown in simplified form, showing only the reference layer, the free layer and the intermediate tunnel barrier, but in actual implementation, it will generally include the above description of Figure 5 The additional structure.

[0087] An MRAM element 602 including a free layer 601, a tunnel barrier 603, and a reference layer 605 is formed above a threshold switch selector 609, wherein this series combination of the MRAM element 602 and the threshold switch selector 609 together forms a layer 1 cell between a bit line 610 and a word line 1600. The series combination of the MRAM element 602 and the threshold switch selector 609 operates largely as described above when the threshold switch selector 609 is turned on. However, it is initially necessary to apply a voltage V higher than the threshold voltage V of the threshold switch selector 609. th The voltage is used to turn on the threshold switch selector 609, and then the bias current or voltage needs to be maintained high enough to be higher than the holding current or holding voltage of the threshold switch selector 609 so that it remains turned on during subsequent read or write operations.

[0088] On the second layer, an MRAM element 612 including a free layer 611, a tunnel barrier 613, and a reference layer 615 is formed above a threshold switch selector 619, wherein the series combination of the MRAM element 612 and the threshold switch selector 619 together forms a layer 2 cell between the bit line 610 and the word line 2 620. The layer 2 cell will operate like the layer 1 cell, but the lower conductor now corresponds to the bit line 610, and the upper conductor is now the word line, i.e., word line 2 620. Additional paired layers may similarly share another bit line between them having a pattern of WL1, BL1, WL2, WL3, BL2, WL4, or have separate bit lines in a pattern of, for example, WL1, BL1, WL2, BL2. Or separate bit lines in a pattern of WL1, BL1, BL2, WL2.

[0089] exist Fig. 6A In the embodiment of the present invention, the threshold switch selector 609 / 619 is formed below the MRAM element 602 / 612, but in alternative embodiments, the threshold switch selector can be formed above the MRAM element in one or both layers. The MRAM memory cell is directional. Fig. 6A , MRAM elements 602 and 612 have the same orientation, with free layers 601 / 611 above reference layers 605 / 615 (relative to a substrate not shown). Forming these layers between conductive lines having the same structure can have many advantages, particularly with respect to processing, because each of the two layers, and subsequent layers in embodiments having more layers, can be formed according to the same processing sequence.

[0090] Figure 6B Shown with Fig. 6A An alternative embodiment is similarly arranged, except that in the layer 2 unit, the positions of the reference layer and the free layer are reversed. More specifically, as Fig. 6AAs in, between word line 1 650 and bit line 660, layer 1 cell includes MRAM element 1 having a free layer 651 formed over a tunnel barrier 653, which in turn is formed over a reference layer 655, wherein an MRAM element 652 is formed over a threshold switch selector 659. Figure 6B The second layer of the embodiment of the present invention also has an MRAM element 662 formed above the threshold switch selector 669 between the bit line 660 and the word line 2 670, but with respect to Fig. 6A , MRAM element 662 is inverted such that reference layer 661 is now formed above tunnel barrier 663 and free layer 665 is now formed below tunnel barrier 663. Alternatively, the configuration of MRAM element 662 may be used for Tier 1 cells, and the configuration of MRAM cell 652 may be used for Tier 2 cells.

[0091] Although Figure 6B The embodiment of the invention requires a different processing sequence for forming these layers, but in some embodiments, it can have advantages. In particular, the directionality of the MRAM structure can make Figure 6B The embodiment of is attractive because when writing or reading in the same direction (relative to the reference layer and the free layer), the bit line will be biased the same amount for both the lower layer and the upper layer, and both word lines will also be biased the same amount. For example, if both the layer 1 memory cell and the layer 2 memory cell are sensed in the P2AP direction (relative to the reference layer and the free layer), the bit line layer 660 will be biased, such as in the P2AP direction, with the bit line 660 biased low (e.g., 0V) for both the upper cell and the lower cell, and both word line 1 650 and word line 2 670 are biased to a higher voltage level. Similarly, with respect to writing, to write a high resistance AP state, the bit line 660 is biased low (e.g., 0V) for both the upper cell and the lower cell, and both word line 1 650 and word line 2 670 are biased to a higher voltage level.

[0092] Reading data from or writing data to an MRAM memory cell involves passing a current through the memory cell. In embodiments where a threshold switch selector is placed in series with the MRAM element, the threshold switch selector may be turned on by applying a sufficiently large voltage across the series combination of the threshold switch selector and the MRAM element and applying a current through the series combination before current can pass through the MRAM element.

[0093] Figure 7 An embodiment of a memory array 700 having a cross-point architecture is depicted. The memory array 700 may be included in Figure 2 or Figure 3700 has a set of first conductive lines 706a to 706h and a set of second conductive lines 708a to 708d. In one embodiment, the set of first conductive lines 706a to 706h are word lines, and the set of second conductive lines 708a to 708b are bit lines. For ease of discussion, the set of first conductive lines 706a to 706h may be referred to as word lines, and the set of second conductive lines 708a to 708b may be referred to as bit lines. However, the set of first conductive lines 706a to 706h may be bit lines, and the set of second conductive lines 708a to 708b may be word lines.

[0094] The memory array 700 has a plurality of programmable resistance memory cells 401. Each memory cell 401 is connected between one of the first conductive lines 706 and one of the second conductive lines 708. In one embodiment, each memory cell 401 has a magnetoresistive random access memory (MRAM) element connected in series with a threshold switch selector. The threshold switch selector 502 is configured to become conductive with a lower resistance in response to applying a voltage level exceeding the threshold voltage of the threshold switch selector 502, and remain conductive with a lower resistance until the current through the switch selector 502 is reduced to below the selector holding current Ihold. The threshold switch selector 502 can be a two-terminal device. In one embodiment, the threshold switch selector 502 includes an OTS.

[0095] For the purpose of discussion, memory cell 401a is selected for access. This can be a read or write access. The selected memory cell 401a is located at the intersection of the selected word line 706g and the selected bit line 708b. The selected memory cell means the memory cell selected for a memory operation such as a read or write. The selected memory cell is connected between the selected word line and the selected bit line. To select the memory cell 401, a select voltage such as near ground (V select_BL ) is provided to the selected bit line (eg, bit line 708b), and drives (or forces) the access current (I access ) through a selected word line (e.g., word line 706g). A selected word line means that the word line is connected to at least one selected memory cell. A selected word line will typically be connected to one or more unselected memory cells. A selected bit line means that the bit line is connected to at least one selected memory cell. A selected bit line will typically be connected to one or more unselected memory cells.

[0096] In one embodiment, V select_BLhas a sufficient magnitude so that the threshold switch selector 502 in the selected memory cell will turn on, assuming that I is applied to the selected word line with a sufficient compliance voltage relative to the BL voltage. access For example, V select_BL can be about 0 V. On the other hand, V unsel_BL has a magnitude such that the threshold switch selector 502 in the unselected memory cells will not turn on, for example, if the positive supply voltage is 3.3V, then V select_BL It can be about 1.65V. The drive access current (I access ) through at least a portion of the selected word line 706g. The access current may also flow through the selected memory cell 401a and in a portion of the selected bit line 708b after OTS is turned on. For example, such a selected WL may be driven high by a current source having a compliance voltage of, for example, 3.3V, 15μA for reading or 30μA for writing. To write the opposite polarity, for example, -30μA is imposed on the selected word line and the selected bit line is imposed to near 3.3V.

[0097] Other memory cells are not selected for access (i.e., are unselected memory cells). An unselected memory cell means a memory cell that is not currently selected for access (e.g., reading or writing). An unselected word line is connected only to unselected memory cells. An unselected bit line is connected only to unselected memory cells. Unselected word lines and bit lines are referred to as unselected word lines or unselected bit lines, respectively. In one embodiment, word lines and bit lines can be unselected by forcing them to an unselected voltage (such as Vmid) that is approximately half (e.g., 1.65V) of the drive compliance voltage (e.g., 3.3V). The unselected voltage (V unsel_BL ) is provided to unselected bit lines (e.g., bit lines 708a, 708c, 708d). The unselected voltage (V unsel_WL ) such as Vmid is provided to unselected word lines (e.g., word lines 710a, 710b, 710c, 710d, 710e, 710f, and 710h). access Can flow in either direction through a selected word line (and selected bit line). In one embodiment, no current other than leakage is forced through the unselected word lines (eg, 706a, 706b, 706c, 706d, 706e, 706f, and 706h).

[0098] exist Figure 7 In one embodiment, there are more word lines than bit lines in the cross-point array. In one embodiment, there are more bit lines than word lines in the cross-point array. In one embodiment, the number of bit lines in the cross-point array is equal to the number of word lines. Figure 7In the example of , there are twice as many word lines as bit lines in the cross-point array; however, different ratios may be used. Thus, different stripe sizes may be implemented. For example, a stripe may have 1024 BLs by 2048 WLs, which may be constructed as a module of 2048×4096 cells by center-driving the WLs and BLs between four stripes. In one embodiment, a read is performed on a group of memory cells by, for example, selecting a memory cell in each of a number of stripes. In some embodiments, more than one memory cell from a stripe may be selected for reading.

[0099] In some embodiments, a current forcing method is used to access memory cells in a cross-point memory array. A threshold switch selector can be used in series with a memory cell. The threshold switch selector can be connected in series with a memory element between a word line and a bit line. Therefore, any voltage on the switch selector will reduce the voltage across the memory element. Typically, there will be some variation in the offset voltage or holding voltage between the switch selectors. The current forcing method can help mitigate the offset voltage variation between the threshold switch selectors, thereby helping to minimize the cell current variation between the selected cells.

[0100] Figure 8 8 is a diagram of an embodiment of a system for reading a memory cell with a threshold switch selector. The system has a current source 802, a control circuit 804, and a sense amplifier 806. The memory cell 401 has a programmable resistance memory element 702 connected in series with a threshold switch selector 502. In one embodiment, the memory cell 401 is an MRAM cell, wherein the programmable resistance memory element 702 is a magnetoresistive memory element and the threshold switch selector 502 is an OTS. However, the memory cell can be a PCM cell, a ReRam cell, etc. The threshold switch selector 502 does not need to be an OTS. The threshold switch selector 502 can alternatively be a volatile conductive bridge (VCB), a metal-insulator-metal (MIM), or other materials that provide a high nonlinear dependence of the current on the selection voltage. The voltage Vselect on the bit line (BL) is a voltage of an appropriate magnitude to select a memory cell, such as 0V. In one embodiment, the Vselect to the bit line is close to 3.3V, and in another embodiment is close to 0V.

[0101] The output of current source 802 is connected to a node called VXSP. Node VXSP may be connected to a word line via an address decoding transistor, with the source drain connected between VXSP and the word line, and the gate connected to a binary address signal. Such a transistor may be p or n channel. The system may have a WL decoder for selecting which word line is connected to current source 802. Such a WL decoder is not provided in the Figure 8806 and may be referred to as a sensing node. Current source 802 provides a current (Isource) to the selected word line. Note that current source 802 may use current generators of different magnitudes for read current and write current. In one embodiment, current source 802 provides a first write current to "set" the memory cell and a second write current to "reset" the memory cell, wherein the two write currents have opposite polarities. During reading, the current may charge the selected word line until threshold switch selector 502 is turned on. After threshold switch selector 502 is turned on, Isource is driven through memory cell 401 in a direction and magnitude designed for reading and / or writing.

[0102] Sense amplifier 806 (more briefly, "sense amplifier") can be connected to node VXSP and can sense memory cell 401 when Isource is driven through memory cell 401. Sense amplifier 806 has a set of capacitors 810. In one embodiment, the sense amplifier includes a differential amplifier that can compare the voltage on VXSP with a reference voltage (e.g., Vref). In one embodiment, one of those capacitors in sense amplifier 806 can be connected to node VXSP to sense and store the voltage on VXSP in order to sense the memory cell. In one embodiment, capacitor 810 includes one or more additional capacitors that can be connected to node VXSP (and therefore connected to the selected word line) during a read operation. As will be explained in more detail below, these one or more additional capacitors can be used to add or remove charge from node VXSP (and therefore from the selected word line). In one embodiment, the capacitor can be connected to node VXSP (and therefore connected to the selected word line) immediately after threshold switch selector 502 is turned on. If BL is close to 0, the turn-off OTS occurs on WL at Vth. Until it is turned on, only leakage to the unselected bits flows on the selection WL and BL, and the read current charges WL until OTS is turned on, and then through the selected memory cell. The voltage between WL and BL is then reduced from Vth to Voffset plus Iread×the path resistance from VXSP to ground (as described later, such as selecting transistors T1+T3 to WL and T1+T3 to BL and memory cell resistance and voltage (mram+ots) and driving transistors from ground to bit line T1+T3). Any voltage difference is discharged through the memory cell and other loads. The capacitor is a load that can be precharged to a lower voltage and thereby removes charge from node VXSP (and therefore from the selected word line) when the transistor is connected to VXSP. Removing charge from node VXSP (and therefore from the selected word line) prevents undesirable current exceeding Iread from flowing in memory element 702, thereby helping to avoid the memory element changing its state before sensing the voltage on memory element 702 after the memory element 702 stabilizes after address selection and OTS is turned on. Another benefit of removing charge from node VXSP (and therefore from the selected word line) immediately after threshold switch selector 502 is turned on is to speed up the rate at which the selected word line drops to a stable voltage, thereby reducing read latency in a sense read operation, or reducing the time used to establish a write voltage during a write.

[0103] Capacitor 810 can be used for global reference read (also known as midpoint read) or SRR. In one embodiment of SRR, one of the capacitors is used to provide charge to node VXSP (and therefore to the selected word line) to accelerate the rate at which the word line is charged to the write voltage. This write can be used for destructive writes between Read1 and Read2 or for write-back to restore the original state of memory element 702 when needed. In one embodiment of SRR, one of the capacitors is used to discharge node VXSP (and therefore the selected word line) after the current from current source 802 is reduced from the write current to the read current. Therefore, a capacitor such as can be used to accelerate the rate at which the selected word line is discharged so that Read2 can be performed faster, thereby reducing the read latency.

[0104] Fig. 9 1 is a flow chart of one embodiment of a process 900 for reading a programmable resistance memory cell in a cross point array. The process can be used to read a memory cell having a threshold switch selector 502 such as, but not limited to, an OTS. The process 900 can reduce read latency. The process 900 can improve read accuracy (bit error rate) by preventing a memory cell from inadvertently flipping its state before the cell is sensed. In one embodiment, the process 900 is used in a midpoint read. In one embodiment, the process 900 is used in an SRR.

[0105] Step 902 includes applying a select voltage to a first conductive line. For example, control circuit 804 provides a select voltage to a bit line. As an example, the bit line may be grounded to select the bit line; however, other voltages may be used. Step 902 may include applying a voltage to a global and / or local bit line decoder based on the address of the selected memory cell.

[0106] Step 904 includes providing a signal (e.g., a current) to the second conductive line to turn on the threshold switch selector 502. For example, the control circuit 804 controls the current source 802 to apply Isource to the word line. The control circuit 804 can control the magnitude of the current by selecting which current to apply from the current source 802. Step 902 may include applying a voltage to a global and / or local word line decoder based on the address of the selected memory cell.

[0107] Step 906 includes connecting the first capacitor of the sense amplifier 806 to the second conductive line after the threshold switch selector 502 has been turned on. Step 906 may include connecting the first capacitor to the sense node VXSP, which is connected to the word line, thereby connecting the first capacitor to the word line. The threshold switch selector 502 may have a high resistance before being turned on; however, when the threshold switch selector 502 is turned on, the resistance may drop rapidly. The rapid drop in resistance may result in a condition that may be referred to as "excess charge" at the node VXSP and / or the word line. Excess charge may potentially flow in the memory element 702, which may potentially change the state of the memory element 702, thereby causing a read error. In one embodiment, the excess charge is transferred from the node VXSP and / or the word line to the first capacitor, which may reduce the undesirable current (higher than the desired Iread current) in the memory element 702, thereby preventing the change of the state of the memory element 702. Additionally, by removing charge from node VXSP and / or the word line, the first capacitor can help reduce the time it takes for the voltage on the second word line to stabilize so that the memory cell can be sensed.

[0108] Step 908 includes disconnecting the first capacitor from the second conductive line. The first capacitor can be disconnected after the voltage on the second conductive line has stabilized, but the memory system is not required to wait until the voltage has stabilized before disconnecting the first capacitor from the second conductive line. In one embodiment, the memory system connects more than one capacitor to the second conductive line to quickly reduce the voltage on the second conductive line. Then, after the voltage has dropped significantly, the memory system disconnects one of the capacitors, wherein the other capacitor remains connected to the second conductive line. The two capacitors may include a larger capacitor and a smaller capacitor. The purpose of the larger capacitor is to be large enough to discharge VXSP quickly. However, a large capacitance may result in a longer stabilization time for reaching the Vfinal required to distinguish the two states of the memory cell. Therefore, attaching two capacitors can quickly discharge VXSP. Then, disconnecting the larger capacitor and leaving the smaller capacitor can speed up the stabilization time, so that VXSP reaches Vfinal earlier. This technique using two capacitors can be used to reduce the time it takes to stabilize the voltage on the second conductive line.

[0109] Step 910 includes sensing the memory cell when current is driven through the memory cell and both capacitors, or the first capacitor or the second capacitor, are disconnected from the second conductive line or both are not disconnected. In one embodiment, sensing is used for Read1 of the SRR. In one embodiment, the second capacitor is connected to VXSP to sense the memory cell. The second capacitor can be used in Read1 of the SRR to sense and store the voltage at VXSP. In one embodiment, sensing is used for midpoint reading. In the embodiment of midpoint reading, the sense amplifier 806 can compare the voltage at VXSP to a reference voltage (Vref) after VXSP has been sufficiently stabilized near Vfinal (so the difference is less than the available margin when sensing the bit state).

[0110] Fig.10The voltage on the bit line and word line during the reading of the memory cell with the threshold switch selector is shown. Initially, the voltage on the bit line and word line is set to Vmid (e.g., about 1.65V) respectively. At t1, the bit line is connected to ground, wherein the voltage on the bit line is reduced from Vmid to ground at t2. In this example, close to ground is the selection voltage of the bit line. Also at t1, the voltage on the word line (WL) begins to increase due to the current source 802 starting to provide current to the word line. This current may be equal to the read current used when sensing and using the voltage. At t3, the threshold switch selector 502 is turned on. The resistance of the threshold switch selector 502 may be quickly reduced when it is turned on, which may be referred to as "snapback" in this article, which is the difference between the voltage on the word line when the OTS is turned on and the voltage on the word line after stabilization when the read current flows through the selected memory element. The voltage on the word line begins to drop at t3 (see curve 1010). At t4, the first capacitor is connected to the word line, which quickly discharges the word line (see curve 1012). The word line can reach a stable voltage faster (see curve 1016). The memory cell can be sensed when the word line is at a stable voltage (such as at t5), rather than having to wait until t6 when the first capacitor is not connected to the word line. In one embodiment, the first capacitor is disconnected from the word line before sensing the memory cell. In one embodiment, a second (sensing) capacitor can be connected to the word line to sense and store the voltage from the memory cell for later adjustment to the midpoint of the signal difference that may come from the memory cell. When the first capacitor is connected to the word line, the second (sensing) capacitor can also be connected to the word line. Instead of the second capacitor, the first capacitor can also be used for sensing and storage. The size of the first capacitor can be adjusted for the best drop in the VXSP voltage because it is primarily responsible for discharging the word line. If the first capacitor is not connected to the word line, the voltage on the word line can take much longer to decrease and stabilize (see curve 1014). Therefore, the sensing of the memory cell will need to wait until after t6. Therefore, connecting the first capacitor to the word line after the threshold switch selector 502 is turned on can reduce read latency. In addition, snapback can potentially cause undesirable current in the memory element 702, which can potentially flip the state of the memory element 702, thereby causing a read error. However, connecting the first capacitor to the word line after the threshold switch selector 502 is turned on can divert such undesirable current from flowing in the memory element 702 so as to flow into the first capacitor instead, thereby preventing the aforementioned flipping of the memory element state.

[0111] Fig.111 is a schematic diagram of an embodiment of a read path and a sense amplifier. The read path includes a current source, a word line decoding transistor, a selected word line, a memory cell, a selected bit line, and a bit line decoding transistor. The read path has a Vp positive power supply, such as 4V. The read current source 1102 is connected to the power supply (Vp) and supplies Iread to the memory cell. The read current can be enabled by turning on transistor T1 by making Read* low. The output of T1 as node VXSP also drives the non-inverting input (+) of the differential sense amplifier 806. The P-channel transistor T3P acts as a global WL decoder, which can be selected when the gate of T3P is low (such as when driven by a binary decoder address signal from a host). The P-channel transistor T1P acts as a local WL decoder, which can be selected when the gate of T1P is low (such as when driven by a binary decoder address signal from a host). The P-channel transistor T3P can act as a driver for the selected WL. The memory cell 401 is connected between the selected WL and the selected BL. The memory cell (or bit) has a threshold switch selector 502 and a memory element 702. The selected WL may be one of the N WLs in the array. The selected BL may be one of the M BLs in the array. The memory cell 401 may reside at the intersection of the selected WL and the selected BL on a chip having one or more arrays. The N-channel transistor T1N may act as a local decoder driver into the selected BL. When the T1N gate is high (such as when driven by a binary decoder address signal from a host), the BL may be selected. The N-channel transistor T3N may act as a global decoder, which is selected when the T3N gate is high (such as when driven by a binary decoder address signal from a host). The output of T3N is VYS. The driver (YEN) is located between VYS and the negative power supply (GND). In order to write in reverse, there may be a separate driver connected to VYS and a positive power supply Vp to which VYS is driven, and a parallel p-ch transistor decoding path (n-ch T1 and T3) may be set in parallel with the n-ch driver path described herein. The n-ch path is then turned off and the p-ch path is enabled to Vp together with the driver transistor, wherein the gate is grounded. Similarly, an n-ch path may be provided, together with a current source to ground set in parallel with the p-ch path to the word line described above, which current source is to Vp or some other more suitable voltage. The p-ch path is then turned off, and the n-ch path is enabled by turning on the n-ch driver transistor in series with the current source to ground. The sense amplifier 806 has a non-inverting input (+) and an inverting input (-). The inverting input (-) is provided with a reference voltage (Vref). The non-inverting input (+) is connected to VXSP.

[0112] In one embodiment, the operation of the read path may be as follows. Nodes VXSP, the selected WL, the selected BLBL, and VYS may be transistors precharged to Vmid during the standby phase. The desired WL line (1 of N) may be selected by turning off the precharge and applying a low voltage to the gates of transistors T3P and T1P (the gate voltage is referred to as a decoded address signal). The BL line may be selected by turning off the precharge and applying a high voltage to the gates of transistors T1N and T3N (the gate voltage is referred to as a decoded address signal). The gate of transistor YEN may be made high to connect node VYS to GND. Iread may then be turned on and connected to VXSP by making the gate of T1 low (e.g., Read* becomes low). Therefore, when turned on by YEN becoming H, BL may be quickly pulled to GND by its active driver. The selected WL and VXSP are ramped toward Vp by Iread at a time rate = Ctotal × V / Iread. When the voltage on WL reaches the approximate voltage of Vth(OTS), the threshold switch selector 502 turns on because the I×R drop caused by leakage is relatively low. Here, Vth(OTS) refers to the threshold switch voltage of the threshold switch selector 502, which can be but is not required to be OTS. Then, the voltage on VXSP to the sense amplifier 806 stabilizes back to Vfinal=Vread(final)=Voff(OTS)+Rpath×Iread. Here, Rpath includes the WL and BL wire resistances, the address transistors (T3P, T1P, T1N, T3N) and the driver (YEN) to GND, as well as the resistance 702 of the memory element itself. Here, Voff(OTS) is the voltage across the threshold switch selector 502. The sense amplifier 806 compares the Vfinal input on the sense amplifier (+) with the Vref on the sense amplifier (-).

[0113] Fig.12806 is a schematic diagram of an embodiment of a sense amplifier 806. For each of the n or p-ch transistors, a complementary transistor (p or n-ch) can be added in parallel and driven by a complementary signal, except for the cross-coupled and timed transistors T16, T17, T21. The sense amplifier 806 has a plurality of capacitors C1, C2, C3, and C4. In one embodiment, C1 is a snapback discharge capacitor, which is used to discharge VXSP when or immediately after the threshold switch selector 502 is turned on. In one embodiment, C2 is a Read1 storage capacitor for sensing VXSP (e.g., sensing a memory cell). Note that C2 can also store the voltage sensed at VXSP for comparison with the voltage sensed at VXSP later during Read2 (by turning off T28 and then pulsing positive Vbump sufficiently to raise the voltage (e.g., 150mv) to appropriately adjust the voltage stored on C2). Transistors T19 and T20 provide the ability to switch between Vbump and ground using Bump and Bump_Bar signals. Bump bar here is the logical complement of Bump. In one embodiment, C3 is a write reset discharge capacitor, which is used to discharge VXSP (e.g., discharge the selected WL) after a destructive write of SRR. Capacitor C3 can be used to accelerate the discharge of the selected WL, which occurs when the current decreases from Iwrite to Iread. In one embodiment, C4 is a write reset charge capacitor, which is used to charge VXSP (e.g., charge the selected WL) at the beginning of the destructive write of SRR. When the current increases from the read current to the write current, capacitor C4 can be used to accelerate the charging of the selected WL. In one embodiment, the sense amplifier 806 has a fifth capacitor C5 ( Fig.12 4. If desired, an optional fifth capacitor C5 may be used to charge VXSP (eg, to charge the selected WL) during a second write of the SRR, which is used to restore the original state of the memory cell 401. Further details of the sense amplifier 806 are discussed below.

[0114] In some embodiments, a capacitor in the sense amplifier is used during a global reference read to discharge the selected word line when (or shortly after) the threshold switch selector is turned on. In one embodiment, C1 is a snapback discharge capacitor that is used to discharge VXSP when or just after the threshold switch selector 502 is turned on. In one embodiment, Fig. 9 The process 900 is for global reference reading, where C1 is used as a snapback discharge capacitor, which is used to discharge VXSP when or immediately after the threshold switch selector 502 is turned on.

[0115] Fig.13 is a table 1300 indicating the timing of signals in sense amplifier 806 for an implementation of global reference read, where C1 is used as a snapback discharge capacitor. Fig.12 The read signal is the signal at the gate of the various transistors in the sense amplifier 806 in FIG. 8. The read signal refers to the signal that activates the read current (see Fig.11 1300 provides a description of each signal. Each time frame represents a time interval during which the signal is enabled (black) or disabled (white). The time frames are ordered from earlier time to later time, but each time frame does not necessarily have the same duration. The table is used to illustrate the contemporaneous relationship between the signals. The optimal transition between the enabled and disabled signal states does not need to occur at the beginning of the time interval and may be offset in time relative to other signals in the same time frame. At box 0, one or more capacitors in the sense amplifier 806 are precharged. In one embodiment, C1 is precharged to a voltage such as close to ground, which is tuned to provide a fast discharge of VXSP near its read Vfinal during Read1. In one embodiment, C1 is precharged to close to GND, and in another embodiment is precharged to close to Vmid. The size of C1 can be selected based on other capacitors in the circuit. For example, the size of C1 can be selected based on the capacitance along the read path. These read path capacitors can be divided into two separate capacitors C_CMOS and C_array. For example, C_CMOS is the combined capacitance of transistors, wires, and circuits in the read path between the current mirror and the cross-point array. That is, C_CMOS represents all capacitances outside the cross-point array, whose stored charge will be discharged via the selected memory cell after the selector is turned on. C_array is the combined capacitance of the selected WL or BL, vias, and other wiring between the selected transistor and the selected memory element. As an example, C1 may be between about 10% and 50% of the combined CMOS and array capacitances. The CMOS and array capacitances may be in the range of 50 to 200 fF or greater. The exemplary range of C1 is between 10 and 100 femtofarads (fF) (i.e., between 10×10^-15 farads and 100×10^-15 farads), where the actual range and size are adjusted by the process selection of the CMOS transistors and their size, the array wire length, width, and spacing (pitch), and the memory cell diameter (CD) and height, and the side slope angles along the memory and selector elements. At Box 0, Capture, Precharge, S1, and S3 are high. At Box 1, Capture, Precharge, S1, and S3 are low.

[0116] exist Fig.13 Box 1 in ( Fig.10At time t1 in the example, a read signal is used to enable a read current (eg, turn on the Fig.11 As discussed previously, the read current will charge the selected WL. The duration of frame 1 is long enough to provide enough voltage ( Fig.10 t3 in frame 1). Capture is low in frame 1 and high in frame 2 and frame 3. When Capture is low, the sense amplifier is isolated from the data input. Capture is high so that the signal enters the sense amplifier. At frames 2 to 4, S1 is high. At frame 2, S3 is high. Fig.12 , at Box 2 and Box 3, apply "catch" to T12 and T13. At Box 2, enable the VXSP and VREF connections. Fig.12 , S1 is applied to T11 to connect sense amplifier 806 to VXSP. In block 2 ( Fig.10 At time t4 in FIG. 1 , the snapback discharge capacitor C1 is enabled using signal S3, which is disconnected at block 3. Fig.12 , S3 is applied to the gate of T26 to connect C1 to VXSP. Thus, the snapback discharge capacitor C1 can discharge VXSP (and thus the voltage on WL). After block 3, the snapback discharge capacitor C1 is disconnected from VXSP. Note that with T11 and T12 and T13 and T14 all turned on, T16 and T17 are connected to VXSP and Vref. In addition, S2 is high at blocks 3 and 4 to enable the Vref connection. Reference Fig.12 , S2 is applied to T14 to enable Vref. Note that with both T13 and T14 on, the cross-coupled T16 and T17 are connected to Vref and VXSP. Therefore, the VXSP voltage at the non-inverting input (+) can be compared to Vref at the inverting input (-) by asserting the clock. At block 4, the sense amplifier output is clocked on. Reference Fig.12 , apply the clock to T21.

[0117] Fig.14A and Fig. 14B Further details of timing signals during an implementation of a global reference read are depicted. Fig.14A Depicted is a read current 1410 provided to a selected WL between t1 and t4. Fig. 14B The voltage on the selected WL is depicted. The voltage across the memory cell increases from t1 to ts. The threshold switch selector is turned off between t1 and ts. Between t1 and ts, the current causes the word line voltage to increase. This current also supports any leakage in the path. Once the voltage on the threshold switch selector reaches the threshold voltage V of the threshold switch selector 502 th, the threshold switch selector will be turned on and switched to a low resistance state (at ts). Once the threshold switch selector 502 is in the on state (at ts), current can flow through the selected memory cell 401. The WL voltage will drop to a level that depends on the series resistance of the memory element 702, the on-state resistance of the threshold switch selector 502, together with the address selection transistor and metal resistance in the read path. At t2, the snapback discharge capacitor C1 is connected to VXSP, which can accelerate the rate at which the word line drops to its stable voltage. If the memory cell is in the HRS state, the voltage drops to line 1430. If the memory cell is in the LRS state, the voltage drops to line 1440. The sense amplifier 806 can then sense VXSP and compare with Vref to determine whether the memory cell is in HRS or LRS. Note that after the snapback discharge capacitor C1 is connected to VXSP at t2, the word line voltage drops very quickly and stabilizes to reduce the read delay. Additionally, the snapback discharge capacitor C1 may prevent the state of the memory cell from flipping before the cell is sensed by diverting current that would otherwise flow through the memory element 702 to the capacitor.

[0118] In some embodiments, the capacitor in the sense amplifier 806 is used during the SRR read to discharge the selected word line when the threshold switch selector is turned on (or shortly thereafter). In one embodiment, C1 is used as a snapback discharge capacitor, which is used to discharge VXSP when or just after the threshold switch selector 502 is turned on in the SRR. In one embodiment, the capacitor in the sense amplifier 806 is used during the SRR read to discharge the selected word line. Fig. 9 900, wherein C1 is used as a snapback discharge capacitor for discharging VXSP when or immediately after the threshold switch selector 502 is turned on. In another embodiment, the snapback discharge capacitor remains connected throughout the first read in the SRR. In some embodiments, the capacitor in the sense amplifier is used during the SRR read to discharge the selected word line after the write phase of the SRR in preparation for the second read after destructively writing the bit to the AP. In one embodiment, C3 is used as a write reset discharge capacitor during the SRR by asserting S5.

[0119] Fig.15 is a table 1500 indicating the timing of signals in sense amplifier 806 for an embodiment of an SRR, where C1 is used as a snapback discharge capacitor. C2 is used as a read reference capacitor. Additionally, C3 is used as a write reset discharge capacitor. Table 1500 lists the timing of signals applied to the sense amplifier 806 for an embodiment of an SRR, where C1 is used as a snapback discharge capacitor. C2 is used as a read reference capacitor. Additionally, C3 is used as a write reset discharge capacitor. Fig.12 The read signal is the signal at the gate of the various transistors in the sense amplifier 806 in FIG. 8. The read signal refers to the signal that activates the read current (see Fig.11Read* at the gate of T1 in ). At box 0, one or more capacitors in the sense amplifier 806 are precharged. The precharge voltages of C1, C2, and C3 may be different. In one embodiment, C1 is precharged to a voltage that is tuned to provide a fast discharge of VXSP after the threshold switch selector 502 is turned on. In another embodiment, C1 is precharged to GND. In another embodiment, for example, if Vth is closer to the read Vfinal, C1 is precharged to Vmid (VPC). The size of capacitors C1 and C3 can be selected based on other capacitances in the circuit. For example, the size of capacitors C1 and C3 can be selected based on the capacitance along the read path. An exemplary range of C1 is between 10 and 100 femtofarads (fF). In one embodiment, C2 is precharged to a voltage suitable for sensing. In one embodiment, C2 is precharged to GND, and in another embodiment is precharged to Vmid (VPC). An exemplary range of C2 is between 1 and 10 femtofarads (fF). In one embodiment, C3 is precharged to a voltage that is tuned to provide a fast discharge of VXSP after a destructive write of the SRR. In one embodiment, C3 is precharged from GND to Vmid(VPC). As an example, C3 may be between about 10% and 50% of C_CMOS+C_array. An exemplary range for C3 is between 10 and 100 femtofarads (fF). Fig.12 , the signal "precharge" applied to the gate of T23 can be used to precharge C1 and C3 to VPC. The signal "precharge" applied to the gate of T25 can be used to precharge C2 to VPC or GND. S1 and S2 are turned off / L during precharge. At box 0, capture, S1, S3, S4 and S5 are set high during precharge. Vbump is set to 0V during precharge.

[0120] exist Fig.15 At block 1 in FIG. 1 , a read signal is used to enable a read current (eg, turn on Fig.11 As discussed previously, the read current will charge the selected WL and turn on the threshold switch selector 502. At blocks 2 through 4, capture is high. At blocks 2 through 4, signal S1 to transistor T11 connects sense amplifier 806 to VXSP through block 4, after sample is deasserted. At blocks 2 through 3, S3 is used to enable snapback discharge capacitor C1. Fig.12, S3 is applied to the gate of T26 to connect C1 to VXSP. Thus, the snapback discharge capacitor C1 can discharge VXSP (and thus the voltage on WL). In one embodiment, S3 can be kept high during block 3 to enable greater stabilization time before locking the VXSP voltage on C2 for later use.

[0121] At the beginning of Block 3, read reference capacitor C2 is enabled by asserting Sample and S4 until the end of Block 3. At the beginning of Block 3, snapback discharge capacitor C1 is disconnected from VXSP. During Block 3, Sample is made high to connect C2 to VXSP. Fig.12 , S4 is applied to T28 to enable the read reference capacitor C2, and the "sample" at the gate of T24 is also high to connect C2 to VXSP. Therefore, the read reference capacitor C2 can be used to sense and store the voltage on VXSP generated by the read during the first Read1 of the memory cell 401. The read reference capacitor C2 will store the Read1 result and allow its level to be adjusted using Vbump. In addition, at box 4 after sampling L, the VXSP connection is disabled by making S1 low. In one embodiment, the read reference capacitor C2 is enabled during box 2 along with the snapback discharge capacitor C1, where C1 is disabled at the end of box 2 and C1 is disabled at the end of box 3.

[0122] At block 4, the read current, sampling and capturing are disabled before enabling the write current, preferably as a transition to increase the read current to become the write current without the current dropping to the read current. The read current may be disabled by turning off T1 (see Fig.11 ). Between blocks 4 and 6, capture is low, which can avoid precharge disturbance during write. In one embodiment, there is a separate write current source similar to the read current source 1102. However, the write current can have a larger magnitude than the read current. At block 4, the write current source can be connected to VXSP to provide Iwrite, similar to how the read current source 1102 can be connected to VXSP to supply Iread, or the read current is increased to become Iwrite, or a parallel current source is connected to VXSP to add to the Iread current source. At block 5, the sampled read voltage is bumped using Vbump driven into C2. The bump in voltage can be about half of the expected voltage difference between LRS and HRS (e.g., about 150mV). Fig.12 It shows how T19 can be used to bump the voltage via Vbump.

[0123] At block 7, the write current is disabled and the read current is enabled. The read current can be enabled by turning T1 on again (see Fig.11 ). At block 7, enable the VXSP connection again. Fig.12 , S1 is applied to T11 to connect the sense amplifier 806 to VXSP (note that capture is high at t7 and t8). At box 7, after the write current decreases to the read current, write reset discharge capacitor C3 is enabled. Fig.12 , making S5 at the gate of T27 high to connect C3 to VXSP. Therefore, C3 can accelerate the rate of discharge to VXSP to accelerate the rate at which the WL voltage drops after the current decreases from Iwrite to Iread.

[0124] Capture is high at blocks 7 and 8 and then low at block 9 before asserting the clock at block 9. Fig.12 , "Capture" is applied to T12 and T13 to reopen the sense amplifier for the signal. Therefore, T16 and T17 are connected to VXSP to sample the battery voltage. In addition, T16 and T17 are connected to the surge voltage from Read1 through T13. In one embodiment, Vref is removed because it is not used for SRR. Therefore, the voltage at the inverting input (+) can be compared with the surge voltage provided by T19. At box 9, the sense amplifier is clocked off. Reference Fig.12 , apply the clock to T21.

[0125] In some implementations, a capacitor in the sense amplifier is used during SRR read to charge the selected word line at the start of a destructive write. In one implementation, C4 is used as a write reset charging capacitor. Fig.16 is a table 1600 indicating the timing of signals in the sense amplifier 806 for an implementation of the SRR, where C4 is used as a write reset charge capacitor. In addition, similar to the example in table 1500, C1 is used as a snapback discharge capacitor and C3 is used as a write reset discharge capacitor. Therefore, many of the signals in table 1600 are similar to those in table 1500 and will not be discussed again. At box 4, the read current is disabled and the write current is enabled, similar to the discussion of table 1500. Between boxes 4 and 6, capture is low, which avoids pre-charge interference during write. Table 1600 shows that the capacitor can be pre-charged at t0. Referring to Fig.12 , the signal "precharge" applied to the gate of T22 can be used to precharge C4 to Vpcw. The precharging of C1, C2, and C3 has been described in conjunction with Table 1500. The size of capacitor C4 can be selected based on other capacitances in the circuit. For example, the size of capacitor C4 can be selected based on the capacitance along the read path. As an example, C4 can be between approximately 10% and 50% of C_CMOS+C_array. An exemplary range for C4 is between 100 and 200 femtofarads (fF). Table 1600 shows enabling a write reset charging capacitor C4 at box 4. Reference Fig.12 , signal S6 at the gate of T15 goes high to connect the write reset charging capacitor C4 to VXSP. Note that S1 is applied again to T11 at blocks 7 to 10 to connect the sense amplifier to VXSP. Also note that the capture Figure 8 Medium is high.

[0126] Fig.17A and Fig. 17B Further details of the timing signals during implementation of the SRR are depicted. Fig.17A Depicted are a read current 1702 provided to a selected WL between t1 and t4, a write current 1704 provided to a selected WL between t4 and t7, and a read current 1706 provided to a selected WL between t7 and t10. Fig. 17B The voltage on the selected WL is depicted. The voltage across the memory cell increases from t1 to ts. The threshold switch selector is turned off between t1 and ts. Between t1 and ts, the current causes the word line voltage to increase. This current also supports any leakage in the path. Once the voltage on the threshold switch selector reaches the threshold voltage V of the threshold switch selector 502 th , the threshold switch selector will be turned on and switched to a low resistance state (at ts). Once the threshold switch selector 502 is in the on state (at ts), the discharge current caused by the OTS turn-on and the read current (minus the leakage to the unselected cells) can flow through the selected memory cell 401. The WL voltage will drop to a level that depends on the series resistance of the memory element 702, the on-state resistance of the threshold switch selector 502 and the Voffset voltage, together with the address selection transistors and metal resistances in the read path. At t2, the snapback discharge capacitor C1 is connected to VXSP, which can accelerate the rate at which the word line drops to its stable value. If the memory cell is in the HRS state, the voltage drops to line 1710. If the memory cell is in the LRS state, the voltage drops to line 1712. Note that after the snapback discharge capacitor C1 is connected to VXSP at t2, the word line voltage drops very quickly and stabilizes to reduce the read delay. Additionally, the snapback discharge capacitor C1 may prevent the state of the memory cell from flipping before the cell is sensed by diverting some of the discharge current that would otherwise flow through the memory element 702 .

[0127] At t4, the current increases from Iread to Iwrite. To help speed up the rate at which the WL voltage increases in response to the increased current through the memory cell 401, a write reset charging capacitor C4 is connected to WL at t4 (and S2 remains using C4 during t4 to allow its effect on VXSP1, and). If the memory cell was already in HRS, the WL voltage may increase to a level of 1720. If the memory cell was initially in LRS, the WL voltage may increase to a level of 1722. The write current resets the memory cell to HRS so that the memory cell will end the write phase at a level of 1720 after LRS is written to HRS during this write. If initially in the HRS state, remain in HRS.

[0128] At t7, the current decreases from Iwrite to Iread. To help speed up the rate at which the WL voltage decreases in response to the decreasing current through the memory cell 401, the write reset discharge capacitor C3 is connected to WL at t7. The WL voltage decreases quickly to level 1730.

[0129] Fig.18 1 is a flow chart of one embodiment of a process 1800 for controlling a capacitor during an SRR to accelerate charging of a word line during a destructive write phase. Step 1802 includes precharging a write reset charging capacitor C4. In one embodiment, the write reset charging capacitor C4 is precharged to a charge assist voltage. As used throughout this document, the term "charge assist voltage" means a voltage on a capacitor that will enable the capacitor to transfer charge to a node (e.g., VXSP) to increase the voltage at the node. In one embodiment, the write reset charging capacitor C4 is precharged to Vp (see Fig.11 1804 includes increasing the current from Iread to Iwrite. Step 1806 includes connecting the write reset charging capacitor C4 to the selected WL to accelerate the rate at which the selected WL is charged. Step 1808 includes disconnecting the write reset charging capacitor C4 from the selected WL after the write is completed, thereby accelerating the decay of the WL to the read voltage level.

[0130] Fig.191 is a flow chart of one embodiment of a process 1900 for controlling capacitors during SRR to accelerate the discharge of word lines after a destructive write phase. Step 1902 includes precharging the write reset discharge capacitor C3. In one embodiment, the write reset discharge capacitor C3 is precharged to Vmid (or VPC). In another embodiment, the write reset discharge capacitor C3 is precharged to a voltage equal to or close to GND. The capacitor and precharge voltage are adjusted to ensure that the coupling voltage is not lower than the read Vfinal, because this can turn off OTS and require that WL be recharged to Vth before the Read2 voltage is sensed and compared with the adjusted Read1 voltage. Step 1904 includes reducing the current from Iwrite to Iread. Step 1906 includes connecting the write reset discharge capacitor C3 to the selected WL to accelerate the rate at which the selected WL is discharged. Step 1908 includes disconnecting the write reset discharge capacitor C3 from the selected WL. Step 1910 includes sensing the memory cell when the read current is driven through the memory cell.

[0131] The final stage of the SRR may include writing the memory cell to restore its original state in the case of a destructive write-altered state. This final stage may be referred to as write-set or write-back. The write-back stage may include increasing the current to the write current. In one embodiment, a capacitor in the sense amplifier 806 may be used to accelerate the rate at which the word line is charged toward GND during the write-back stage. In one embodiment, a capacitor in the sense amplifier 806 may be used to accelerate the rate at which the word line is discharged at the end of the write-back stage. Fig. 202000 is a table indicating the timing of signals in the sense amplifier 806 for an embodiment of the write back phase of the SRR. Table 2000 refers to a write setup charging capacitor (C5), which may be in one embodiment of the sense amplifier 806. The size of capacitor C5 may be selected based on other capacitances in the circuit. For example, the size of capacitor C5 may be selected based on the capacitance along the read path. As an example, C5 may be between about 10% and 50% of C_CMOS+C_array. An exemplary range of C5 is between 5 and 50 femtofarads (fF). At t0, C5 is precharged. In one embodiment, C5 is precharged to GND (because the write for mram is the reverse WL and BL direction from the destructive write reset). At box 11, capture is high. Between boxes 12 and 14, capture is low, which can avoid precharge interference during writing. At t12, the write setup current is enabled. The write setup current may have a polarity opposite to the write current in the destructive write. At t12, the VXSP connection is enabled by applying S1 to T11, as discussed previously. At t12, the write set charging capacitor C5 is enabled. In one embodiment, the write set charging capacitor C5 is added to the Fig.12 A sense amplifier 806 is provided at the gate of this transistor. A signal S7 may be applied at the gate of this transistor to connect the write setup charge capacitor to VXSN (using the n-ch path for write setup). Thus, the write setup discharge capacitor C5 may be used to speed up the rate at which WL is charged at the beginning of the write back phase. Another option is to add a write setup discharge capacitor to speed up the rate at which the word line is discharged at the end of the write back phase.

[0132] Fig.21 21 is a flow chart of an embodiment of a process 2100 of controlling capacitors to accelerate the charging of word lines during the write-back phase of the SRR. Step 2102 includes precharging the write-set charging capacitor C5. In one embodiment, the write-set charging capacitor C5 is precharged to Gnd. Step 2104 includes increasing the current to Iwrite. Step 2106 includes connecting the write-set discharge capacitor C5 to the selected WL to accelerate the rate at which the selected WL is charged. Step 2108 includes disconnecting the write-set discharge capacitor C5 from the selected WL. Step 2110 includes reducing the current after the write-back, such as to 0A. In other embodiments, these steps 2108 and 2110 are reversed or performed approximately simultaneously. Another option is to connect the write-set discharge capacitor to accelerate the rate at which the word lines are discharged at the end of the write-back phase. In another embodiment, a transistor that connects WL and BL (precharge) to Vmid (together with all other WLs and BLs if the cycle has ended) appears.

[0133] A cross-point memory array may have multiple levels (or layers). The WL and BL voltages may be different for the upper and lower layers. Therefore, modifications may be made to the various circuits depicted herein (eg, sense amplifier 806).

[0134] In view of the foregoing, it can be seen that, according to an embodiment, a device includes a sense amplifier having a plurality of capacitors. The device includes a control circuit that communicates with the array and with the plurality of capacitors. The control circuit is configured to be connected to an array including a plurality of first conductive lines, a plurality of second conductive lines, and a memory cell. Each memory cell resides at the intersection of a first conductive line and a second conductive line. Each memory cell includes a threshold switch selector connected in series with a memory element. The control circuit is configured to provide a signal to turn on the threshold switch selector of the selected memory cell during a read operation. The selected memory cell resides between the selected first conductive line and the selected second conductive line. The control circuit is configured to connect a first capacitor of the plurality of capacitors to the selected first conductive line after the threshold switch selector has been turned on to transfer charge between the selected first conductive line and the first capacitor when the voltage on the selected first conductive line changes. The control circuit is configured to control the sense amplifier to sense the selected memory cell during the read operation when the first capacitor is disconnected from the selected first conductive line.

[0135] In another embodiment, the control circuit is configured to connect the first capacitor to the selected first conductive line to accelerate the discharge of the selected first conductive line to a stable voltage after the threshold switch selector has been turned on. The control circuit is configured to control the sense amplifier to sense the selected memory cell when the selected first conductive line is at the stable voltage.

[0136] In another embodiment, the control circuit is configured to pre-charge the first capacitor to a pre-charge voltage, the magnitude of which is tuned to accelerate the discharge of the selected first conductive line to the regulated voltage after the threshold switch selector has been turned on.

[0137] In another embodiment, the control circuit is configured to disconnect the first capacitor from the selected first conductive line. The control circuit is configured to connect a second capacitor of the plurality of capacitors to the selected first conductive line. The first capacitor has a capacitance different from that of the second capacitor. The control circuit is configured to sense the selected memory cell through the second capacitor when the selected first conductive line is at a stable voltage and the first capacitor is disconnected from the selected first conductive line.

[0138] In another embodiment, the control circuit is configured to connect the second capacitor to the selected first conductive line while connecting the first capacitor to the first conductive line. The control circuit is configured to disconnect the first capacitor from the selected first conductive line while maintaining the second capacitor connected to the first conductive line.

[0139] In another embodiment, the control circuit is configured to precharge the first capacitor to a charge assist voltage before connecting the first capacitor to the selected first conductive line. The control circuit is configured to drive a write current to the selected first conductive line to write to the selected memory cell after turning on the threshold switch selector and after a first read of a self-referenced read of the selected memory cell during the read operation. The control circuit is configured to connect the first capacitor to the selected first conductive line to accelerate charging of the selected first conductive line in response to the write current.

[0140] In another embodiment, the control circuit is configured to drive a current having a write magnitude to the selected first conductive line to charge the selected first conductive line to write the selected memory cell after a first read of the self-referenced read of the selected memory cell during the read operation. The control circuit is configured to reduce the current driven to the selected first conductive line to the read magnitude after writing the selected memory cell. The control circuit is configured to connect the first capacitor to accelerate the discharge of the selected first conductive line after reducing the current to the read magnitude.

[0141] In another embodiment, the control circuit is configured to pre-charge the first capacitor to a voltage that is tuned to accelerate the discharge of the selected first conductive line after the current decreases to the read magnitude.

[0142] In another embodiment, the control circuit is configured to precharge the first capacitor to a charge assist voltage before connecting the first capacitor to the selected first conductive line. The control circuit is configured to drive a write current to the selected first conductive line to write to the selected memory cell during a write-back phase of a self-referenced read of the read operation. The control circuit is configured to connect the first capacitor to the selected first conductive line to accelerate charging of the selected first conductive line during the write-back phase.

[0143] In another embodiment, the device includes the array. The threshold switch selector includes an unidirectional threshold switch (OTS). The memory element includes a magnetoresistive random access memory (MRAM) element.

[0144] One embodiment includes a method for reading a selected memory cell in a cross-point array. The method includes applying a selection voltage to a selected bit line in the cross-point array. The method includes driving a current to a selected word line in the cross-point array to charge the voltage on the selected word line. The selected memory cell resides between the selected bit line and the selected word line. The selected memory cell includes a threshold switch selector connected in series with a memory element. The method includes connecting a first capacitor in a sense amplifier to the selected word line after the threshold switch selector has been turned on to accelerate the discharge of the selected word line toward a stable voltage while driving the current through a path including the selected word line, the selected memory cell, and the selected bit line. The method includes disconnecting the first capacitor from the selected word line. The method includes sensing the selected memory cell through the sense amplifier when the selected word line is at the stable voltage while continuing to drive the current through the path when the first capacitor is disconnected from the selected word line.

[0145] One embodiment includes a memory system including a cross-point array including a word line, a bit line, and a programmable resistance memory cell. Each memory cell resides at the intersection of a word line and a bit line. Each memory cell includes a threshold switch selector connected in series with a programmable resistance memory element. The threshold switch selector has a high resistance in an off state and a low resistance in an on state. The memory system includes one or more sense amplifiers coupled to the cross-point array. Each sense amplifier includes one or more capacitors. The memory system includes a control circuit that communicates with the array and the sense amplifier. The control circuit is configured to apply a selection voltage to a selected bit line in the cross-point array. The selected memory cell resides between the selected bit line and the selected word line on a read path, the read path including a sense node, a selected word line, a selected memory cell, and a selected bit line. The control circuit is configured to drive a current to the selected word line to charge the voltage on the sense node to turn on the threshold switch selector of the selected memory cell. The control circuit is configured to connect a first capacitor in a first sense amplifier of the one or more sense amplifiers to the sense node after the threshold switch selector has been turned on to accelerate the discharge of the sense node toward a stable voltage. The control circuit is configured to disconnect the first capacitor from the sense node. The control circuit is configured to control the first sense amplifier to sense the voltage on the sense node when the sense node is at the stable voltage and when the read current is driven through the read path when the first capacitor is disconnected from the sense node. The control circuit may be configured to connect the first capacitor to the sense node and then disconnect the capacitor after its voltage is almost equal to the sense node. The disconnected voltage may be raised by a voltage and used as a reference to be compared by the sense amplifier with another read voltage on the sense node after a destructive write.

[0146] For the purposes of this document, references in the specification to "an embodiment," "one embodiment," "some embodiments," or "another embodiment" may be used to describe different embodiments or the same embodiment.

[0147] For the purposes of this document, a connection may be a direct connection or an indirect connection (e.g., via one or more other components). In some cases, when an element is referred to as being connected or coupled to another element, the element may be directly connected to the other element, or indirectly connected to the other element via an intervening element. When an element is referred to as being directly connected to another element, there are no intervening elements between the element and the other element. Two devices are "in communication" if they are directly connected or indirectly connected, such that they are able to communicate electronic signals between them.

[0148] For the purposes of this document, the term "based on" may be understood as "based, at least in part, on."

[0149] For the purposes of this document, the use of numerical terms such as a "first" object, a "second" object, and a "third" object without additional context may not imply an ordering of the objects, but may be used for identification purposes to identify different objects.

[0150] The terms "top" and "bottom", "upper" and "lower", and "vertical" and "horizontal", and forms thereof, as used herein, are used herein by way of example only and for illustrative purposes, and are not intended to limit the description of the technology, as the referenced items may be interchanged in position and orientation. Additionally, as used herein, the terms "substantially" and / or "approximately" mean that a specified dimension or parameter may vary within an acceptable tolerance for a given application.

[0151] The above detailed description has been provided for the purpose of illustration and description. It is not intended to be exhaustive or to limit the precise form disclosed by the invention. Many modifications and variations are possible in light of the above teachings. The described embodiments are selected to best explain the principles of the proposed technology and its practical application, thereby enabling others skilled in the art to best utilize it in various embodiments and in various modifications suitable for the specific use contemplated. The scope of the invention is intended to be defined by the appended claims.

Claims

1. A device, comprising: a sense amplifier having a plurality of capacitors; and a control circuit configured to be connected to an array including a plurality of first conductive lines, a plurality of second conductive lines, and memory cells, wherein each memory cell resides at an intersection of the first conductive line and the second conductive line, wherein each memory cell includes a threshold switch selector connected in series with a memory element, the control circuit being in communication with the array and with the plurality of capacitors, the control circuit being configured to: providing a signal to turn on the threshold switch selector of a selected memory cell during a read operation, wherein the selected memory cell resides between a selected first conductive line and a selected second conductive line; connecting a first capacitor of the plurality of capacitors to a selected first conductive line after the threshold switch selector has been turned on to transfer charge between the selected first conductive line and the first capacitor when a voltage on the selected first conductive line changes; as well as During the read operation, when the first capacitor is disconnected from the selected first conductive line, the sense amplifier is controlled to sense the selected memory cell.

2. The apparatus according to claim 1, wherein the control circuit is configured to: connecting the first capacitor to the selected first conductive line to accelerate the discharge of the selected first conductive line to a stable voltage after the threshold switch selector has been turned on; and The sense amplifier is controlled to sense the selected memory cell when the selected first conductive line is at the stable voltage.

3. The apparatus according to claim 2, wherein the control circuit is configured to: The first capacitor is pre-charged to a pre-charge voltage whose magnitude is tuned to accelerate the discharge of the selected first conductive line to the regulated voltage after the threshold switch selector has been closed.

4. The apparatus according to claim 1, wherein the control circuit is configured to: disconnecting the first capacitor from the selected first conductive line; connecting a second capacitor of the plurality of capacitors to the selected first conductive line, wherein the first capacitor has a different capacitance than the second capacitor; and When the selected first conductive line is at a stable voltage and the first capacitor is disconnected from the selected first conductive line, the selected memory cell is sensed through the second capacitor.

5. The apparatus of claim 4, wherein the control circuit is configured to: While connecting the first capacitor to the first conductive line, connecting the second capacitor to the selected first conductive line; and The first capacitor is disconnected from the selected first conductive line while maintaining the second capacitor connected to the first conductive line.

6. The apparatus of claim 1 , wherein the control circuit is configured to: precharging the first capacitor to a charge assist voltage before connecting the first capacitor to the selected first conductive line; driving a write current to the selected first conductive line to write to the selected memory cell after turning on the threshold switch selector and after a first read of a self-referenced read of the selected memory cell during the read operation; as well as The first capacitor is connected to the selected first conductive line to accelerate charging of the selected first conductive line in response to the write current.

7. The apparatus of claim 1 , wherein the control circuit is configured to: driving a current having a write magnitude to the selected first conductive line to charge the selected first conductive line to write the selected memory cell after a first read of the selected memory cell during the read operation from the referenced read; reducing the current driven to the selected first conductive line to a read value after writing the selected memory cell; as well as The first capacitor is connected after reducing the current to the read value to accelerate the discharge of the selected first conductive line.

8. The apparatus of claim 7, wherein the control circuit is configured to: The first capacitor is pre-charged to a voltage tuned to accelerate the discharge of the selected first conductive line after the current decreases to the read magnitude.

9. The apparatus of claim 1 , wherein the control circuit is configured to: precharging the first capacitor to a charge assist voltage before connecting the first capacitor to the selected first conductive line; driving a write current to the selected first conductive line to write to the selected memory cell during a write-back phase of a self-referenced read of the read operation; as well as The first capacitor is connected to the selected first conductive line to accelerate charging of the selected first conductive line during the write-back phase.

10. The device according to claim 1, wherein: The device comprises the array; The threshold switch selector comprises a two-way threshold switch (OTS); and The memory element includes a magnetoresistive random access memory (MRAM) element.

11. A method for reading a selected memory cell in a cross-point array, the method comprising: applying a select voltage to a selected bit line in the cross-point array; driving a current into a selected word line in the cross-point array to charge a voltage on the selected word line, wherein a selected memory cell resides between a selected bit line and the selected word line, wherein the selected memory cell includes a threshold switch selector in series with a memory element; connecting a first capacitor in a sense amplifier to a selected word line after the threshold switch selector has been turned on to accelerate discharge of the selected word line toward a stable voltage while driving the current through a path including the selected word line, the selected memory cell, and the selected bit line; disconnecting the first capacitor from the selected word line; as well as The selected memory cell is sensed by the sense amplifier when the selected word line is at the stable voltage while continuing to drive the current through the path with the first capacitor disconnected from the selected word line.

12. The method according to claim 11, further comprising: The first capacitor is precharged to a precharge voltage whose magnitude is tuned to accelerate the discharge of the selected word line to the regulated voltage after the threshold switch selector has been turned on.

13. The method according to claim 11, further comprising: performing a destructive write of the selected memory cell after sensing the selected memory cell, including driving a write current through the path; After performing the destructive writing, reducing the current through the path from the write current to a read current; as well as A second capacitor is connected to the selected word line when the current through the path is at the read current to accelerate the discharge of the voltage on the selected word line in response to a decrease in the current through the path.

14. The method according to claim 13, further comprising: disconnecting the second capacitor from the selected word line; as well as While the read current continues to be driven through the path and the second capacitor is disconnected from the selected word line, the selected memory cell is sensed through the third capacitor.

15. A memory system, comprising: a cross-point array comprising word lines, bit lines, and programmable resistance memory cells, wherein each memory cell resides at an intersection of a word line and a bit line, wherein each memory cell comprises a threshold switch selector connected in series with the programmable resistance memory element, wherein the threshold switch selector has a high resistance in an off state and a low resistance in an on state; one or more sense amplifiers coupled to the cross-point array, wherein each sense amplifier includes one or more capacitors; and a control circuit in communication with the array and the one or more sense amplifiers, the control circuit being configured to: applying a select voltage to a selected bit line in the cross-point array, wherein a selected memory cell resides between the selected bit line and a selected word line on a read path including a sense node, the selected word line, the selected memory cell, and the selected bit line; driving a current to the selected word line to charge a voltage on the sense node to turn on the threshold switch selector of the selected memory cell; connecting a first capacitor in a first sense amplifier of the one or more sense amplifiers to the sense node after the threshold switch selector has been turned on to accelerate discharge of the sense node toward a stable voltage; disconnecting the first capacitor from the sensing node; as well as The first sense amplifier is controlled to sense a voltage on the sense node when the sense node is at the stable voltage and when a read current is driven through the read path with the first capacitor disconnected from the sense node.

16. The memory system of claim 15, wherein the control circuit is further configured to: The first capacitor is pre-charged to a pre-charge voltage whose magnitude is tuned to accelerate discharge of the sense node after the threshold switch selector has been turned on.

17. The memory system of claim 15, wherein the control circuit is further configured to: sensing the selected memory cell through a second capacitor in the first sense amplifier when the sense node is at the stable voltage; performing a destructive write of the selected memory cell after sensing the selected memory cell through the second capacitor, including driving a write current through the read path; reducing the current to the read path to a read current after performing the destructive write; as well as A third capacitor of the first sense amplifier is connected to the sense node when the current is at the read current to accelerate the discharge of the voltage on the sense node in response to the decrease in the current.

18. The memory system of claim 17, wherein the control circuit is further configured to: The third capacitor is precharged to a precharge voltage whose magnitude is tuned to accelerate discharge of the sense node in response to the reduction in the current.

19. The memory system of claim 17, wherein the control circuit is further configured to: precharging a fourth capacitor of the first sense amplifier to a charge auxiliary voltage; increasing the current to the read path from a read current to a write current after sensing the selected memory cell through the second capacitor; and The fourth capacitor is connected to the sense node when the current is at the write current to accelerate the charging of the voltage on the sense node.

20. The memory system of claim 15, wherein the control circuit is further configured to: disconnecting the first capacitor from the sensing node after the voltage on the first capacitor is almost equal to the voltage at the sensing node; adjusting the voltage on the first capacitor by boosting the voltage; as well as The burst voltage on the first capacitor is used as a reference voltage for comparison with another read voltage of the selected memory cell on the sense node after destructive writing of the selected memory cell.

Images