Chip Fault Detection Method

Abstract

The present invention provides a chip fault detection method, comprising: performing a write 0 operation on all sub-units according to a preset address sequence; performing a read 0 operation on all sub-units according to a preset address sequence, performing a write positive checkerboard data operation twice on all sub-units according to a preset address sequence, performing a read positive checkerboard data operation twice on all sub-units according to a preset address sequence, performing a write reverse checkerboard data operation twice on all sub-units according to a preset address sequence, performing a read reverse checkerboard data operation twice on all sub-units according to a preset address sequence, performing a write 1 operation on all sub-units according to a preset address sequence, performing a read 1 operation twice on all sub-units according to a preset address sequence, performing a write positive checkerboard data operation on all sub-units according to a preset address sequence, performing a read positive checkerboard data operation on all sub-units according to a preset address sequence, the detection coverage rate of coupled write type faults reaches 100%, and the complexity is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a chip fault detection method. Background Art

[0002] The coupled write fault of static random-access memory (SRAM) refers to a double-cell fault, that is, an operation on one storage cell causes the value of another cell to change. The coupled write fault includes a total of 12 fault types.

[0003] Currently, in the detection of coupled write faults of SRAM, checkerboard and March algorithms are usually used to detect coupled write faults of SRAM, wherein the March algorithm includes the March C+ algorithm and the March C+ modified algorithm.

[0004] However, for the detection of 12 coupled write faults, the chessboard is read only after the chessboard data of 10 / 01 is written in the preset address sequence, that is, the same data cannot be written to the background data, and other fault sensitization sequences that can trigger coupled write faults cannot be provided, resulting in the inability to detect 12 coupled write faults, and the fault detection coverage of coupled write faults is 0%. The March C+ algorithm lacks the step of writing the same data to the background data, such as reading 0 and writing 0, and can only provide fault sensitization sequences (1w0, 1) or (0w1, 0), resulting in the March C+ algorithm being able to detect only 4 coupled write faults, and the fault detection coverage of coupled write faults is only 33%, that is, the use of the March C+ algorithm for coupled write fault detection has the problem of low fault detection coverage of coupled write faults. Although the March C+ modified algorithm can achieve 100% fault detection coverage for coupled write type faults, the complexity of the March C+ modified algorithm is 22N (22N can be understood as 22 read and write operations need to be performed on all sub-units), and the complexity is relatively high. As a result, the use of the MarchC+ modified algorithm for coupled write type fault detection has the problem of high detection time cost and low detection efficiency for coupled write type faults.

[0005] In view of this, how to improve the coverage of coupled write-type fault testing, shorten the testing time cost, and improve the testing efficiency is a technical problem that technical personnel in this field urgently need to solve. Summary of the invention

[0006] The present invention provides a chip fault detection method, which can solve the problem of high detection time cost and low detection efficiency of coupled write type faults when using March C+ modified algorithm for coupled write type fault detection.

[0007] The present invention provides a chip fault detection method, the chip includes several sub-units, and the method includes:

[0008] Perform a write-0 operation on all sub-units in a preset address order;

[0009] Performing a read 0 operation on all sub-units according to the preset address sequence, performing a write positive checkerboard data operation twice on all sub-units according to the preset address sequence, and performing a read positive checkerboard data operation on all sub-units according to the preset address sequence;

[0010] Performing a read operation on the positive checkerboard data on all sub-units according to the preset address sequence, performing a write operation on the reverse checkerboard data twice on all sub-units according to the preset address sequence, and performing a read operation on the reverse checkerboard data on all sub-units according to the preset address sequence;

[0011] Performing a read reverse checkerboard data operation on all sub-units according to the preset address sequence, performing a write 1 operation on all sub-units according to the preset address sequence, and performing a read 1 operation on all sub-units according to the preset address sequence;

[0012] A read 1 operation is performed on all sub-units according to the preset address sequence, a write positive checkerboard data operation is performed on all sub-units according to the preset address sequence, and a read positive checkerboard data operation is performed on all sub-units according to the preset address sequence.

[0013] Optionally, the preset address sequence is a sequence from low address to high address or a sequence from high address to low address.

[0014] Optionally, performing a write-0 operation on all sub-units in a preset address sequence includes:

[0015] A reset voltage is applied to all sub-units according to the preset address sequence, so that all sub-units perform a write-0 operation.

[0016] Optionally, performing a read 0 operation on all sub-units according to the preset address sequence includes:

[0017] Reading the voltages of the subunits in sequence according to the preset addresses;

[0018] When the voltage is the reset voltage, a read 0 operation is performed on the sub-unit.

[0019] Optionally, performing a checkerboard data read operation on all sub-units according to the preset address sequence includes:

[0020] Reading the voltages of the subunits in sequence according to the preset addresses;

[0021] When the voltage is a set voltage, a read 1 operation is performed on the sub-unit;

[0022] When the voltage is the reset voltage, a read 0 operation is performed on the sub-unit.

[0023] Optionally, performing a read-inverse checkerboard data operation on all sub-units according to the preset address sequence includes:

[0024] Reading the voltages of the subunits in sequence according to the preset addresses;

[0025] When the voltage is the reset voltage, a read 0 operation is performed on the sub-unit;

[0026] When the voltage is the set voltage, a read 1 operation is performed on the sub-unit.

[0027] Optionally, performing a write 1 operation on all sub-units according to the preset address sequence includes:

[0028] The set voltage is applied to all sub-units according to the preset address sequence, so that all sub-units perform a write 1 operation.

[0029] Optionally, performing a read 1 operation on all sub-units according to the preset address sequence includes:

[0030] When the voltage is the set voltage, a read 1 operation is performed on the sub-unit.

[0031] Furthermore, the method further comprises:

[0032] After each data read operation is performed, the read voltage is compared with the preset voltage to obtain a fault detection result of the memory.

[0033] Optionally, in the positive checkerboard data, the voltage of the first sub-unit to be written is applied as a set voltage;

[0034] In the inverse checkerboard data, the voltage of the first sub-unit to be written is applied as a reset voltage.

[0035] In the embodiment of the present invention, 12 fault sensitization sequences of coupled write type faults can be generated, and then through the generated 12 fault sensitization sequences of coupled write type faults, comprehensive detection of 12 coupled write type faults is achieved, and the fault detection coverage of coupled write type faults reaches 100%, which solves the problem of low fault detection coverage of coupled write type faults when using March C+ algorithm for coupled write type fault detection; and, if the fault detection coverage of coupled write type faults is to reach 100%, the complexity of March C+ modified algorithm is 22N, while the complexity of the fault detection method of the chip provided by the embodiment of the present invention is 15N, that is, the complexity of the fault detection method of the chip provided by the embodiment of the present invention is less than the complexity of March C+ modified algorithm, which shortens the fault detection time of coupled write type faults, reduces the detection cost of fault detection of coupled write type faults, improves the detection efficiency of fault detection of coupled write type faults, and solves the problem of high detection time cost and low detection efficiency of coupled write type faults when using March C+ modified algorithm for coupled write type fault detection. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0037] Figure 1 It is a flowchart of a chip fault detection method provided by an embodiment of the present invention;

[0038] Figure 2 It is a schematic diagram of the state after all sub-units are written to 0 in the chip fault detection method provided by an embodiment of the present invention;

[0039] Figure 3 is a schematic diagram of the positive chessboard data provided by an embodiment of the present invention;

[0040] Figure 4 It is a schematic diagram of the state change of all sub-units after the first write operation of the positive checkerboard data is executed in the chip fault detection method provided by the embodiment of the present invention;

[0041] Figure 5 It is a schematic diagram of the state change of all sub-units after the second write operation of the positive checkerboard data is performed in the chip fault detection method provided by the embodiment of the present invention;

[0042] Figure 6 is a schematic diagram of inverse chessboard data provided by an embodiment of the present invention;

[0043] Figure 7 It is a schematic diagram of the state change of all sub-units after the first reverse checkerboard data writing operation is performed in the chip fault detection method provided by the embodiment of the present invention;

[0044] Figure 8 It is a schematic diagram of the state change of all sub-units after the second reverse checkerboard data writing operation is performed in the chip fault detection method provided by the embodiment of the present invention;

[0045] Fig. 9 It is a schematic diagram of the state change after all sub-units are subjected to a write 1 operation in the chip fault detection method provided by an embodiment of the present invention;

[0046] Fig.10 It is a schematic diagram of the state change of all sub-units after the third write checkerboard data operation is performed in the chip fault detection method provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0047] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0048] The terms "including" and "having" and any variations thereof in the specification and claims of the present invention and the above-mentioned drawings are intended to cover non-exclusive inclusions. For example, a process, method, system, product or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products or apparatuses.

[0049] The technical solution of the present invention is described in detail with specific embodiments below. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0050] Figure 1 The present invention provides a flow chart of a chip fault detection method according to an embodiment of the present invention. The chip includes several sub-units. As an implementation method, the chip may be a memory, such as a static random access memory (SRAM), etc., and the sub-unit is a storage unit. Figure 1 , the method may specifically include the following steps:

[0051] Step 101, performing a write-0 operation on all sub-units according to a preset address sequence.

[0052] Among them, the address sequence can be understood as the logical address sequence of each sub-unit of the chip, and the preset address sequence can be understood as the preset logical address sequence of the sub-units that perform read and write operations on all sub-units; the preset address sequence can be the sequence from low address to high address / the sequence from high address to low address, the sequence from low address to high address can be understood as the logical address sequence of increasing address, and the sequence from high address to low address can be understood as the logical address sequence of decreasing address; if the preset address sequence in step 101 is the sequence from low address to high address, then the preset address sequence in all subsequent steps is the sequence from low address to high address, and if the preset address sequence in step 101 is the sequence from high address to low address, then the preset address sequence in all subsequent steps is the sequence from high address to low address. Since the logical address sequence of the chip can be from low address to high address or from high address to low address, in an optional implementation, if the logical address sequence of the chip is from low address to high address, the preset address sequence is from low address to high address, and the preset address sequence in all subsequent steps is from low address to high address; if the logical address sequence of the chip is from high address to low address, the preset address sequence is from high address to low address, and the preset address sequence in all subsequent steps is from high address to low address. Coupling faults are usually double-unit faults, and the probability of coupling faults in two adjacent sub-units is higher than that in any two sub-units, so increasing or decreasing the address sequence can achieve higher test efficiency.

[0053] In an optional implementation, a reset voltage may be applied to all sub-units in a preset address sequence so that all sub-units perform a write-0 operation; if the reset voltage is defined as a write-0 operation, all reset voltages in subsequent steps are write-0 operations.

[0054] For example, assuming that the chip includes 16 sub-units, a reset voltage is applied to all sub-units in order from low address to high address, so that all sub-units perform a write-0 operation. The states of the sub-units of the chip are as follows: Figure 2 As shown, Figure 2 The x in the numeral y can be understood as a row identifier, and the y can be understood as a column identifier. For example, (00, 01) is the subunit of the first row and the second column.

[0055] Step 102, performing a read 0 operation on all sub-units according to a preset address sequence, performing a write positive checkerboard data operation twice on all sub-units according to a preset address sequence, and performing a read positive checkerboard data operation on all sub-units according to a preset address sequence.

[0056] Among them, the positive checkerboard data can be understood as a digital string starting with 1 and alternately set with 1 and 0, such as Figure 3 As shown, it is a schematic diagram of the positive chessboard data. Figure 3 It can be seen that the states of all sub-units are alternating between 1 and 0. In the positive checkerboard data, the voltage of the first sub-unit to be written is applied as a set voltage, corresponding to the writing of 1; the voltage of the second sub-unit to be written is applied as a reset voltage, corresponding to the writing of 0; and so on, to achieve the positive checkerboard data with alternating settings of 1 and 0, the number of digits included in the digital string is determined by the capacity of the chip storage unit.

[0057] In an optional implementation, the voltage of the sub-unit can be read in a preset address sequence, and when the voltage of the read sub-unit is a reset voltage, a read 0 operation is performed on the sub-unit; then, the set voltage and the reset voltage can be applied alternately to all sub-units in a preset address sequence, so that all sub-units alternately perform write 1 operations and write 0 operations, and then the set voltage and the reset voltage are applied alternately to all sub-units in a preset address sequence, so that all sub-units alternately perform write 1 operations and write 0 operations, thereby completing two write operations of positive checkerboard data on all sub-units in a preset address sequence; finally, the voltage of the sub-unit can be read in a preset address sequence, and when the voltage of the read sub-unit is a set voltage, a read 1 operation is performed on the sub-unit, and when the voltage of the read sub-unit is a reset voltage, a read 0 operation is performed on the sub-unit.

[0058] Through the operation of reading 0 in step 102, it can be confirmed whether the chip is successfully written with 0. If the chip is not successfully written with 0, the write 0 operation is performed on all sub-units again in the preset address sequence to ensure that the chip is successfully written with 0; if the chip is successfully written with 0, the write positive checkerboard data operation is performed twice on all sub-units in the preset address sequence.

[0059] Through the operation of reading the positive checkerboard data in step 102, it can be confirmed whether the chip is successfully written with the positive checkerboard data and the fault sensitization sequence can be read out. If the chip is not successfully written with the positive checkerboard data, the operation of writing the positive checkerboard data is performed twice on all sub-units in a preset address sequence to ensure that the chip is successfully written with the positive checkerboard data; if the chip is successfully written with the positive checkerboard data, the operation of reading the positive checkerboard data is performed on all sub-units in a preset address sequence to ensure that the positive checkerboard data written into the chip is not rewritten when the reverse checkerboard writing operation in step 103 is performed.

[0060] For example, the voltage of each sub-unit can be read in order from the low address to the high address. When the voltage of the sub-unit read is the reset voltage, a read 0 operation is performed on the sub-unit; then Figure 2In order from low address to high address, set voltage and reset voltage are applied alternately to all sub-units, so that all sub-units perform write 1 operation and write 0 operation alternately, and the first write operation of positive checkerboard data is completed for all sub-units. The state changes of each sub-unit of the chip are as follows: Figure 4 As shown; then, set voltage and reset voltage are alternately applied to all sub-units in the order from low address to high address, so that all sub-units perform write 1 operation and write 0 operation alternately, and the second write operation of positive checkerboard data is completed on all sub-units. The state changes of each sub-unit of the chip are as shown Figure 5 shown.

[0061] Table 1 Execution operations, sensitization sequences, and triggered fault types corresponding to subunits

[0062]

[0063] Table 1 shows the execution operations, fault sensitization sequences, and triggered fault types corresponding to the subunits provided in the embodiment of the present invention. The execution operations in Table 1 can be understood as the operations that each fault detection method needs to perform on the same chip (the same chip can be understood as the same operation unit). r0 represents a read 0 operation, r1 represents a read 1 operation, w0 represents a write 0 operation, w1 represents a write 1 operation, r10 represents a read positive checkerboard data operation, r01 represents a read negative checkerboard data operation, w10 represents a write positive checkerboard data operation, and w01 represents a write negative checkerboard data operation.

[0064] As an example, from Figure 4 It can be seen that when writing 0 to the subunit (01, 00), the state of the adjacent subunit (01, 01) is 0, and a fault sensitization sequence (0w0; 0) is generated. If the adjacent subunit (01, 01) has an interference coupling write-invariant fault <0w0; 0 / ↑ / ->, after executing the execution operation corresponding to the subunit (01, 00) in Table 1, when writing 0 to the subunit (01, 00), due to the existence of the fault sensitization sequence (0w0; 0), the state of the subunit (01, 01) changes at the same time, and the fault <0w0; 0 / ↑ / -> is triggered at this time, and the fault can be detected in the reading of the subunit (01, 01) data. Figure 5 It can be seen that when there is an interference coupling write-invariant fault <1w1; 0 / ↑ / ->, after performing the operation corresponding to the subunit (00, 00) in Table 1 on the subunit (00, 00), Figure 5It can be seen that when writing 1 to the sub-unit (00, 00), the state of the adjacent sub-unit (00, 01) is 0, and a fault sensitization sequence (1w1; 0) will be generated. If the state of the adjacent sub-unit (00, 01) changes from 0 to 1, the fault <1w1; 0 / ↑ / -> is triggered, and the fault can be detected in the data of the sub-unit (00, 01). This scheme is to perform the read 0 operation on the sub-unit, write the sub-unit twice, and read the sub-unit data in sequence. The corresponding execution operation is ↑(r0, w10, w10, r10), which can diagnose whether this fault exists. The diagnosis of other fault types is similar. For details, see Table 1 for the faults and fault sensitization sequences corresponding to the same operation, which will not be repeated here.

[0065] From step 101 to step 102, by generating 7 fault sensitization sequences of coupled write-type faults: (0w0; 0), (0; 0w0), (0w1; 0), (0w0; 1), (1w1; 0), (0; 1w1), (1; 0w0), 7 coupled write-type faults are detected. At this time, the fault detection coverage of the fault detection method of the chip provided by the embodiment of the present invention reaches 7 / 12≈58%; the execution operations in step 101 to step 102 include: w0, r0, w10, w10, r10, and the total number of execution operations in step 101 to step 102 is 5, then the complexity of step 101 to step 102 of the fault detection algorithm of the chip provided by the embodiment of the present invention is 5N.

[0066] Step 103, read the positive checkerboard data operation on all sub-units according to the preset address sequence, write the reverse checkerboard data operation twice on all sub-units according to the preset address sequence, and read the reverse checkerboard data operation on all sub-units according to the preset address sequence.

[0067] Among them, the anti-checkerboard data can be understood as a digital string starting with 0 and alternately set with 0 and 1, such as Figure 6 As shown, it is a schematic diagram of the reverse chessboard data. Figure 6 It can be seen that the states of all sub-cells are alternately 0 and 1. In the inverse checkerboard data, the voltage of the first sub-cell to be written is applied as a reset voltage.

[0068] In an optional implementation, a reset voltage and a set voltage may be applied alternately to all sub-units in a preset address sequence, so that all sub-units perform a write 0 operation and a write 1 operation alternately, and then a reset voltage and a set voltage may be applied alternately to all sub-units in a preset address sequence, so that all sub-units perform a write 0 operation and a write 1 operation alternately, thereby completing the operation of writing reverse checkerboard data twice to all sub-units in a preset address sequence. The voltage of the sub-unit is read in a preset address sequence, and when the voltage is a reset voltage, a read 0 operation is performed on the sub-unit, and when the voltage is a set voltage, a read 1 operation is performed on the sub-unit, thereby completing the operation of reading reverse checkerboard data to all sub-units in a preset address sequence.

[0069] Through the operation of reading the positive checkerboard data in step 103, it can be confirmed whether the positive checkerboard data written into the chip has been rewritten; if the positive checkerboard data written into the chip has not been rewritten, the operation of writing the negative checkerboard data is performed twice on all sub-units according to the preset address sequence; if the positive checkerboard data written into the chip has been rewritten, it is triggered to execute the operation of writing the positive checkerboard data twice on all sub-units according to the preset address sequence.

[0070] Through the operation of reading the reverse checkerboard data in step 103, it can be confirmed whether the chip is successfully written with the reverse checkerboard data and the fault sensitization sequence can be read out. If the chip is not successfully written with the reverse checkerboard data, the reverse checkerboard data writing operation is performed twice on all sub-units in a preset address sequence to ensure that the chip is successfully written with the reverse checkerboard data; if the chip is successfully written with the reverse checkerboard data, the reverse checkerboard data reading operation is performed on all sub-units in a preset address sequence to ensure that the reverse checkerboard data written into the chip is not rewritten when the write 1 operation in step 104 is performed.

[0071] For example, Figure 5 All sub-units in the chip are reset and set in sequence from low address to high address, so that all sub-units perform write 0 and write 1 operations alternately, completing the first write operation of anti-checkerboard data to all sub-units. The state changes of each sub-unit of the chip are as follows: Figure 7 As shown; then, the reset voltage and the set voltage are applied alternately to all sub-units in the order from low address to high address, so that all sub-units perform write 0 operation and write 1 operation alternately, completing the second write operation of anti-checkerboard data to all sub-units. The state changes of each sub-unit of the chip are shown as follows Figure 8 As shown in Table 1, through step 103, through Figure 7 and Figure 8The three fault sensitization sequences of coupled write type faults are generated: (1w0; 0), (0w1; 1), and (1w1; 1), which realize the detection of three coupled write type faults. There are 12 types of coupled write type faults in total. Since seven fault sensitization sequences are generated in step 102 and three fault sensitization sequences are generated in step 103, at this time, the fault detection coverage of the fault detection method of the chip provided by the embodiment of the present invention reaches (7+3) / 12≈83%; the complexity of chip fault detection can be understood as the total number of all operations performed on all sub-units. The execution operations in step 101 to step 103 of the chip fault detection algorithm provided by the embodiment of the present invention include: w0, r0, w10, w10, r10, r10, w01, w01, r01; then the total number of execution operations in step 101 to step 103 is 9, and the complexity of steps 101 to step 103 of the chip fault detection algorithm provided by the embodiment of the present invention is 9N, and the March C+ algorithm can only cover interference-coupled write-variable faults, that is, compared with the March C+ algorithm, under the same complexity, the fault detection coverage of the chip fault detection method provided by the embodiment of the present invention is also much greater than the fault detection coverage of the March C+ algorithm.

[0072] Step 104 , performing a read reverse checkerboard data operation on all sub-units according to a preset address sequence, performing a write 1 operation on all sub-units according to a preset address sequence, and performing a read 1 operation on all sub-units according to a preset address sequence.

[0073] In an optional implementation, a set voltage is applied to all sub-units in a preset address sequence so that all sub-units perform a write 1 operation, and then the voltage of the sub-unit is read in a preset address sequence, and when the voltage is the set voltage, a read 10 operation is performed on the sub-unit. If the set voltage is defined as a write 1 operation, all set voltages in subsequent steps are write 1 operations.

[0074] Through the anti-checkerboard data reading operation in step 104, it can be confirmed whether the anti-checkerboard data written into the chip has been rewritten; if the anti-checkerboard data written into the chip has not been rewritten, a write 1 operation is performed on all sub-units in a preset address sequence; if the anti-checkerboard data written into the chip has been rewritten, a trigger is executed to execute two write anti-checkerboard data operations on all sub-units in a preset address sequence.

[0075] Through the read 1 operation in step 104, it can be confirmed whether the chip is successfully written with 1 and the fault sensitization sequence can be read out. If the chip is not successfully written with 1, the write 1 operation is performed on all sub-units again according to the preset address sequence to ensure that the chip is successfully written with 1; if the chip is successfully written with 1, the read 1 operation is performed on all sub-units according to the preset address sequence to ensure that the 1 written into the chip is not rewritten when the write positive checkerboard data operation is performed in step 105.

[0076] For example, Figure 8 All sub-units of the chip apply set voltages in order from low address to high address, so that all sub-units perform write 1 operations. The state changes of each sub-unit of the chip are as follows: Fig. 9 As an example, when there is a coupled write corruption fault <1; 1w1 / ↓ / ->, after performing the operation corresponding to the subunit (00, 11) in Table 1 on the subunit (00, 11), Fig. 9 It can be seen that when 1 is written to the sub-unit (00, 11), the state of the adjacent sub-unit (01, 00) is 1, and a fault sensitization sequence (1; 1w1) will be generated. If the state of the sub-unit (00, 11) changes from 1 to 0, the fault <1; 1w1 / ↓ / -> is triggered. In this way, the detection of a coupled write type fault can be achieved by generating a fault sensitization sequence of a coupled write type fault. At this point, a total of 11 fault sensitization sequences are generated from step 101 to step 104. At this time, the fault detection coverage of the chip fault detection method provided by the embodiment of the present invention reaches 11 / 12≈92%; the execution operations in steps 101 to 104 include: w0, r0, w10, w10, r10, r10, w01, w01, r01, w1, r1, and the total number of execution operations in steps 101 to 108 is 11. The complexity of steps 101 to 104 of the chip fault detection algorithm provided by the embodiment of the present invention is 11N.

[0077] Step 105 , performing a read 1 operation on all sub-units according to a preset address sequence, performing a write operation on all sub-units according to a preset address sequence, and performing a read operation on all sub-units according to a preset address sequence.

[0078] Through the read 1 operation in step 105, it can be confirmed whether the 1 written into the chip is overwritten; if the 1 written into the chip is not overwritten, the write checkerboard data operation is performed on all sub-units according to the preset address sequence; if the 1 written into the chip is overwritten, the write 1 operation is triggered to be performed on all sub-units according to the preset address sequence.

[0079] Through the operation of reading the positive checkerboard data in step 105, it can be confirmed whether the chip is successfully written with the positive checkerboard data and the fault sensitization sequence can be read out. If the chip is not successfully written with the positive checkerboard data, the operation of writing the positive checkerboard data is performed on all sub-units again in a preset address sequence to ensure that the chip is successfully written with the positive checkerboard data; if the chip is successfully written with the positive checkerboard data, the operation of reading the positive checkerboard data is performed on all sub-units in a preset address sequence to read out the fault sensitization sequence.

[0080] For example, Fig. 9 All sub-units of the chip are alternately applied with set voltage and reset voltage in the order from low address to high address, so that all sub-units perform write 1 operation and write 0 operation alternately, and complete the write operation of positive checkerboard data to all sub-units. The state changes of each sub-unit of the chip are as follows: Fig.10 As shown by Fig.10 It can be seen that when there is an interference coupling write fault <1w0; 1 / ↓ / ->, after performing the operation corresponding to the subunit (00, 01) in Table 1 on the subunit (00, 01), Fig.10 It can be seen that when 0 is written to the sub-unit (00, 01), when the state of the adjacent sub-unit (00, 10) is 1, a fault sensitization sequence (1w0; 1) will be generated. If the state of the adjacent sub-unit (00, 10) changes from 1 to 0, the fault <1w0; 1 / ↓ / -> is triggered. In this way, the detection of a coupled write type fault can be achieved by generating a fault sensitization sequence of a coupled write type fault. At this point, a total of 12 fault sensitization sequences are generated from step 101 to step 105. At this time, the fault detection coverage of the chip fault detection method provided by the embodiment of the present invention reaches 100%; the execution operations in steps 101 to 105 include: w0, r0, w10, w10, r10, r10, w01, w01, r01, r01, w1, r1, r1, w10, r10, and the total number of execution operations in steps 101 to 110 is 15. The complexity of steps 101 to 105 of the chip fault detection algorithm provided by the embodiment of the present invention is 15N.

[0081] In some embodiments, after each data read operation is performed, the read voltage is compared with a preset voltage to obtain a fault detection result of the memory. In this way, the fault detection result of the coupled write type fault caused by the high address unit in the previous round of write operation can be detected by performing a read operation first and then a write operation, thereby improving the fault detection efficiency of the coupled write type fault.

[0082] In order to compare with the existing fault detection methods for coupled write type faults (chessboard, March C+ algorithm, March C+ modified algorithm), a coupled write type fault detection experiment was carried out on the same SARM. Table 2 is a fault detection comparison table of different fault detection methods provided in an embodiment of the present invention.

[0083] The execution operations in Table 2 can be understood as the operations that each fault detection method needs to perform on the same chip (the same chip can be understood as the same operation unit). As can be seen from Table 2, the fault detection coverage of coupled write-type faults of the existing March C+ algorithm can only reach 33%, and it is impossible to achieve a 100% fault detection coverage of coupled write-type faults, and the March C+ algorithm needs to perform 14 read and write operations to achieve a 33% fault detection coverage of coupled write-type faults, that is, the complexity of the March C+ algorithm is 14N, while the chip fault detection method provided by the embodiment of the present invention achieves the purpose of achieving a 100% fault detection coverage of coupled write-type faults, and the complexity is only 15N.

[0084] For the existing March C+ modified algorithm, if the fault detection coverage of coupled write type faults is to reach 100%, it can be seen from Table 2 that the March C+ modified algorithm needs to perform 22 read and write operations, that is, the complexity of the March C+ modified algorithm is 22N, and the test time of the March C+ modified algorithm is 36s. The chip fault detection method provided in the embodiment of the present invention only needs to perform 15 read and write operations, with a complexity of 15N, and the test time of the chip fault detection method is 25s, that is, the complexity of the chip fault detection method provided in the embodiment of the present invention is less than the complexity of the March C+ modified algorithm, and the test time is also less than the March C+ modified algorithm, which shortens the fault detection time of coupled write type faults, reduces the detection cost of fault detection of coupled write type faults, and improves the detection efficiency of fault detection of coupled write type faults, thereby solving the problem that the detection time cost of coupled write type faults and the detection efficiency are high when using the March C+ modified algorithm for coupled write type fault detection.

[0085] Table 2 Fault detection comparison table

[0086]

[0087]

[0088] In the embodiment of the present invention, a write-0 operation is performed on all sub-units according to a preset address sequence; a read-0 operation is performed on all sub-units according to a preset address sequence, a write-positive checkerboard data operation is performed twice on all sub-units according to a preset address sequence, and a read-positive checkerboard data operation is performed on all sub-units according to a preset address sequence, that is, operations (2)-(5) of the chip fault detection method in Table 2 are performed, and a fault sensitization sequence (0w0; 0), (0; 0w0), (0w1; 0), (0w0; 1), (1w1 ; 0), (0; 1w1), (1; 0w0); read the positive checkerboard data operation for all sub-units according to the preset address sequence, write the reverse checkerboard data operation twice for all sub-units according to the preset address sequence, and read the reverse checkerboard data operation for all sub-units according to the preset address sequence, that is, on the basis of the aforementioned operations, perform operations (6)-(9) of the chip fault detection method in Table 2, and generate a fault sensitization sequence (1w0; 0), (0w1; 1), (1w1; 1); according to the preset The reverse chessboard data read operation is performed on all sub-units in address order, the write 1 operation is performed on all sub-units in preset address order, and the read 1 operation is performed on all sub-units in preset address order, that is, the operations (10)-(12) of the chip fault detection method in Table 2 are performed on the basis of the aforementioned operations, and the fault sensitization sequence (1; 1w1) can be generated again; the read 1 operation is performed on all sub-units in preset address order, the positive chessboard data write operation is performed on all sub-units in preset address order, and the positive chessboard data read operation is performed on all sub-units in preset address order, that is, the operations (13)-(15) of the chip fault detection method in Table 2 are performed on the basis of the aforementioned operations, and the fault sensitization sequence (1w0; 1) can be generated again, that is, 12 kinds of coupled write-type fault sensitization sequences can be generated, and then the 12 kinds of coupled write-type fault sensitization sequences generated can be used to achieve comprehensive detection of the 12 kinds of coupled write-type faults, and the fault detection coverage of coupled write-type faults reaches 100%, which solves the problem of using March The C+ algorithm for coupled write-type fault detection has the problem of low fault detection coverage of coupled write-type faults; and, if the fault detection coverage of coupled write-type faults is to reach 100%, the complexity of the March C+ modified algorithm is 22N, while the complexity of the chip fault detection method provided by the embodiment of the present invention is 15N, that is, the complexity of the chip fault detection method provided by the embodiment of the present invention is less than the complexity of the March C+ modified algorithm, which shortens the fault detection time of coupled write-type faults, reduces the detection cost of coupled write-type fault detection, and improves the detection efficiency of coupled write-type fault detection, thereby solving the problem of high detection time cost and low detection efficiency of coupled write-type faults when using the March C+ modified algorithm for coupled write-type fault detection.

[0089] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A chip fault detection method, characterized in that: The chip includes several sub-units, and the method includes: Perform a write-0 operation on all sub-units in a preset address order; Performing a read 0 operation on all sub-units according to the preset address sequence, performing a write positive checkerboard data operation twice on all sub-units according to the preset address sequence, and performing a read positive checkerboard data operation on all sub-units according to the preset address sequence; Performing a read operation on the positive checkerboard data on all sub-units according to the preset address sequence, performing a write operation on the reverse checkerboard data twice on all sub-units according to the preset address sequence, and performing a read operation on the reverse checkerboard data on all sub-units according to the preset address sequence; Performing a read reverse checkerboard data operation on all sub-units according to the preset address sequence, performing a write 1 operation on all sub-units according to the preset address sequence, and performing a read 1 operation on all sub-units according to the preset address sequence; A read 1 operation is performed on all sub-units according to the preset address sequence, a write positive checkerboard data operation is performed on all sub-units according to the preset address sequence, and a read positive checkerboard data operation is performed on all sub-units according to the preset address sequence.

2. The method according to claim 1, characterized in that The preset address sequence is a sequence from a low address to a high address or a sequence from a high address to a low address.

3. The method according to claim 1, characterized in that The performing a write-0 operation on all sub-units according to a preset address sequence includes: A reset voltage is applied to all sub-units according to the preset address sequence, so that all sub-units perform a write-0 operation.

4. The method according to claim 3, characterized in that The performing a read 0 operation on all sub-units according to the preset address sequence includes: Reading the voltages of the subunits in sequence according to the preset addresses; When the voltage is the reset voltage, a read 0 operation is performed on the sub-unit.

5. The method according to claim 3, characterized in that: Performing a checkerboard data read operation on all sub-units according to the preset address sequence includes: Reading the voltages of the subunits in sequence according to the preset addresses; When the voltage is a set voltage, a read 1 operation is performed on the sub-unit; When the voltage is the reset voltage, a read 0 operation is performed on the sub-unit.

6. The method according to claim 5, characterized in that Performing a read-inverse checkerboard data operation on all sub-units according to the preset address sequence includes: Reading the voltages of the subunits in sequence according to the preset addresses; When the voltage is the reset voltage, a read 0 operation is performed on the sub-unit; When the voltage is the set voltage, a read 1 operation is performed on the sub-unit.

7. The method according to claim 5, characterized in that Performing a write 1 operation on all sub-units according to the preset address sequence includes: The set voltage is applied to all sub-units according to the preset address sequence, so that all sub-units perform a write 1 operation.

8. The method according to claim 5, characterized in that The performing a read 1 operation on all sub-units according to the preset address sequence includes: When the voltage is the set voltage, a read 1 operation is performed on the sub-unit.

9. The method according to claim 1, characterized in that: The method further comprises: After each data read operation is performed, the read voltage is compared with the preset voltage to obtain a fault detection result of the memory.

10. The method according to claim 1, characterized in that In the positive checkerboard data, the voltage of the first sub-unit to be written is applied as the set voltage; In the inverse checkerboard data, the voltage of the first sub-unit to be written is applied as a reset voltage.

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