Test device, operating method of test device and test system

Abstract

A test device, an operation method of the test device and a test system are disclosed. The test device includes: a vector memory configured to store a plurality of vector data; a test control circuit configured to test an external memory device by the following operations: receiving first vector data, sending a memory request, a memory address and memory data included in the first vector data, and comparing read data from the external memory device with expected data; and a physical layer configured to: communicate with the external memory device through a data line and a command / address line, output a command corresponding to the memory request and an address corresponding to the memory address through the command / address line, output write data corresponding to the memory data through the data line, receive a memory request, a memory address and memory data from the test control circuit, and receive read data from the external memory device through the data line.

Description

[0001] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0133691 filed on October 6, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The inventive concept relates to a semiconductor memory, and more particularly, to a test device, an operating method of the test device, and a test system including the test device. Background Art

[0003] Semiconductor memories are classified into volatile memory devices (such as static random access memory (SRAM) and dynamic RAM (DRAM)), which lose data stored therein when power is turned off, and nonvolatile memory devices (such as flash memory devices, phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), and ferroelectric RAM (FRAM)), which retain data stored therein even when power is turned off.

[0004] A semiconductor memory device is a device that stores data. Recently, as electronic devices and semiconductor memory devices become smaller and more highly integrated, the designs of semiconductor memory devices become more diverse, and the process of testing the functions of designed or manufactured semiconductor memory devices becomes more complicated.

[0005] For example, developing a memory testing device and setting new conditions for each semiconductor memory device requires a lot of time and effort, considering the type of memory device to be tested, the standard specifications applied to the memory device, the content of the test operation to be performed on the memory device, the range of memory cells among the memory cells of the memory device for performing the test operation, and the protocol used to communicate with the memory device. Summary of the invention

[0006] The inventive concept provides a test device that is easy to manufacture and develop and has wide test coverage, an operating method of the test device, and a test system.

[0007] According to one aspect of the inventive concept, a test device is provided, comprising: a vector memory configured to store multiple vector data; a test control circuit configured to test an external memory device by: receiving first vector data among multiple vector data, sending a memory request, a memory address and memory data included in the first vector data, and comparing read data from the external memory device with expected data; and a physical layer configured to: communicate with the external memory device through a data line and a command / address line, output a command corresponding to the memory request and an address corresponding to the memory address through the command / address line, output write data corresponding to the memory data through the data line, receive a memory request, a memory address and memory data from the test control circuit, and receive read data from the external memory device through the data line, wherein the first vector data includes the memory request, the memory address, the memory data and the expected data.

[0008] According to another aspect of the inventive concept, a method for operating a test device is provided, the test device including a physical layer, a vector memory and a test control circuit, the method comprising: the test control circuit receiving vector data stored in the vector memory, the test control circuit sending a memory request, a memory address and memory data included in the vector data to the physical layer, the physical layer sending a command corresponding to the memory request and an address corresponding to the memory address to an external memory device through a command / address line, and the physical layer sending data corresponding to the memory data to the external memory device through a data line.

[0009] According to another aspect of the inventive concept, a test system is provided, including: a test device and a memory device, wherein the test device includes: a vector memory configured to store a plurality of vector data; a test control circuit configured to test the memory device by: receiving first vector data among the plurality of vector data, sending a memory request, a memory address and memory data included in the first vector data, and comparing read data from the memory device with expected data included in the first vector data to generate and store a test result; and a physical layer configured to: communicate with the memory device through a data line and a command / address line, output a command corresponding to the memory request and an address corresponding to the memory address through the command / address line, output write data corresponding to the memory data through the data line, and receive read data through the data line. The physical layer includes an intellectual property (IP) block, and the memory request, the memory address and the memory data are signals defined by a double data rate (DDR) PHY interface (DFI) standard. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Embodiments will be more clearly understood from the following detailed description in conjunction with the accompanying drawings.

[0011] Figure 1 is a block diagram illustrating a test system according to an embodiment.

[0012] Figure 2 is a block diagram illustrating vector data according to an embodiment.

[0013] Figure 3 is a block diagram illustrating a test system according to an embodiment.

[0014] Figure 4A and Figure 4B Each is a block diagram illustrating an example of an operation method of a test system according to an embodiment.

[0015] Figure 5 is a block diagram illustrating a test system according to an embodiment.

[0016] Figure 6 is a block diagram illustrating an example of an operating method of a test system according to an embodiment.

[0017] Figure 7 is a block diagram illustrating a test system according to an embodiment.

[0018] Figure 8 is a flowchart illustrating an example of an operating method of a command decoder according to an embodiment.

[0019] Fig. 9 is a block diagram illustrating a test system according to an embodiment.

[0020] Fig.10 is a flowchart illustrating an example of an operating method of a test system according to an embodiment.

[0021] Fig.11 is a block diagram showing a memory device according to an embodiment.

[0022] Fig. 12A and Fig. 12B Each is a timing chart showing the operation of the test apparatus according to the embodiment.

[0023] Fig.13 is a flowchart illustrating an example of an operating method of a test system according to an embodiment.

[0024] Fig.14 is a flowchart illustrating an example of an operating method of a test system according to an embodiment.

[0025] Fig.15 is a block diagram illustrating a test system according to an embodiment. DETAILED DESCRIPTION

[0026] Hereinafter, the embodiments will be described in detail and clearly to the extent that a person having ordinary skill in the art can easily realize the inventive concept.

[0027] Figure 1 is a block diagram illustrating a test system 1000 according to an embodiment.

[0028] Reference Figure 1 , the test system 1000 may include a test device 1100 and a memory device 1200. In one embodiment, the test system 1000 may be used to detect defects in the memory device 1200 during a manufacturing process of the memory device 1200. That is, the test system 1000 may test defects in the memory device 1200 in advance.

[0029] The test device 1100 may include a vector memory 1110, a test control circuit 1120, and a physical layer (PHY) 1130. The test device 1100 may perform a test operation on the memory device 1200. The test device 1100 may perform a test operation to detect a defect in the memory device 1200. For example, the test device 1100 may perform a test operation to determine whether the memory device 1200 normally performs various operations (e.g., a write operation, a read operation, a mode setting operation, etc.).

[0030] The test device 1100 may be configured to control the memory device 1200 so as to test the operation of the memory device 1200. The test device 1100 may write test data to the memory device 1200 based on the vector data (or packet) stored in the vector memory 1110. The test device 1100 may read the test data written in the memory device 1200. The test device 1100 may determine whether the memory device 1200 is defective by comparing the read test data with the original data (or expected data). That is, the test system 1000 may determine whether the memory device 1200 has a defect based on the test data and the expected data.

[0031] The test device 1100 may send a command or data to the memory device 1200. The test device 1100 may receive data from the memory device 1200. For example, the test device 1100 may send a test command and test write data to the memory device 1200. The test device 1100 may receive test read data from the memory device 1200.

[0032] The vector memory 1110 may store test data. The test data may include a plurality of vector data. The vector memory 1110 may store a plurality of vector data. For example, the vector data may include a memory request, a memory address, memory data, and expected data.

[0033] The vector memory 1110 may output vector data in response to a load command received from the test control circuit 1120. The vector memory 1110 may transmit the vector data stored therein to the test control circuit 1120. For example, the vector memory 1110 may be at least one of various types of memories such as static random access memory (SRAM), dynamic RAM (DRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), phase change RAM (PRAM), magnetic RAM (MRAM), and flash memory.

[0034] The test control circuit 1120 may test the memory device 1200 through the PHY 1130. The test control circuit 1120 may control the memory device 1200 through the PHY 1130. In one embodiment, the test control circuit 1120 and the PHY 1130 may communicate with each other according to a double data rate (DDR) PHY interface (DFI) communication protocol.

[0035] The test control circuit 1120 may receive vector data from the vector memory 1110. The test control circuit 1120 may send a memory request, a memory address, and memory data in the vector data to the PHY 1130. The test control circuit 1120 may compare expected data included in the vector data with the read data. For example, the read data may refer to data received from the memory device 1200 through the PHY 1130. The test control circuit 1120 may test the memory device 1200 by comparing the read data with the expected data to generate and store a test result.

[0036] The PHY 1130 may communicate with the memory device 1200. The PHY 1130 may communicate with the memory device 1200 through a command / address line, a data line, a data strobe line, etc. The PHY 1130 may output a command corresponding to a memory request and an address corresponding to a memory address through a command / address line. The PHY 1130 may output write data corresponding to memory data through a data line. The PHY 1130 may receive read data through a data line. For example, a memory request, a memory address, and memory data may be signals defined by a DFI standard. The memory request, the memory address, and the memory data may have a DFI format.

[0037] In one embodiment, the PHY 1130 may be electrically connected to the memory device 1200. The PHY 1130 may be electrically connected to a physical layer of the memory device 1200. The PHY 1130 may also be referred to as a memory interface circuit.

[0038] In one embodiment, PHY 1130 may be an intellectual property (IP) block. PHY 1130 may be a DDR PHY IP block. Designers of integrated circuits, such as systems on a chip (SoC), microprocessors, microcontrollers, and other systems, may use IP blocks to simplify system design. IP blocks are modular, independent hardware blocks that can be easily integrated into a design. Because IP blocks are modular and self-contained, designers of integrated circuits may simply drop-in an IP block to use its functionality. An IP block may be a "black box." That is, a system integrator using an IP block may not know or need to know the specific implementation details of the IP block.

[0039] The memory device 1200 may operate under the control of the test device 1100. For example, the memory device 1200 may be a device under test (DUT). For example, the memory device 1200 may receive a clock signal CK (see Fig. 9 ) and command / address signal CA (see Fig. 9 ), and in response to the received signal, the data signal DQ and the data strobe signal DQS may be sent to the test device 1100 (see Fig. 9 ) or receives a data signal DQ and a data select signal DQS from the test device 1100.

[0040] For example, the memory device 1200 may be a DRAM device, but the scope of the inventive concept is not limited thereto. For example, the memory device 1200 may include at least one of various types of memory devices such as DRAM devices, SRAM devices, RRAM devices, FRAM devices, PRAM devices, MRAM devices, and flash memory devices.

[0041] Automatic test equipment (ATE) may include a timing generator and a pin control circuit. The timing generator and the pin control circuit may be implemented as an application specific integrated circuit (ASIC). The timing generator may generate a timing change of a test signal applied to a DUT or a memory device. The pin control circuit may generate a level change (or voltage change) of a test signal applied to a DUT or a memory device. As the speed or performance of the memory device increases, the difficulty of ATE development increases, and the ATE development time increases.

[0042] A test device including a memory controller may test a memory device by using only limited commands (e.g., a read command or a write command). A test device including a memory controller may have difficulty sending commands based on a clock cycle (or clock cycle). For example, a test device including a memory controller may have difficulty sending an activation command, a write command, and a precharge command to a memory device at a user-desired timing. A test device including a memory controller may have difficulty performing various tests. A test device including a memory controller may have lower test coverage than an ATE device.

[0043] The test device 1100 may detect defects occurring in the memory device 1200 by performing a test operation. The test device 1100 may include a PHY 1130 as an IP block. The test device 1100 may include a PHY 1130 as an IP block instead of a timing generator and a pin control circuit of an ATE. When developing the test device 1100 including the PHY 1130 as an IP block, the development difficulty may be reduced, and the development time and manufacturing cost may be reduced.

[0044] The test device 1100 may include a test control circuit 1120 instead of a memory controller. The test control circuit 1120 may perform a test operation on the memory device 1200 based on the vector data. The test control circuit 1120 may send the DFI signal included in the vector data to the PHY 1130 without change. Therefore, the test control circuit 1120 may not perform packet format conversion or data conversion. The test control circuit 1120 may be simplified or lightweight. The test device 1100 may have an increased degree of freedom for test implementation. The test device 1100 may have a test coverage that is the same as or similar to the test coverage of ATE.

[0045] Figure 2 is a block diagram showing vector data VD according to an embodiment.

[0046] Reference Figure 1 and Figure 2 , the vector memory 1110 may store vector data VD. The test control circuit 1120 may load the vector data VD from the vector memory 1110. In one embodiment, the vector data VD may include a command field, a DFI field, and a comparison field. The command field may include an operation code OPCODE and an operand OPERAND. The DFI field may include a memory request MRQ, a memory address MA, and a memory data MDT. The comparison field may include a comparison enable signal CEN and expected data EDT. That is, the vector data VD may include an operation code OPCODE, an operand OPERAND, a memory request MRQ, a memory address MA, a memory data MDT, a comparison enable signal CEN, and expected data EDT.

[0047] The command field may be used in the test control circuit 1120. The test control circuit 1120 may perform a decoding operation based on the command field. The operation code OPCODE may indicate one of a stop code and a loop code. When the operation code OPCODE indicates a stop code, the test control circuit 1120 may stop the test operation. The operand OPERAND may be used to set a loop counter. For example, the operand OPERAND may be used to adjust the time interval between commands sent to the memory device 1200.

[0048] The DFI field may be input to the PHY 1130. The memory request MRQ may correspond to a command transmitted to the memory device 1200, the memory address MA may correspond to an address transmitted to the memory device 1200, and the memory data MDT may correspond to data transmitted to the memory device 1200. The data transmitted to the memory device 1200 may include a data signal DQ and a data strobe signal DQS.

[0049] In one embodiment, the DFI field may include a signal input to the PHY 1130 according to the DFI standard. For example, the DFI field may include a DFI address bus signal, a DFI bank bus signal, a DFI column address strobe signal, a write data bus signal, a write data and data mask signal, a read data bus signal, a read data enable signal, etc. However, the scope of the inventive concept is not limited thereto.

[0050] The comparison field may be used in the test control circuit 1120. The comparison enable signal CEN may be a signal for enabling a comparator of the test control circuit 1120. When the comparison enable signal CEN is enabled, the test control circuit 1120 may compare the expected data EDT with the read data. The expected data EDT may be test data written to the memory device 1200. The expected data EDT may be used to compare with the read data received from the memory device 1200.

[0051] Figure 3 is a block diagram illustrating a test system 1000 according to an embodiment.

[0052] Reference Figure 1 and Figure 3 , the test system 1000 may include a test device 1100, a memory device 1200, and a host device 1300. The test device 1100 may include a vector memory 1110, a test control circuit 1120, a PHY 1130, and a host interface circuit 1140. For ease of description, a detailed description of the components described above is omitted.

[0053] The host device 1300 may test the memory device 1200 through the test device 1100. For example, the host device 1300 may be one of various computing devices such as a desktop computer, a laptop computer, a workstation, a server, a smart phone, a tablet personal computer (PC), a digital camera, and a black box.

[0054] The host device 1300 may control the operation of the test device 1100. The host device 1300 may execute an operating system, a program, or an application. For example, the host device 1300 may include a user interface (not shown). The host device 1300 may receive test parameters from a user through the user interface. Alternatively, the host device 1300 may receive setting information through the user interface.

[0055] In one embodiment, the host device 1300 may generate test data TD based on the test parameters (see Figure 4A ). The test parameters may include the type of the memory device 1200, the standard specification applied to the memory device 1200, the protocol for communicating with the memory device 1200, the type of test operation to be performed on the memory device 1200, the range of memory addresses for performing the test operation, etc. The host device 1300 may generate a plurality of vector data VD based on the test parameters. The host device 1300 may send test data TD including the plurality of vector data VD to the test device 1100. The host device 1300 may store the test data TD (or the plurality of vector data VD) in the vector memory 1110 of the test device 1100.

[0056] The host device 1300 may send a test start request and a start address to the test device 1100. The test start request may be a request for the test device 1100 to start a test operation on the memory device 1200. The start address may indicate an address of vector data VD to be loaded first by the test device 1100.

[0057] The host device 1300 may receive a test end signal from the test device 1100. In response to the test end signal, the host device 1300 may read the data stored in the buffer memory 1124 (see Figure 5 The host device 1300 may send a test result request to the test device 1100 in response to the test end signal.

[0058] For example, the test result request may be used to request a test result stored in the buffer memory 1124. The test result may include a plurality of failure entries. The failure entry may include a failure address, read data, or expected data. The host device 1300 may receive the test result from the test device 1100. The host device 1300 may detect defects in the memory device 1200 based on the test result.

[0059] The test device 1100 may communicate with the host device 1300 through the host interface circuit 1140. The test device 1100 may receive test data TD (or a plurality of vector data VD) from the host device 1300. The test device 1100 may store the test data TD in the vector memory 1110. The test device 1100 may receive a test start request or a start address from the host device 1300.

[0060] The test device 1100 may transmit a test end signal to the host device 1300. The test device 1100 may receive a test result request. In response to the test result request, the test device 1100 may transmit the test result stored in the buffer memory 1124 to the host device 1300.

[0061] Figure 4A and Figure 4B Each is a block diagram illustrating an example of an operation method of the test system 1000 according to the embodiment.

[0062] Reference Figure 3 and Figure 4A In operation S110, the host device 1300 may send test data TD to the test device 1100. The host device 1300 may generate test data TD for testing the memory device 1200. The test data TD may include a plurality of vector data VD. The host device 1300 may store the test data TD in the vector memory 1110 of the test device 1100. The test device 1100 may receive the test data TD through the host interface circuit 1140. The test device 1100 may store the test data TD in the vector memory 1110.

[0063] In operation S120, a test start request (RQ) and a start address may be sent to the test device 1100. The host device 1300 may send the test start request and the start address to the test device 1100 to start a test operation on the memory device 1200. The test device 1100 may receive the test start request and the start address through the host interface circuit 1140. The test control circuit 1120 may receive the test start request and the start address.

[0064] In operation S130, the test control circuit 1120 may send a load command to the vector memory 1110. The test control circuit 1120 may send the load command to the vector memory 1110 in response to the test start request. The load command may include a start address. The test control circuit 1120 may read the vector data VD corresponding to the start address. The test control circuit 1120 may read the vector data VD while sequentially increasing the address from the start address.

[0065] In operation S140, the vector memory 1110 may transmit the vector data VD to the test control circuit 1120. The vector memory 1110 may transmit the vector data VD corresponding to the start address to the test control circuit 1120 in response to the load command. The test control circuit 1120 may receive the vector data VD.

[0066] In operation S150, the test control circuit 1120 may transmit the DFI field in the vector data VD to the PHY 1130. The test control circuit 1120 may perform a decoding operation based on the vector data VD. The test control circuit 1120 may determine whether to continue to perform the test based on the operation code OPCODE included in the vector data VD.

[0067] The test control circuit 1120 may extract the DFI field from the vector data VD. The test control circuit 1120 may send the memory request MRQ, the memory address MA, and the memory data MDT in the vector data VD to the PHY 1130. The test control circuit 1120 may send the DFI standard signal included in the vector data VD to the PHY 1130 without change.

[0068] The PHY 1130 may receive the DFI field in the vector data VD. The PHY 1130 may receive the memory request MRQ, the memory address MA, and the memory data MDT. The PHY 1130 may receive the DFI standard signal included in the vector data VD without change.

[0069] In operation S160, the PHY 1130 may send a command CMD, an address ADDR, and data DT to the memory device 1200. The data DT may include a data signal DQ and a data strobe signal DQS. The PHY 1130 may send the command CMD, the address ADDR, and the data DT based on the DFI field received from the test control circuit 1120. In one embodiment, the command CMD and the address ADDR may be sent through a command / address line, the data signal DQ may be sent through a data line, and the data strobe signal DQS may be sent through a data strobe line. The command CMD may correspond to a memory request MRQ, the address ADDR may correspond to a memory address MA, and the data DT may correspond to a memory data MDT.

[0070] The test apparatus 1100 may repeatedly perform operations S130 to S160. The test apparatus 1100 may repeatedly perform operations S130 to S160 until the test operation is stopped.

[0071] In operation S170, the test device 1100 may send a test end signal to the host device 1300. For example, the test end signal may be a signal for notifying the host device 1300 that the test operation has been completed. When the test control circuit 1120 determines that the operation code OPCODE in the vector data VD indicates a stop code, the test control circuit 1120 may stop the test operation. The test control circuit 1120 may send the test end signal to the host device 1300 through the host interface circuit 1140 in response to the operation code OPCODE as the stop code. In one embodiment, the test end signal may indicate whether the test device 1100 has detected a defect in the memory device 1200.

[0072] In operation S180, the host device 1300 may send a test result request to the test device 1100. For example, the host device 1300 may send a test result request command to the test device 1100. The test result request may be a request for a test result stored in the test device 1100. For example, the test result request may be a test result request command. The test result may be a log of defects (or errors) detected by testing the memory device 1200. For example, the test result may include a plurality of failed entries. Each of the plurality of failed entries may include a memory address, read data, and expected data. The test control circuit 1120 may receive the test result request (or test result request command) through the host interface circuit 1140. For example, the host device 1300 may send the test result request to the test control circuit 1120 after receiving a test end signal from the test control circuit 1120.

[0073] In operation S190, the test device 1100 may transmit the test result TR to the host device 1300. In response to the test result request (or test result request command), the test control circuit 1120 may transmit the test result TR stored in the test device 1100 to the host device 1300 through the host interface circuit 1140.

[0074] As described above, the vector data VD may include a DFI field (or a DFI signal). The test control circuit 1120 may send the DFI signal included in the vector data VD without change. The test control circuit 1120 may not newly generate a DFI signal based on the vector data VD or convert the DFI signal. Therefore, the test control circuit 1120 may be simplified and lightweight.

[0075] Figure 5 is a block diagram illustrating a test system 1000 according to an embodiment.

[0076] Reference Figure 5, the test system 1000 may include a test device 1100, a memory device 1200, and a host device 1300. The test device 1100 may include a vector memory 1110, a test control circuit 1120, a PHY 1130, and a host interface circuit 1140. For ease of description, a detailed description of the components described above is omitted.

[0077] In one embodiment, the test control circuit 1120 may include a sequencer 1121, a command decoder 1122, a comparator 1123, and a buffer memory 1124. The sequencer 1121 may perform a load operation. The load operation may refer to an operation of loading vector data VD from the vector memory 1110. The sequencer 1121 may read the vector data VD from the vector memory 1110. The sequencer 1121 may send the vector data VD to the command decoder 1122.

[0078] The sequencer 1121 may start a load operation in response to a test start request or a start address received from the host device 1300. For example, the sequencer 1121 may receive a test start request and a start address from the host device 1300. The sequencer 1121 may load vector data VD from the vector memory 1110 in response to the test start request. The sequencer 1121 may load the vector data VD corresponding to the start address. The sequencer 1121 may read the vector data VD while sequentially increasing the address from the start address. The sequencer 1121 may send a load command to the vector memory 1110. The sequencer 1121 may receive the vector data VD from the vector memory 1110.

[0079] In one embodiment, the sequencer 1121 may read the vector data VD while sequentially increasing the address from the start address until a stop signal is received. The sequencer 1121 may receive the stop signal from the command decoder 1122. In response to the stop signal, the sequencer 1121 may stop reading the vector data VD from the vector memory 1110. The sequencer 1121 may no longer load the vector data VD after receiving the stop signal. The sequencer 1121 may stop the loading operation in response to the stop signal.

[0080] The command decoder 1122 may receive the vector data VD from the sequencer 1121. The command decoder 1122 may extract the command field from the vector data VD. The command decoder 1122 may extract the operation code OPCODE and the operand OPERAND from the vector data. The command decoder 1122 may extract the DFI field from the vector data VD. The command decoder 1122 may extract the memory request MRQ, the memory address MA, and the memory data MDT from the vector data VD. The command decoder 1122 may extract the comparison field from the vector data VD. The command decoder 1122 may extract the comparison enable signal CEN and the expected data EDT from the vector data VD.

[0081] The command decoder 1122 may send the DFI field in the vector data VD to the PHY 1130. The command decoder 1122 may send the memory request MRQ, the memory address MA, and the memory data MDT in the vector data VD to the PHY 1130. The command decoder 1122 may send the comparison field in the vector data VD to the comparator 1123. The command decoder 1122 may send the comparison enable signal CEN and the expected data EDT in the vector data VD to the comparator 1123.

[0082] The command decoder 1122 may perform a decoding operation. The command decoder 1122 may control a test based on the operation code OPCODE. The command decoder 1122 may stop the test operation in response to the operation code OPCODE as a stop code. The command decoder 1122 may adjust the time interval (or the number of clock cycles) between commands sent to the memory device 1200 based on the operation code OPCODE as a cycle code and the operand OPERAND.

[0083] The comparator 1123 may receive a comparison enable signal CEN and expected data EDT from the command decoder 1122. The comparator 1123 may receive read data RDT from the PHY 1130 (see Figure 6 ). When the comparison enable signal CEN is enabled, the comparator 1123 may compare the read data RDT with the expected data EDT. The comparator 1123 may determine whether the read data RDT is the same as the expected data EDT.

[0084] When the read data RDT is different from the expected data EDT, the comparator 1123 may generate a fail entry FE (see Figure 6 ). The fail entry FE may include a memory address MRA, read data RDT, and expected data EDT. The comparator 1123 may send the generated fail entry FE to the buffer memory 1124.

[0085] The buffer memory 1124 may receive the fail entry FE from the comparator 1123. The buffer memory 1124 may store the fail entry FE. The buffer memory 1124 may store a plurality of fail entries FE. The plurality of fail entries FE may be referred to as a test result TR. The buffer memory 1124 may store the test result TR.

[0086] The buffer memory 1124 may receive a test result request from the host device 1300 through the host interface circuit 1140. In response to the test result request, the buffer memory 1124 may transmit the test result TR (ie, a plurality of fail entries FE) to the host device 1300 through the host interface circuit 1140.

[0087] Figure 6is a block diagram illustrating an example of an operating method of the test system 1000 according to an embodiment.

[0088] Reference Figure 5 and Figure 6 For ease of description, detailed description of the above described operations is omitted. In operation S210, the sequencer 1121 may send a load command to the vector memory 1110. In operation S220, the vector memory 1110 may send vector data VD corresponding to the load command to the sequencer 1121. In operation S230, the sequencer 1121 may send the vector data VD to the command decoder 1122.

[0089] In operation S240, the command decoder 1122 may send the DFI field to the PHY 1130. The command decoder 1122 may extract the DFI field from the vector data VD. The command decoder 1122 may extract the memory request MRQ, the memory address MA, and the memory data MDT from the vector data VD. The command decoder 1122 may send the memory request MRQ, the memory address MA, and the memory data MDT to the PHY 1130.

[0090] In operation S250 , the command decoder 1122 may transmit the comparison field to the comparator 1123 . The command decoder 1122 may extract the comparison enable signal CEN and the expected data EDT from the vector data VD . The command decoder 1122 may transmit the comparison enable signal CEN and the expected data EDT to the comparator 1123 .

[0091] In operation S260, the PHY 1130 may transmit a command CMD and an address ADDR to the memory device 1200. For example, the PHY 1130 may transmit the command CMD and the address ADDR to the memory device 1200 through a command / address line. For example, the command CMD may be a read command. Therefore, the PHY 1130 may not transmit data to the memory device 1200. The memory device 1200 may receive the command CMD and the address ADDR.

[0092] In operation S270, the memory device 1200 may send data DT to the PHY 1130. The data DT may be data corresponding to the command CMD. The PHY 1130 may receive the data DT. The data DT may include a data signal DQ and a data strobe signal DQS. In operation S280, the PHY 1130 may send read data RDT to the comparator 1123. The PHY 1130 may send the read data RDT to the comparator 1123 based on the data DT. The PHY 1130 may send the data DT as the read data RDT to the comparator 1123. The value of the read data RDT may be the same as the value of the data DT. Alternatively, the read data RDT may be the data DT.

[0093] In operation S290, the comparator 1123 may send a fail entry FE to the buffer memory 1124. The comparator 1123 may receive a comparison enable signal CEN, an expected data EDT, and a read data RDT. When the comparison enable signal CEN is enabled, the comparator 1123 may compare the expected data EDT with the read data RDT. When the expected data EDT is different from the read data RDT, the comparator 1123 may generate a fail entry FE. The fail entry FE may include a memory address MA, an expected data EDT, and a read data RDT. The comparator 1123 may send the memory address MA, the expected data EDT, and the read data RDT to the buffer memory 1124. The buffer memory 1124 may receive the fail entry FE. The buffer memory 1124 may store the fail entry FE.

[0094] Figure 7 is a block diagram illustrating a test system 1000 according to an embodiment.

[0095] Reference Figure 7 , the test system 1000 may include a test device 1100, a memory device 1200, and a host device 1300. The test device 1100 may include a vector memory 1110, a test control circuit 1120, a PHY 1130, and a host interface circuit 1140. In one embodiment, the test control circuit 1120 may include a sequencer 1121, a command decoder 1122, a comparator 1123, and a buffer memory 1124. For ease of description, a detailed description of the components described above is omitted.

[0096] In one embodiment, the command decoder 1122 may include a first-in-first-out (FIFO) memory, an operation code decoder OD, and a loop counter LC. The FIFO memory may receive the vector data VD from the sequencer 1121. The FIFO memory may receive a FIFO enable signal FEN from the loop counter LC. The FIFO memory may output the vector data VD in response to the FIFO enable signal FEN.

[0097] The FIFO memory may output the vector data VD. The FIFO memory may send the command field in the vector data VD to the operation code decoder OD. The FIFO memory may send the operation code OPCODE and the operand OPERAND in the vector data VD to the operation code decoder OD. The FIFO memory may send the DFI field in the vector data VD to the PHY 1130. The FIFO memory may send the memory request MRQ, the memory address MA, and the memory data MDT in the vector data VD to the PHY 1130. The FIFO memory may send the comparison field in the vector data VD to the comparator 1123. The FIFO memory may send the comparison enable signal CEN and the expected data EDT in the vector data VD to the comparator 1123.

[0098] The operation code decoder OD may receive a command field from the FIFO memory. The operation code decoder OD may receive an operation code OPCODE and an operand OPERAND. The operation code decoder OD may perform a decoding operation based on the operation code OPCODE. When the operation code OPCODE indicates a stop code, the operation code decoder OD may output a stop signal HSIG to the sequencer 1121. When the operation code OPCODE indicates a loop code, the operation code decoder OD may send the operand OPERAND to the loop counter LC. In other words, the operation code decoder OD may output a stop signal HSIG to the sequencer 1121 in response to the operation code OPCODE indicating the stop code, and may send the operand OPERAND to the loop counter LC in response to the operation code OPCODE indicating the loop code.

[0099] The loop counter LC may receive an operand OPERAND from the operation code decoder OD. The loop counter LC may set the operand OPERAND to a count value. The loop counter LC may reduce the count value by 1 for each clock. When the count value is "0", the loop counter LC may output a FIFO enable signal FEN to the FIFO memory. For example, the loop counter LC may output the FIFO enable signal FEN to the FIFO memory after the number of clock cycles corresponding to the count value. For example, if the count value is 5, the number of clock cycles is 5.

[0100] The sequencer 1121 may receive a stop signal HSIG from the operation code decoder OD. The sequencer 1121 may stop the operation. The sequencer 1121 may stop the load operation of loading the vector data VD from the vector memory 1110. The sequencer 1121 may stop the operation of sending the vector data VD to the command decoder 1122. The sequencer 1121 may send a test end signal to the host device 1300 through the host interface circuit 1140 in response to the stop signal HSIG.

[0101] In one embodiment, the memory request MRQ included in the vector data VD may correspond to any one of an activation command, a precharge command, a write command, a read command, and a mode register setting command. The test device 1100 may send a command to the memory device 1200 based on the vector data VD. Therefore, the test device 1100 may send various commands other than the read command and the write command to the memory device 1200. The test device 1100 may test a plurality of commands defined in the standard specification.

[0102] As described above, the test control circuit 1120 may include a cycle counter LC. By using the cycle counter LC, the test control circuit 1120 may send a command to the memory device 1200 based on a clock cycle. Therefore, the test device 1100 may perform a test while adjusting a time interval between commands sent to the memory device 1200. The test device 1100 may have an increased test coverage.

[0103] Figure 8 is a flowchart illustrating an example of an operation method of the command decoder 1122 according to an embodiment.

[0104] Reference Figure 7 and Figure 8 In operation S310, the command decoder 1122 may receive the vector data VD. The FIFO memory may load the vector data VD from the sequencer 1121. In operation S320, the command decoder 1122 may decode the operation code OPCODE. The FIFO memory may send the command field to the operation code decoder OD. The operation code decoder OD may perform decoding based on the operation code OPCODE.

[0105] In operation S330, the command decoder 1122 may determine whether the operation code OPCODE is a stop code. When the operation code OPCODE is a stop code, the operation code decoder OD may perform operation S340. When the operation code OPCODE is not a stop code, the operation code decoder OD may perform operation S350.

[0106] In operation S340, the command decoder 1122 may send a stop signal HSIG to the sequencer 1121. The command decoder 1122 may output the stop signal HSIG to the sequencer 1121 to stop the test operation. The sequencer 1121 may receive the stop signal HSIG. The sequencer 1121 may stop the load operation in response to the pause signal HSIG. The sequencer 1121 may stop the operation of sending the vector data VD to the command decoder 1122. The sequencer 1121 may send a test end signal to the host device 1300. For example, the sequencer 1121 may send the test end signal to the host device 1300 in response to the stop signal HSIG.

[0107] In operation S350, the command decoder 1122 may determine whether the operation code OPCODE is a cyclic code. When the operation code OPCODE is a cyclic code, the operation code decoder OD may perform operation S360. When the operation code OPCODE is not a cyclic code, the operation code decoder OD may perform operation S310.

[0108] In operation S360, the command decoder 1122 may set a count value CV. The operation code decoder OD may send an operand OPERAND to a loop counter LC. The loop counter LC may set the operand OPERAND to a count value CV. The count value CV is used to describe the repetition of the loop operation and does not limit the scope of the inventive concept.

[0109] In operation S370, the command decoder 1122 may determine whether the count value CV is "0". When the count value CV is "0", the command decoder 1122 may perform operation S310, and when the count value CV is not "0", operation S380 may be performed. In operation S380, the command decoder 1122 may reduce the count value CV by 1. Then, the command decoder 1122 may perform operation S370.

[0110] Fig. 9 is a block diagram illustrating a test system 1000 according to an embodiment.

[0111] Reference Fig. 9 , the test system 1000 may include a test device 1100, a memory device 1200, and a host device 1300. The test device 1100 may include a vector memory 1110, a test control circuit 1120, a PHY 1130, and a host interface circuit 1140. In one embodiment, the test control circuit 1120 may include a sequencer 1121, a command decoder 1122, a comparator 1123, and a buffer memory 1124. For ease of description, a detailed description of the components described above is omitted.

[0112] Under the control of the test control circuit 1120, the PHY 1130 may transmit a clock signal CK and a command / address signal CA to the memory device 1200, and may exchange a data signal DQ and a data strobe signal DQS with the memory device 1200. For example, the PHY 1130 may be a DDR-PHY configured to support a DDR interface. For example, the PHY 1130 may be configured to support various standard interfaces defined by the Joint Electron Device Engineering Council (JEDEC) standard, such as DDR, Graphics DDR (GDDR), and Low Power DDR (LPDDR), but the scope of the inventive concept is not limited thereto.

[0113] The memory device 1200 may operate under the control of the test device 1100. For example, the memory device 1200 may receive a clock signal CK and a command / address signal CA from the test device 1100, and in response to the received signals, may transmit or receive a data signal DQ and a data strobe signal DQS to or from the test device 1100.

[0114] The PHY 1130 may include a clock generator (CK GEN) 1131, a command / address generator (CA GEN) 1132, a data receiver 1133, and a data transmitter 1134. The PHY 1130 may receive a DFI signal or a DFI field. The PHY 1130 may generate a signal having a timing and a level conforming to a standard protocol based on the DFI signal, and may transmit the generated signal to the memory device 1200. The PHY 1130 may sample a signal received from the memory device 1200. The PHY 1130 may convert the sampled signal into a DFI signal conforming to the DFI standard. The PHY 1130 may transmit the converted DFI signal to the test control circuit 1120. For example, the PHY 1130 may transmit the read data RDT to the comparator 1123.

[0115] The clock generator 1131 may generate a clock signal CK to be provided to the memory device 1200. The generated clock signal CK may be provided to the memory device 1200 through a clock line. For example, the memory device 1200 may operate based on the clock signal CK provided from the test device 1100. The command / address generator 1132 may generate a command / address signal CA to be transmitted to the memory device 1200 under the control of the test control circuit 1120. The generated command / address signal CA may be provided to the memory device 1200 through a command / address line.

[0116] Although the terms "command / address signal CA", "data signal DQ" and "data strobe signal DQS" are used for simplifying the drawings and facilitating description, these terms may refer to a command / address line, a data line and a data strobe signal line between the test device 1100 and the memory device 1200, respectively, or may refer to signals transmitted through corresponding lines. Here, the command / address signal CA may correspond to Figure 4A and Figure 6 The data signal DQ can correspond to the command CMD and address ADDR. Figure 4A and Figure 6 The data DT.

[0117] The data receiver 1133 may receive a data signal DQ and a data strobe signal DQS from the memory device 1200. The data receiver 1133 may be configured to capture the data signal DQ at a rising edge or a falling edge of the data strobe signal DQS. The received data output from the data receiver 1133 may be provided to the test control circuit 1120. The data transmitter 1134 may output the data signal DQ and the data strobe signal DQS provided from the test control circuit 1120 to the memory device 1200.

[0118] Fig.10 is a flowchart illustrating an example of an operating method of the test system 1000 according to an embodiment.

[0119] Reference Figure 3 and Fig.10 , the test device 1100 may perform a test operation on the memory device 1200. The host device 1300 may generate test data TD. The host device 1300 may generate test data TD including a plurality of vector data VD. One vector data may correspond to one command. The test device 1100 may perform a test on the memory device 1200 in the order of the vector data VD generated by the host device 1300.

[0120] For example, the host device 1300 may generate first to fourth vector data VD1 to VD4. The host device 1300 may sequentially store the first to fourth vector data VD1 to VD4 in the vector memory 1110. For example, the vector memory 1110 may store the first to fourth vector data VD1 to VD4. The first vector data VD1 may include a first memory request MRQ1, the second vector data VD2 may include a second memory request MRQ2, the third vector data VD3 may include a third memory request MRQ3, and the fourth vector data VD4 may include a fourth memory request MRQ4. The vector memory 1110 may sequentially store the first vector data VD1, the second vector data VD2, the third vector data VD3, and the fourth vector data VD4.

[0121] In one embodiment, the addresses corresponding to the first vector data VD1 to the fourth vector data VD4, respectively, may be sequential addresses. For example, the first address corresponding to the first vector data VD1 stored therein, the second address corresponding to the second vector data VD2 stored therein, the third address corresponding to the third vector data VD3 stored therein, and the fourth address corresponding to the fourth vector data VD4 stored therein may be sequential addresses. A sequential address may refer to a group of consecutive addresses. The fact that each of the first to fourth addresses is a sequential address may mean that there are no other addresses between each pair of addresses in the first to fourth addresses. For example, the first to fourth addresses may have sequential address values.

[0122] In operation S401, the test control circuit 1120 may send a load command to the vector memory 1110. For example, the load command may include a first address. In operation S402, the vector memory 1110 may send first vector data VD1 including a first memory request MRQ1 to the test control circuit 1120.

[0123] In operation S403, the test control circuit 1120 may send a first memory request MRQ1 to the PHY 1130. The test control circuit 1120 may extract a DFI field from the first vector data VD1. The test control circuit 1120 may send the DFI field to the PHY 1130. For example, the test control circuit 1120 may send a first memory request MRQ1 in the first vector data VD1 to the PHY 1130.

[0124] In operation S404, the PHY 1130 may transmit a first command CMD1 to the memory device 1200. The first command CMD1 may correspond to a first memory request MRQ1. The PHY 1130 may transmit the first command CMD1 to the memory device 1200 based on the first memory request MRQ1.

[0125] In operation S405, the test control circuit 1120 may send a load command to the vector memory 1110. For example, the load command may include a second address after the first address. In operation S406, the vector memory 1110 may send second vector data VD2 including a second memory request MRQ2 to the test control circuit 1120. In operation S407, the test control circuit 1120 may send the second memory request MRQ2 to the PHY 1130. In operation S408, the PHY 1130 may send a second command CMD2 to the memory device 1200. The second command CMD2 may correspond to the second memory request MRQ2.

[0126] In operation S409, the test control circuit 1120 may send a load command to the vector memory 1110. For example, the load command may include a third address after the second address. In operation S410, the vector memory 1110 may send third vector data VD3 including a third memory request MRQ3 to the test control circuit 1120. In operation S411, the test control circuit 1120 may send the third memory request MRQ3 to the PHY 1130. In operation S412, the PHY 1130 may send a third command CMD3 to the memory device 1200. The third command CMD3 may correspond to the third memory request MRQ3.

[0127] In operation S413, the test control circuit 1120 may send a load command to the vector memory 1110. For example, the load command may include a fourth address after the third address. In operation S414, the vector memory 1110 may send fourth vector data VD4 including a fourth memory request MRQ4 to the test control circuit 1120. In operation S415, the test control circuit 1120 may send the fourth memory request MRQ4 to the PHY 1130. In operation S416, the PHY 1130 may send a fourth command CMD4 to the memory device 1200. The fourth command CMD4 may correspond to the fourth memory request MRQ4.

[0128] Typically, a memory controller may include a bank status register and a command scheduler. The bank status register may store status information about a plurality of banks in a memory device. For example, the status information may indicate whether a bank is activated or whether a bank is precharged. The command scheduler may adjust the order in which memory commands and memory addresses are processed based on the status information about the banks stored in the bank status register.

[0129] For example, the memory controller may receive a first request from the processor and then receive a second request. To improve performance, the command scheduler of the memory controller may send a second command corresponding to the second request to the memory device and then send a first command corresponding to the first request to the memory device. In this way, because the memory controller may change the processing order of the commands, it is difficult to send the commands to the memory device in the order originally set by the user or the host device.

[0130] In contrast, the test device 1100 according to the inventive concept may not include a command scheduler. The test device 1100 may not adjust the order of commands to be sent to the memory device 1200. The test device 1100 may sequentially process a plurality of vector data VD included in the test data TD. The test device 1100 may send commands to the memory device 1200 based on the vector data VD. The test device 1100 may send commands to the memory device 1200 in the order initially set by the user or the host device 1300. The test device 1100 may not change the order of commands to be sent to the memory device 1200.

[0131] For example, the test control circuit 1120 may sequentially read first vector data VD1, second vector data VD2, third vector data VD3, and fourth vector data VD4 from the vector memory 1110. The test control circuit 1120 may sequentially send a first memory request MRQ1, a second memory request MRQ2, a third memory request MRQ3, and a fourth memory request MRQ4 to the PHY 1130. The PHY 1130 may sequentially send a first command CMD1, a second command CMD2, a third command CMD3, and a fourth command CMD4 to the memory device 1200.

[0132] Fig.11 is a block diagram illustrating a memory device 1200 according to an embodiment.

[0133] Reference Figure 1 and Fig.11 , the memory device 1200 may include a memory cell array 1201, a decoder 1202, a write driver and sense amplifier 1203, a command / address decoder 1205, a serializer 1206, a deserializer 1207, and buffer circuits (i.e., a clock buffer 1208, a command / address buffer 1209, a DQS buffer 1210, and a DQ buffer 1211).

[0134] The memory cell array 1201 may include a plurality of memory cells connected to word lines and bit lines (not shown), respectively. Each of the plurality of memory cells may be configured to store data or output stored data under the control of the decoder 1202 and the write driver and sense amplifier 1203.

[0135] The decoder 1202 may control a plurality of memory cells included in the memory cell array 1201. The decoder 1202 may control the plurality of memory cells based on information (eg, a decoding result) received from the command / address decoder 1205. For example, the decoder 1202 may decode the row address RA (see Fig. 12A ) and activates a word line corresponding to the row address RA. The decoder 1202 may decode the column address COA and activate a column selection line corresponding to the column address COA.

[0136] The write driver and sense amplifier 1203 may be configured to write data to a plurality of memory cells included in the memory cell array 1201 or output data stored in the plurality of memory cells included in the memory cell array 1201 .

[0137] The command / address decoder 1205 may decode the command / address signal CA received through the command / address buffer 1209. The command / address decoder 1205 may transmit the decoding result to the decoder 1202.

[0138] The serializer 1206 may serialize read data read from the memory cell array 1201. The serialized data may be transmitted to the test device 1100 through the DQ buffer 1211. The deserializer 1207 may deserialize write data received from the test device 1100. The deserialized write data may be stored in the memory cell through the bit line.

[0139] The clock buffer 1208 may receive a clock signal CK from the test device 1100. The memory device 1200 may operate based on the received clock signal CK. The command / address buffer 1209 may receive a command / address signal CA from the test device 1100 through a command / address line.

[0140] The command / address buffer 1209 may transmit the received command / address signal CA to the command / address decoder 1205. The DQS buffer 1210 may receive a data strobe signal DQS from the test device 1100 through a data strobe line. The memory device 1200 may detect input data by sampling, capturing, or deserializing the input data using the data strobe signal DQS. The DQ buffer 1211 may receive input data from the test device 1100 through a plurality of data lines DQ.

[0141] Fig. 12A and Fig. 12B Each is a timing chart showing the operation of the test apparatus 1100 according to the embodiment.

[0142] Reference Figure 7 , Fig.11 and Fig. 12A , the memory device 1200 may receive an activation command ACT CMD. At least one word line among a plurality of word lines may be selected by a row address RA. The selected word line may be activated by an activation signal ACT. Here, for ease of description, the terms activation command ACT CMD and activation signal ACT may be used interchangeably. In addition, at least one bit line among a plurality of bit lines may be selected by a column address COA, and a read operation may be performed by a read command RD CMD (or a read command RD).

[0143] The memory cells connected to the selected word line may be activated in response to the activation signal ACT, and after a reference time interval (e.g., ACT to internal read or write delay time (tRCD)) has passed, the column address COA and the read command RD CMD may be input to the decoder 1202. Although the above embodiments have been described based on the read operation of the memory device 1200, the scope of the inventive concept is not limited thereto. For example, even in the write operation of the memory device 1200, a write command may be received after a reference time interval (e.g., tRCD) has passed from the time point when the activation command ACT CMD is received.

[0144] For example, the test device 1100 may send an active command ACT CMD and a row address RA at a first time point t1 and may send a read command RD CMD and a column address COA at a second time point t2 after a reference time interval (eg, tRCD) has elapsed from the first time point t1.

[0145] At the first time point t1, the memory device 1200 may receive an active command ACT CMD and a row address RA. In the memory device 1200, in response to the active command ACT CMD, a word line may be selected by the row address RA transmitted from the decoder 1202 to the memory cell array 1201. In addition, an active signal ACT may be transmitted to the selected word line.

[0146] Thereafter, at a second time point t2 after a reference time interval (eg, tRCD) has elapsed from the first time point t1, the memory device 1200 may receive a read command RD CMD and a column address COA. The column address COA and the read command RD CMD may be transmitted to the decoder 1202.

[0147] Reference Figure 7 , Fig.11 and Fig. 12B , the test device 1100 may send an activation command ACT CMD and a row address RA at a first time point t1. The test device 1100 may send a read command RD CMD and a column address COA at a third time point t3 after a first time interval T1 has passed from the first time point t1. The first time interval T1 may be less than a reference time interval (e.g., tRCD). For example, the PHY 1130 may send an activation command ACT CMD to the memory device 1200, and send a read command RD CMD to the memory device 1200 after a time less than the reference time interval (e.g., tRCD).

[0148] To test the memory device 1200, the test device 1100 may send a command different from the established protocol. The test device 1100 may inject an error to check whether the memory device 1200 handles the error correctly. That is, the test device 1100 may test the memory device 1200 by performing an error injection operation. The test device 1100 may check the error handling of the memory device 1200 through the error injection operation.

[0149] In one embodiment, in order to inject an error, the test device 1100 may send a command or an output signal at a time different from the time determined by the standard specification. For example, the test device 1100 may send a read command RD CMD after a first time interval T1 less than a reference time interval (e.g., tRCD) has passed from a time point (i.e., t1) when the activation command ACT CMD is sent. However, the scope of the inventive concept is not limited thereto, and various reference time intervals determined by the standard may be adjusted.

[0150] In one embodiment, in order to inject errors, the test device 1100 may send commands or output signals with values ​​different from those determined by the standard specification. The test device 1100 may send invalid commands that violate the standard specification to the memory device 1200. For example, the test device 1100 may set and output signal values ​​different from the signal values ​​in the command truth table determined by the standard specification. The test device 1100 may send all (or most) commands implemented in the ATE to the memory device 1200 and test the commands.

[0151] The test device 1100 may adjust the time interval between commands (the number of switching times of the clock signal) by using the operand OPERAND included in the vector data VD. The test device 1100 may send a command that does not comply with the standard specification to the memory device 1200. For example, the test device 1100 may adjust the time interval between commands by decreasing or increasing the value of the operand OPERAND of the vector data VD.

[0152] For example, in order to inject an error, the test device 1100 may send an activation command ACT CMD at a first time point t1, and may send a read command RD CMD at a third time point t3 after the first time interval T1. The test device 1100 may reduce the time interval (or the number of switching times of the clock signal) between the activation command ACT CMD and the read command RD CMD by reducing the value of the operand OPERAND of the vector data VD.

[0153] As described above, a test device including a memory controller may have difficulty in performing an error injection operation. In contrast, the test device 1100 according to an embodiment may perform a test operation based on the vector data VD. The vector data VD may include a DFI signal without change. The test control circuit 1120 may send the DFI signal to the PHY 1130 without change. For example, in order to perform an error injection operation, the test device 1100 may perform a test operation on the memory device 1200 based on the test data generated by the host device 1300. The test device 1100 may perform the same function as ATE.

[0154] Fig.13is a flowchart illustrating an example of an operating method of the test system 1000 according to an embodiment.

[0155] The memory device 1200 may enter an active state from an idle state in response to an activation command ACT. The active state may refer to a state in which a selected word line is activated. The memory device 1200 in an active state, a write state, or a read state may enter a write state or a read state in response to a write command WR or a read command RD, and may enter an active state after performing a write operation (i.e., an operation of writing data to a memory cell) or a read operation (i.e., an operation of outputting data).

[0156] The memory device 1200 in the active state, the write state, or the read state may enter the write state or the read state in response to the write command WRA with automatic precharge or the read command RDA with automatic precharge, and may enter the precharge state after performing the write operation or the read operation. The write command WRA with automatic precharge or the read command RDA with automatic precharge may be a command for performing a precharge operation after completing the write operation or the read operation without a separate precharge command PRE.

[0157] The memory device 1200 in the active state, the write state, or the read state may enter the precharge state in response to the precharge command PRE. The memory device 1200 in the precharge state may enter the idle state after completing the precharge operation.

[0158] Reference Figure 1 and Fig.13 , in operation S510, the test device 1100 may send a first write command WR1 to the memory device 1200. In operation S520, the test device 1100 may send a first write command WRA1 with automatic precharge to the memory device 1200. In operation S530, the test device 1100 may send a second write command WR2 to the memory device 1200. In operation S540, the test device 1100 may send a second write command WRA2 with automatic precharge to the memory device 1200. For example, the PHY 1130 may sequentially send the first write command WR1, the first write command WRA1 with automatic precharge, the second write command WR2, and the second write command WRA2 with automatic precharge to the memory device 1200.

[0159] Although the above embodiments have been described based on the write operation of the memory device 1200 , the scope of the inventive concept is not limited thereto. For example, the test device 1100 may perform a test on the memory device 1200 by using a combination of a read command RD and a read command RDA with auto precharge.

[0160] Typically, the memory controller may not send a write command WR and a write command WRA with automatic precharge in combination to the memory device 1200. That is, the memory controller may send only a plurality of write commands WR. Alternatively, the memory controller may send only a plurality of write commands WRA with automatic precharge. In addition, the memory controller may not send a read command RD and a read command RDA with automatic precharge in combination to the memory device 1200. That is, the memory controller may send only a plurality of read commands RD. Alternatively, the memory controller may send only a plurality of read commands RDA with automatic precharge. In this way, due to the limitation of the memory controller, a test device including a memory controller may not be able to replace an ATE device. A test device including a memory controller may not be able to perform various tests on the memory device 1200.

[0161] In contrast, the test device 1100 according to an embodiment may perform a test in which a write command WR and a write command WRA with automatic precharge are combined. For example, the test device 1100 may send a write command WR and a write command WRA with automatic precharge to the memory device 1200 in combination. The test device 1100 may perform a test operation based on the vector data VD, and may send a DFI signal included in the vector data VD to the PHY 1130 without conversion. The test device 1100 may perform tests of various sequences or patterns. Therefore, the test device 1100 may have an increased test coverage.

[0162] Fig.14 is a flowchart illustrating an example of an operating method of the test system 1000 according to an embodiment.

[0163] In operation S610, the test device 1100 may receive test data from the host device 1300. For example, the host device 1300 may generate test data including a plurality of vector data VD. The host device 1300 may store the test data in the vector memory 1110 of the test device 1100.

[0164] In operation S620, the test device 1100 may perform a write test based on the plurality of vector data VD. The test control circuit 1120 may send a memory request (e.g., a write request), a memory address, and memory data included in the vector data VD to the PHY 1130. The PHY 1130 may send a write command and an address to the memory device 1200 through a command / address line. The PHY 1130 may send data to the memory device 1200 through a plurality of data lines. The test control circuit 1120 may write data to the memory device 1200.

[0165] In operation S630, the test device 1100 may perform a read test based on the plurality of vector data VD. The test control circuit 1120 may send a memory request (e.g., a read request) and a memory address included in the vector data VD to the PHY 1130. The PHY 1130 may send a read command and an address to the memory device 1200 through a command / address line. The PHY 1130 may receive data from the memory device 1200 through a plurality of data lines.

[0166] The test control circuit 1120 may detect defects in the memory device 1200 by comparing read data received from the memory device 1200 with expected data included in the vector data VD. The test control circuit 1120 may store the test result in the buffer memory 1124. The test result may include information about defects occurring in a write or read operation.

[0167] In operation S640, the test device 1100 may transmit the test result to the host device 1300. For example, in order to confirm and analyze defects in the memory device 1200 based on the test result, the host device 1300 may transmit a test result request to the test device 1100. The test device 1100 may transmit the test result stored in the buffer memory 1124 to the host device 1300.

[0168] In one embodiment, if no defect occurs in the memory device 1200, the test device 1100 may not generate a test result. When the test result is not stored in the buffer memory 1124, the test device 1100 may not send the test result in response to the test result request received from the host device 1300. Alternatively, the test device 1100 may send dummy data to the host device 1300. For example, the dummy data may be a signal having a logic level of "0".

[0169] In another embodiment, if the DUT is not present, the test device 1100 may not generate and transmit a test result in response to a test result request received from the host device 1300 .

[0170] In one embodiment, the host device 1300 may determine the success or failure of the test operation based on the presence or absence of the test result. For example, when there is no test result in the buffer memory 1124, the host device 1300 may determine that the test operation is successful (i.e., the memory device 1200 is not defective). When there is a test result in the buffer memory 1124, the host device 1300 may determine that the test operation fails (i.e., the memory device 1200 has a defect).

[0171] Fig.15 is a block diagram illustrating a test system 2000 according to an embodiment.

[0172] Reference Fig.15 , the test system 2000 may include a test device 2100, a plurality of memory devices (eg, first to fourth memory devices 2210, 2220, 2230, and 2240), and a host device 2300. The test device 2100 may include a vector memory 2110, a test control circuit 2120, a PHY 2130, and a host interface circuit 2140. As shown in FIG. Figures 1 to 3 , Figure 4A , Figure 4B , Figures 5 to 11 , Fig. 12A , Fig. 12B , Fig.13 and Fig.14 As described, the testing device 2100 can perform testing operations.

[0173] The test device 2100 may perform a test operation on the first to fourth memory devices 2210, 2220, 2230, and 2240. For example, the test device 2100 may simultaneously test the first to fourth memory devices 2210, 2220, 2230, and 2240. However, the scope of the inventive concept is not limited thereto, and the number of memory devices may be increased or decreased according to implementation.

[0174] The test device 2100 may communicate with the first to fourth memory devices 2210, 2220, 2230, and 2240 through a plurality of channels (e.g., the first to fourth channels CH1 to CH4). For example, the test device 2100 may communicate with the first memory device 2210 through the first channel CH1, may communicate with the second memory device 2220 through the second channel CH2, may communicate with the third memory device 2230 through the third channel CH3, and may communicate with the fourth memory device 2240 through the fourth channel CH4. In example embodiments, a command / address signal CA, a clock signal CK, a data signal DQ, and a data strobe signal DQS may be provided to each of the first to fourth channels CH1 to CH4.

[0175] In example embodiments, a command / address signal CA may be commonly provided to the first to fourth memory devices 2210 , 2220 , 2230 , and 2240 , and a clock signal CK may be commonly provided to the first to fourth memory devices 2210 , 2220 , 2230 , and 2240 .

[0176] In example embodiments, the first command / address signal CA may be commonly provided to the first memory device 2210 and the second memory device 2220, and the first clock signal CK may be commonly provided to the first memory device 2210 and the second memory device 2220. The second command / address signal CA may be commonly provided to the third memory device 2230 and the fourth memory device 2240, and the second clock signal CK may be commonly provided to the third memory device 2230 and the fourth memory device 2240.

[0177] For example, the test device 2100 may test the first memory device 2210 through the first channel CH1. The test device 2100 may test the second memory device 2220 through the second channel CH2. The test device 2100 may test the third memory device 2230 through the third channel CH3. The test device 2100 may test the fourth memory device 2240 through the fourth channel CH4.

[0178] Typically, ATE equipment may have a per-pin architecture. Therefore, the ATE device may require multiple ASICs to generate signals for one DUT. In contrast, the test device 1100 according to the embodiment can perform test operations on multiple memory devices or DUTs at the same time. Therefore, when implementing the test system, the cost and space used to manufacture the equipment can be reduced.

[0179] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the invention as set forth in the following claims.

Claims

1. A testing device, comprising: A vector memory configured to store a plurality of vector data; a test control circuit configured to test the external memory device by: receiving first vector data among the plurality of vector data, sending a first memory request, a memory address, and memory data included in the first vector data, and comparing read data from the external memory device with expected data; as well as a physical layer configured to: communicate with an external memory device through a data line and a command / address line, output a first command corresponding to a first memory request and an address corresponding to a memory address through the command / address line, output write data corresponding to memory data through the data line, receive the first memory request, the memory address, and the memory data from a test control circuit, and receive read data from the external memory device through the data line, The first vector data includes a first memory request, a memory address, memory data and expected data.

2. The testing device according to claim 1, wherein: The physical layer includes a double data rate physical layer intellectual property block.

3. The testing device according to claim 1, wherein: The test control circuit and the physical layer communicate with each other according to a double data rate physical layer interface.

4. The testing device according to claim 1, wherein: The first memory request, the memory address, and the memory data comprise signals defined by a double data rate physical layer interface standard.

5. The testing device according to claim 1, wherein: The test control circuit includes: A sequencer configured to: load first vector data from a vector memory, and send the first vector data; A command decoder configured to: receive first vector data from a sequencer, send a first memory request, a memory address and memory data in the first vector data to a physical layer, and send a compare enable signal and expected data in the first vector data; a comparator configured to: receive a comparison enable signal and expected data from a command decoder, receive read data from a physical layer, generate a fail entry based on a comparison result between the read data and the expected data, and transmit the fail entry; and A buffer memory is configured to receive the failed entries from the comparator.

6. The testing device according to claim 5, wherein: The sequencer is also configured to: Receive a starting address from an external host device, and reading first vector data from the vector memory in response to the start address, and The buffer memory is further configured to send the test result including the plurality of failed entries to the external host device in response to a test result request command received from the external host device.

7. The testing device according to claim 5, wherein: The first vector data includes a command field, a double data rate physical layer interface field and a comparison field, The command field includes the operation code and operand. The double data rate physical layer interface field includes a first memory request, a memory address, and memory data, and The compare field includes a compare enable signal and expected data.

8. The testing device according to claim 7, wherein: The command decoder includes: a first-in-first-out memory configured to: store first vector data received from a sequencer, send a command field in response to a first-in-first-out enable signal, send a double data rate physical layer interface field to the physical layer, and send a comparison field to a comparator; an opcode decoder configured to: receive a command field from the FIFO memory, perform a decoding operation based on the opcode, output a stop signal to the sequencer in response to the opcode indicating a stop code, and send an operand in response to the opcode indicating a loop code; and The loop counter is configured to: receive an operand from an opcode decoder, set the operand to a count value, and output a first-in-first-out enable signal after a number of clock cycles corresponding to the count value.

9. The testing device according to claim 1, wherein: The plurality of vector data further includes second to fourth vector data, The second vector data includes a second memory request, The third vector data includes a third memory request, The fourth vector data includes a fourth memory request, and The test control circuit is further configured to sequentially read first, second, third and fourth vector data from the vector memory and sequentially send first, second, third and fourth memory requests to the physical layer.

10. The testing device according to claim 9, wherein: The physical layer is further configured to sequentially send the first command, the second command corresponding to the second memory request, the third command corresponding to the third memory request, and the fourth command corresponding to the fourth memory request to the external memory device.

11. The testing device according to any one of claims 1 to 10, wherein: The physical layer is also configured to sequentially send a first write command, a first write command with auto-precharge, a second write command, and a second write command with auto-precharge to the external memory device.

12. The testing device according to any one of claims 1 to 10, wherein: The physical layer is further configured to send the activate command and send the read command after a time interval that is less than the reference time interval.

13. An operating method of a test device, the test device comprising a physical layer, a vector memory and a test control circuit, the operating method comprising: receiving, by the test control circuit, vector data stored in the vector memory; sending, by the test control circuit, a memory request, a memory address and memory data included in the vector data to the physical layer; The physical layer sends a command corresponding to the memory request and an address corresponding to the memory address to the external memory device through a command / address line; as well as Data corresponding to the memory data is sent to the external memory device by the physical layer through the data line.

14. The operating method according to claim 13, further comprising: The test control circuit receives a test start request and a start address from an external host device; In response to the test start request, the test control circuit sends a load command to the vector memory to load vector data from the vector memory; receiving, by the vector memory, test data including a plurality of vector data from an external host device; as well as The test data is stored in the vector memory.

15. The operating method according to claim 13, further comprising: receiving data from an external memory device by the physical layer; The physical layer sends the data as read data to the test control circuit; comparing, by the test control circuit, the read data with expected data included in the vector data; and When the read data differs from the expected data, a failure entry is generated and stored.

16. The operating method according to claim 15, further comprising: receiving, by the test control circuit, a test result request from an external host device; as well as In response to the test result request, the test control circuit sends the test result including the plurality of failed entries to the external host device, The test results include memory address, read data, and expected data.

17. The operating method according to any one of claims 13 to 16, further comprising: determining, by the test control circuit, whether an operation code included in the vector data is a stop code; When the operation code is a stop code, the test control circuit stops the loading operation of loading vector data from the vector memory; as well as When the loading operation stops, a test end signal is sent to the external host device by the test control circuit.

18. A testing system comprising: Test equipment; and a memory device, The test device includes: A vector memory configured to store a plurality of vector data; a test control circuit configured to test a memory device by receiving first vector data among the plurality of vector data, sending a memory request, a memory address, and memory data included in the first vector data, and comparing read data from the memory device with expected data included in the first vector data to generate and store a test result; and a physical layer configured to communicate with a memory device through a data line and a command / address line, output a command corresponding to a memory request and an address corresponding to a memory address through the command / address line, output write data corresponding to memory data through the data line, and receive read data through the data line, Wherein, the physical layer includes the intellectual property block, and Wherein, the memory request, the memory address and the memory data comprise signals defined by a double data rate physical layer interface standard.

19. The test system according to claim 18, wherein: The test control circuit includes: A sequencer configured to: load first vector data from a vector memory, and send the first vector data; A command decoder configured to: receive first vector data from a sequencer, send a memory request, a memory address and memory data in the first vector data to a physical layer, and send a comparison enable signal and expected data in the first vector data; a comparator configured to receive a comparison enable signal and expected data from a command decoder, receive read data from a physical layer, and send a fail entry based on a comparison result between the read data and the expected data; and A buffer memory is configured to receive the failed entries from the comparator.

20. The test system of claim 19, wherein: The first vector data includes a command field, a double data rate physical layer interface field and a comparison field, The command field includes the operation code and operand. The double data rate physical layer interface fields include memory request, memory address, and memory data. The compare field includes a compare enable signal and expected data, and The command decoder includes: a first-in-first-out memory configured to: store first vector data received from a sequencer, send a command field in response to a first-in-first-out enable signal, send a double data rate physical layer interface field to the physical layer, and send a comparison field to a comparator; an opcode decoder configured to: receive a command field from the FIFO memory, perform a decoding operation based on the opcode, output a stop signal to the sequencer in response to the opcode indicating a stop code, and send an operand in response to the opcode indicating a loop code; and The loop counter is configured to: receive an operand from an opcode decoder, set the operand to a count value, and output a first-in-first-out enable signal after a number of clock cycles corresponding to the count value.

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