A silicon wafer and a method, device, apparatus and medium for improving the warpage of a silicon wafer

Abstract

The present disclosure provides a silicon wafer and a method, device, equipment and medium for improving the warping degree of the silicon wafer, the method comprising: obtaining the warping state of the silicon wafer and a measurement value of the warping degree; when the warping state of the silicon wafer is convex warping, determining a first thickness and a first number of thin film deposition processes according to the measurement value of the warping degree and a target thickness, and performing a thin film deposition process according to the first thickness and the first number of thin film deposition processes to form a back sealing thin film conforming to the target thickness; when the warping state of the silicon wafer is concave warping, determining a second thickness and a second number of thin film deposition processes according to the measurement value of the warping degree and the target thickness, and performing a thin film deposition process according to the second thickness and the second number of thin film deposition processes to form a back sealing thin film conforming to the target thickness.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing technology, and in particular to a silicon wafer and a method, apparatus, device and medium for improving the warpage of the silicon wafer. Background Technology

[0002] In semiconductor manufacturing processes, the warpage of monocrystalline silicon wafers affects both wafer quality and the overall process. For example, during photolithography, if the wafer deforms, its surface becomes uneven, preventing the mask structure from forming a clear image and thus impacting etching accuracy. As manufacturing processes continue to advance, the structural precision of semiconductor devices also increases; therefore, it is necessary to control the warpage of monocrystalline silicon wafers within increasingly stringent limits.

[0003] For doped silicon wafers in monocrystalline silicon, it is necessary to prevent self-doping during the epitaxial growth stage. This occurs because, under the high-temperature environment of epitaxial growth, dopants diffuse outward from the front and back sides of the silicon wafer, mixing with the reactive gases and depositing to form the epitaxial layer. This leads to resistivity drift, severely impacting the quality of the silicon wafer. Back-sealing technology is a commonly used method to prevent self-doping. It involves depositing a back-sealing film, such as silicon dioxide, on the back of the silicon wafer to enclose dopant atoms within the wafer, effectively suppressing dopant diffusion.

[0004] Currently, the warpage of back-sealed silicon wafers is poor, and how to improve the warpage of back-sealed silicon wafers is a problem that needs to be solved. Summary of the Invention

[0005] This disclosure provides a silicon wafer and a method, apparatus, device, and medium for improving the warpage of the silicon wafer; it can reduce the warpage of the back-sealed silicon wafer, thereby improving the flatness of the back-sealed silicon wafer.

[0006] The technical solution disclosed herein is implemented as follows:

[0007] In a first aspect, this disclosure provides a method for improving the warpage of a silicon wafer, the method comprising:

[0008] Obtain the warp state and warp degree measurement of the silicon wafer;

[0009] When the warpage of the silicon wafer is convex warpage, a first thickness and a first number of thin film deposition processes are determined based on the warpage measurement and the target thickness, and a thin film deposition process is performed according to the first thickness and the first number of thin film deposition processes to form a back sealing film that conforms to the target thickness; the convex warpage indicates that the center part of the front side of the silicon wafer is higher than the edge part, and the back sealing film layer of the first thickness generates tensile stress on the back surface of the silicon wafer;

[0010] When the warpage of the silicon wafer is concave, a second thickness and a second number of thin film deposition processes are determined based on the warpage measurement and the target thickness. A thin film deposition process is then performed according to the second thickness and the second number of thin film deposition processes to form a back seal film that conforms to the target thickness. The concave warpage indicates that the center portion of the front side of the silicon wafer is lower than the edge portion. The back seal film layer of the second thickness generates compressive stress on the back cover of the silicon wafer.

[0011] Secondly, this disclosure provides an apparatus for improving the warpage of silicon wafers, the apparatus comprising: an acquisition unit, a determination unit, and an execution unit; wherein,

[0012] The acquisition unit is configured to acquire the warpage state of the silicon wafer and a measure of the warpage degree.

[0013] The determining unit is configured to determine a first thickness and a first thin film deposition process number based on the warp degree measurement and the target thickness when the warp state of the silicon wafer is convex warp. The convex warp indicates that the center portion of the front side of the silicon wafer is higher than the edge portion, and the back sealing film layer of the first thickness generates tensile stress on the back cover of the silicon wafer.

[0014] Furthermore, when the warpage of the silicon wafer is concave warpage, a second thickness and a second thin film deposition process number are determined based on the warpage measurement and the target thickness. The concave warpage indicates that the center portion of the front side of the silicon wafer is lower than the edge portion, and the back sealing film layer of the second thickness generates compressive stress on the back cover of the silicon wafer.

[0015] The execution unit is configured to perform a thin film deposition process to form a back seal film conforming to the target thickness according to the first thickness and the first number of thin film deposition processes when the warp state of the silicon wafer is convex warp; and to perform a thin film deposition process to form a back seal film conforming to the target thickness according to the second thickness and the second number of thin film deposition processes when the warp state of the silicon wafer is concave warp.

[0016] Thirdly, this disclosure provides a computing device including a processor and a memory; the processor is configured to execute instructions stored in the memory to implement the method for improving silicon wafer warpage as described in the first aspect.

[0017] Fourthly, this disclosure provides a computer-readable storage medium storing at least one instruction that is executed by a processor to implement the method for improving silicon wafer warpage as described in the first aspect.

[0018] Fifthly, this disclosure provides a silicon wafer, wherein a back sealing film is formed on the back side of the silicon wafer according to the method for improving the warpage of the silicon wafer described in the first aspect, and the warpage of the silicon wafer is measured in the range of [0, 500].

[0019] This disclosure provides a silicon wafer and a method, apparatus, device, and medium for improving the warpage of the silicon wafer; the warpage of the silicon wafer is improved by utilizing the relationship between the thickness of the back sealing film layer and the stress generated therefrom, thereby reducing the warpage of the silicon wafer after back sealing deposition and improving the flatness of the silicon wafer after back sealing deposition. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the deposition chamber provided in this disclosure.

[0021] Figure 2 This is a schematic flowchart of a method for improving silicon wafer warpage provided in this disclosure.

[0022] Figure 3 A in the diagram is a schematic diagram of the convex warping state provided in this disclosure.

[0023] Figure 3 B in the diagram is a schematic diagram of the concave warped state provided in this disclosure.

[0024] Figure 4 Box plot of Embodiment 1 provided in this disclosure.

[0025] Figure 5 Box plot of Embodiment 2 provided in this disclosure.

[0026] Figure 6 Box plot of Embodiment 3 provided in this disclosure.

[0027] Figure 7 Box plot of Embodiment 4 provided in this disclosure.

[0028] Figure 8 Box plot of Embodiment 5 provided in this disclosure.

[0029] Figure 9 Box diagram of Embodiment Six provided in this disclosure.

[0030] Figure 10 Box plot of Embodiment Seven provided in this disclosure.

[0031] Figure 11 Box plot of Embodiment 8 provided in this disclosure.

[0032] Figure 12 This is a schematic diagram comparing the measurement values ​​of silicon wafer warpage before and after performing a thin film deposition process, as provided in this disclosure.

[0033] Figure 13 This is a schematic diagram comparing the measurement values ​​of silicon wafer warpage before and after performing another thin film deposition process, as provided in this disclosure.

[0034] Figure 14 This is a schematic diagram of an apparatus for improving silicon wafer warpage provided in this disclosure.

[0035] Figure 15 This is a schematic diagram of the structure of a computing device provided in this disclosure. Detailed Implementation

[0036] The technical solutions in this disclosure will now be clearly and completely described with reference to the accompanying drawings.

[0037] In order to clearly distinguish the two surfaces of the silicon wafer in the future, in this disclosure, the front surface of the silicon wafer is the surface on which the silicon wafer is patterned during the semiconductor device manufacturing process, while the surface on the silicon wafer opposite to the front surface is the back surface.

[0038] See Figure 1 This illustrates a schematic diagram of a deposition chamber structure applicable to the method for improving silicon wafer warpage proposed in this disclosure. For example... Figure 1 As shown, the deposition chamber 1 includes a support stage 11 for supporting the silicon wafer W to be back-sealed, and a reaction gas (such as...) is disposed above the support stage 11 for spraying reaction gas onto the back of the silicon wafer W. Figure 1 The spraying device 12 (shown by the dashed arrow) and the heating device 13 located below the support stage 11 for heating the silicon wafer W to the temperature required for the deposition reaction are described. In some examples, the front side of the silicon wafer W is in contact with the support stage 11, such that the back side of the silicon wafer W faces the spraying device 12 to chemically react with the reactive gases. In some examples, the reactive gases can be silicon source gases and oxygen source gases, such as silane (SiH4) and nitrous oxide (N2O). These reactive gases chemically react with the back side of the silicon wafer W under the high-temperature environment provided by the heating device 13, thereby depositing a back-sealing film on the back side of the silicon wafer W. This process of forming the back-sealing film can be referred to as the back-sealing deposition process in this disclosure.

[0039] During the back-sealing deposition process, the high-temperature environment reduces the hardness of the silicon wafer, and the weight of the silicon wafer affects its flatness. Furthermore, the stress of the back-sealing film also affects the flatness of the silicon wafer. These combined effects can easily lead to a deterioration in the flatness of the back-sealed silicon wafer. To eliminate this deterioration, this disclosure uses the bending of the wafer (BOW) as an evaluation index for flatness and provides a method for improving the bending of the silicon wafer, such as... Figure 2 As shown, the method includes:

[0040] S201: Obtain the warp state of the silicon wafer and the measurement of the warp degree.

[0041] In this disclosure, silicon wafers with poor flatness are typically in two warp states: convex warp and concave warp. Specifically, they are as follows: Figure 3 (A) and Figure 3 As shown in (B), convex warpage indicates that the center of the silicon wafer's front side is higher than the edge, while concave warpage indicates that the center of the silicon wafer's front side is lower than the edge. For both warpage states, the degree of warpage is measured by the vertical distance between the highest and lowest points on the silicon wafer's front side. Understandably, in convex warpage, the highest point on the silicon wafer's front side is at the center, and the lowest point is at the edge. In concave warpage, the highest point is at the edge, and the lowest point is at the center. In some examples, when the silicon wafer is convexly warped, the center of the front side is higher than the edge, resulting in a positive warpage. When the silicon wafer is concavely warped, the center is lower than the edge, resulting in a negative warpage.

[0042] Before the back-sealing deposition process via the aforementioned deposition chamber, the warpage state and warpage measure of the silicon wafer to be back-sealed can be detected using flatness detection methods. In some examples, a beam of light can first be split into two beams using double-sided interference in polar coordinates with the center of the front side of the silicon wafer as the pole, and these beams can be used to illuminate the front and back sides of the silicon wafer respectively to obtain the reflected light from the front and back sides of the silicon wafer. Then, the reflected light is combined to generate interference fringes formed by the phase difference between the two reflected beams. Next, the phase difference between the two reflected beams is measured by measuring the interference fringes, and the morphology information of the front side of the silicon wafer is calculated based on the phase difference. Subsequently, the warpage state of the silicon wafer is determined to be convex or concave based on the morphology information, and when the warpage state is convex or concave, the difference between the maximum and minimum height values ​​in the morphology information of the front side of the silicon wafer is determined as the warpage measure. Specifically, the height data of each sampling point on the front side of the silicon wafer can be measured using contact or non-contact measurement methods. After obtaining the height data of all sampling points, a fitted surface of the front side of the silicon wafer is obtained through fitting. Based on this fitted surface, it is possible to analyze whether the warpage of the silicon wafer is convex or concave, and calculate the warpage measure based on the difference between the maximum and minimum height values ​​in the fitted surface.

[0043] S202: When the warpage of the silicon wafer is convex, the first thickness and the first number of thin film deposition processes are determined according to the warpage measurement and the target thickness, and the thin film deposition process is performed according to the first thickness and the first number of thin film deposition processes to form a back sealing film that meets the target thickness.

[0044] S203: When the warpage of the silicon wafer is concave, determine the second thickness and the number of second thin film deposition processes based on the warpage measurement and the target thickness, and perform the thin film deposition process according to the second thickness and the number of second thin film deposition processes to form a back sealing film that meets the target thickness.

[0045] Specifically, the stress in the back-sealing film originates from the difference in the coefficients of thermal expansion between different materials. That is, under the same temperature change, the back-sealing film and the silicon wafer have different coefficients of thermal expansion, leading to differences in the rates of expansion and contraction. This generates stress at the interface between the back-sealing film and the silicon wafer. This stress stretches or compresses the back side of the silicon wafer where the back-sealing film is deposited; these are referred to as tensile stress and compressive stress, respectively. The inventors have discovered that as the thickness of the back-sealing film increases, the stress generated by the film changes accordingly, even transitioning between tensile and compressive stress. Based on this discovery, this disclosure utilizes the relationship between the thickness of the back-sealing film layer and the stress it generates to improve the warpage of the silicon wafer, thereby reducing the warpage of the silicon wafer after back-sealing deposition and improving its flatness.

[0046] The following examples illustrate the relationship between the thickness of the back sealing film layer and the stress it generates.

[0047] Example 1

[0048] Setting based on Figure 1 The deposition chamber shown employs atmospheric pressure chemical vapor deposition (APCVD) as the thin film deposition process, with a deposition temperature of 450 degrees Celsius. The back-sealing film is made of silicon dioxide. Based on these settings, a 500 angstrom back-sealing film is deposited on 16 silicon wafers with an average warpage of 1408.39 nm. Figure 4 As shown, the average warpage of the deposited silicon wafer is 1069.79 nm. This demonstrates that a 500 angstrom back-sealing film can provide tensile stress on the back side of the silicon wafer to reduce its concave warpage, and the warpage reduction metric is 338.6 nm, meaning the absolute value of the average warpage is reduced by 338.6 nm.

[0049] Example 2

[0050] Consistent with the setup in Example 1, a back-sealing film with a thickness of 750 angstroms was deposited on 16 silicon wafers to be back-sealed, with an average warpage of 2551.95. Figure 5 As shown, the average warpage of the deposited silicon wafer is 1680.55 nm. This indicates that the 750 angstrom back seal film can provide tensile stress on the back side of the silicon wafer to reduce the degree of convex warpage of the silicon wafer, and the warpage elimination metric is 871.4 nm, that is, the absolute value of the average warpage is reduced by 871.4 nm.

[0051] Example 3

[0052] Consistent with the setup in Example 1, a back-sealing film with a thickness of 1000 angstroms was deposited on 16 silicon wafers to be back-sealed, with an average warpage of 1784.12 nm. Figure 6 As shown, the average warpage of the deposited silicon wafer is 543.89 nm. This indicates that the 1000 angstrom back seal film can provide tensile stress on the back side of the silicon wafer to reduce the degree of convex warpage of the silicon wafer, and the warpage elimination metric is 1240.23 nm, that is, the absolute value of the average warpage is reduced by 1240.23 nm.

[0053] Example 4

[0054] Consistent with the setup in Example 1, a back-sealing film with a thickness of 1200 angstroms was deposited on 16 silicon wafers to be back-sealed, with an average warpage of 1042.57 nm. Figure 7 As shown, the average warpage of the deposited silicon wafer is -145.91 nm. This indicates that the 1200 angstrom back seal film can provide tensile stress on the back side of the silicon wafer to reduce the degree of convex warpage. The warpage elimination metric is 1188.48 nm, which means that the absolute value of the average warpage is reduced by 1188.48 nm.

[0055] Example 5

[0056] Consistent with the setup in Example 1, a back-sealing film with a thickness of 1500 angstroms was deposited on 16 silicon wafers to be back-sealed, with an average warpage of 1324.26 nm. Figure 8 As shown, the average warpage of the deposited silicon wafer is 671.44 nm. This indicates that the 1500 angstrom back seal film can provide tensile stress on the back side of the silicon wafer to reduce the degree of convex warpage of the silicon wafer, and the warpage elimination metric is 652.82 nm, that is, the absolute value of the average warpage is reduced by 652.82 nm.

[0057] Example 6

[0058] Consistent with the setup in Example 1, a back-sealing film with a thickness of 2000 angstroms was deposited on 16 silicon wafers to be back-sealed, with an average warpage of -1201.23 nm. Figure 9 As shown, the average warpage of the deposited silicon wafer is 711.27 nm. This indicates that a 2000 angstrom back seal film can provide compressive stress on the back side of the silicon wafer to reduce the concave warpage of the wafer, and the warpage elimination metric is 1912.5 nm.

[0059] Example 7

[0060] Consistent with the setup in Example 1, a back-sealing film with a thickness of 2200 angstroms was deposited on 16 silicon wafers to be back-sealed, with an average warpage of -2383.91 nm. Figure 10 As shown, the average warpage of the deposited silicon wafer is -292.84 nm. This indicates that the 2200 angstrom back seal film can provide compressive stress on the back side of the silicon wafer to reduce the concave warpage of the silicon wafer, and the warpage elimination metric is 2091.07 nm.

[0061] Example 8

[0062] Consistent with the setup in Example 1, a back-sealing film with a thickness of 2500 angstroms was deposited on 16 silicon wafers to be back-sealed, with an average warpage of -2618.77 nm. Figure 11 As shown, the average warpage of the deposited silicon wafer is -882.15 nm. This indicates that the 2500 angstrom back seal film can provide compressive stress on the back side of the silicon wafer to reduce the concave warpage of the silicon wafer, and the warpage elimination metric is 1736.62 nm.

[0063] Analysis of the results of the above eight embodiments shows that when the silicon wafer to be back-sealed is convex and warped, the degree of convex warping can be reduced by depositing a back-sealing film layer with a first thickness of 500 to 1500 angstroms. When the silicon wafer to be back-sealed is concave and warped, the degree of concave warping can be reduced by depositing a back-sealing film layer with a second thickness of 2000 to 2500 angstroms.

[0064] In detail, when the thickness of the back-sealing film layer is between 500 and 1500 angstroms, its deposition thickness is relatively small, resulting in less accumulation of internal stress and defects. This allows the molecules and atoms of the film to arrange themselves more orderly during the back-sealing deposition process, thus forming a film layer with a uniform structure and regular grain arrangement. Under such conditions of a film layer with a uniform structure and regular grain arrangement, due to the thermal expansion coefficient of silicon dioxide (0.5 × 10⁻⁶), -6 The coefficient of thermal expansion ( / K) is less than that of monocrystalline silicon (2.5×10). -6 / K), which means that the film expands less than the silicon wafer when the temperature changes, thus creating tensile stress on the back side of the silicon wafer (i.e., the back cover), thereby reducing the degree of convex warpage of the silicon wafer when viewed from the front side. It is worth noting that, in conjunction with Examples 6 to 8, it can be seen that when the first thickness is in the range of 750 angstroms to 1200 angstroms, the warpage elimination metric is higher than that of other thickness values ​​in the range of 500 angstroms to 1500 angstroms. In other words, when the first thickness is in the range of 750 angstroms to 1200 angstroms, its ability to reduce the degree of convex warpage is stronger.

[0065] When the thickness of the back-sealing film layer is 2000 to 2500 angstroms, its deposition thickness is relatively large, resulting in greater accumulation of internal stress and defects. This leads to poor regularity in the molecular and atomic arrangement of the film during the back-sealing deposition process, making it impossible to form a film layer with a uniform structure and regular grain arrangement. Furthermore, a longer relaxation time is required to reach equilibrium, thus creating compressive stress on the back side of the silicon wafer (i.e., the back cover). Consequently, from the front view of the silicon wafer, this reduces the degree of concave warp. It is worth noting that, combining Examples 1 to 5, it can be seen that when the second thickness is in the range of 2000 to 2200 angstroms, the warp reduction metric value is higher than other thickness values ​​in the 2000 to 2500 angstrom range. In other words, when the second thickness is in the range of 2000 to 2200 angstroms, its ability to reduce the degree of concave warp is stronger.

[0066] By analyzing the comparative results of Examples 1 to 8 above, the correspondence between the thickness of the back-sealing film layer and the stress it generates can be obtained. This allows for the selection of appropriate thin-film deposition processes for different warpage states and degrees of silicon wafers, thereby reducing wafer warpage. Understandably, as the number of silicon wafers used in the experiments increases, the accuracy of this correspondence will further improve.

[0067] In some examples, when the silicon wafer is in a convex warp state, determining the first thickness and the number of first thin film deposition processes based on a measure of warp degree and a target thickness includes:

[0068] Based on the target thickness and the range of the first thickness, multiple first candidate groups are selected, consisting of candidate values ​​of the first thickness and the corresponding number of first thin film deposition processes;

[0069] For each candidate value of the first thickness and the corresponding candidate value of the first thin film deposition process number in each first candidate group, obtain the warpage elimination metric value for each first candidate group;

[0070] Based on the warp measure and the warp elimination measure corresponding to each candidate group, the first candidate group with the smallest absolute value of the difference is selected from all first candidate groups;

[0071] The first thickness candidate value and the corresponding first thin film deposition process number candidate value in the first candidate group with the smallest absolute value of the difference are determined as the first thickness and the first thin film deposition process number.

[0072] In the above example, specifically, the thickness of the back-sealing film to be deposited on the silicon wafer is usually fixed, which may be referred to as the target thickness in this disclosure. By selecting multiple first thicknesses within a first thickness range and sequentially performing the back-sealing deposition process, a back-sealing film of the target thickness can be deposited. The number of times the back-sealing deposition process is performed is the number of first film deposition processes. For example, taking a target thickness of 2000 angstroms as an example, this can be achieved by performing two back-sealing deposition processes (i.e., the number of first film deposition processes is 2), with each back-sealing deposition process depositing a back-sealing film layer thickness of 1000 angstroms. Alternatively, it can be achieved by performing four back-sealing deposition processes (i.e., the number of first film deposition processes is 4), with each back-sealing deposition process depositing a back-sealing film layer thickness of 500 angstroms. Or, it can be achieved by performing three back-sealing deposition processes (i.e., the number of first film deposition processes is 3), with back-sealing film layer thicknesses of 500 angstroms, 1000 angstroms, and 500 angstroms respectively. In the above possible implementation methods, three first candidate groups are formed, each of which includes a first thickness candidate value and a corresponding first film deposition process number candidate value. Of course, based on the range of the first thickness, more first candidate groups can be formed, which will not be elaborated in this disclosure.

[0073] For each first candidate group, the warpage elimination metric can be calculated by summing the warpage elimination metrics based on the warpage elimination metric corresponding to the first thickness candidate value and the first thin film deposition process number candidate value. This sum is the warpage elimination metric corresponding to each first candidate group. Taking the previous example, for a first candidate group with a first thickness candidate value of 1000 angstroms and a first thin film deposition process number candidate value of 2, the warpage elimination metric corresponding to a film thickness of 1000 angstroms is 1240.23 nm. Since the thin film deposition process is executed 2 times, the sum of the warpage elimination metrics is 1240.23 nm + 1240.23 nm = 2 × 1240.23 nm, which is the warpage elimination metric corresponding to this first candidate group as 2480.46 nm.

[0074] After obtaining the warpage elimination metric values ​​for all first candidate groups based on the above examples, the difference between the warpage metric value of the silicon wafer and the warpage elimination metric value for each first candidate group is calculated. The first thickness candidate value and the corresponding first thin film deposition process number candidate value from the first candidate group with the smallest absolute value of the difference are then determined as the first thickness and the first thin film deposition process number. It can be understood that when the thin film deposition process is performed according to the first thickness candidate value and the corresponding first thin film deposition process number candidate value from the first candidate group with the smallest absolute value of the difference, the warpage of the back-sealed silicon wafer can be minimized, thereby reducing the warpage of the back-sealed silicon wafer and improving its flatness.

[0075] In some examples, when the silicon wafer is in a convex warp state, determining the second thickness and the number of second thin film deposition processes based on a measure of warp degree and a target thickness includes:

[0076] Based on the target thickness and the range of the second thickness, multiple second candidate groups are selected, consisting of candidate values ​​of the second thickness and the corresponding number of second thin film deposition processes;

[0077] For each candidate value of the second thickness and the corresponding candidate value of the second thin film deposition process number in each second candidate group, obtain the warpage elimination metric value for each second candidate group.

[0078] Based on the warp measure and the warp elimination measure corresponding to each second candidate group, the second candidate group with the smallest absolute value of the difference is selected from all the second candidate groups.

[0079] The second thickness candidate value and the corresponding second thin film deposition process number candidate value in the second candidate group with the smallest absolute value of the difference are determined as the second thickness and the second thin film deposition process number.

[0080] Specifically, for the target thickness, multiple second thicknesses can be selected within the range of the second thickness and the back-sealing deposition process can be performed sequentially to deposit a back-sealing film of the target thickness. The number of times the back-sealing deposition process is performed is the number of times the second film deposition process is performed. Furthermore, one or more second candidate groups can be formed, and each second candidate group includes a candidate value for the second thickness and a corresponding candidate value for the number of times the second film deposition process is performed.

[0081] For each second candidate group, the warpage elimination metric can be calculated by summing the warpage elimination metrics based on the warpage elimination metric corresponding to the second thickness candidate value and the second thin film deposition process number candidate value. This sum is the warpage elimination metric for each second candidate group. After obtaining the warpage elimination metric for all second candidate groups, the difference between the silicon wafer warpage metric and the warpage elimination metric for each second candidate group is calculated. The second thickness candidate value and the corresponding second thin film deposition process number candidate value in the second candidate group with the smallest absolute difference are determined as the second thickness and the second thin film deposition process number. It can be understood that when the thin film deposition process is performed according to the second thickness candidate value and the corresponding second thin film deposition process number candidate value in the second candidate group with the smallest absolute difference, the warpage of the back-sealed silicon wafer can be minimized, thereby reducing the warpage of the back-sealed silicon wafer and improving its flatness.

[0082] For the two examples above, back-sealing deposition is performed on a group of 10 convex warped silicon wafers A and a group of 10 concave warped silicon wafers B, each with a target thickness of 2000 angstroms. For group A of 10 wafers, the average warpage metric is 2503. Thin-film deposition processes are performed on these 10 wafers with a first thickness of 1000 angstroms and a first thin-film deposition process of 2 passes. The warpage metrics before and after the thin-film deposition process are compared as follows: Figure 12 As shown, the average warpage of the back-sealed silicon wafer decreased to -17.3.

[0083] For the 10 silicon wafers in group B, the average warpage metric is -2423.1. Thin film deposition processes were performed on these 10 wafers with a second thickness of 2000 angstroms and a second thin film deposition process of 1 run. The warpage metrics before and after the thin film deposition process are compared as follows: Figure 13 As shown, the average warpage of the back-sealed silicon wafer decreased to -365.6.

[0084] pass Figure 12 as well as Figure 13 It can be seen that the technical solution provided in this disclosure can effectively reduce the warpage of silicon wafers and improve their flatness.

[0085] Based on the same inventive concept as the aforementioned technical solution, see [link to inventive concept]. Figure 14 The present disclosure illustrates an apparatus 140 for improving silicon wafer warpage, comprising: an acquisition unit 1401, a determination unit 1402, and an execution unit 1403; wherein,

[0086] The acquisition unit 1401 is configured to acquire the warpage state of the silicon wafer and a measure of the warpage degree.

[0087] The determining unit 1402 is configured to determine a first thickness and a first thin film deposition process number based on a warp degree measurement and a target thickness when the warp state of the silicon wafer is convex warp. Convex warp means that the center part of the front side of the silicon wafer is higher than the edge part, and the back sealing film layer of the first thickness generates tensile stress on the back cover of the silicon wafer.

[0088] Furthermore, when the warping state of the silicon wafer is concave warping, the second thickness and the number of second thin film deposition processes are determined based on the warping degree measurement and the target thickness. Concave warping indicates that the center part of the front side of the silicon wafer is lower than the edge part, and the second thickness of the back sealing film layer generates compressive stress on the back cover of the silicon wafer.

[0089] The execution unit 1403 is configured to perform a thin film deposition process to form a back seal film with a target thickness according to a first thickness and a first number of thin film deposition processes when the warp state of the silicon wafer is convex warp; and to perform a thin film deposition process to form a back seal film with a target thickness according to a second thickness and a second number of thin film deposition processes when the warp state of the silicon wafer is concave warp.

[0090] In some examples, the first thickness ranges from 500 angstroms to 1500 angstroms; the second thickness ranges from 2000 angstroms to 2500 angstroms.

[0091] In some examples, the determination unit 1402 is configured to:

[0092] Based on the target thickness and the range of the first thickness, multiple first candidate groups are selected, each consisting of a first thickness candidate value and the corresponding number of first thin film deposition processes.

[0093] For each candidate value of the first thickness and the corresponding candidate value of the first thin film deposition process number in each first candidate group, obtain the warpage elimination metric value for each first candidate group;

[0094] Based on the warp degree measurement value and the warp degree elimination measurement value corresponding to each candidate group, the first candidate group with the smallest absolute value of the difference is selected from all the first candidate groups;

[0095] The first thickness candidate value and the corresponding first thin film deposition process number candidate value in the first candidate group with the smallest absolute value of the difference are determined as the first thickness and the first thin film deposition process number.

[0096] In some examples, the determination unit 1402 is configured to:

[0097] Based on the target thickness and the range of the second thickness, multiple second candidate groups are selected, consisting of candidate values ​​of the second thickness and the corresponding number of second thin film deposition processes;

[0098] For each candidate value of the second thickness and the corresponding candidate value of the second thin film deposition process number in each second candidate group, obtain the warpage elimination metric value for each second candidate group.

[0099] Based on the warp degree measurement value and the warp degree elimination measurement value corresponding to each second candidate group, the second candidate group with the smallest absolute value of the difference is selected from all the second candidate groups;

[0100] The second thickness candidate value and the corresponding second thin film deposition process number candidate value in the second candidate group with the smallest absolute value of the difference are determined as the second thickness and the second thin film deposition process number.

[0101] In some examples, the acquisition unit 1401 is configured as follows:

[0102] Multiple sampling points are obtained by uniformly sampling the front side of the silicon wafer using polar coordinates with the center of the front side of the silicon wafer as the pole.

[0103] Measure the height data of each sampling point;

[0104] The warpage state of the silicon wafer is determined to be either convex warpage or concave warpage based on the height data of all sampling points.

[0105] When the warping state of the silicon wafer is either convex or concave, the absolute value of the difference between the maximum and minimum height values ​​on the front side of the silicon wafer is determined as the measure of the warping degree.

[0106] In some examples, the thin film deposition process is atmospheric pressure chemical vapor deposition (APCVD).

[0107] In some examples, the temperature during the thin film deposition process in the APCVD process is 450 degrees.

[0108] In some examples, the back sealing film is made of silicon dioxide.

[0109] Please refer to Figure 15This diagram illustrates a structural block diagram of a computing device provided in an exemplary embodiment of this disclosure. In some examples, the computing device 150 can be at least one of devices such as a smartphone, smartwatch, desktop computer, laptop, virtual reality terminal, augmented reality terminal, wireless terminal, and laptop computer. The computing device 150 has communication capabilities and can access wired or wireless networks. The computing device 150 can refer to one of a plurality of terminals, and those skilled in the art will understand that the number of such terminals can be more or less. In some examples, the computing device 150 can receive data based on the accessed wired or wireless network. It is understood that the computing device 150 undertakes the calculation and processing work of the technical solution of this disclosure, and this disclosure does not limit it in this respect.

[0110] like Figure 15 As shown, the computing device in this disclosure may include one or more of the following components: processor 1510 and memory 1520.

[0111] Optionally, the processor 1510 connects various parts within the computing device using various interfaces and lines, and performs various functions and processes data by running or executing instructions, programs, code sets, or instruction sets stored in the memory 1520, and by calling data stored in the memory 1520. Optionally, the processor 1510 can be implemented using at least one hardware form of Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), or Programmable Logic Array (PLA). The processor 1510 can integrate one or a combination of several of the following: Central Processing Unit (CPU), Graphics Processing Unit (GPU), Neural-network Processing Unit (NPU), and baseband chip. Specifically, the CPU primarily handles the operating system, user interface, and applications; the GPU is responsible for rendering and drawing the content required for display on the touch screen; the NPU is used to implement Artificial Intelligence (AI) functions; and the baseband chip is used for wireless communication. It is understandable that the aforementioned baseband chip may not be integrated into the processor 1510, but may be implemented as a separate chip.

[0112] The memory 1520 may include random access memory (RAM) or read-only memory (ROM). Optionally, the memory 1520 may include a non-transitory computer-readable storage medium. The memory 1520 may be used to store instructions, programs, code, code sets, or instruction sets. The memory 1520 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for at least one function (such as touch function, sound playback function, image playback function, etc.), instructions for implementing the various method embodiments described above, etc.; the data storage area may store data created according to the use of the computing device, etc.

[0113] In addition, those skilled in the art will understand that the structure of the computing device shown in the above figures does not constitute a limitation on the computing device. The computing device may include more or fewer components than shown, or combine certain components, or have different component arrangements. For example, the computing device may also include a display screen, camera assembly, microphone, speaker, radio frequency circuit, input unit, sensors (such as accelerometer, angular velocity sensor, light sensor, etc.), audio circuit, WiFi module, power supply, Bluetooth module, etc., which will not be described in detail here.

[0114] This disclosure also provides a computer-readable storage medium storing at least one instruction, which is executed by a processor to implement the methods for improving silicon wafer warpage as described in the various embodiments above.

[0115] This disclosure also provides a computer program product including computer instructions stored in a computer-readable storage medium; a processor of a computing device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computing device to perform the methods for improving silicon wafer warpage described in the various embodiments above.

[0116] In addition, this disclosure also provides a silicon wafer, wherein a back sealing film is formed on the back side of the silicon wafer according to the method for improving silicon wafer warpage described in any of the foregoing embodiments, and the warpage of the silicon wafer is measured in the range of [0, 500].

[0117] Those skilled in the art will recognize that the functions described in this disclosure in one or more of the examples above can be implemented using hardware, software, firmware, or any combination thereof. When implemented in software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any medium that facilitates the transfer of a computer program from one place to another. Storage media can be any available medium accessible to a general-purpose or special-purpose computer.

[0118] It should be noted that the technical solutions described in this disclosure can be combined arbitrarily as long as they do not conflict.

[0119] The above are merely specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for improving wafer bow, comprising: The method comprises: obtaining a warping state and a warping degree of the silicon wafer; when the warping state of the silicon wafer is convex warping, determining a first thickness and a first number of thin film deposition processes according to the warping degree and a target thickness, and performing a thin film deposition process according to the first thickness and the first number of thin film deposition processes to form a back sealing thin film layer with the target thickness; the convex warping means that the center of the front surface of the silicon wafer is higher than the edge, and the first thickness of the back sealing thin film layer generates tensile stress on the back sealing surface of the silicon wafer; wherein the interval range of the first thickness is 500 angstrom to 1500 angstrom; when the warping state of the silicon wafer is concave warping, determining a second thickness and a second number of thin film deposition processes according to the warping degree and the target thickness, and performing a thin film deposition process according to the second thickness and the second number of thin film deposition processes to form a back sealing thin film layer with the target thickness; the concave warping means that the center of the front surface of the silicon wafer is lower than the edge, and the second thickness of the back sealing thin film layer generates compressive stress on the back sealing surface of the silicon wafer; wherein the interval range of the second thickness is 2000 angstrom to 2500 angstrom; the determining of the first thickness and the first number of thin film deposition processes according to the warping degree and the target thickness comprises: selecting a plurality of first candidate groups composed of a first thickness candidate value and a corresponding first number of thin film deposition processes according to the target thickness and the interval range of the first thickness; for each first thickness candidate value and the corresponding first number of thin film deposition processes in each first candidate group, obtaining a warping degree elimination metric value corresponding to each first candidate group; selecting a first candidate group with the minimum absolute value of the difference from all first candidate groups according to the warping degree and the warping degree elimination metric value corresponding to each candidate group; determining the first thickness candidate value and the corresponding first number of thin film deposition processes in the first candidate group with the minimum absolute value of the difference as the first thickness and the first number of thin film deposition processes; selecting a plurality of second candidate groups composed of a second thickness candidate value and a corresponding second number of thin film deposition processes according to the target thickness and the interval range of the second thickness; for each second thickness candidate value and the corresponding second number of thin film deposition processes in each second candidate group, obtaining a warping degree elimination metric value corresponding to each second candidate group; selecting a second candidate group with the minimum absolute value of the difference from all second candidate groups according to the warping degree and the warping degree elimination metric value corresponding to each second candidate group; determining the second thickness candidate value and the corresponding second number of thin film deposition processes in the second candidate group with the minimum absolute value of the difference as the second thickness and the second number of thin film deposition processes.

2. The method of claim 1, wherein, the obtaining of the warping state and the warping degree of the silicon wafer comprises: obtaining the reflected light of the front surface and the back surface of the silicon wafer in polar coordinates with the center of the front surface of the silicon wafer as the pole point; obtaining the topographic information of the front surface of the silicon wafer according to the phase difference between the reflected light of the front surface and the back surface of the silicon wafer; determine, according to the profile information, a warping state of the silicon wafer as the convex warping or the concave warping; determine, when the warping state of the silicon wafer is the convex warping or the concave warping, an absolute value of a difference between a maximum height value and a minimum height value on the front surface of the silicon wafer as a measurement value of the warping degree.

3. The method of claim 1, wherein, The thin film deposition process is an atmospheric pressure chemical vapor deposition (APCVD) process.

4. The method of claim 3, wherein, During the APCVD process, a temperature for performing the thin film deposition process is 450 degrees.

5. The method of claim 1, wherein, The back sealing thin film is made of silicon dioxide.

6. An apparatus for performing the method of improving wafer bow according to any one of claims 1 to 5, characterized in that The device comprises an obtaining unit, a determining unit and an executing unit, wherein: The obtaining unit is configured to obtain a warping state of a silicon wafer and a measurement value of a warping degree. The determining unit is configured to, when the warping state of the silicon wafer is convex warping, which means that a center part of the front surface of the silicon wafer is higher than an edge part, determine, according to the measurement value of the warping degree and a target thickness, a first thickness and a first number of thin film deposition processes, wherein the first thickness of a back sealing thin film layer generates tensile stress on a back sealing surface of the silicon wafer; and, when the warping state of the silicon wafer is concave warping, which means that the center part of the front surface of the silicon wafer is lower than the edge part, determine, according to the measurement value of the warping degree and the target thickness, a second thickness and a second number of thin film deposition processes, wherein the second thickness of a back sealing thin film layer generates compressive stress on the back sealing surface of the silicon wafer. The executing unit is configured to, when the warping state of the silicon wafer is convex warping, perform a thin film deposition process according to the first thickness and the first number of thin film deposition processes to form a back sealing thin film that meets the target thickness; and, when the warping state of the silicon wafer is concave warping, perform a thin film deposition process according to the second thickness and the second number of thin film deposition processes to form a back sealing thin film that meets the target thickness. The computing device comprises a processor and a memory, and the processor is configured to execute instructions stored in the memory to implement the method for improving the warping degree of the silicon wafer.

7. A computing device, comprising: The computer readable storage medium stores at least one instruction for being executed by a processor to implement the method for improving the warping degree of the silicon wafer.

8. A computer-readable storage medium, characterized in that, The back surface of the silicon wafer is formed with a back sealing thin film according to the method for improving the warping degree of the silicon wafer, and a measurement value of the warping degree of the silicon wafer is within a range of [0, 500].

9. A silicon wafer, characterized by ​

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