Method for realizing multi-chip packaging on strip

Abstract

The invention relates to the technical field of chip packaging, and discloses a method for realizing multi-chip packaging on a strip, and the method comprises the following steps: 1, preparing a strip substrate; step 2, embedding a heat conduction layer and a heat dissipation channel in the strip base material; 3, the surface of the strip base material is cleaned and activated, and the middle functional layer is coated with a bonding material; 4, flip-chip welding a plurality of chips to different chip welding areas of the strip base material, and fixing the chips through the bonding material; step 5, coating a protective layer on the bonded chip and curing the protective layer; and step 6, carrying out a dynamic bending test on the strip, and verifying the reliability of the packaging structure. According to the invention, the metal wiring and the heat conduction layer are embedded in the strip base material, and the bonding material is adopted to realize the electrical connection of the chip and the wiring, so that the effect of considering both the electrical reliability and the heat conduction performance is achieved. Compared with the prior art that a wiring structure is insufficient in heat dissipation capacity, the problem that performance is reduced due to local heat accumulation of multi-chip packaging is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of chip packaging, and in particular to a method for implementing multi-chip packaging on a strip. Background Art

[0002] In the existing IC card chip packaging field, with the rapid development of integrated circuit technology, IC cards are gradually shifting from single-chip packaging to multi-chip packaging to meet higher functional requirements and a wider range of application scenarios. Multi-chip packaging of IC cards requires reliable connection of multiple chips within an extremely limited space, good heat dissipation management, and high reliability in dynamic environments. However, current packaging technology still faces many technical challenges: Insufficient heat dissipation performance: In existing technologies, the strip substrates used in IC card chip packaging mostly use a single wiring structure, lacking an efficient heat dissipation path design. In multi-chip packaging, the dense arrangement of chips leads to heat accumulation. Especially during long-term operation, localized heat accumulation seriously affects the stability and performance of the chip. Poor electrical connection reliability: Existing IC card packaging often uses soldering or conventional conductive adhesives for connection. However, the rigidity of soldering makes it difficult to adapt to dynamic bending environments, and solder joints are prone to fracture or detachment due to mechanical stress. Conductive adhesives also lack sufficient bonding strength over long-term use and are prone to failure under dynamic loads, making it difficult to ensure the long-term reliability of the electrical connection. Summary of the Invention

[0003] In response to the shortcomings of the existing technology, the present invention provides a method for realizing multi-chip packaging on a strip, which solves the problems in the existing IC card chip packaging, that is, under multi-chip packaging conditions, local heat accumulation seriously affects the stability and performance of the chip, and the conductive adhesive has insufficient bonding strength during long-term use, making it difficult to ensure the long-term reliability of the electrical connection.

[0004] To achieve the above objectives, the present invention is implemented through the following technical solutions: A method for implementing multi-chip packaging on a strip, comprising the following steps: Step 1: Prepare a strip substrate, which includes a surface layer, an intermediate functional layer, and a bottom layer, wherein the surface layer is a protective film, the intermediate functional layer is embedded with metal wiring and a thermal conductive layer, and the bottom layer is a supporting material; Surface function: Made of polyimide or liquid crystal polymer, the surface layer can maintain dimensional stability in high temperature environments, while also being corrosion-resistant and flexible, adapting to the complex environment of multi-chip operation; Function of the middle layer: Metal wiring realizes the electrical interconnection of multiple chips. The thermal conductivity of the thermal conductive graphite film is higher than 1500W / m·K, which can quickly guide the heat of the chip from the operating area to the outer surface of the substrate. Bottom layer function: The high toughness and low coefficient of thermal expansion (CTE) of liquid crystal polymer materials ensure the mechanical reliability of the strip during dynamic bending, while reducing chip shedding or solder joint failure caused by thermal expansion and contraction Step 2: embedding a heat-conducting layer and heat dissipation channels in the strip substrate to guide the heat during chip operation; The function of the thermal conductive layer: The thermal conductive graphite film or micro heat pipe forms an efficient heat conduction path inside the substrate, which can quickly diffuse the heat of the chip, reduce the chip operating temperature, and improve operating stability.

[0005] The function of the heat dissipation channel: The heat dissipation channel is distributed in the area under the chip to form a heat diffusion network of the heat conductive layer, further reducing local overheating in the chip area and extending the chip life.

[0006] Step 3: Clean and activate the surface of the strip substrate, and apply adhesive material to the middle functional layer; Cleaning function: The cleaning process removes dirt and oxide layers on the surface of the strip, ensuring direct contact between the adhesive material and the substrate, thus improving the bonding strength; Surface activation: Plasma treatment can introduce polar functional groups (such as hydroxyl or carbonyl groups), significantly improving the chemical bonding between the strip surface and the adhesive material, thereby enhancing bonding reliability.

[0007] Step 4: flip-chip soldering multiple chips to different chip soldering areas of the strip substrate, fixing them separately with adhesive materials, and electrically connecting each chip soldering point to the strip metal wiring; Chip distribution design: Linear arrangement or matrix arrangement can optimize the space utilization of multi-chip packaging and improve integration; Selection of bonding materials: Conductive nano glue has excellent electrical conductivity, good flexibility and bonding strength, can adapt to dynamic bending and thermal expansion environments, and reduce the risk of solder joints falling off.

[0008] Step 5: Apply a protective layer to the bonded chip and cure it; The function of epoxy resin coating is to seal the chip surface to prevent environmental moisture or chemical corrosion; The function of the flexible silicone coating: graphene enhances heat dissipation performance, alumina particles improve the hardness and wear resistance of the coating, and the silicone matrix maintains flexibility to adapt to the dynamic bending environment of the strip.

[0009] Step 6: Perform a dynamic bending test on the strip to verify the reliability of the packaging structure.

[0010] Dynamic test objectives: Verify the flexibility of the strip substrate and the bonding reliability of the multi-chip package under dynamic conditions; Test purpose: By simulating actual usage conditions, it ensures that the multi-chip package still has good mechanical strength and electrical connection performance under dynamic stress.

[0011] Preferably, in step 1, the surface layer of the strip substrate is a polyimide film with a thickness of 5 to 20 μm, the intermediate functional layer is embedded with metal wiring and a thermal conductive graphite film, the intermediate functional layer has a thickness of 10 to 50 μm, the metal wiring has a thickness of 5 to 15 μm, the thermal conductive graphite film has a thickness of 5 to 35 μm, and the bottom layer is a liquid crystal polymer film, and the total thickness is controlled at 25 to 100 μm.

[0012] Preferably, in step 2, the heat-conducting layer is a heat-conducting graphite film or a micro heat pipe, the thermal conductivity of which is greater than 1500 W / m·K, and the width of the heat dissipation channel is 0.5 to 1 mm, which is distributed under multiple chip welding areas and is used to conduct the heat generated by the chip during operation to the heat dissipation surface of the strip substrate.

[0013] Preferably, in step 4: Cleaning includes: (1) Preliminary cleaning: Place the strip substrate in an ultrasonic cleaning device filled with isopropyl alcohol and clean it at 40-60 Hz for 20-25 minutes. After cleaning, rinse the strip substrate with deionized water. (2) Deep cleaning: Use plasma cleaning equipment to clean the strip substrate after preliminary cleaning. Oxygen gas is used, the gas flow rate is 10-50 sccm, the working pressure is 100-300 mTorr, the RF power is 50-200W, and the cleaning time is 1-2 minutes. Surface activation includes: (1) Plasma activation: Use plasma equipment to activate the surface of the cleaned strip. Oxygen is used as gas, the gas flow rate is 10-30 sccm, the working pressure is 100-200 mTorr, the RF power is 50-100 W, and the cleaning time is 0.5-1 min.

[0014] Preferably, the bonding material includes conductive nano glue.

[0015] Preferably, in step 4, multiple chips are distributed on the strip substrate in a linear arrangement or a matrix arrangement, the spacing between each chip is 1 to 5 mm, and the electrical connection between the solder joints and the metal wiring is bonded by conductive nano glue.

[0016] Preferably, in step 5, the protective layer is divided into two layers, the first layer is an epoxy resin protective coating with a thickness of 20 to 50 μm, and the second layer is a flexible silicone coating with a thickness of 30 to 50 μm, and the first layer is close to the chip.

[0017] Preferably, the flexible silicone coating comprises: Flexible silicone matrix, accounting for 70% to 80%; Alumina nanoparticles, accounting for 10% to 15%; Graphene accounts for 5% to 10%.

[0018] Preferably, the curing conditions of the flexible silicone coating are: temperature 80-120° C., and time 0.8-1 h.

[0019] Preferably, the dynamic bending test in step 6 simulates a bending radius of less than 5 mm and repeated bending times of not less than 10,000 times, to verify the reliability of the strip substrate and chip packaging.

[0020] The present invention provides a method for implementing multi-chip packaging on a strip, which has the following beneficial effects: 1. By embedding metal wiring and a thermally conductive layer within a strip substrate and achieving electrical connection between the chip and the metal wiring through an adhesive, this invention achieves both reliable electrical connections and optimized thermal conductivity. Compared to the existing single wiring structure's lack of efficient heat dissipation, this solution addresses the issues of severe localized heat accumulation and low heat dissipation efficiency in multi-chip packaging, which can lead to reduced chip performance.

[0021] 2. By designing a thermally conductive graphite film and heat dissipation channel structure within the intermediate functional layer, combined with a linear or matrix arrangement of multiple chips, this invention achieves the technical effect of rapid heat dissipation and uniform distribution during chip operation. Compared to existing technologies that lack optimized heat dissipation paths and result in inter-chip thermal interference, this technology addresses the technical shortcoming of performance fluctuations and reduced reliability caused by localized overheating when densely packed chips are used.

[0022] 3. This invention utilizes a dual-layer protective coating: a first epoxy resin coating provides basic sealing and mechanical protection, while a second flexible silicone coating enhances bending resistance and heat dissipation, achieving the technical effect of long-term reliability of the package structure in dynamic environments. Compared to existing single-coat designs, which are prone to cracking or shedding during dynamic bending and thermal cycling, this design significantly improves the coating's adhesion and environmental adaptability, addressing the high failure rate of multi-chip packages under complex operating conditions. DETAILED DESCRIPTION

[0023] The following is a clear and complete description of the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present invention.

[0024] In order to better understand the present invention, the above contents are described in detail below in conjunction with specific embodiments.

[0025] An embodiment of the present invention provides a method for implementing multi-chip packaging on a strip, comprising the following steps: Step 1: Prepare a strip substrate, which includes a surface layer, an intermediate functional layer, and a bottom layer. The surface layer is a protective film, the intermediate functional layer is embedded with metal wiring and a thermal conductive layer, and the bottom layer is a supporting material. Step 2: embedding a heat-conducting layer and heat dissipation channels in the strip substrate to guide the heat during chip operation; Step 3: Clean and activate the surface of the strip substrate, and apply adhesive material to the middle functional layer; Step 4: flip-chip soldering multiple chips to different chip soldering areas of the strip substrate, fixing them separately with adhesive materials, and electrically connecting each chip soldering point to the strip metal wiring; Step 5: Apply a protective layer to the bonded chip and cure it; Step 6: Perform a dynamic bending test on the strip to verify the reliability of the packaging structure.

[0026] In step 1 of this embodiment: The strip substrate consists of a multi-layer composite structure, including a surface layer, an intermediate functional layer and a bottom layer: Surface layer: a protective film made of polyimide film with a thickness of 5 to 20 μm, used to provide basic protection against wear resistance, chemical corrosion resistance and external environment; Middle functional layer: embedded with metal wiring and thermal conductive layer. The metal wiring is used for electrical connection of the chip and has a thickness of 5 to 15 μm. The thermal conductive layer uses thermal conductive graphite film or other thermal conductive materials with a thickness of 5 to 35 μm to achieve heat conduction when the chip is working. Bottom layer: As the supporting material, a liquid crystal polymer (LCP) film with a thickness of 15 to 50 μm is selected to provide the mechanical strength and flexibility of the strip, while ensuring that the strip has reliable mechanical properties and stability under dynamic bending conditions.

[0027] In step 2: Embedding thermal conductive layers and heat dissipation channels in the middle functional layer of the strip substrate: Thermal conductive layer: uses thermal conductive graphite film or micro heat pipe, with a thermal conductivity greater than 1500W / m·K, forming an efficient heat conduction path; Heat dissipation channel: The heat dissipation channel is 0.5 to 1 mm wide and is evenly distributed under multiple chip welding areas. It is used to guide the heat generated during chip operation from the bottom area of ​​the chip to the heat dissipation surface of the strip, thereby reducing the impact of local heat accumulation on chip operation.

[0028] Function: The design of the thermal conductive layer and heat dissipation channel ensures the temperature stability of the chip under high-density operation, extending the service life of the chip. At the same time, the uniform layout of the heat dissipation channel optimizes the thermal management performance of the entire package.

[0029] In step 3: In order to enhance the bonding strength and reliability between the chip and the strip substrate, the surface of the strip substrate needs to be cleaned and activated as follows: Initial cleaning: Place the strip substrate in an ultrasonic cleaning device filled with isopropyl alcohol and perform ultrasonic cleaning at 40-60 Hz for 20-25 minutes to remove particles, organic matter and other contaminants on the strip surface; after cleaning, rinse thoroughly with deionized water.

[0030] Deep cleaning: Use plasma cleaning equipment to deep clean the strip surface, using oxygen plasma to remove residual oxides and trace impurities on the surface; cleaning parameters include oxygen flow rate of 10-50sccm, working pressure of 100-300mTorr, RF power of 50-200W, and cleaning time of 1-2 minutes.

[0031] Surface Activation: Plasma activation is performed on the cleaned strip surface to further increase surface energy and enhance bonding performance. Activation parameters include an oxygen flow rate of 10-30 sccm, an operating pressure of 100-200 mTorr, an RF power of 50-100W, and an activation time of 0.5-1 minute.

[0032] Effect: After cleaning and activation, the cleanliness and bonding performance of the strip surface are significantly improved, providing reliable surface conditions for subsequent chip bonding and welding.

[0033] In step 4: Chip layout design: Multiple chips are arranged linearly or in a matrix on a strip substrate, with a spacing of 1 to 5 mm between chips. By optimizing the chip arrangement, the integration density of the multi-chip package can be increased to meet the needs of high-performance, high-integration applications.

[0034] Soldering Process: A flip-chip bonding process is used to align the chip's solder joints with the metal wiring areas of the strip substrate. Conductive nano-adhesive or low-temperature curing conductive silver adhesive is used for bonding and electrical connection. Conductive nano-adhesive has excellent conductivity and bonding strength, can adapt to dynamic bending and thermal expansion environments, and reduces the risk of solder joints falling off.

[0035] Fixing method: Each chip is fixed to the strip substrate through adhesive material, achieving mechanical connection and electrical interconnection at the same time.

[0036] Effect: The distributed design and reliable bonding method of multi-chip welding not only improves the packaging density, but also effectively improves the stability and reliability of multi-chip operation.

[0037] In step 5: Protective layer structure: The protective layer is divided into two layers: The first layer: epoxy resin coating, with a thickness of 20 to 50 μm, close to the chip surface, is mainly used to seal the chip surface and provide basic moisture and corrosion protection; The second layer is a flexible silicone coating with a thickness of 30 to 50 μm. It consists of a flexible silicone matrix (70% to 80%), aluminum oxide nanoparticles (10% to 15%), and graphene (5% to 10%). The flexible silicone matrix provides mechanical flexibility, the aluminum oxide particles enhance wear resistance, and the graphene enhances heat dissipation.

[0038] Curing conditions: The flexible silicone coating is cured at a temperature of 80-120°C for 0.8-1 hour to form a uniform and dense protective film.

[0039] Effect: The double-layer protective coating design not only achieves comprehensive protection for the chip, but also enhances heat dissipation performance and resistance to mechanical bending, ensuring the reliability of multi-chip packaging in dynamic usage scenarios.

[0040] In step 6: Test conditions: Simulate a dynamic bending environment with a bending radius of less than 5mm to test the reliability of the strip packaging structure under dynamic stress; the number of repeated bends is not less than 10,000 times.

[0041] Test content: Focus on testing the mechanical strength of the strip substrate, the adhesion strength between the chip and the strip, and the electrical connection stability between the chip solder joints and metal wiring.

[0042] Effect: Dynamic bending testing can verify the long-term reliability of multi-chip packages under dynamic stress conditions and ensure the stable operating performance of the strips in complex environments such as bending and stretching.

[0043] In step 1, the surface layer of the strip substrate is a polyimide film with a thickness of 5 to 20 μm. The middle functional layer is embedded with metal wiring and thermal conductive graphite film. The thickness of the middle functional layer is 10 to 50 μm, the thickness of the metal wiring is 5 to 15 μm, the thickness of the thermal conductive graphite film is 5 to 35 μm, and the bottom layer is a liquid crystal polymer film. The total thickness is controlled at 25 to 100 μm.

[0044] In this embodiment: the surface layer is a polyimide film, which has high heat resistance. Its long-term operating temperature can reach 200-300°C, and its short-term heat resistance can reach 400°C, ensuring the stability of the packaging structure in a high-temperature environment. The tensile strength of the polyimide film is usually greater than 150MPa, which can effectively resist deformation and damage under external forces; and it has strong corrosion resistance to acid, alkali and other chemical substances, which can prevent the external chemical environment from corroding the strip substrate; at the same time, it can withstand multiple bending without cracking, and is suitable for dynamic application scenarios; at the same time, it has high insulation performance, and its breakdown voltage can reach 150kV / mm, ensuring electrical isolation of the chip and wiring.

[0045] The carrier substrate for the intermediate functional layer is polyimide (PI), which provides the necessary electrical insulation and support between the metal wiring and the thermally conductive graphite film. PI is a stable polymer material with the following thermal stability characteristics: it can operate for long periods in environments of 200-300°C without degradation, and it maintains its physical and chemical properties at extreme temperatures of 400°C. Its performance is largely unaffected at ultra-low temperatures of -200°C, thus meeting the high-temperature conditions encountered in multi-chip packages. This prevents material deformation or failure caused by high temperatures, ensuring the thermal stability of the package structure. It also exhibits strong corrosion resistance to a variety of chemicals (acids, alkalis, oils, etc.), resisting reactions with common chemicals and maintaining long-term stability in harsh environments. Therefore, it provides chemical protection for chips and other sensitive components within the package structure, ensuring the long-term service life of the strip substrate in industrial environments such as high humidity and highly corrosive gases.

[0046] The metal wiring is made of copper. Since copper has a resistivity of only 1.68μΩ·cm, it can effectively transmit the chip's signals and power. Moreover, the copper wiring can be precisely processed into the required path through laser etching, electroplating and other technologies to ensure precise connection with multiple chips. At the same time, it has reliable environmental stability: after surface plating treatment, the copper wiring is not easily oxidized or corroded in high temperature and high humidity environments. Therefore, using metal wiring as a signal transmission path ensures electrical connection between multiple chips and between chips and external interfaces, which is suitable for high-density packaging requirements.

[0047] Since thermally conductive graphite film typically has a thermal conductivity of 1500-2000 W / m·K, four to five times that of traditional metal thermal conductive materials (such as copper and aluminum), it can quickly transfer heat generated by chip operation from high-temperature areas to low-temperature areas. Its efficient lateral thermal conductivity evenly distributes heat over a larger heat dissipation surface. Furthermore, in multi-chip packages, thermally conductive graphite film effectively reduces localized heat accumulation at the bottom of the chip, improving chip operational stability. This reduces performance degradation or failure due to overheating and extends chip life. Thermally conductive graphite film also exhibits excellent flexibility and mechanical properties: it can maintain integrity with a bending radius of less than 1mm and will not crack or damage even during repeated bending. Therefore, in the flexible strips of multi-chip packages, thermally conductive graphite film can adapt to the complex operating environment of the strips' dynamic bending and stretching, thereby maintaining the integrity of the thermal path without compromising heat dissipation performance.

[0048] Liquid crystal polymer film: a polymer material with excellent performance. Due to its mechanical properties, thermal properties, electrical properties and chemical stability, it has been widely used in the field of electronic packaging. It is particularly suitable for the strip substrate design in multi-chip packaging. It has high tensile strength and elastic modulus, typically reaching a tensile strength of 150MPa to 300MPa, which can provide sufficient mechanical support for the strip substrate. The LCP film also has a high elongation at break, which can resist fatigue cracking under dynamic bending or tensile conditions. At the same time, its tight molecular structure and smooth surface exhibit good wear resistance. Therefore, in multi-chip packaging, the LCP film, as the bottom layer of the substrate, can effectively support the entire packaging structure, preventing damage due to external forces or dynamic use; by providing mechanical protection, it ensures the reliability of the strip substrate in long-term operation in complex environments.

[0049] In step 2, the heat-conducting layer is a heat-conducting graphite film or a micro heat pipe, with a thermal conductivity greater than 1500W / m·K. The width of the heat dissipation channel is 0.5 to 1mm, which is distributed under multiple chip welding areas and is used to conduct the heat generated by the chip during operation to the heat dissipation surface of the strip substrate.

[0050] In step 4: Cleaning includes: (1) Preliminary cleaning: Place the strip substrate in an ultrasonic cleaning device filled with isopropyl alcohol and clean it at 40-60 Hz for 20-25 minutes. After cleaning, rinse the strip substrate with deionized water. (2) Deep cleaning: Use plasma cleaning equipment to clean the strip substrate after preliminary cleaning. Oxygen gas is used, the gas flow rate is 10-50 sccm, the working pressure is 100-300 mTorr, the RF power is 50-200W, and the cleaning time is 1-2 minutes. Surface activation includes: (1) Plasma activation: Use plasma equipment to activate the surface of the cleaned strip. Oxygen is used as gas, the gas flow rate is 10-30 sccm, the working pressure is 100-200 mTorr, the RF power is 50-100 W, and the cleaning time is 0.5-1 min.

[0051] In this embodiment, isopropyl alcohol is a medium polar solvent with a molecular formula of C3H8O that can dissolve a variety of polar and non-polar organic substances; Isopropyl alcohol is low in toxicity, highly volatile, and easily evaporates, leaving no residue on the substrate surface. It also exhibits strong solubility, being completely miscible with water and capable of dissolving grease, organic contaminants, and dust. Furthermore, its low toxicity makes it safer to use. Compared to other industrial solvents (such as acetone and toluene), it is gentler on substrates and effectively cleans without damaging the surface. Therefore, it can be used to remove organic contaminants (such as grease, fingerprints, and flux residue) and fine dust particles from substrate surfaces, providing a clean surface for subsequent deep cleaning and surface activation.

[0052] The bonding material includes conductive nano glue.

[0053] In step 4, multiple chips are distributed on the strip substrate in a linear arrangement or a matrix arrangement, with a spacing of 1 to 5 mm between each chip, and the electrical connection between the solder joints and the metal wiring is bonded by conductive nano glue.

[0054] In this embodiment, the chip arrangement includes Linear arrangement: In the chip bonding area of ​​the strip substrate, the chips are arranged in a linear pattern, evenly spaced along the length of the strip. This approach is suitable for narrow strip substrate designs, optimizing chip arrangement space. It also simplifies metal wiring design, shortening signal transmission paths and reducing latency and electromagnetic interference.

[0055] Matrix arrangement: Chips are arranged in a matrix grid within the strip substrate, arranged both lengthwise and widthwise. This increases chip integration density, making it suitable for multi-chip, high-density packaging applications and accommodating more complex multi-channel signal transmission and power distribution requirements.

[0056] And the minimum pitch is 1mm: it is suitable for ultra-high-density packaging design, and can integrate more chips within the limited strip substrate area; it can enhance the integration of the system, but has high requirements for heat dissipation and electrical connection precision.

[0057] Maximum spacing of 5mm: Suitable for chip designs with high heat dissipation requirements, increasing the heat diffusion area between chips and reducing thermal interference between adjacent chips.

[0058] Electrical connection between solder joints and metal wiring At the same time, solder joints are key nodes for the transmission of chip electrical signals and power. Their connection design with metal wiring must ensure low impedance and high reliability; the layout of solder joints must be precisely aligned with the designed path of metal wiring to ensure the transmission integrity of signals and power.

[0059] Conductive nanoadhesive consists of highly conductive nanoparticles (such as silver nanoparticles) dispersed in an adhesive matrix (such as epoxy resin). The nanoparticles form conductive pathways, providing excellent electrical conductivity. These adhesives offer high conductivity, low resistivity, and the ability to transmit high-frequency signals and high currents. They also exhibit flexibility, adapting to the dynamic bending conditions of the strip substrate and preventing solder joint failure due to substrate deformation. Furthermore, they exhibit high bonding strength, firmly securing chips and metal wiring in dynamic use scenarios, ensuring long-term electrical connection reliability.

[0060] In step 5, the protective layer is divided into two layers. The first layer is an epoxy resin protective coating with a thickness of 20 to 50 μm, and the second layer is a flexible silicone coating with a thickness of 30 to 50 μm. The first layer is close to the chip.

[0061] Flexible silicone coating includes: Flexible silicone matrix, accounting for 70% to 80%; Alumina nanoparticles, accounting for 10% to 15%; Graphene accounts for 5% to 10%.

[0062] The curing conditions of the flexible silicone coating are: temperature 80-120°C, time 0.8-1h.

[0063] In this embodiment, the protective layer adopts a double-layer structure design. The first layer is an epoxy resin protective coating with a thickness of 20 to 50 μm. This coating is in close contact with the surface of the chip and mainly plays a basic sealing and protective role. Epoxy resin has excellent mechanical strength and chemical stability, which can effectively prevent moisture, oxides and other external pollutants from eroding the chip surface. At the same time, its high adhesion ensures that the coating forms a firm bond with the chip surface, thereby improving the overall sealing performance of the protective layer. In addition, epoxy resin has a low thermal expansion coefficient, which matches the thermal expansion characteristics of the chip and the substrate, can reduce the stress caused by uneven thermal expansion, and prevent the chip surface coating from cracking or falling off. The second layer is a flexible silicone coating with a thickness of 30 to 50 μm. This coating covers the epoxy resin protective layer, further enhancing the protective performance of the entire protection system. The flexible silicone coating is composed of a flexible silicone matrix, aluminum oxide nanoparticles, and graphene. The flexible silicone matrix accounts for 70% to 80%, providing the coating's flexibility and elasticity, enabling it to adapt to deformation of the strip substrate under dynamic bending or thermal expansion, thereby preventing the coating from cracking or delamination during long-term use. Aluminum oxide nanoparticles account for 10% to 15%, enhancing the coating's wear resistance and mechanical strength, improving the coating's surface impact resistance and durability. Graphene, which accounts for 5% to 10%, has extremely high thermal conductivity, further enhancing the coating's heat dissipation capacity, quickly transferring heat generated during chip operation to the external environment, reducing the chip's operating temperature and improving its operational stability. The flexible silicone coating uses curing conditions of 80 to 120°C for 0.8 to 1 hour to fully cure and form a uniform and dense protective film. Its flexibility and thermal conductivity are optimized after curing. The double-layer protective layer design not only provides basic physical protection and sealing effects for the chip, but also effectively improves the ability to resist mechanical stress and heat dissipation performance in dynamic environments, thereby ensuring the stability and reliability of the chip in long-term and efficient operation.

[0064] The dynamic bending test in step 6 simulates a bending radius of less than 5 mm and repeated bending times of no less than 10,000 times to verify the reliability of the strip substrate and chip packaging.

[0065] Example 1: Step 1: Prepare the strip substrate.

[0066] The surface layer of the strip substrate is a polyimide film with a thickness of 10μm, the middle functional layer is embedded with a high thermal conductivity graphite film with a thickness of 25μm and a copper wiring with a thickness of 10μm, and the bottom layer is a liquid crystal polymer film with a thickness of 40μm. The total thickness is 80μm.

[0067] Step 2: Embedding of thermal conductive structure.

[0068] The middle functional layer is evenly embedded with a thermally conductive graphite film with a thermal conductivity of 1800W / m·K. Heat dissipation channels are designed with a width of 0.8mm and a spacing of 3mm. These channels are distributed beneath each chip soldering area to ensure rapid heat dissipation.

[0069] Step 3: Cleaning.

[0070] The strip substrate was first cleaned with isopropyl alcohol using an ultrasonic frequency of 50 Hz for 22 minutes. This was followed by a deep clean using oxygen plasma at an oxygen flow rate of 20 sccm and an RF power of 150 W for 1.5 minutes.

[0071] Step 4: Chip soldering.

[0072] Multiple chips were arranged in a linear array with a 2mm spacing between each chip. Conductive nano-adhesive was used to complete the electrical connection of the solder joints. The nano-adhesive was cured at 100°C for 40 minutes.

[0073] Step 5: Protective coating.

[0074] Apply a first layer of epoxy resin protective coating with a thickness of 30μm, cure temperature of 120℃ for 1 hour. Then apply a second layer of flexible silicone coating with a thickness of 40μm, silicone matrix accounting for 75%, aluminum oxide nanoparticles accounting for 12%, and graphene accounting for 8%. The curing conditions are temperature of 100℃ and time of 50 minutes.

[0075] Example 2 Step 1: Prepare the substrate.

[0076] The strip substrate uses a liquid crystal polymer film as the bottom layer with a thickness of 30μm. The middle functional layer includes a high thermal conductivity graphite film with a thickness of 20μm and a gold-plated copper wiring with a thickness of 8μm. The surface layer is a polyimide film with a thickness of 15μm.

[0077] Step 2: Embed the heat dissipation channel.

[0078] A thermally conductive graphite film is placed beneath the chip soldering area, with a heat dissipation channel designed to be 1mm wide. The graphite film is combined with the copper wiring to form a highly efficient heat conduction network. The heat dissipation channel covers 60% of the entire strip.

[0079] Step 3: Cleansing and activating treatment.

[0080] Isopropyl alcohol solution was used for cleaning, with an ultrasonic frequency of 55 Hz for 20 minutes. Deep cleaning was performed using oxygen plasma at 120 W of radio frequency for 1 minute, followed by surface activation at an oxygen flow rate of 15 sccm for 40 seconds.

[0081] Step 4: Chip installation and soldering.

[0082] The chips were arranged in a matrix with a 3mm spacing between each chip. The chips were connected to the metal wiring using low-temperature conductive silver glue, which was cured at 90°C for 35 minutes.

[0083] Step 5: Curing of the protective layer.

[0084] The first layer is a 25μm-thick epoxy resin coating; the second layer is a 30μm-thick flexible silicone coating, composed of 70% silicone matrix, 15% aluminum oxide nanoparticles, and 10% graphene. Curing conditions are 110°C for 0.8 hours.

[0085] Example 3 Step 1: Substrate preparation.

[0086] The middle functional layer of the strip substrate is embedded with 15μm thick copper wiring and 10μm thick high thermal conductivity graphite film. The thermal conductivity coefficient of the thermal conductive graphite film is 1600W / m·K. The surface layer is a polyimide film with a thickness of 12μm, and the bottom layer is a liquid crystal polymer film with a thickness of 35μm.

[0087] Step 2: Thermal management structure design.

[0088] The graphite film covers the chip area, with a heat dissipation channel width of 0.7mm and a spacing of 2.5mm. The channel design adopts a multi-layer alternating structure to optimize the heat conduction path and enhance heat dissipation capacity.

[0089] Step 3: Substrate cleaning.

[0090] Isopropyl alcohol cleaning was used, with an ultrasonic frequency of 45 Hz for 25 minutes. Oxygen plasma cleaning was performed with a gas flow rate of 30 sccm, a radio frequency power of 140 W, and a cleaning time of 1 minute.

[0091] Step 4: Chip installation and arrangement.

[0092] The chips are arranged in a matrix with a row and column spacing of 2 mm. The solder joints are bonded to the metal wiring using conductive nano-adhesive, and the curing conditions are a temperature of 100°C and a time of 30 minutes.

[0093] Step 5: Protective layer process.

[0094] The first layer of protective coating is made of epoxy resin with a thickness of 30μm and the curing conditions are a temperature of 90°C and a time of 1 hour; the second layer of flexible silicone coating is 35μm thick, with a silicone matrix accounting for 75%, alumina nanoparticles accounting for 10%, and graphene accounting for 10%. The curing conditions are a temperature of 100°C and a time of 40 minutes.

[0095] Example 4 Step 1: Substrate preparation.

[0096] The total thickness of the substrate is controlled at 50μm, of which the surface layer is a polyimide film with a thickness of 8μm, the middle functional layer is embedded with tinned copper wiring with a thickness of 7μm and a thermal conductive graphite film with a thickness of 10μm, and the bottom layer is a liquid crystal polymer film with a thickness of 25μm.

[0097] Step 2: Layout of thermal conductive graphite film.

[0098] The thermal conductive graphite film covers the bottom of the welding area, and the heat dissipation channel width is 0.6mm and the spacing is 3mm, forming a heat diffusion network.

[0099] Step 3: Cleaning and surface preparation.

[0100] Ultrasonic cleaning conditions were 50 Hz for 22 minutes, followed by oxygen plasma cleaning at a gas flow rate of 20 sccm and a radio frequency power of 110 W for 1 minute. Surface activation time was 0.5 minutes.

[0101] Step 4: Chip Installation.

[0102] The chips are arranged in a linear array with a spacing of 1.5 mm. Electrical connections between the chip solder joints and the metal wiring are achieved using conductive nano-adhesive, which is cured at 80°C for 0.9 hours.

[0103] Step 5: Apply protective layer.

[0104] The first layer of epoxy resin coating is 20 μm thick, and the second layer of flexible silicone coating is 30 μm thick. The silicone matrix accounts for 72%, the aluminum oxide nanoparticles account for 13%, and the graphene accounts for 8%. The coating curing conditions are a temperature of 90°C and a time of 50 minutes. Comparative Example 1 Preparation process: Substrate Preparation: The strip substrate's middle functional layer utilizes only 20μm thick copper wiring as a heat conduction path. No thermally conductive graphite film is embedded, and no heat dissipation channels are provided. The top layer is a 10μm thick polyimide film, and the bottom layer is a 40μm thick liquid crystal polymer film, for a total thickness of 70μm.

[0105] Cleaning treatment: The same isopropyl alcohol ultrasonic cleaning process and plasma cleaning treatment as in Example 1 were adopted.

[0106] Chip soldering: Chips are arranged in a linear pattern with a spacing of 2 mm. Conductive nano-adhesive is used to connect the solder joints to the metal wiring. Curing conditions are 100°C and 40 minutes.

[0107] Protective coating: The first layer is an epoxy resin coating with a thickness of 30 μm. The second layer is a flexible silicone coating with a thickness of 40 μm. The silicone matrix accounts for 75%, the aluminum oxide nanoparticles account for 12%, and the graphene accounts for 8%. The curing conditions are the same as those in Example 1.

[0108] Comparative Example 2 Preparation process: Substrate preparation: The surface layer of the strip substrate is a polyimide film with a thickness of 15 μm, the middle functional layer includes 8 μm thick gold-plated copper wiring and a 20 μm thick high thermal conductivity graphite film, and the bottom layer is a liquid crystal polymer film with a thickness of 30 μm.

[0109] Heat dissipation channel: The heat dissipation channel width is set to 1.5mm and the spacing is 1mm. Compared with Example 2, the heat dissipation channel is more dense.

[0110] Cleaning and surface treatment: The cleaning and activation process is the same as in Example 2.

[0111] Chip mounting and soldering: Chips are arranged in a linear array, with the spacing between each chip reduced to 0.5mm. The solder joints are connected to the metal wiring using conductive nano-adhesive. Curing conditions are 90°C and 35 minutes.

[0112] Protective coating: The protective coating design is the same as that in Example 2.

[0113] Comparative Example 3 Preparation process: Substrate preparation: Same as Example 3, the surface layer of the strip substrate is a polyimide film with a thickness of 12 μm, the middle functional layer includes a copper wiring with a thickness of 15 μm and a high thermal conductivity graphite film with a thickness of 10 μm, and the bottom layer is a liquid crystal polymer film with a thickness of 35 μm.

[0114] Heat dissipation channel design: The heat dissipation channel width is 0.7 mm and the spacing is 2.5 mm, which is consistent with Example 3.

[0115] Chip welding: The chips were arranged in a matrix with a spacing of 2 mm, and the solder joints were bonded to the metal wiring using conductive nano-adhesive. The curing conditions were the same as in Example 3.

[0116] Protective coating: The first protective coating layer is made of epoxy resin with a thickness of 30 μm and the curing condition is 90°C for 1 hour; The second layer of flexible silicone coating does not add aluminum oxide nanoparticles and graphene, but only uses a silicone matrix with a thickness of 35 μm and a curing condition of 100°C for 40 minutes.

[0117] Comparative Example 4: Preparation process: Substrate preparation: The surface layer of the strip substrate is a polyimide film with a thickness of 8μm, the middle functional layer is embedded with tinned copper wiring with a thickness of 7μm and a thermal conductive graphite film with a thickness of 10μm, and the bottom layer is a liquid crystal polymer film with a thickness of 25μm.

[0118] Heat dissipation channel design: The heat dissipation channel width is 0.6 mm and the spacing is 3 mm, which is consistent with Example 4.

[0119] Cleaning: Initial cleaning was performed with ordinary water instead of isopropyl alcohol solution, without ultrasonic cleaning, and only manual stirring and cleaning for 2 minutes; For deep cleaning, plasma cleaning equipment was not used. The surface was directly rinsed with deionized water without activation treatment.

[0120] Chip soldering and protective coating: The chip mounting and protective coating steps are the same as those in Example 4.

[0121] Comparative Example 5: Preparation process: Substrate preparation: The substrate preparation was consistent with Example 1.

[0122] Chip mounting and soldering: The connection between the solder joints and the metal wiring was not made with conductive nano-glue, but with a traditional high-temperature soldering process. The soldering temperature was set at 250°C and the soldering time was 30 seconds per solder joint.

[0123] Protective coating: The design of the protective coating is consistent with that of Example 1.

[0124] Experiment 1: Thermal Management Performance Test Experimental Description: This experiment compared the thermal management performance of Example 1 with that of Comparative Example 1 to verify how the design of the thermal conductive layer and heat dissipation channels improves chip heat dissipation and management capabilities. By simulating the operating environment of a high-power chip, the temperature rise on the substrate surface, heat accumulation between chips, and the temperature distribution in the heat dissipation channels were tested.

[0125] Experimental procedures Substrate preparation: Example 1: A thermally conductive graphite film (thermal conductivity 1800 W / m·K) and heat dissipation channels (width 0.8 mm, spacing 3 mm) are embedded in a strip substrate.

[0126] Comparative Example 1: The substrate contains only metal wiring, and no thermal conductive graphite film and heat dissipation channels are provided.

[0127] Chip installation: 8 heat simulation chips are installed on the strip substrate, with each chip having a heat output of 2W; the chips are arranged linearly with a spacing of 2mm.

[0128] Test environment: Place the strip substrate in a thermal cycle test device, set the ambient temperature to 30°C, and run the chip for 60 minutes.

[0129] Data collection: Use an infrared thermal imager to record the substrate surface temperature distribution every 10 minutes; record the maximum temperature on the chip surface, the average temperature and temperature difference in the substrate heat dissipation channel area.

[0130] The experimental data were collected as follows Table 1: Comparative data of thermal management performance of Example 1 and Comparative Example 1 Experimental Summary The synergistic effect of the thermally conductive graphite film and the heat dissipation channel was very intuitively demonstrated in this experiment. The efficient lateral thermal conductivity of the thermally conductive graphite film quickly diffused the heat of the chip to a larger area of ​​the substrate, while the heat dissipation channel further guided the heat from the bottom of the chip to the surface of the substrate. This structural optimization significantly reduced heat accumulation between chips and made the heat dissipation path more uniform. Therefore, from the beginning of operation, the temperature distribution of Example 1 was smoother, while Comparative Example 1 showed more obvious local overheating.

[0131] Without the thermally conductive graphite film, heat is mainly transferred by metal wiring. This limitation is very obvious in the experiment, especially in the chip-dense area, where the heat conduction efficiency drops rapidly, causing local temperature rise. The maximum temperature of the chip in Comparative Example 1 rises rapidly, and even after 20 minutes of operation, it is more than 10°C higher than that of Example 1. This overheating may not only lead to the degradation of chip performance, but also affect the reliability of the entire packaging system. The temperature control capability of Example 1 is obviously more suitable for the needs of high-power chips.

[0132] Another point worth noting is that the design of the heat dissipation channels is crucial in dynamic environments. Experimental average temperature difference data demonstrates that the channel width and spacing not only optimize overall heat dissipation efficiency but also play a key role in lateral heat dissipation uniformity. This structural design significantly reduces inter-chip thermal interference and ensures operational stability. This is undoubtedly a significant breakthrough for high-density, multi-chip packaging applications.

[0133] Experiment 2: Dynamic Bending Reliability Test Experimental Description: This experiment evaluated the performance of Example 2 and Comparative Example 5 under dynamic bending conditions, verifying the reliability differences between different conductive connection processes (conductive nano-adhesive and traditional high-temperature soldering) on ​​flexible substrates and under high dynamic stress conditions. Repeated dynamic bending was performed to test solder joint resistance changes and structural integrity.

[0134] Experimental procedures Substrate preparation: Example 2: Conductive nano-glue is used to connect chip solder joints and metal wiring, and the curing conditions are temperature 90° C. and time 35 minutes.

[0135] Comparative Example 5: Traditional high-temperature welding (welding temperature 250°C, welding time 30 seconds / soldering point) was used for connection.

[0136] Test setup: The dynamic bending test equipment was set to a 5mm bending radius, with fixtures securing both ends of the strip substrate and applying cyclic bending stress. The bending frequency was set to 50 cycles / minute, for a total of 50,000 tests.

[0137] Testing process: After every 10,000 bends, the resistance of the chip's solder joints is recorded using electrical performance testing equipment. The interface between the solder joints and the metal wiring is inspected under a microscope to observe whether there are cracks or breaks.

[0138] Test parameters: Solder resistance change (Ω): record the fluctuation of solder resistance; Solder failure rate (%): calculate the proportion of solder failures; observe whether there are cracks or peeling on the coating surface.

[0139] Table 2: Comparison of solder joint performance between Example 2 and Comparative Example 5 under dynamic bending conditions Experimental Summary The difference in solder joint performance under dynamic bending is obvious. The resistance change of the solder joint in Example 2 is very small, and even after 50,000 bends, it remains within 0.22Ω. This shows that the conductive nano-adhesive has high flexibility and adhesion under dynamic stress, can adapt to the bending deformation of the strip substrate, and continue to maintain good electrical connection. In contrast, the traditional high-temperature welding used in Comparative Example 5, because the solder joint is rigid after curing, gradually develops interface microcracks and increased resistance after multiple bends, ultimately resulting in a solder joint failure rate of more than 30%. This phenomenon is closely related to the inherent brittleness of metal solder joints in traditional welding methods.

[0140] Looking at the coating's performance, the flexible silicone coating in Example 2 maintained excellent adhesion and elasticity throughout the experiment, with no cracking or flaking observed. The flexible silicone's toughness provided the necessary cushioning for the substrate surface, while effectively protecting the solder joints and chip area under dynamic bending conditions. In contrast, the epoxy coating in Comparative Example 5, due to its lack of flexibility, began to exhibit localized cracking after 30,000 bends, accelerating solder joint failure.

[0141] It must be mentioned that the bending radius is set to 5mm, simulating a more severe dynamic working environment. The adhesion strength and dynamic adaptability of the flexible conductive adhesive showed unique advantages in this test, and it can maintain the continuity of the electrical connection. In contrast, the rigidity defects of the traditional welding method under high dynamic stress are exposed. It can be seen that the process design of Example 2 is more suitable for flexible electronics and dynamic application scenarios, especially in multi-chip high-density packaging, and can better meet the dual needs of mechanical reliability and electrical stability.

[0142] Experiment 3: Comparison of packaging density and heat dissipation efficiency Experimental Description: This experiment aims to evaluate the impact of different chip arrangements and spacing designs on packaging density and heat dissipation performance. By comparing the matrix arrangement of Example 2 with the linear arrangement of Comparative Example 2, the differences in chip thermal management and space utilization efficiency are analyzed to verify the advantages of the optimized design.

[0143] Experimental procedures Substrate preparation: Example 2: The strip substrate is arranged in a matrix, the chip spacing is 3 mm, the thermal conductive graphite film thickness is 20 μm, the heat dissipation channel width is 1 mm, and the spacing is 2 mm; Comparative Example 2: The strip substrate is arranged linearly, the chip spacing is 0.5 mm, and the heat dissipation channel density is not adjusted.

[0144] Chip installation: 16 analog chips are installed on each strip substrate. The power of a single chip is 1.5W, and the total power is 24W. The analog chips are connected using conductive nano glue, and the curing conditions are 90℃ and the time is 35 minutes.

[0145] Experimental setup: Test equipment: Install the strip substrate on the test platform and record the chip operating temperature after power is applied; Test time: The chip running time is set to 30 minutes; Monitoring method: Infrared thermal imager records the temperature distribution of the chip surface and heat dissipation channel every 10 minutes.

[0146] Experimental data collection: temperature rise of the chip after 30 minutes of operation; temperature uniformity (temperature difference range) on the surface of the heat dissipation channel; number of chips per unit area, as an indicator of packaging density.

[0147] Table 3: Comparative data of packaging density and heat dissipation performance between Example 2 and Comparative Example 2 Experimental Summary The results of the experiment are clear at a glance. Example 2 with a matrix arrangement shows a more balanced heat dissipation capability. The optimized design of the heat dissipation channel plays a key role in controlling the temperature rise. In the thermal imaging diagram, there is almost no temperature difference on the surface of the channel in Example 2, indicating that the combination of the graphite film and the channel achieves efficient heat diffusion. However, in Comparative Example 2, a linear arrangement is used, and the distance between the chips is too small, resulting in local accumulation of heat, which leads to a significant increase in the temperature difference on the surface of the channel. This temperature difference not only limits the heat dissipation efficiency, but may also cause thermal interference between chips.

[0148] The difference in packaging density is also worth noting. Although Comparative Example 2 uses a smaller chip pitch and increases the number of chips per unit area, the heat dissipation problem it brings is difficult to ignore. High-density arrangement, without corresponding heat dissipation optimization design, can easily weaken overall performance due to heat accumulation. On the other hand, Example 2 uses a reasonable chip pitch and matrix layout, slightly sacrificing some density in exchange for more stable heat dissipation performance. This trade-off is obviously more practical.

[0149] It is worth mentioning that the layout design of the heat dissipation channel plays a decisive role in reducing the operating temperature of the chip. In Comparative Example 2, the width and spacing of the heat dissipation channel are not optimized, making it difficult for the chip heat to diffuse quickly. In contrast, in Example 2, the channel width is larger and the density is higher, forming an efficient heat conduction network. In the multi-chip packaging scenario, this improvement in thermal management can obviously significantly improve operating efficiency and reliability.

[0150] Experiment 4: Mechanical Strength and Heat Dissipation Performance Test of Protective Coating Experimental description: This experiment aimed to evaluate the effects of adding aluminum oxide nanoparticles and graphene to a flexible silicone coating on its mechanical strength and heat dissipation performance. By comparing Example 3 with Comparative Example 3, the performance advantages of the optimized protective coating were verified and its actual effectiveness during chip operation was tested.

[0151] Experimental procedures Sample preparation: Example 3: The protective coating consists of two layers: the first layer is an epoxy resin protective coating with a thickness of 30 μm; the second layer is a flexible silicone coating with a thickness of 35 μm, the silicone matrix accounts for 75%, the aluminum oxide nanoparticles account for 10%, and the graphene accounts for 10%.

[0152] Comparative Example 3: The protective coating is only a silica gel matrix (without adding aluminum oxide nanoparticles and graphene), with a thickness of 35 μm.

[0153] Mechanical strength test: Use wear resistance testing equipment to load the grinding wheel to perform friction test on the coating surface; Test parameters: grinding wheel pressure was set to 0.5N, and friction time was 10 minutes. After the test, the wear depth of the coating was measured using a thickness gauge.

[0154] Heat dissipation performance test: Eight heat simulation chips were installed on the strip substrate of each sample. The power of each chip was 1.5W, and the total power was 12W. The operating time was 30 minutes. The temperature distribution on the coating surface was recorded every 10 minutes using an infrared thermal imager. The heat dissipation capacity and temperature difference distribution of the coating surface were analyzed.

[0155] Test parameter records: Mechanical strength: Coating wear depth (μm); Heat dissipation performance: Coating surface average temperature and temperature difference (℃) Table 4: Comparative data of mechanical strength and heat dissipation performance between Example 3 and Comparative Example 3 Experimental Summary The improved effect of the flexible silicone coating was clearly demonstrated in the experiment. The coating in Example 3 exhibited better wear resistance, with a wear depth of only 3.2 μm, thanks to the reinforcing effect of the aluminum oxide nanoparticles. As a high-hardness filler, the aluminum oxide particles formed a dense dispersed network in the coating, effectively improving the surface strength. In Comparative Example 3, due to the lack of this filler, the mechanical strength of the silicone matrix was lower, resulting in a wear depth of up to 8.5 μm under friction pressure. This strength difference directly affects the stability of the coating during long-term use.

[0156] In the heat dissipation performance test, the addition of graphene also shows its value. In Example 3, the average temperature of the coating surface is only 43.7°C, which has a significant cooling effect compared to 56.1°C in Comparative Example 3. The high thermal conductivity of graphene can quickly transfer the heat generated by the chip operation from a local area to a larger range, thereby reducing the temperature accumulation on the chip surface. On the contrary, due to the lack of efficient heat conduction materials, the temperature difference on the coating surface in Comparative Example 3 is as high as 10.4°C, showing a serious problem of local heat accumulation. The unevenness of heat dissipation further highlights the necessity of graphene in the coating.

[0157] The test data also reveals the trade-offs and optimization potential in material design. The flexible silicone matrix itself possesses good elasticity and adaptability, but in dynamic applications, a single matrix material struggles to simultaneously meet the requirements for mechanical strength and heat dissipation. By introducing different functional fillers, such as alumina and graphene, into the matrix, not only does the coating's durability improve, but thermal management is also optimized. This multifunctional material combination strategy is clearly more suitable for the complex operating conditions of high-density multi-chip packaging.

[0158] Experiment 5: Effect of Cleaning Process on Bond Strength Experimental description: This experiment aimed to evaluate the effects of different cleaning processes on the bond strength between chip solder joints and substrates. By comparing Example 4 with Comparative Example 4, we analyzed the effect of using isopropyl alcohol and plasma cleaning on bond strength, verifying the necessity of surface treatment and its contribution to the bonding performance of conductive nano-adhesives.

[0159] Experimental procedures Sample preparation: Example 4: The strip substrate was cleaned by isopropyl alcohol ultrasonic cleaning (50 Hz, 22 minutes) and oxygen plasma cleaning (RF power 110 W, cleaning time 1 minute), and surface activation treatment was completed (oxygen flow rate 20 sccm, cleaning time 30 seconds).

[0160] Comparative Example 4: The strip substrate was manually cleaned with ordinary water only, without ultrasonic or plasma treatment.

[0161] Chip installation: 8 analog chips are installed on each substrate, and the solder joints and metal wiring are bonded using conductive nano-adhesive. The curing condition of the nano-adhesive is 90°C for 35 minutes.

[0162] Test setup: Bond strength testing was performed using a tensile testing device. A clamp secured the strip substrate, gradually applying load and recording the maximum tensile force at which the solder joint began to separate. Each chip was tested three times, with the data recorded and averaged.

[0163] Test parameter records: Bond strength (N / mm²): record the maximum tensile force value of the solder joint; Interface failure ratio (%): calculate the percentage of the total number of solder joint failures.

[0164] Table 5: Comparative data on bonding strength between Example 4 and Comparative Example 4 Experimental Summary The role of the cleaning process in improving the bonding strength is obviously not to be ignored. Experimental data show that the bonding strength of the substrate of Example 4 after isopropyl alcohol and plasma cleaning reached 12.8N / mm², while that of Comparative Example 4 was only 7.5N / mm², a gap of nearly 70%. This strength difference is due to the effective removal of contaminants on the surface of the substrate by the cleaning process. Impurities such as particles and organic matter may remain on the surface of the untreated substrate. These contaminants will prevent the conductive nano glue from forming a tight bond with the substrate. Plasma cleaning not only cleans the surface, but also improves the wettability and adhesion of the nano glue through surface activation, forming a stronger bonding interface.

[0165] On the other hand, the proportion of interface failures can better reflect the profound impact of the cleaning process. In Comparative Example 4, 15% of the solder joints failed during the tensile test, indicating that insufficient surface cleaning can lead to microcracks or weak bonding areas at the bonding interface. These defects can easily expand in high-stress environments and ultimately cause overall failure. In contrast, in Example 4, due to the improved chemical and physical bonding strength of the substrate surface after cleaning and activation, the solder joints maintained their integrity under the same conditions and did not fail during the test.

[0166] Improved bonding performance is also closely related to the properties of the conductive nanoadhesive. The bond strength of the conductive adhesive depends not only on its own adhesion but also on the wettability and chemical affinity of the substrate surface. Plasma activation treatment increases the free energy of the substrate surface, strengthening the intermolecular forces of the conductive adhesive and creating a more stable connection between the solder joint and the metal wiring. This combined cleaning and activation process is clearly crucial for improving bonding reliability in multi-chip packaging.

[0167] Experiment 6: Low temperature environment performance test Experimental description: The experiment aimed to evaluate the performance stability of multi-chip packages of different designs in low-temperature environments and verify the electrical connection reliability and solder joint failure of Examples 1, 2, and Comparative Example 3 under extreme conditions. The low-temperature operation tests analyzed the adaptability and advantages of the combined process of thermally conductive graphite film and conductive nano-adhesive at low temperatures.

[0168] Experimental procedures Sample preparation: Example 1: A thermally conductive graphite film and an optimized heat dissipation channel are embedded in the substrate, and the solder joints are connected using conductive nano-adhesive. The curing conditions are 90°C and the curing time is 35 minutes. Example 2: A matrix-arranged chip arrangement is used, conductive nano-glue is used as the solder joint connection material, and the curing conditions are the same as above; Comparative Example 3: No thermal conductive graphite film was added, only a single silicone matrix was used as a protective coating, and the solder joints were soldered using a high-temperature soldering process (250°C, 30 seconds / solder point).

[0169] Experimental setup: The samples were placed in a low-temperature test chamber with the ambient temperature set to -40°C. The chip operating state was simulated, with each chip consuming 1.5W of power and a total operating time of 60 minutes. Electrical testing equipment was used to record the resistance changes of the chip solder joints every 10 minutes.

[0170] Test parameters: Chip solder joint resistance change (Ω): monitors the stability of electrical connections; Solder joint failure rate (%): measures the percentage of solder joints that are completely broken after the test.

[0171] Table 6: Performance comparison data of Example 1, Example 2 and Comparative Example 3 under low temperature conditions Experimental Summary Under low temperature conditions, the differences in material properties and connection processes are further amplified. The resistance variation of the solder joints in Example 1 and Example 2 is only 0.02Ω and 0.03Ω, respectively, showing extremely high electrical connection stability. This result shows that the bonding ability of the conductive nano-adhesive is not significantly affected in a low temperature environment. Its flexible properties enable it to adapt to the deformation of the substrate during low temperature shrinkage, avoiding interface fracture or microcracks. Comparative Example 3 is different. Due to the use of a high-temperature welding process, the solder joints became brittle in a low temperature environment, resulting in a resistance variation of up to 0.11Ω, and the solder joint failure rate reached 18%. This shows that traditional welding processes have poor adaptability in extreme environments.

[0172] More notably, the effectiveness of the thermally conductive graphite film was also verified in experiments. In Examples 1 and 2, the graphite film's efficient lateral thermal conductivity helped the chip maintain a relatively uniform heat distribution during low-temperature operation, alleviating stress concentration caused by localized thermal expansion and contraction differences. This was not evident in Comparative Example 3, where the sample without the graphite film exhibited uneven internal heat distribution, exacerbating thermal stress failure in the solder joints.

[0173] In addition, the role of the protective coating cannot be ignored. The flexible silicone coating in Example 1 and Example 2 not only improves the mechanical strength by optimizing the formula, but also maintains good flexibility under low temperature conditions. The coating forms a buffer area between the chip and the environment, which effectively resists the stress concentration and crack propagation caused by low temperature. However, Comparative Example 3 only uses a single silicone matrix and lacks the support of reinforcing fillers. The mechanical properties of the coating are greatly reduced, which is also one of the reasons for the high solder joint failure rate. These data once again prove the key significance of material optimization and process improvement for adaptability to extreme environments.

[0174] While embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions, and variations may be made to these embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the appended claims and their equivalents.

Claims

1. A method for implementing multi-chip packaging on a strip, characterized in that: The following steps are involved: Step 1, preparing a strip substrate, wherein the strip substrate includes a surface layer, an intermediate functional layer and a bottom layer, wherein the surface layer is a protective film, the intermediate functional layer is embedded with metal wiring and a heat conducting layer, and the bottom layer is a supporting material; Step 2: embedding a heat-conducting layer and a heat-dissipating channel in the strip substrate to guide the heat when the chip is running; Step 3: Clean and activate the surface of the strip substrate, and apply adhesive material to the middle functional layer; Step 4, flip-chip soldering multiple chips to different chip soldering areas of the strip substrate, fixing them respectively by adhesive materials, and electrically connecting each chip soldering point to the strip metal wiring; Step 5, coating the bonded chip with a protective layer and curing it; Step 6: Perform a dynamic bending test on the strip to verify the reliability of the packaging structure.

2. A method for implementing multi-chip packaging on a strip according to claim 1, characterized in that: In the step 1, the surface layer of the strip substrate is a polyimide film with a thickness of 5 to 20 μm, the middle functional layer is embedded with metal wiring and a thermal conductive graphite film, the middle functional layer is 10 to 50 μm thick, the metal wiring is 5 to 15 μm thick, the thermal conductive graphite film is 5 to 35 μm thick, and the bottom layer is a liquid crystal polymer film, and the total thickness is controlled at 25 to 100 μm.

3. The method for implementing multi-chip packaging on a strip according to claim 1, characterized in that: In step 2, the heat-conducting layer is a heat-conducting graphite film or a micro heat pipe, and its thermal conductivity is greater than 1500 W / m·K. The width of the heat dissipation channel is 0.5 to 1 mm, which is distributed under multiple chip welding areas and is used to conduct the heat generated by the chip during operation to the heat dissipation surface of the strip substrate.

4. The method for implementing multi-chip packaging on a strip according to claim 1, characterized in that: In step 4: Cleaning includes: (1) Preliminary cleaning: Place the strip substrate in an ultrasonic cleaning device filled with isopropyl alcohol and clean it at 40-60 Hz for 20-25 min. After cleaning, rinse the strip substrate with deionized water. (2) Deep cleaning: Use plasma cleaning equipment to clean the strip substrate after preliminary cleaning. Oxygen is used as gas, the gas flow rate is 10-50sccm, the working pressure is 100-300mTorr, the RF power is 50-200W, and the cleaning time is 1-2min. Surface activation includes: (1) Plasma activation: Use plasma equipment to activate the surface of the cleaned strip. Oxygen is used as gas, the gas flow rate is 10-30sccm, the working pressure is 100-200mTorr, the RF power is 50-100W, and the cleaning time is 0.5-1min.

5. The method for implementing multi-chip packaging on a strip according to claim 4, characterized in that: The bonding material includes conductive nano glue.

6. The method for implementing multi-chip packaging on a strip according to claim 5, characterized in that: In step 4, multiple chips are distributed on the strip substrate in a linear arrangement or a matrix arrangement, the spacing between each chip is 1 to 5 mm, and the electrical connection between the solder joints and the metal wiring is bonded by conductive nano glue.

7. The method for implementing multi-chip packaging on a strip according to claim 1, characterized in that: In step 5, the protective layer is divided into two layers, the first layer is an epoxy resin protective coating with a thickness of 20 to 50 μm, and the second layer is a flexible silicone coating with a thickness of 30 to 50 μm, and the first layer is close to the chip.

8. The method for implementing multi-chip packaging on a strip according to claim 6, characterized in that: Flexible silicone coating includes: Flexible silicone matrix, accounting for 70% to 80%; Alumina nanoparticles, accounting for 10% to 15%; Graphene accounts for 5% to 10%.

9. The method for implementing multi-chip packaging on a strip according to claim 1, characterized in that: The curing conditions of the flexible silicone coating are: temperature 80-120°C, time 0.8-1h.

10. The method for implementing multi-chip packaging on a strip according to claim 1, characterized in that: The dynamic bending test in step 6 simulates a bending radius of less than 5 mm and repeated bending times of not less than 10,000 times, and is used to verify the reliability of the strip substrate and chip packaging.

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