RFSOI structure and its formation method

Abstract

The present invention provides an RFSOI structure and a method for forming the same. The first charge capture layer and the second charge capture layer are sequentially formed on a supporting wafer. The materials of the first charge capture layer and the second charge capture layer are different and the insulation of the second charge capture layer is higher than that of the first charge capture layer. Since the second charge capture layer has high insulation, the electrical insulation of the substrate can be effectively improved, thereby enhancing the radio frequency performance of the RFSOI structure. Since the second charge capture layer is added, the present invention can enhance the radio frequency performance of the RFSOI structure without setting a thicker first charge capture layer. Therefore, the present invention reduces the thickness of the first charge capture layer. The first charge capture layer is thinner, has smaller grains, and has more grain boundaries, and has a stronger charge capture capability, that is, the charge capture capability of the first charge capture layer is improved, and the thickness of the first charge capture layer is reduced while reducing the warpage of the RFSOI structure. In this way, the present invention improves the geometric performance and radio frequency performance of the RFSOI structure.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a RFSOI structure and a method for forming the same. Background Art

[0002] SOI (Silicon-On-Insulator) is a semiconductor material in which a thin layer of silicon is placed on top of an insulating layer (usually silicon dioxide). This structure can improve device performance and reduce parasitic capacitance and leakage current, thereby improving power efficiency and signal performance. In addition, SOI technology helps reduce device size and meet the requirements of increasingly miniaturized modern electronic devices.

[0003] RFSOI (Radio Frequency Silicon-On-Insulator) is an emerging technology that combines radio frequency (RF) technology with SOI. This technology is mainly used in radio frequency integrated circuits (RFIC), radio frequency front-end modules and other wireless communication devices. RFSOI performs well in high-frequency operations and can process high-frequency signals while reducing signal loss. Due to the characteristics of SOI materials, RFSOI circuits generally have lower power consumption, which helps to improve the battery life of mobile devices. RFSOI allows more functions to be integrated on a chip, reducing the size of the device and improving the reliability of the system. The RFSOI structure can effectively manage heat dispersion and reduce the negative impact of thermal effects on circuit performance.

[0004] RFSOI improves the electrical insulation of the substrate and enhances the RF performance by introducing polysilicon (poly-Si) as a charge trapping layer between the support wafer and the buried oxide layer. The smaller the poly-Si grains, the more grain boundaries there are, and the stronger the ability to trap charges. However, the grain size is uncontrollable during the growth process. As the thickness of polysilicon increases, the grains become larger, and thicker polysilicon will worsen the warpage of RFSOI. Summary of the invention

[0005] The object of the present invention is to provide a RFSOI structure and a method for forming the same, so as to solve at least one of the problems of a thicker charge trapping layer, larger grains and worsened warpage in the RFSOI structure.

[0006] In order to solve the above technical problems, the present invention provides a method for forming a RFSOI structure, comprising:

[0007] Provide support wafers and device wafers;

[0008] forming a first charge trapping layer, wherein the first charge trapping layer is located on the supporting wafer;

[0009] forming a second charge capture layer, the second charge capture layer being located on the supporting wafer and covering the first charge capture layer, the first charge capture layer and the second charge capture layer being made of different materials and having higher insulation than the first charge capture layer;

[0010] performing a thermal oxidation process to form a buried oxide layer on the device wafer;

[0011] A bonding process is performed to bond the support wafer and the device wafer, and the second charge trapping layer is bonded to the buried oxide layer to form a RFSOI structure.

[0012] Optionally, the first charge trapping layer is formed by a normal pressure chemical vapor deposition process, and the second charge trapping layer is formed by an atomic layer deposition process.

[0013] Optionally, the first charge trapping layer is polycrystalline silicon or porous silicon, and the second charge trapping layer is aluminum oxide.

[0014] Optionally, the thickness of the first charge capture layer is 0.01 micrometer to 0.05 micrometer, and the thickness of the second charge capture layer is 0.01 micrometer to 0.05 micrometer.

[0015] Optionally, the warpage of the RFSOI structure is less than 50 microns, and the second harmonic loss of the RFSOI structure is less than or equal to -100 dBm.

[0016] Optionally, before performing the bonding process, an ion implantation process is performed to form an implantation damage layer below the buried oxide layer of the device wafer and near the interface between the buried oxide layer and the device wafer; and after performing the bonding process, a stripping process is performed to strip the device wafer at the implantation damage layer to reduce the thickness of the device wafer.

[0017] Optionally, the ions implanted in the ion implantation process are hydrogen ions or hydrogen-helium mixed ions.

[0018] Optionally, the implantation depth of the ion implantation process is 0.2 micrometer to 0.3 micrometer.

[0019] Optionally, after performing the bonding process and the stripping process, a planarization and thinning process is performed to make the thickness of the device wafer be 0.01 micrometer to 0.1 micrometer.

[0020] Based on the same inventive concept, the present invention also provides an RFSOI structure, including a supporting wafer and a device wafer located on the supporting wafer, the supporting wafer is used to support the device wafer, a first charge capture layer, a second charge capture layer and a buried oxide layer are formed in the supporting wafer and the device wafer; the first charge capture layer and the second charge capture layer are made of different materials and the second charge capture layer has higher insulation than the first charge capture layer.

[0021] In the method for forming the RFSOI structure provided by the present invention, a first charge capture layer and a second charge capture layer are sequentially formed on a supporting wafer, wherein the materials of the first charge capture layer and the second charge capture layer are different and the insulation of the second charge capture layer is higher than that of the first charge capture layer. Since the second charge capture layer has high insulation, the electrical insulation of the substrate can be effectively improved, thereby enhancing the RF performance of the RFSOI structure. Since the second charge capture layer is added, the present invention can enhance the RF performance of the RFSOI structure without setting a thicker first charge capture layer. Therefore, the present invention reduces the thickness of the first charge capture layer, the first charge capture layer has a thinner thickness, smaller grains, more grain boundaries, and a stronger charge capture capability, that is, the charge capture capability of the first charge capture layer is improved, and the thickness of the first charge capture layer is reduced while reducing the warpage of the RFSOI structure. In this way, the present invention improves the geometric performance and RF performance of the RFSOI structure. In the present invention, the thickness of the first charge capture layer does not need to be too thick, which avoids the problem of excessively large grains, weak charge capture capability, and deterioration of the warpage of the RFSOI structure caused by the excessive thickness of the first charge capture layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Those skilled in the art will appreciate that the accompanying drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.

[0023] Figure 1 It is a flow chart of a method for forming an RFSOI structure according to an embodiment of the present invention.

[0024] Figures 2 to 7 It is a structural schematic diagram corresponding to the steps of the method for forming the RFSOI structure according to an embodiment of the present invention.

[0025] In the attached figure:

[0026] 10 - support wafer; 11 - first charge trapping layer; 12 - second charge trapping layer; 20 - device wafer; 21 - buried oxide layer. DETAILED DESCRIPTION

[0027] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.

[0028] As used in the present invention, the singular forms "one", "an" and "the" include plural objects, the term "or" is usually used to include the meaning of "and / or", the term "several" is usually used to include the meaning of "at least one", and the term "at least two" is usually used to include the meaning of "two or more". In addition, the terms "first", "second" and "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined as "first", "second" and "third" can explicitly or implicitly include one or at least two of the features. In addition, as used in the present invention, an element is arranged on another element, which usually only indicates that there is a connection, coupling, matching or transmission relationship between the two elements, and the connection, coupling, matching or transmission between the two elements can be direct or indirect through an intermediate element, and cannot be understood as indicating or implying the spatial position relationship between the two elements, that is, an element can be in any orientation such as inside, outside, above, below or on one side of another element, unless the content clearly indicates otherwise. For those skilled in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0029] Figure 1 : is a flow chart of a method for forming an RFSOI structure according to an embodiment of the present invention. This embodiment provides a method for forming an RFSOI structure, comprising:

[0030] Step S10, providing a support wafer and a device wafer;

[0031] Step S20, forming a first charge trapping layer, wherein the first charge trapping layer is located on the supporting wafer;

[0032] Step S30, forming a second charge capture layer, wherein the second charge capture layer is located on the support wafer and covers the first charge capture layer, the first charge capture layer and the second charge capture layer are made of different materials and the second charge capture layer has higher insulation than the first charge capture layer;

[0033] Step S40, performing a thermal oxidation process to form a buried oxide layer on the device wafer;

[0034] Step S50 , performing a bonding process to bond the support wafer and the device wafer, and the second charge trapping layer is bonded to the buried oxide layer to form a RFSOI structure.

[0035] Figures 2 to 7 1 is a schematic diagram of the corresponding structure of the method for forming the RFSOI structure of the embodiment of the present invention. In order to make the above-mentioned purpose, features and beneficial effects of the present invention more obvious and easy to understand, the following is a schematic diagram of the corresponding structure of the method for forming the RFSOI structure of the embodiment of the present invention. Figures 2 to 7 The specific embodiments of the present invention are described in detail.

[0036] like Figure 2 and Figure 4 As shown, a support wafer 10 and a device wafer 20 are provided, and the support wafer 10 is used to support the device wafer 20 when the device wafer 20 is thinned. The device wafer 20 provides an operating platform for subsequent processes, and can be any substrate for carrying semiconductor integrated circuit components known to those skilled in the art, and can be a bare chip or a wafer processed by an epitaxial growth process. In detail, the substrate of the device wafer 20 is, for example, a silicon-on-insulator (SOI) substrate, a bulk silicon substrate, a germanium substrate, a germanium silicon substrate, an indium phosphide (InP) substrate, a gallium arsenide (GaAs) substrate, or a germanium-on-insulator substrate. In this embodiment, the device wafer 20 is a silicon wafer.

[0037] Specifically, the supporting wafer 10 in this embodiment is selected by providing a silicon ingot grown by the Czochralski method, the crystal growth direction of which is <100> , the edge of the ingot is rolled to the target diameter and segmented. The crystal segment is sliced, and the slicing angle is controlled to be within 5° to 9°, wherein the slicing angle is the angle between the surface and the (100) surface, and then the final silicon wafer is obtained as the support wafer 10 after grinding, polishing and cleaning. The thickness of the support wafer 10 is, for example, 500 microns to 800 microns. The wafer diameter of the support wafer 10 is 150mm, 200mm or 300mm. The resistivity of the support wafer 10 is higher than 500ohm-cm, and the oxygen content in the support wafer 10 is not higher than 5new ppma.

[0038] Specifically, the device wafer 10 in this embodiment is selected by providing another crystal segment, the crystal growth direction of which is <100> The slice angle is controlled to be 0.1° to 0.5°, and the final silicon wafer is obtained as the device wafer 10 after subsequent grinding, polishing and cleaning. The thickness of the device wafer 10 is, for example, 500 microns to 800 microns. The diameter of the device wafer 10 is, for example, 150 mm, 200 mm or 300 mm.

[0039] Please continue to refer to Figure 2, forming a first charge capture layer 11, the first charge capture layer 11 is located on the support wafer 10, and the first charge capture layer 11 is introduced to improve the electrical insulation of the support wafer 10 and enhance the RF performance of the RFSOI structure. The material of the first charge capture layer 11 is polycrystalline silicon or porous silicon. The material of the first charge capture layer 11 in this embodiment is, for example, polycrystalline silicon. The first charge capture layer 11 is formed by an APCVD (Atmospheric Pressure Chemical Vapor Deposition) process. The process temperature of the APCVD process is, for example, 850°C to 1050°C, and the gas source of the APCVD process is micro SiHCl3 and H2. By controlling the growth time of the APCVD process, and after the first charge capture layer 11 is formed, a chemical mechanical polishing (CMP) single-side polishing process is performed to make the thickness of the first charge capture layer 11 0.01 microns to 0.05 microns. Since the thickness of the first charge capture layer 11 is relatively thin, the grain size of the first charge capture layer 11 is controlled to be less than 0.5 microns. The first charge trapping layer 11 has smaller grains and more grain boundaries, and has a stronger charge trapping capability. After the chemical mechanical polishing process, the support wafer 10 is cleaned to remove the natural oxide layer on the surface of the support wafer 10, and the cleaning solution includes hydrofluoric acid (HF).

[0040] like Figure 3 As shown, a second charge capture layer 12 is formed, and the second charge capture layer 12 is located on the support wafer 10 and covers the first charge capture layer 11. The materials of the first charge capture layer 11 and the second charge capture layer 12 are different, and the insulation of the second charge capture layer 12 is higher than that of the first charge capture layer 11. The material of the second charge capture layer 12 is aluminum oxide (Al2O3). The thickness of the second charge capture layer 12 is 0.01 microns to 0.05 microns. The second charge capture layer 12 is formed by an atomic layer deposition process (ALD). The gas source of the atomic layer deposition process is Al(CH3)3 and water vapor. It is worth emphasizing that the time interval between the cleaning process after the double-sided polishing process and the atomic layer deposition process does not exceed 4 hours to avoid the formation of a natural oxide layer on the surface of the support wafer 10 again. In this embodiment, by adding the second charge capture layer 12, the second charge capture layer 12 has high mechanical strength, good thermal conductivity, high electrical strength and insulation, low dielectric loss, and relatively stable electrical properties with temperature and frequency changes. It is worth emphasizing that insulation refers to the resistivity of a material. For example, the resistivity of polysilicon is 1000 ohm.cm-20000 ohm.cm, and the resistivity of aluminum oxide is usually around 10 14 ohm.cm to 10 16ohm.cm, the resistivity of aluminum oxide is much higher than that of polysilicon, that is, the insulation of aluminum oxide is much higher than that of polysilicon. In other words, the insulation of the second charge capture layer 12 is much higher than that of the first charge capture layer 11. Due to the high insulation of the second charge capture layer 12, the electrical insulation between the support wafer 10 and the device wafer 20 can be effectively improved, thereby enhancing the RF performance of the RFSOI structure. There is no need to set a thicker first charge capture layer in the RFSOI structure, which solves the problem of excessively large grains, weak charge capture capability, and worsened warpage caused by the excessive thickness of the first charge capture layer in the traditional RFSOI structure.

[0041] like Figure 4 As shown, a thermal oxidation process is performed to form a buried oxide layer 21 on the device wafer 20. The buried oxide layer has a thickness of 0.01 micrometer to 0.2 micrometer.

[0042] like Figure 5 As shown, an ion implantation process is performed to form an implantation damage layer below the buried oxide layer 21 of the device wafer 20 and near the interface between the buried oxide layer 21 and the device wafer 20. The ions implanted in the ion implantation process are hydrogen ions or hydrogen-helium mixed ions. The implantation depth of the ion implantation process is 0.2 microns to 0.3 microns.

[0043] like Figure 6 As shown, a bonding process is performed to bond the support wafer 10 and the device wafer 20, and the second charge trapping layer 12 is bonded to the buried oxide layer 21 to form a RFSOI structure.

[0044] like Figure 7As shown, a stripping process is performed, and the device wafer 20 is stripped at the injection damage layer to reduce the thickness of the device wafer, so that the top silicon of the RFSOI structure reaches the target thickness. In the stripping process, the thickness of part of the device wafer 20 away from the buried oxide layer 21 is stripped. The stripping process is a smart stripping (Smart-Cut) technology. Smart stripping technology includes an annealing process, which causes the ion-implanted H+ or He+ to form bubbles, that is, to form a stripping layer; then the stripping layer is separated to achieve thinning of the device wafer 20. After performing the stripping process, a flattening and thinning process is performed to make the thickness of the device wafer 20 0.01 microns to 0.1 microns. The RFSOI structure in this embodiment adds a second charge capture layer. Since the second charge capture layer has high insulation, it can effectively improve the electrical insulation of the substrate, thereby enhancing the RF performance of the RFSOI structure. The second harmonic loss (HD2) of the RFSOI structure is less than or equal to -100dBm. And due to the thinning of the first charge capture layer of the RFSOI structure, the grain size of the first charge capture layer 11 is controlled to be less than 0.5 microns, which improves the charge capture capability and reduces the warping of the RFSOI structure so that the warping of the RFSOI structure is less than 50um.

[0045] Please continue to refer to Figure 7 , this embodiment also provides an RFSOI structure, including a support wafer 10 and a device wafer 20 located on the support wafer 10 and bonded to the support wafer 10, the support wafer 10 is used to support the device wafer 20, the support wafer 10 and the device wafer 20 are formed with a first charge capture layer 11, a second charge capture layer 12 and a buried oxide layer 21, the first charge capture layer 11 and the second charge capture layer 12 are made of different materials and the insulation of the second charge capture layer 12 is higher than the insulation of the first charge capture layer 11. In this embodiment, by adding the second charge capture layer 12, due to the high insulation of the second charge capture layer 12, the electrical insulation between the support wafer 10 and the device wafer 20 can be effectively improved, thereby enhancing the RF performance of the RFSOI structure. There is no need to set a thicker first charge capture layer in the RFSOI structure, which solves the problem of excessively large grains, weak charge capture capability, and deteriorated warpage of the RFSOI structure caused by the excessive thickness of the first charge capture layer in the traditional RFSOI structure.

[0046] The inventor conducted an experiment, and the experiment was set up in three groups. In the first and second experiments, only a first charge capture layer 11 was formed on the supporting wafer, and the first charge capture layer 11 was a polycrystalline silicon layer, but the thickness of the first charge capture layer 11 was different. The thickness of the first charge capture layer 11 in the first experiment was 0.04 microns, and the thickness of the first charge capture layer 11 in the second experiment was 1.8 microns. The third experiment was the technical solution of the present embodiment, that is, not only a first charge capture layer 11 but also a second charge capture layer 12 was formed on the supporting wafer 10, and the second charge capture layer 12 was an aluminum oxide layer. And the thickness of the first charge capture layer 11 was 0.04 microns, which was the same as the thickness of the first charge capture layer 11 in the first experiment, and the thickness of the second charge capture layer 12 was 0.02 microns. Other experimental conditions were the same: a silicon ingot grown by the Czochralski method was provided, and the crystal growth direction was <100> , grind the edge of the ingot to the target diameter and cut it into segments. Slice the crystal segment, control the slicing angle to be 5.2°, and then obtain the final silicon wafer as the support wafer 10 after grinding, polishing and cleaning. The thickness of the support wafer 10 is, for example, 774 microns, the resistivity of the support wafer 10 is, for example, 3200 ohm-cm, and the oxygen content of the support wafer 10 is, for example, 4.1 new ppma. Provide another crystal segment, the crystal growth direction is <100> , the cutting angle is controlled to be 0.28°, and the final silicon wafer is obtained as the device wafer 20 after grinding, polishing and cleaning. The thickness of the device wafer 20 is, for example, 773 microns. The support wafer 10 grows the first charge capture layer 11 through the APCVD process. The process temperature of the APCVD process is 900°C. The gas source of the APCVD process is SiHCl3 and H2. The grain size of the first charge capture layer 11 is controlled to be less than 0.5 microns. By controlling the growth time and subsequent chemical mechanical polishing, the thickness of the first charge capture layer 11 is 0.04 microns. The device wafer 20 is thermally oxidized to obtain a buried oxide layer 21, and the thickness of the buried oxide layer 21 is 0.2 microns. The oxidized device wafer 20 is hydrogen-implanted, and the injection depth is 0.25 microns. The device wafer 20 and the support wafer 10 are bonded after RCA cleaning, and the stripping process is performed after bonding. After the flattening and thinning process, the top silicon thickness of the final device wafer 20 is 0.08 microns.

[0047] Table 1 Experimental study on the effect of the second charge trapping layer on the RFSOI structure

[0048]

[0049] As shown in Table 1, the curvature of the RFSOI structure of the first group of experiments is 32 microns, and the second harmonic loss (HD2) is -56dBm. The curvature of the RFSOI structure of the second group of experiments is 76 microns, and the second harmonic loss (HD2) is -88dBm. The curvature of the RFSOI structure of the third group of experiments is 38 microns, and the second harmonic loss (HD2) is -113dBm. It can be seen that with the increase of the thickness of the first charge capture layer 11, the second harmonic loss (HD2) of the RFSOI structure will indeed increase, that is, the RF performance of the RFSOI structure will increase, but with the increase of the thickness of the first charge capture layer 11, the curvature of the RFSOI structure will also increase. The technical solution provided in this embodiment, by adding the second charge capture layer 12, greatly increases the second harmonic loss (HD2) of the RFSOI structure, and the curvature of the RFSOI structure only increases slightly, which is basically the same as the curvature of the RFSOI structure in the first group of experiments. Therefore, this embodiment adds the second charge capture layer 12. Due to the high insulation of the second charge capture layer 12, when the thickness of the second charge capture layer 12 is very thin, the electrical insulation of the support wafer 10 can be effectively improved, thereby enhancing the RF performance of the RFSOI structure. In the RFSOI structure in this embodiment, there is no need to set a thicker first charge capture layer 11, which solves the problem of excessively large grains due to the excessive thickness of the first charge capture layer 11, weakened charge capture capability, and worsened warpage of the RFSOI structure.

[0050] In summary, in the method for forming the RFSOI structure provided by the embodiment of the present invention, by sequentially forming the first charge capture layer and the second charge capture layer on the supporting wafer, the first charge capture layer and the second charge capture layer are made of different materials and the second charge capture layer has higher insulation than the first charge capture layer. Since the second charge capture layer has high insulation, the electrical insulation of the substrate can be effectively improved, thereby enhancing the RF performance of the RFSOI structure. Since the second charge capture layer is added, the present invention can enhance the RF performance of the RFSOI structure without setting a thicker first charge capture layer. Therefore, the present invention reduces the thickness of the first charge capture layer, the first charge capture layer has a thinner thickness, smaller grains, more grain boundaries, and a stronger charge capture capability, that is, the charge capture capability of the first charge capture layer is improved, and the thickness of the first charge capture layer is reduced while reducing the warpage of the RFSOI structure. In this way, the present invention improves the geometric performance and RF performance of the RFSOI structure. In the present invention, the thickness of the first charge capture layer does not need to be too thick, which avoids the problem of excessively large grains, weak charge capture capability, and deteriorated warpage caused by the excessive thickness of the first charge capture layer.

[0051] In addition, it should be recognized that although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiment according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still belongs to the scope of protection of the technical solution of the present invention.

Claims

1. A method for forming an RFSOI structure, characterized in that: include: Provide support wafers and device wafers; forming a first charge trapping layer, wherein the first charge trapping layer is located on the supporting wafer; forming a second charge capture layer, the second charge capture layer being located on the supporting wafer and covering the first charge capture layer, the first charge capture layer and the second charge capture layer being made of different materials and having higher insulation than the first charge capture layer; performing a thermal oxidation process to form a buried oxide layer on the device wafer; A bonding process is performed to bond the support wafer and the device wafer, and the second charge trapping layer is bonded to the buried oxide layer to form a RFSOI structure.

2. The method for forming the RFSOI structure according to claim 1, characterized in that: The first charge trapping layer is formed by a normal pressure chemical vapor deposition process, and the second charge trapping layer is formed by an atomic layer deposition process.

3. The method for forming the RFSOI structure according to claim 1, characterized in that: The first charge trapping layer is polysilicon or porous silicon, and the second charge trapping layer is aluminum oxide.

4. The method for forming the RFSOI structure according to claim 1, characterized in that: The thickness of the first charge trapping layer is 0.01 micrometer to 0.05 micrometer, and the thickness of the second charge trapping layer is 0.01 micrometer to 0.05 micrometer.

5. The method for forming the RFSOI structure according to claim 1, characterized in that: The warpage of the RFSOI structure is less than 50 micrometers, and the second harmonic loss of the RFSOI structure is less than or equal to -100 dBm.

6. The method for forming the RFSOI structure according to claim 1, characterized in that: Before performing the bonding process, performing an ion implantation process to form an implantation damage layer below the buried oxide layer of the device wafer and near the interface between the buried oxide layer and the device wafer; After the bonding process is performed, a stripping process is performed, and the device wafer is stripped at the implantation damage layer to reduce the thickness of the device wafer.

7. The method for forming the RFSOI structure according to claim 1, characterized in that: The ions implanted in the ion implantation process are hydrogen ions or hydrogen-helium mixed ions.

8. The method for forming the RFSOI structure according to claim 1, characterized in that: The implantation depth of the ion implantation process is 0.2 micrometer to 0.3 micrometer.

9. The method for forming the RFSOI structure according to claim 1, characterized in that: After performing the bonding process and the peeling process, a planarization and thinning process is performed to make the thickness of the device wafer be 0.01 micrometer to 0.1 micrometer.

10. An RFSOI structure, characterized in that: It includes a supporting wafer and a device wafer located on the supporting wafer, wherein the supporting wafer is used to support the device wafer, and a first charge capture layer, a second charge capture layer and a buried oxide layer are formed in the supporting wafer and the device wafer; the first charge capture layer and the second charge capture layer are made of different materials and the second charge capture layer has higher insulation than the first charge capture layer.

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