Method for manufacturing a semiconductor structure

Abstract

The present application discloses a method for manufacturing a semiconductor structure, comprising forming a film layer on a semiconductor layer; forming a patterned resist layer on the film layer; etching the film layer via the patterned resist layer to transfer the pattern of the resist layer to the film layer; and removing the resist layer; wherein the resist layer and etching products are removed by using a plasma containing an oxygen component and a plasma containing a fluorine component.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor structure. Background Art

[0002] The patterning of the semiconductor film layer usually requires photolithography and etching processes. The specific steps usually include: forming a resist layer on the semiconductor film layer, patterning the resist layer using a photolithography process, and etching the semiconductor film layer through the patterned resist layer to transfer the pattern of the resist layer to the semiconductor film layer.

[0003] However, in the process of etching the semiconductor film layer through the patterned resist layer, some etching products are usually introduced or generated. These etching products will affect the subsequent process steps and further affect the overall performance of the semiconductor device. Summary of the invention

[0004] In view of the above problems, an object of the present invention is to provide a method for manufacturing a semiconductor structure.

[0005] According to one aspect of the present invention, a method for manufacturing a semiconductor structure is provided, comprising: forming a film layer on a semiconductor layer; forming a patterned resist layer on the film layer; etching the film layer through the patterned resist layer to transfer the pattern of the resist layer to the film layer; and removing the resist layer and etching products using a plasma containing an oxygen component and a plasma containing a fluorine component.

[0006] Optionally, the resist layer and the etching products are removed by a single ashing step, in which a mixed gas of plasma containing oxygen components and plasma containing fluorine components is used to remove the resist layer and the etching products.

[0007] Optionally, in the mixed gas, the flow rate of the plasma containing the oxygen component is 4000 sccm to 100000 sccm.

[0008] Optionally, in the mixed gas, the flow rate of the plasma containing the fluorine component is 5 sccm to 1000 sccm.

[0009] Optionally, in the mixed gas, the flow rate of the plasma containing the fluorine component is 5 sccm to 300 sccm.

[0010] Optionally, two or more ashing steps are used to remove the resist layer and the etching products; in the first ashing step, a plasma containing a fluorine component or a plasma containing an oxygen component is used; in the second ashing step, a mixed gas of a plasma containing an oxygen component and a plasma containing a fluorine component is used.

[0011] Optionally, in the first ashing step, the flow rate of the plasma containing the fluorine component is 5 sccm-1000 sccm, or the flow rate of the plasma containing the oxygen component is 500 sccm-100000 sccm.

[0012] Optionally, in the second ashing step, the flow rate of the plasma containing the fluorine component is 5 sccm-300 sccm, and the flow rate of the plasma containing the oxygen component is 4000 sccm-100000 sccm.

[0013] Optionally, in the second ashing step, the flow rate of the plasma containing the fluorine component is 5 sccm-1000 sccm, and the flow rate of the plasma containing the oxygen component is 4000 sccm-100000 sccm.

[0014] Optionally, in the second ashing step, the flow rate of the plasma containing the oxygen component is 500 sccm-100000 sccm, and the flow rate of the plasma containing the fluorine component is 5 sccm-1000 sccm.

[0015] Optionally, in the second ashing step, the flow rate of the plasma containing the oxygen component is 500 sccm-100000 sccm, and the flow rate of the plasma containing the fluorine component is 300 sccm-1000 sccm.

[0016] Optionally, a third ashing step may be included, wherein the third ashing step uses plasma containing fluorine components.

[0017] Optionally, in the third ashing, the flow rate of the plasma containing the fluorine component is 5 sccm to 300 sccm.

[0018] Optionally, the ashing step is performed within a pressure range of 0.5 Torr to 2.0 Torr.

[0019] Optionally, the ashing step is performed at a temperature range of 100°C to 350°C.

[0020] The manufacturing method of the semiconductor structure provided by the present invention adopts plasma containing oxygen components and plasma containing fluorine components to remove the resist layer and remove the etching products generated by etching the film layer at the same time.

[0021] In a preferred embodiment, the film layer is an interlayer dielectric layer formed on the semiconductor layer, and the interlayer dielectric layer is etched through the patterned resist layer to form a contact hole in the interlayer dielectric layer. The etching product generated by etching the film layer is a polymer generated by the reaction between the etchant used to etch the interlayer dielectric layer and the resist layer. This embodiment is dedicated to using plasma containing oxygen (O) components (such as O2 plasma) and plasma containing fluorine (F) components (such as CF4 plasma) to remove the polymer at the bottom and sidewall of the contact hole of the resist layer.

[0022] In a preferred embodiment, the film layer is a metal layer formed on a semiconductor layer, and the metal layer is etched through a patterned resist layer to form wiring. The etching product generated by etching the film layer is a product of the reaction between the etchant used to etch the metal layer and the metal layer. This embodiment is dedicated to using a plasma containing an oxygen (O) component (such as O2 plasma) and a plasma containing a fluorine (F) component (such as CF4 plasma) to remove the resist layer and the etching products generated by etching the metal layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0024] Figure 1 A flow chart showing a method for manufacturing a semiconductor structure according to an embodiment of the present application is shown;

[0025] Figure 2 A schematic cross-sectional view showing the formation of an interlayer dielectric layer in the manufacturing process of the semiconductor structure of the first embodiment of the present application is shown;

[0026] Figure 3 A schematic cross-sectional view showing the formation of a contact hole in the manufacturing process of the semiconductor structure according to the first embodiment of the present application;

[0027] Figures 4 to 6b A schematic cross-sectional view showing a step of removing the resist layer PR in the manufacturing process of the semiconductor structure according to the first embodiment of the present application;

[0028] Figure 7 A schematic cross-sectional view showing a patterning step of forming a conductive channel in a manufacturing process of a semiconductor structure according to a first embodiment of the present application;

[0029] Figure 8 A schematic cross-sectional view showing the formation of a metal layer in a manufacturing process of a semiconductor structure according to a second embodiment of the present application;

[0030] Fig. 9 A schematic cross-sectional view showing the formation of wiring in the manufacturing process of the semiconductor structure according to the second embodiment of the present application;

[0031] Figure 10 to Figure 12c A schematic cross-sectional view showing a step of removing the resist layer PR in the manufacturing process of the semiconductor structure according to the second embodiment of the present application;

[0032] Fig.13 A schematic diagram showing defects caused to wiring by etching products in the second embodiment of the present application is shown. DETAILED DESCRIPTION

[0033] The present application will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown.

[0034] When describing the structure of a device, when a layer or a region is referred to as being "on" or "over" another layer or region, it may mean that it is directly on the other layer or region, or that other layers or regions are included between it and the other layer or region. Furthermore, if the device is turned over, the layer or region will be "below" or "beneath" another layer or region.

[0035] If it is intended to describe a situation where it is directly on another layer or another area, this article will use the expression “directly on…” or “on… and adjacent to…”.

[0036] Unless otherwise specified below, the various parts of the semiconductor structure may be composed of materials known to those skilled in the art. Semiconductor materials include, for example, III-V semiconductors, such as gallium arsenide (GaAs), gallium nitride (GaN), etc., IV-IV semiconductors, such as silicon carbide (SiC), etc., II-VI compound semiconductors, such as cadmium sulfide (CdS), cadmium telluride (CdTe), etc., and IV semiconductors, such as silicon (Si), germanium (Ge), etc. The gate conductor may be formed of various materials capable of conducting electricity, such as a metal layer, a doped polysilicon layer, or a stacked gate conductor including a metal layer and a doped polysilicon layer, or other conductive materials, such as TaC, TiN, TaSiN, HfSiN, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSix, Ni3Si, Pt, Ru, W, and combinations of various conductive materials. The gate dielectric layer may be formed of SiO2 or a material having a dielectric constant greater than SiO2, such as oxide, nitride, oxynitride, silicate, aluminate, and titanate. Furthermore, the gate dielectric layer may be formed of not only materials known to those skilled in the art, but also materials developed in the future for the gate dielectric layer.

[0037] This application may be presented in a variety of forms, some examples of which are described below.

[0038] Figure 1 A flow chart of a method for manufacturing a semiconductor structure according to an embodiment of the present application is shown. Figure 1 As shown, the method for manufacturing a semiconductor structure includes:

[0039] forming a film layer on the semiconductor layer;

[0040] forming a patterned resist layer on the film layer;

[0041] Etching the film layer through the patterned resist layer to transfer the pattern of the resist layer into the film layer; and

[0042] The resist layer and the etching products are removed by using plasma containing oxygen and plasma containing fluorine.

[0043] Figures 2 to 7 The cross-sectional views of various stages in the manufacturing process of the semiconductor structure according to the first embodiment of the present application are shown. In this embodiment, the film layer is an interlayer dielectric layer formed on the semiconductor layer, and the interlayer dielectric layer is etched through a patterned resist layer to form a contact hole in the interlayer dielectric layer. The etching product produced by etching the film layer is a polymer generated by the reaction of the etchant used to etch the interlayer dielectric layer and the resist layer. Specifically, during the etching process of the interlayer dielectric layer, the etchant used to etch the interlayer dielectric layer reacts with the resist layer to produce a polymer at the bottom and sidewalls of the contact hole. The embodiment of the present application is committed to using a plasma containing an oxygen (O) component (such as an O2 plasma) and a plasma containing a fluorine (F) component (such as a CF4 plasma) to remove the resist layer and the polymer at the bottom and sidewalls of the contact hole.

[0044] Figure 2 A schematic cross-sectional view showing the formation of an interlayer dielectric layer on a semiconductor layer in the manufacturing process of the semiconductor structure according to the first embodiment of the present application is shown.

[0045] like Figure 2 As shown, the semiconductor layer includes a substrate 101 and a device structure formed in the substrate 101. The device structure includes a diode (Diode), a bipolar junction transistor (Bipolar Junction Transistor, BJT), a field-effect transistor (Field-Effect Transistors, FET), an insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, IGBT) and an integrated circuit integrating one or more of a diode (Diode), a bipolar junction transistor (Bipolar Junction Transistor, BJT), a field-effect transistor (Field-Effect Transistors, FET), and an insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, IGBT) and other device structures. Field-Effect Transistors (Field-Effect Transistors, FET) may also include metal oxide semiconductor field effect transistors (MOSFET), junction field effect transistors (JFET), etc.

[0046] In this embodiment and the following embodiments, the device structure formed in the substrate 101 is described by taking a trench gate MOSFET as an example, but the invention is not limited thereto. Figure 2 As shown, the semiconductor layer includes a substrate 101 and a trench gate structure located in the substrate 101. The substrate 101 has a first surface and a second surface relative to each other and a plurality of trenches 102, and the trenches 102 extend from the first surface to the second surface into the substrate 101. The trench gate structure is located in the trench 102. The substrate 101 is, for example, a semiconductor substrate or a stacked structure consisting of a semiconductor substrate and an epitaxial layer. However, the embodiments of the present disclosure are not limited thereto, and those skilled in the art can make other settings for the material and number of layers of the substrate 101 as needed.

[0047] The trench gate structure includes a gate dielectric layer 106 and a gate conductor 107. The gate dielectric layer 106 covers the inner surface of the trench 102, and the gate conductor 107 is located in the trench 102. The gate dielectric layer 106 is located between the substrate 101 and the gate conductor 107, and is used to separate the substrate 101 from the gate conductor 107.

[0048] The substrate 101 includes a body region 103, a source region 105, and a body contact region 104. The source region 105 is of a first doping type, the body region 103 and the body contact region 104 are of a second doping type, and the doping concentration of the body contact region 104 is greater than the doping concentration of the body region 103. The first doping type is opposite to the second doping type. The first doping type is one of a P type and an N type, and the second doping type is the other of a P type and an N type. The body region 103 is located in the substrate 101 and is adjacent to the trench 102. The source region 105 extends from the first surface of the substrate 101 toward the second surface and is adjacent to the trench 102. The contact region 140 extends from the first surface of the substrate 101 toward the second surface and is adjacent to the body region 103.

[0049] An interlayer dielectric layer (ILD) 108 is formed on the semiconductor layer, and the interlayer dielectric layer 108 covers the trench gate structure, the source region 105, and the body contact region 104. The interlayer dielectric layer 108 is composed of silicon oxide, for example.

[0050] Figure 3 A schematic cross-sectional view showing the formation of contact holes in the manufacturing process of the semiconductor structure of the first embodiment of the present application is shown. Figure 3 As shown, in this step, an etchant layer PR1 is formed on the interlayer dielectric layer 108, the etchant layer PR1 is patterned using a photolithography process, and the interlayer dielectric layer 108 is etched using an etching process to transfer the pattern of the etchant layer PR1 to the interlayer dielectric layer 108 to form a contact hole 130 in the interlayer dielectric layer 108.

[0051] In the etching step, the resist layer PR1 is used as a mask to remove the exposed portion of the interlayer dielectric layer 108 through the opening area of ​​the resist layer PR1. Due to the selectivity of the etchant, the etching stops at the surface of the source region 105 and the body contact region 104 of the semiconductor structure 100, thereby forming a contact hole 130 reaching the surface of the source region 105 and the body contact region 104. It is worth noting that in the case of different Figure 3 In the cross section shown, a contact hole reaching the gate conductor 107 may also be formed simultaneously. This embodiment and the second embodiment are described by taking the contact hole of the source region 105 as an example.

[0052] It should be noted that during the etching process of the contact hole, the etchant for etching the interlayer dielectric layer 108 reacts with the resist layer PR1 to form a polymer 109 at the bottom and sidewalls of the contact hole. The polymer 109 at the bottom and sidewalls of the contact hole will constitute an isolation medium between the subsequently formed conductive channel and the source region 105 and the body contact region 104, thereby introducing abnormal resistance and affecting the conductive properties of the semiconductor structure. Therefore, the polymer 109 at the bottom and sidewalls of the contact hole needs to be removed before forming the conductive channel.

[0053] In the conventional process, plasma containing oxygen (O) is usually used to remove the resist layer PR1. The plasma containing oxygen (O) has a significant effect on removing the resist layer PR1, but has limitations on removing the polymer. Based on this, the present embodiment introduces a plasma containing fluorine (F) to cooperate with the plasma containing oxygen (O) to remove the polymer at the bottom and sidewall of the contact hole while removing the resist layer PR1.

[0054] Figures 4 to 6b A schematic cross-sectional view showing a step of removing the resist layer PR1 and the polymer at the bottom and sidewall of the contact hole in the manufacturing process of the semiconductor structure according to the first embodiment of the present application.

[0055] Figure 4 In the embodiment shown, a single ashing step is used to remove the resist layer PR1 and the polymer at the bottom and sidewall of the contact hole. In the single ashing step, a mixed gas of plasma containing oxygen (O) and plasma containing fluorine (F) is used. In one embodiment, in the mixed gas, the flow rate of the plasma containing oxygen (O) is 4000 sccm to 100000 sccm, and the flow rate of the plasma containing fluorine (F) is 5 sccm to 300 sccm.

[0056] In this embodiment, the flow rate of the plasma containing fluorine (F) components is set to be relatively low because the introduction of the plasma containing fluorine (F) components will hinder the etching rate of the plasma containing oxygen (O) components in etching the resist layer PR1. Setting the flow rate of the plasma containing fluorine (F) components to be relatively high will make the entire ashing step take too long. At the same time, the thickness of the polymer is much smaller than the thickness of the resist layer PR1, and setting the flow rate of the plasma containing fluorine (F) components to be relatively low will not affect the overall etching progress.

[0057] Figure 5a and Figure 5b In the illustrated embodiment, two or more ashing steps (eg, two ashing steps) are used to remove the resist layer PR1 and the polymer remaining at the bottom and sidewall of the contact hole.

[0058] In the first ashing step, a plasma containing a fluorine (F) component is used to primarily remove the polymer 109, such as Figure 5a It is worth noting that, relative to Figure 4 In the embodiment shown, the flow rate of the plasma containing fluorine (F) components can be set to be higher in the first ashing step to quickly remove the polymer. The flow rate of the plasma containing fluorine (F) components in the first ashing step is, for example, 5 sccm to 1000 sccm.

[0059] In the second ashing step, the flow rate of the plasma containing the fluorine (F) component is lowered, and the plasma containing the oxygen (O) component is added at the same time, such as Figure 5b As shown. In the second ashing step, the flow rate of the plasma containing the fluorine (F) component is lowered to 5 sccm~300 sccm, and the flow rate of the plasma containing the oxygen (O) component is, for example, 4000 sccm~100000 sccm. In the first ashing step, the polymer 109 has been substantially removed, and the main purpose of the second ashing step is to remove the resist layer PR1, and the plasma containing the fluorine (F) component has an obstructive effect on the removal of the resist layer PR1. Therefore, in the second ashing step, the flow rate of the plasma containing the fluorine (F) component can be lowered to reduce the obstructive effect of the plasma containing the fluorine (F) component and speed up the progress of the overall process.

[0060] exist Figure 6a and Figure 6b In the illustrated embodiment, two or more ashing steps (eg, two ashing steps) are used to remove the resist layer PR1 and the polymer remaining at the bottom and sidewall of the contact hole.

[0061] In the first ashing step, plasma containing oxygen (O) is used to mainly remove the resist layer PR1, such as Figure 6aAs shown. It is worth noting that the reason why a single plasma containing oxygen (O) components is used in the first ashing step, rather than a mixed gas of a plasma containing oxygen (O) components (such as O2) and a plasma containing fluorine (F) components, is because the plasma containing fluorine (F) components has an obstructive effect on the removal of the resist layer PR1. A single plasma containing oxygen (O) components is used to pre- and quickly remove most of the resist layer PR1, so as to shorten the time required for the entire ashing step and avoid the problem of too long ashing time caused by the addition of plasma containing fluorine (F) components. And because there is no obstruction from the plasma containing fluorine (F) components, in the first ashing step, the flow rate of the plasma containing oxygen (O) components can be relatively lowered, for example, to 500 sccm~100000 sccm.

[0062] In the second ashing step, the flow rate of the plasma containing oxygen (O) components (e.g., O2) is kept constant, and the plasma containing fluorine (F) components is added, such as Figure 6b As shown. The second ashing step is mainly dedicated to removing the polymer 109. It is worth noting that in the second ashing step, most of the resist layer PR1 has been removed, and the addition of the plasma containing the fluorine (F) component will not affect the overall progress of the removal of the resist layer PR1. In this step, the flow rate of the plasma containing the fluorine (F) component can even be increased, for example, to 5 sccm~1000 sccm.

[0063] Further, any of the above ashing steps is performed in a nitrogen atmosphere, wherein the flow rate of the nitrogen is, for example, 50 sccm to 15000 sccm, preferably 100 sccm to 10000 sccm.

[0064] Furthermore, any of the above ashing steps is performed within a pressure range of 0.5 Torr to 2.0 Torr, preferably within a pressure range of 0.6 Torr to 1.2 Torr.

[0065] Further, any of the above ashing steps is performed within a temperature range of 100°C to 350°C, preferably within a temperature range of 200°C to 300°C.

[0066] Through the above-mentioned ashing step, the resist layer PR1 and the polymer 109 are removed.

[0067] Figure 7 A schematic cross-sectional view showing a patterning step of forming a conductive channel in a manufacturing process of a semiconductor structure according to a first embodiment of the present application. Figure 7As shown, in this step, a conductive layer is formed on the surface of the interlayer dielectric layer 108 and inside the contact hole 130, and then, for example, a CMP (Chemical Mechanical Polishing) process is used to remove the conductive layer on the surface of the interlayer dielectric layer 108, and the conductive layer inside the contact hole 130 is retained to form a conductive channel 110. Since the polymer 109 in the contact hole 130 is removed, the conductive channel 110 forms a good conductive contact with the source region.

[0068] Figures 8 to 12c The cross-sectional views of various stages in the semiconductor structure manufacturing process according to the second embodiment of the present application are shown. In this embodiment, the film layer is a metal layer formed on the semiconductor layer, and the metal layer is etched through a patterned resist layer to form wiring. The etching product produced by etching the film layer is the product of the reaction between the etchant used for etching the metal layer and the metal layer. Specifically, during the etching process of the metal layer, the etchant used for etching the metal layer reacts with the metal layer, thereby achieving etching of the metal layer. The product of the reaction between the etchant and the metal layer is volatile, but at the same time there will be a part trapped in the resist layer. The embodiment of the present application is committed to using a plasma containing an oxygen (O) component (such as an O2 plasma) and a plasma containing a fluorine (F) component (such as a CF4 plasma) to remove the resist layer and the etching products produced by etching the metal layer.

[0069] Figure 8 A schematic cross-sectional view showing the formation of a metal layer on a semiconductor layer in the manufacturing process of the semiconductor structure according to the second embodiment of the present application.

[0070] like Figure 8 As shown, the semiconductor layer includes a substrate 201 and a trench gate structure located in the substrate 201. The substrate 201 has a first surface and a second surface relative to each other and a plurality of trenches 202, and the trenches 202 extend from the first surface to the second surface into the substrate 201. The trench gate structure is located in the trench 202. The substrate 201 is, for example, a semiconductor substrate or a stacked structure consisting of a semiconductor substrate and an epitaxial layer. However, the embodiments of the present disclosure are not limited thereto, and those skilled in the art may make other settings for the material and number of layers of the substrate 201 as needed.

[0071] The trench gate structure includes a gate dielectric layer 206 and a gate conductor 207. The gate dielectric layer 206 covers the inner surface of the trench 202, and the gate conductor 207 is located in the trench 202. The gate dielectric layer 206 is located between the substrate 201 and the gate conductor 207 to separate the substrate 201 from the gate conductor 207.

[0072] The substrate 201 includes a body region 203, a source region 205, and a body contact region 204. The source region 205 is of a first doping type, the body region 203 and the body contact region 204 are of a second doping type, and the doping concentration of the body contact region 204 is greater than the doping concentration of the body region 203. The first doping type is opposite to the second doping type. The first doping type is one of a P type and an N type, and the second doping type is the other of a P type and an N type. The body region 203 is located in the substrate 201 and is adjacent to the trench 202. The source region 205 extends from the first surface of the substrate 201 toward the second surface and is adjacent to the trench 202. The contact region 240 extends from the first surface of the substrate 201 toward the second surface and is adjacent to the body region 203.

[0073] An interlayer dielectric layer 208 is formed on the semiconductor layer, and the interlayer dielectric layer 208 covers the trench gate structure, the source region 205, and the body contact region 204. The interlayer dielectric layer 208 is composed of, for example, silicon oxide, and is used to isolate the active region of the semiconductor structure from the wiring formed subsequently. The interlayer dielectric layer 208 also forms a conductive channel 210, which penetrates the interlayer dielectric layer 208 and the source region 205 to form a good conductive contact, so as to lead the source region 205 to the surface of the interlayer dielectric layer 208 away from the substrate 201. It is worth noting that in a case different from Figure 8 In the interface shown, a conductive channel is also formed to lead the gate conductor 207 to the surface of the interlayer dielectric layer 208 away from the substrate 201. This embodiment is described by taking the conductive channel 210 of the source region 205 as an example.

[0074] A metal layer 220a is formed on the surface of the semiconductor layer (specifically, on the surface of the interlayer dielectric layer 208), and the metal layer 220a is in contact with the conductive path 210 exposed on the surface of the interlayer dielectric layer 208. In a preferred embodiment, an adhesion layer may be formed before forming the metal layer 220a. The metal layer 220a is bonded to the surface of the interlayer dielectric layer 208 via the adhesion layer. The adhesion layer, for example, includes one or more of a titanium (Ti) layer and a titanium nitride (TiN) layer. The metal layer 220a, for example, is one or more of an aluminum (Al) layer, a copper (Cu) layer, and a tungsten (W). In one embodiment, the adhesion layer, for example, includes a stacked titanium (Ti) layer and a titanium nitride (TiN) layer, and the material of the metal layer 220a is, for example, metal aluminum (Al).

[0075] Fig. 9 FIG. 2 is a schematic cross-sectional view showing a wiring pattern formed in a manufacturing process of a semiconductor structure according to a second embodiment of the present application. Fig. 9As shown, a resist layer PR2 is formed on the surface of the metal layer 220a, the resist layer PR2 is patterned by a photolithography process, and the metal layer 220a is etched through the opening of the resist layer PR2, and the pattern of the resist layer PR2 is transferred to the metal layer 220a to form a wiring 220. The wiring 220 is conductively connected to the source region 205 via the conductive channel 210 to achieve interconnection of the source region 205.

[0076] Generally speaking, a plasma containing chlorine (Cl) components (such as Cl2, BCl3, etc.) is used as an etchant to etch the metal layer 220a (aluminum metal) to form a wiring pattern. The plasma containing chlorine (Cl) components reacts with the metal layer 220a (aluminum metal) to produce a volatile product aluminum chloride (AlCl3). The metal layer 220a is etched away due to the reaction with the etchant, and the volatile product aluminum chloride (AlCl3) needs to be extracted. However, a large amount of aluminum chloride (AlCl3) may be trapped inside the etchant layer PR2 used to cover the metal layer 220a (aluminum metal). When the metal layer 220a (aluminum metal) and the etchant layer PR2 are exposed to the air, the aluminum chloride (AlCl3) may react with water vapor in the air to form hydrochloric acid (HCl), and the hydrochloric acid (HCl) may corrode the metal layer 220a (aluminum metal), such as Fig.13 shown.

[0077] The reaction formula of the above process is as follows:

[0078] Al+3 / 2Cl2→AlCl3(1)

[0079] AlCl3+3H2O→Al(OH)3+3HCl (2)

[0080] Al+3HCl→AlCl3+3 / 2H2(3)

[0081] Reaction equation (1) shows the reaction equation of the metal layer 220a (aluminum) reacting with chlorine gas (Cl2) to generate aluminum chloride (AlCl3) during the etching process, reaction equation (2) shows the reaction equation of the reaction product aluminum chloride (AlCl3) reacting with water vapor in the air to generate hydrochloric acid (HCl), and reaction equation (3) shows the reaction equation of hydrochloric acid (HCl) reacting with aluminum to generate aluminum chloride (AlCl3) again, that is, the reaction equation of hydrochloric acid (HCl) corroding wiring 220.

[0082] Therefore, as long as moisture is provided in the air, the residual etching product aluminum chloride (AlCl3) will form hydrochloric acid (HCl) that corrodes the wiring 220. Based on this, in this embodiment, before the wiring 220 is exposed to the air, the plasma containing oxygen (O) component is used to remove the resist layer PR2 and the aluminum chloride (AlCl3) remaining in the etching product.

[0083] In conventional processes, plasma containing oxygen (O) components is usually used to remove the resist layer PR2. Plasma containing oxygen (O) components has a significant effect on removing the resist layer PR2, but has limitations on removing the etching product aluminum chloride (AlCl3). In order to overcome the limitations of using a single plasma containing oxygen (O) components to remove etching products, this embodiment adds a plasma containing chlorine (Cl) components to cooperate with the plasma containing oxygen (O) components to improve the semiconductor process, so as to more smoothly remove the resist layer PR2 and the etching products, thereby preventing any potential problems in advance and achieving stable product production.

[0084] Figure 10 to Figure 12c A schematic cross-sectional view showing a step of removing the resist layer PR2 in the manufacturing process of the semiconductor structure according to the second embodiment of the present application. Figure 10 to Figure 12c The steps shown are directed to removing etching products trapped in the resist layer PR2 while removing the resist layer PR2 using plasma containing oxygen (O) components (eg, O2 plasma) and plasma containing fluorine (F) components (eg, CF4 plasma).

[0085] Fig.10 In the embodiment shown, a single ashing step is used to remove the resist layer PR2 and the etching products remaining in the resist layer PR2. In the single ashing step, a mixed gas of a plasma containing an oxygen (O) component and a plasma containing a fluorine (F) component is used. In one embodiment, in the mixed gas, the flow rate of the plasma containing the oxygen (O) component is 4000 sccm~100000 sccm, and the flow rate of the plasma containing the fluorine (F) component is 5 sccm~1000 sccm.

[0086] In this embodiment, although most of the etching products are trapped in the resist layer PR2, since the etching products are volatile, discrete etching products still exist, and as the resist layer PR2 is gradually removed, the etching products trapped in the resist layer PR2 will also be released. Therefore, the flow rate of the plasma containing fluorine (F) components cannot be set too low. Therefore, in this embodiment, the flow rate of the plasma containing fluorine (F) components is set to a relatively high 5sccm~1000sccm.

[0087] Fig.11a and Fig.11b In the illustrated embodiment, two or more ashing steps (eg, two ashing steps) are used to remove the resist layer PR2 , the etching products remaining in the resist layer PR2 , and the etching products on the sidewalls of the wiring.

[0088] In the first ashing step, a plasma containing a fluorine (F) component is used to primarily remove discrete etching products, such as Fig.11aAs shown, the flow rate of the plasma containing fluorine (F) is, for example, 5 sccm to 1000 sccm. Although most of the etching products are trapped in the resist layer PR2, since the etching products are volatile, there are still discrete etching products. The first ashing step is intended to remove the discrete etching products in advance.

[0089] In the second ashing step, the flow rate of the plasma containing the fluorine (F) component is kept constant, and the plasma containing the oxygen (O) component is added at the same time, such as Fig.11b As shown, the flow rate of the plasma containing oxygen (O) is, for example, 4000 sccm to 100000 sccm. In the first ashing step, the discrete etching products have been substantially removed, and the main purpose of the second ashing step is to remove the resist layer PR1 and the etching products trapped in the resist layer PR1.

[0090] exist Figures 12a to 12c In the illustrated embodiment, two or more ashing steps (eg, three ashing steps) are used to remove the resist layer PR1 and the etching products.

[0091] In the first ashing step, plasma containing oxygen (O) is used to mainly remove the resist layer PR1, such as Fig.12a As shown. It is worth noting that the reason why a single plasma containing oxygen (O) components is used in the first ashing step, rather than a mixed gas of a plasma containing oxygen (O) components (such as O2) and a plasma containing fluorine (F) components, is because the plasma containing fluorine (F) components has an obstructive effect on the removal of the resist layer PR2. A single plasma containing oxygen (O) components is used to pre- and quickly remove most of the resist layer PR2, so as to shorten the time required for the entire ashing step and avoid the problem of too long ashing time caused by the addition of a plasma containing fluorine (F) components. And because there is no obstruction from the plasma containing fluorine (F) components, in the first ashing step, the flow rate of the plasma containing oxygen (O) components can be relatively lowered, for example, to 500 sccm~100000 sccm. Furthermore, after the resist layer PR2 is substantially removed, the etching products trapped in the resist layer PR2 are released and are in a discrete state, making it easier to be removed in the second ashing step.

[0092] In the second ashing step, the flow rate of the plasma containing oxygen (O) component is kept constant, and the plasma containing fluorine (F) component is added, such as Figure 12bAs shown, the second ashing step is mainly dedicated to removing the etching products. It is worth noting that in the second ashing step, most of the resist layer PR2 has been removed, and the addition of the plasma containing fluorine (F) components will not affect the overall progress of the removal of the resist layer PR2. In this step, the flow rate of the plasma containing fluorine (F) components can even be increased, for example, to 300 sccm~1000 sccm.

[0093] In the third ashing step, the addition of plasma containing oxygen (O) components is stopped, and plasma containing fluorine (F) components is used alone, such as Fig.12c The third ashing step is mainly used to perform the final removal of the residual etching products to ensure that the etching products are completely removed. In this step, the flow rate of the plasma containing the fluorine (F) component can be lowered, for example, to 5 sccm~300 sccm.

[0094] It should be noted that any of the above ashing steps is performed before contacting with water vapor. In a preferred embodiment, any of the above ashing steps is performed in a nitrogen atmosphere. The flow rate of the plasma containing nitrogen (N) components is 50 sccm to 15000 sccm, preferably 100 sccm to 10000 sccm.

[0095] Furthermore, any of the above ashing steps is performed within a pressure range of 0.5 Torr to 2.0 Torr, preferably within a pressure range of 0.6 Torr to 1.2 Torr.

[0096] Further, any of the above ashing steps is performed in a temperature range of 100°C to 350°C, preferably in a temperature range of 200°C to 300°C.

[0097] Through the above-mentioned ashing step, the resist layer PR2 and the etching products are removed.

[0098] According to the embodiments of the present invention as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A method for manufacturing a semiconductor structure, comprising: forming a film layer on the semiconductor layer; forming a patterned resist layer on the film layer; Etching the film layer through the patterned resist layer to transfer the pattern of the resist layer into the film layer; as well as The resist layer and the etching products are removed by using plasma containing oxygen and plasma containing fluorine.

2. The method for manufacturing a semiconductor structure according to claim 1, wherein: The resist layer and the etching products are removed by a single ashing step, in which a mixed gas of plasma containing an oxygen component and plasma containing a fluorine component is used to remove the resist layer and the etching products.

3. The method for manufacturing a semiconductor structure according to claim 2, wherein: The flow rate of the plasma containing the oxygen component in the mixed gas is 4000 sccm~100000 sccm.

4. The method for manufacturing a semiconductor structure according to claim 2, wherein: The flow rate of the plasma containing the fluorine component in the mixed gas is 5 sccm to 1000 sccm.

5. The method for manufacturing a semiconductor structure according to claim 4, wherein: The flow rate of the plasma containing the fluorine component in the mixed gas is 5 sccm to 300 sccm.

6. The method for manufacturing a semiconductor structure according to claim 1, wherein: Adopting two or more ashing steps to remove the resist layer and etching products; In the first ashing step, a plasma containing a fluorine component or a plasma containing an oxygen component is used; In the second ashing step, a mixed gas of plasma containing an oxygen component and plasma containing a fluorine component is used.

7. The method for manufacturing a semiconductor structure according to claim 6, wherein: In the first ashing step, the flow rate of the fluorine-containing plasma is 5 sccm to 1000 sccm, or The flow rate of the plasma containing the oxygen component is 500 sccm to 100,000 sccm.

8. The method for manufacturing a semiconductor structure according to claim 6, wherein: In the second ashing step, the flow rate of the plasma containing the fluorine component is 5 sccm-300 sccm, and the flow rate of the plasma containing the oxygen component is 4000 sccm-100000 sccm.

9. The method for manufacturing a semiconductor structure according to claim 6, wherein: In the second ashing step, the flow rate of the plasma containing the fluorine component is 5 sccm-1000 sccm, and the flow rate of the plasma containing the oxygen component is 4000 sccm-100000 sccm.

10. The method for manufacturing a semiconductor structure according to claim 6, wherein: In the second ashing step, the flow rate of the plasma containing the oxygen component is 500 sccm-100000 sccm, and the flow rate of the plasma containing the fluorine component is 5 sccm-1000 sccm.

11. The method for manufacturing a semiconductor structure according to claim 6, wherein: In the second ashing step, the flow rate of the plasma containing the oxygen component is 500 sccm-100000 sccm, and the flow rate of the plasma containing the fluorine component is 300 sccm-1000 sccm.

12. The method for manufacturing a semiconductor structure according to claim 6, wherein: A third ashing step may also be included, wherein the third ashing step uses plasma containing a fluorine component.

13. The method for manufacturing a semiconductor structure according to claim 12, wherein: In the third ashing, the flow rate of the plasma containing the fluorine component is 5 sccm to 300 sccm.

14. The method for manufacturing a semiconductor structure according to any one of claims 2 to 13, wherein: The ashing step is performed within a pressure range of 0.5 Torr to 2.0 Torr.

15. The method for manufacturing a semiconductor structure according to any one of claims 2 to 13, wherein: The ashing step is performed in a temperature range of 100°C to 350°C.

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