Vertically stacked SIP packaging structure with high heat dissipation and high reliability

Abstract

The invention discloses a vertically stacked SIP packaging structure with high heat dissipation and high reliability. The vertically stacked SIP packaging structure comprises a plastic packaging material, an upper-layer resistance-capacitance device, a low-power-consumption chip, a first circuit substrate, a lower-layer resistance-capacitance device, a first tin column, a high-power-consumption chip, a heat dissipation block, a second circuit substrate and a second tin column, the upper-layer resistance-capacitance device is mounted on the front surface of the first circuit substrate, the lower-layer resistance-capacitance device is mounted on the front surface of the second circuit substrate, and the heat dissipation block is connected with the second circuit substrate; the high-power chip is mounted on the upper surface of the heat dissipation block; the first circuit substrate and the second circuit substrate are connected with each other through a first tin column; and the second tin column is welded on the back surface of the second circuit substrate. According to the invention, vertical interconnection and external signal interconnection adopt a column planting process, the column planting process is mature and stable, the tin column has strong environmental adaptability such as vibration resistance and impact resistance, and the overall reliability of the product can be improved; and the circuit substrate adopts the thickened copper layer and the heat dissipation solid via holes which are locally designed, so that the internal thermal resistance of the product is reduced.

Description

Technical Field

[0001] The present invention relates to the field of advanced packaging technology, and in particular to a high-heat dissipation and high-reliability vertical stacking SIP packaging structure. Background Art

[0002] The main heat source of packaged devices is the heat consumption of the chip itself when it is working. With the increase of bare chip functional complexity, performance indicators, and wiring density, the power consumption of a single bare chip is getting higher and higher. Due to the high heat consumption of a single chip, compact layout, and greatly increased heat flux density, the temperature rise increases, reducing the performance and reliability of the entire packaged device, so the heat dissipation problem is particularly important.

[0003] As high-power SIP devices develop in the trend of miniaturization and high power, the reliability and stability of the devices face serious challenges. As the power density of the device increases, the heat accumulation effect inside the SIP device increases rapidly, causing its various performance indicators to deteriorate seriously, and the power advantage of the device cannot be brought into play. Therefore, the heat dissipation problem has become a constraint on the further development and widespread application of high-power SIP devices.

[0004] The heat dissipation conditions of system components are limited. When designing the system, it is impossible to provide more effective forced heat dissipation measures such as air cooling and liquid cooling for high-power SIP devices. The system can only rely on natural convection, radiation heat dissipation and other measures to dissipate heat. Therefore, reducing the thermal resistance of the device at the packaging level has become an important performance indicator of the product. Summary of the invention

[0005] The object of the present invention is to provide a high heat dissipation and high reliability vertical stacking SIP packaging structure to solve the problems in the background technology.

[0006] In order to solve the above technical problems, the present invention provides a high heat dissipation and high reliability vertical stacking SIP packaging structure, including: a plastic packaging material, an upper layer resistor and capacitor component, a low power consumption chip, a first circuit substrate, a lower layer resistor and capacitor component, a first tin column, a high power consumption chip, a heat dissipation block, a second circuit substrate, and a second tin column;

[0007] The low power consumption chip and the upper layer resistor and capacitor components are mounted on the front of the first circuit substrate, the lower layer resistor and capacitor components are mounted on the front of the second circuit substrate, the heat sink is interconnected with the second circuit substrate; the high power chip is mounted on the upper surface of the heat sink;

[0008] The first circuit substrate and the second circuit substrate are interconnected via a first tin column;

[0009] The second tin column is welded to the back side of the second circuit substrate;

[0010] The entire device is encapsulated with a plastic encapsulation material on the upper surface of the second circuit substrate, and the device transmits and controls signals with the outside through the second tin column.

[0011] In one embodiment, the upper layer resistor and capacitor component is soldered to the first circuit substrate via a first solder, and the low power consumption chip is bonded to the surface of the first circuit substrate via a first conductive adhesive with high heat dissipation; the lower layer resistor and capacitor component is soldered to the second circuit substrate via a first solder, and the first tin column interconnects the first circuit substrate and the second circuit substrate via the first solder.

[0012] In one embodiment, the heat sink is formed by integrating diamond copper and oxygen-free copper by welding with a second solder, and the surfaces of the diamond copper and the oxygen-free copper are both gold-plated.

[0013] In one embodiment, the high power consumption chip is bonded to the diamond copper of the heat dissipation block by a second conductive adhesive made of ultra-high heat dissipation nano silver, and the heat dissipation block is soldered to a corresponding position of the second circuit substrate by a first solder.

[0014] In one embodiment, the first conductive adhesive is a high heat dissipation conductive adhesive, and the second conductive adhesive is an ultra-high dispersion nano silver material conductive adhesive.

[0015] In one embodiment, solid copper-filled holes are designed at the chip mounting area of ​​the first circuit substrate and at the interconnection points between the tin pillars of the second circuit substrate and the first circuit substrate.

[0016] In one embodiment, the heat sink blocks on the surface of the second circuit substrate are evenly distributed; and the chips on the surface of the first circuit substrate are evenly distributed.

[0017] In one embodiment, both the first tin column and the second tin column are high-lead tin columns, and the second tin column has a larger height and diameter than the first tin column.

[0018] In one embodiment, both the first circuit substrate and the second circuit substrate are designed with a thickened copper layer.

[0019] The invention provides a high heat dissipation and high reliability vertical stacking SIP packaging structure, which has the following beneficial effects:

[0020] (1) In order to prevent the heavy weight of the packaged device, the deformation of the interconnect solder during device welding will be large, which will lead to the problem of reduced device reliability. The device uses a mature pillar planting process. To a certain extent, the height and diameter of the tin pillar can be reasonably increased through mechanical simulation to increase the reliability of SIP microsystem products. The circuit substrate uses a thickened copper layer and locally designed heat dissipation solid vias to reduce the internal thermal resistance of the product.

[0021] (2) The chip is assembled by means of a high heat dissipation conductive adhesive sheet. This technology is mature and can reduce the thermal resistance on the chip conduction path and leave a welding temperature gradient for substrate stacking and resistor and capacitor welding.

[0022] (3) The heat sink is formed by integrated welding of diamond copper and oxygen-free copper. Diamond copper and oxygen-free copper have high thermal conductivity. Diamond copper matches the thermal expansion coefficient of the chip to prevent the chip from cracking. The thermal expansion coefficient of oxygen-free copper matches the substrate to prevent the oxygen-free copper and the second circuit substrate from warping or even cracking after welding.

[0023] (4) Place power chips and power resistors evenly to prevent excessive heat concentration and local over-temperature. The number of vertical stacking layers can be adjusted according to actual design requirements to meet the needs of miniaturization and high integration. The overall plastic packaging method is used for packaging, which has mature technology, low cost and short production cycle. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a front view schematic diagram of a high heat dissipation and high reliability vertical stacked SIP package in an embodiment.

[0025] Figure 2 It is a side view of a high heat dissipation and high reliability vertical stacked SIP package in an embodiment.

[0026] Figure 3 Schematic diagram of the bottom surface of a high heat dissipation and high reliability vertical stacked SIP package in an embodiment.

[0027] Figure 4 1 is an exploded view of a high heat dissipation and high reliability vertical stacked SIP package in an embodiment.

[0028] Figure 5 Schematic diagram of a high heat dissipation and high reliability vertical stacked SIP package heat sink in an embodiment.

[0029] Figure 6 Schematic diagram of removing plastic packaging material from a high heat dissipation and high reliability vertical stacked SIP package in an embodiment.

[0030] Figure 7 This is a schematic diagram of a high heat dissipation and high reliability vertical stacked SIP package in an embodiment without upper layer devices. DETAILED DESCRIPTION

[0031] The following is a further detailed description of a high heat dissipation and high reliability vertical stacked SIP packaging structure proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0032] The present invention provides a high heat dissipation and high reliability vertical stacking SIP packaging structure, the front, side and bottom surfaces of which are respectively as follows Figures 1 to 3 As shown, the explosion diagram is as follows Figure 4As shown, it includes a first circuit substrate 5 and a second circuit substrate 12, and a second tin column 13 is soldered to the back of the second circuit substrate 12; the upper low-power chip 3 and the upper resistor and capacitor device 2 are installed on the front of the first circuit substrate 5, and the first circuit substrate 5 and the second circuit substrate 12 are interconnected through the first tin column 7; the lower resistor and capacitor device 6 is installed on the front of the second circuit substrate 12, and the heat sink 10 is interconnected with the second circuit substrate 12; the lower high-power chip 8 is installed on the upper surface of the heat sink 10; the device as a whole is plastic-encapsulated with a plastic encapsulation material 1 on the upper surface of the second circuit substrate 12, and the device transmits signals and controls with the outside through the second tin column 13.

[0033] The first circuit substrate 5 and the second circuit substrate 12 are designed with solder layers on both sides; and the first circuit substrate 5 and the second circuit substrate 12 use thickened copper layers, and the substrate surfaces are gold-plated. The chip mounting part of the first circuit substrate 5 is designed with solid copper-filled holes.

[0034] A high-lead tin column is used as the first tin column for soldering interconnection between the first circuit substrate 5 and the second circuit substrate 12. A solid copper-filled hole is designed in the tin column interconnection area between the second circuit substrate 12 and the first circuit substrate 5.

[0035] The first circuit substrate 5 has exposed chip mounting and bonding areas corresponding to high power consumption; the chips and resistors and capacitors are evenly and symmetrically distributed on the surface of the first circuit substrate 5; and the components are evenly and symmetrically distributed on the surface of the second circuit substrate 12.

[0036] like Figure 5 The figure shows the structure of the heat sink 10. Considering the thermal matching and heat dissipation of different materials, the heat sink 10 is formed by integrating diamond copper 14 and oxygen-free copper 16 through a second solder 15. The diamond copper 14 is thin as a chip heat sink carrier. The surfaces of the diamond copper 14 and the oxygen-free copper 16 are both gold-plated.

[0037] Compared with the first tin column 7 , the second tin column 13 has a larger length and diameter. The second tin column 15 is flush with the lower surface of the heat sink 10 , which is convenient for subsequent overall welding of the device.

[0038] Figure 6 In order to remove the plastic packaging material, the upper resistor and capacitor device 2 is soldered to the first circuit substrate 5 through the first solder 11, and the low power consumption chip 3 is bonded to the surface of the first circuit substrate 5 through the first conductive adhesive 4 with high heat dissipation.

[0039] Figure 7To remove the schematic diagram of the upper layer devices and the first circuit substrate, the lower layer resistor and capacitor device 6 is soldered to the second circuit substrate 12 through the first solder 11, and the first tin column 7 interconnects the first circuit substrate 5 and the second circuit substrate 12 through the first solder 11. Considering the heat dissipation problem of the high-power chip, the high-power chip 8 is bonded to the heat sink 10 through the second conductive glue 9 made of ultra-high heat dissipation nano silver, and the heat sink 10 is soldered to the corresponding position of the second circuit substrate 12 through the first solder 11. The high-power chip 8 mainly dissipates heat directly to the outside through the heat sink 10, and the first circuit substrate 5 assists in heat dissipation; the other devices mainly conduct heat to the second circuit substrate 12 through the second tin column 13 for heat dissipation.

[0040] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A high heat dissipation and high reliability vertical stacking SIP packaging structure, characterized in that: include: Plastic packaging material, upper layer resistor and capacitor components, low power consumption chip, first circuit substrate, lower layer resistor and capacitor components, first tin pillar, high power consumption chip, heat sink, second circuit substrate, second tin pillar; The low power consumption chip and the upper layer resistor and capacitor components are mounted on the front of the first circuit substrate, the lower layer resistor and capacitor components are mounted on the front of the second circuit substrate, the heat sink is interconnected with the second circuit substrate; the high power chip is mounted on the upper surface of the heat sink; The first circuit substrate and the second circuit substrate are interconnected via a first tin column; The second tin column is welded to the back side of the second circuit substrate; The entire device is encapsulated with a plastic encapsulation material on the upper surface of the second circuit substrate, and the device transmits and controls signals with the outside through the second tin column.

2. The high heat dissipation and high reliability vertical stacked SIP packaging structure according to claim 1, characterized in that: The upper layer resistor and capacitor component is soldered to the first circuit substrate through the first solder, and the low power consumption chip is bonded to the surface of the first circuit substrate through the first conductive adhesive with high heat dissipation; the lower layer resistor and capacitor component is soldered to the second circuit substrate through the first solder, and the first tin column interconnects the first circuit substrate and the second circuit substrate through the first solder.

3. The high heat dissipation and high reliability vertical stacked SIP packaging structure according to claim 2, characterized in that: The heat sink block is formed by integrating diamond copper and oxygen-free copper through a second solder, and the surfaces of the diamond copper and the oxygen-free copper are both gold-plated.

4. The high heat dissipation and high reliability vertical stacked SIP packaging structure according to claim 3, characterized in that: The high power consumption chip is bonded to the diamond copper of the heat dissipation block through a second conductive adhesive made of ultra-high heat dissipation nano silver, and the heat dissipation block is soldered to a corresponding position of the second circuit substrate through a first solder.

5. The high heat dissipation and high reliability vertical stacked SIP packaging structure according to claim 4, characterized in that: The first conductive adhesive is made of high heat dissipation conductive adhesive, and the second conductive adhesive is made of ultra-high dispersion nano silver material conductive adhesive.

6. The high heat dissipation and high reliability vertical stacked SIP packaging structure according to claim 1, characterized in that: Solid copper-filled holes are designed at the chip mounting area of ​​the first circuit substrate and at the interconnection points between the tin pillars of the second circuit substrate and the first circuit substrate.

7. The high heat dissipation and high reliability vertical stacked SIP packaging structure according to claim 1, characterized in that: The heat dissipation blocks on the surface of the second circuit substrate are evenly distributed; and the chips on the surface of the first circuit substrate are evenly distributed.

8. The high heat dissipation and high reliability vertical stacked SIP packaging structure according to claim 1, characterized in that: The first tin column and the second tin column are both high-lead tin columns, and the second tin column has a larger height and diameter than the first tin column.

9. The high heat dissipation and high reliability vertical stacked SIP packaging structure according to claim 1, characterized in that: The first circuit substrate and the second circuit substrate both adopt a thickened copper layer design.

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