Chip packaging structure, preparation method thereof and electronic equipment

Abstract

The invention discloses a chip packaging structure, a preparation method thereof and electronic equipment. The chip packaging structure comprises a first rewiring layer, a first adapter plate, a second adapter plate, a second rewiring layer, a first connecting structure, a first chip, a second chip, a third chip and a fourth chip. The first rewiring layer includes a first interconnection structure. The first adapter plate and the second adapter plate are arranged on the first rewiring layer and electrically connected with the first interconnection structure, and at least one of the first adapter plate and the second adapter plate is an active adapter plate. The second rewiring layer comprises a second interconnection structure, and the second rewiring layer is arranged on the sides, away from the first rewiring layer, of the first adapter plate and the second adapter plate and electrically connected with the second interconnection structure. The first chip, the second chip, the third chip and the fourth chip are electrically connected with the second interconnection structure through the multiple first connection structures, horizontal and three-dimensional integrated interconnection of the multiple chips is achieved, and the integration level is improved.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular, relates to a chip packaging structure and a preparation method thereof, and an electronic device. Background Art

[0002] With the development of artificial intelligence and high-performance computing, high-density interconnection between multiple chips is a problem that needs to be solved. How to achieve horizontal and three-dimensional integrated interconnection and improve the integration of packaging structures is one of the key research directions. Summary of the invention

[0003] The present application proposes a chip packaging structure, including a first rewiring layer, a first adapter board and a second adapter board, a second rewiring layer, a plurality of first connection structures, and a first chip, a second chip, a third chip and a fourth chip. The first rewiring layer includes a first interconnection structure. The first adapter board and the second adapter board are arranged on the first rewiring layer and are electrically connected to the first interconnection structure respectively, and at least one of the first adapter board and the second adapter board is an active adapter board. The second rewiring layer includes a second interconnection structure, the second rewiring layer is arranged on a side of the first adapter board away from the first rewiring layer, and is arranged on a side of the second adapter board away from the first rewiring layer, and the first adapter board and the second adapter board are electrically connected to the second interconnection structure respectively. One end of the plurality of first connection structures is electrically connected to the second interconnection structure, and the first chip, the second chip, the third chip and the fourth chip are electrically connected to the other end of the plurality of first connection structures respectively.

[0004] In some embodiments, the chip packaging structure further includes a plurality of second connection structures, one end of the plurality of second connection structures is electrically connected to the first interconnection structure, and the other end of the plurality of second connection structures is electrically connected to the second interconnection structure.

[0005] In some embodiments, the first chip and the third chip are control chips, and the second chip and the fourth chip are memory chips.

[0006] In some embodiments, the first chip is a central processing unit chip, the second chip is a dynamic random access memory chip, the third chip is a graphics processing unit chip, and the fourth chip is a high bandwidth memory chip.

[0007] In some embodiments, the first transfer board and the second transfer board are arranged in parallel with the bottom surface of the first rewiring layer. The first chip, the second chip, the third chip and the fourth chip are arranged in parallel with the bottom surface of the first rewiring layer.

[0008] In some embodiments, the chip packaging structure further includes a first packaging layer and a second packaging layer, wherein the first packaging layer wraps the first adapter board and the second adapter board, and the second packaging layer wraps the first chip, the second chip, the third chip and the fourth chip.

[0009] In an embodiment of the present application, a first adapter board and a second adapter board are arranged on a first rewiring layer, and are electrically connected to the first interconnection structure respectively, so as to realize the interconnection between the two adapter boards. At least one of the first adapter board and the second adapter board is an active adapter board, which can provide a diversified interconnection network. The first adapter board and the second adapter board are electrically connected to the second interconnection structure of the second rewiring layer respectively, one end of a plurality of first connection structures is electrically connected to the second interconnection structure, and the other end is electrically connected to the first chip, the second chip, the third chip and the fourth chip respectively, and the interconnection between the plurality of chips and the plurality of adapter boards is realized through the second rewiring layer and the plurality of first connection structures. The setting of the two layers of rewiring layers enables the chip packaging structure to realize a variety of interconnection relationships, realizes horizontal and three-dimensional integrated interconnection between multiple chips, improves the integration of the packaging structure, and there is no need to re-design the interconnection between the multiple chips on the circuit board.

[0010] On the other hand, the present application also provides a method for preparing a chip packaging structure, comprising the following steps S1 to S6:

[0011] Step S1: disposing a first adapter board and a second adapter board on a carrier board, wherein at least one of the first adapter board and the second adapter board is an active adapter board.

[0012] Step S2: forming a second rewiring layer, the second rewiring layer comprising a second interconnect structure, the second rewiring layer being located on a side of the first adapter board away from the carrier board and on a side of the second adapter board away from the first rewiring layer, the first adapter board and the second adapter board being electrically connected to the second interconnect structure respectively.

[0013] Step S3: forming a plurality of first connection structures, wherein one end of the plurality of first connection structures is electrically connected to the second interconnection structure.

[0014] Step S4: electrically connecting the first chip, the second chip, the third chip and the fourth chip to the other ends of the plurality of first connection structures respectively.

[0015] Step S5: removing the carrier board.

[0016] Step S6: forming a first rewiring layer, the first rewiring layer comprising a first interconnection structure, the first rewiring layer being located on a side of the first adapter board away from the second rewiring layer, and being located on a side of the second adapter board away from the second rewiring layer, the first interconnection structure being electrically connected to the first adapter board and the second adapter board.

[0017] In some embodiments, before forming the first adapter plate and the second adapter plate, the preparation method further includes: forming a plurality of second connection structures on the carrier plate. After forming the second rewiring layer, one end of the plurality of second connection structures is electrically connected to the second interconnection structure, and after forming the first rewiring layer, the other end of the plurality of second connection structures is electrically connected to the first interconnection structure.

[0018] In some embodiments, after forming the first transfer board and the second transfer board and before forming the second rewiring layer, the preparation method further includes: forming a first packaging layer on the carrier, the first packaging layer exposing the surface of the first transfer board away from the carrier, and exposing the surface of the second transfer board away from the carrier. Before removing the carrier, the preparation method further includes: forming a second packaging layer, the second packaging layer encapsulating the first chip, the second chip, the third chip, and the fourth chip.

[0019] The chip packaging structure prepared by the above preparation method realizes horizontal interconnection between the first adapter board and the second adapter board, and realizes interconnection between multiple chips and multiple active adapter boards. The arrangement of the rewiring layers on both sides enables the chip packaging structure to realize multiple interconnection relationships, realizes horizontal and three-dimensional integrated interconnection between multiple chips, improves the integration of the packaging structure, and there is no need to re-design the interconnection between multiple chips on the circuit board.

[0020] In a third aspect, the present application also provides an electronic device, including the chip packaging structure mentioned above, and a circuit board, wherein the chip packaging structure is electrically connected to the circuit board. The chip packaging structure in the electronic device realizes horizontal and three-dimensional integrated interconnection between multiple chips, improves the integration of the packaging structure, and does not need to perform the interconnection design between the multiple chips again on the circuit board.

[0021] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0023] Figure 1 A schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0024] Figure 2 A flow chart of a chip packaging structure preparation method provided in an embodiment of the present application;

[0025] Figure 3 to Figure 13 A step diagram of the preparation method provided in the embodiment of the present application;

[0026] Fig.14An electronic device is provided in an embodiment of the present application. DETAILED DESCRIPTION

[0027] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0028] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0029] In the description of the present application, “plurality” means two or more.

[0030] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0031] When describing some embodiments, the expression "connected" and its derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "electrically connected" indicates, for example, that two or more components are in direct physical or electrical contact, and may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0032] At present, chip-on-wafer-on-substrate (CoWoS) technology is the most common 2.5D packaging solution for high-computing power chips in the world. During the technological iteration process, the size of the adapter board continues to increase, which will inevitably lead to a decrease in the manufacturing yield of the adapter board and subsequent reliability issues of large-size silicon adapter boards, while increasing the corresponding costs.

[0033] In contrast, the silicon bridge embedded active transfer board provides better electrical, signal and power integrity performance than the silicon intermediate connector solution, with lower cost and no limitation on wafer size. The technology is highly scalable and can be seamlessly integrated into complex chip architectures. The use of high-density interconnect silicon bridges to connect chips makes the interconnect line density an order of magnitude higher than traditional organic flip-chip solder packaging.

[0034] However, the current main silicon bridge technology is to produce high-density wiring and fine-pitch micro-bumps on a silicon substrate, and achieve horizontal interconnection between chips through substrate embedment or fan-out packaging integration, but it is unable to achieve horizontal and three-dimensional integrated interconnection. In addition, the integration of the packaging structure is limited, and usually it is necessary to perform interconnection design again on the system-level circuit board to achieve interconnection with other chips.

[0035] To solve the above problems, the present application proposes a chip packaging structure 100, such as Figure 1 As shown, Figure 1 A schematic diagram of a chip packaging structure provided in an embodiment of the present application.

[0036] The chip packaging structure 100 includes a first rewiring layer 10, a first adapter plate 11 and a second adapter plate 12, a second rewiring layer 13, a plurality of first connection structures 14, and a first chip 15, a second chip 16, a third chip 17 and a fourth chip 18. The first rewiring layer 10 includes a first interconnect structure 101. The first adapter plate 11 and the second adapter plate 12 are arranged on the first rewiring layer 10 and are electrically connected to the first interconnect structure 101 respectively. At least one of the first adapter plate 11 and the second adapter plate 12 is an active adapter plate. The second rewiring layer 13 includes a second interconnect structure 131. The second rewiring layer 13 is arranged on a side of the first adapter plate 11 away from the first rewiring layer 10, and is arranged on a side of the second adapter plate 12 away from the first rewiring layer 10. The first adapter plate 11 and the second adapter plate 12 are electrically connected to the second interconnect structure 131 respectively. One ends of the plurality of first connection structures 14 are electrically connected to the second interconnection structure 131 , and the first chip 15 , the second chip 16 , the third chip 17 and the fourth chip 18 are electrically connected to the other ends of the plurality of first connection structures 14 , respectively.

[0037] In the embodiment of the present application, the first adapter board 11 and the second adapter board 12 are arranged on the first rewiring layer 10, and are respectively electrically connected to the first interconnection structure 101, thereby realizing horizontal interconnection between the two adapter boards. In addition, the first rewiring layer 10 also provides a basis for the chip packaging structure 100 to be interconnected with a high-density substrate, which is more flexible.

[0038] In addition, the first adapter board 11 and the second adapter board 12 are electrically connected to the second interconnection structure 131 of the second rewiring layer 13, respectively. The first rewiring layer 10 and the second rewiring layer 13 are respectively arranged on both sides of the first adapter board 11 and the second adapter board 12, which can better realize horizontal interconnection and vertical interconnection, and facilitate signal conditioning. One end of the plurality of first connection structures 14 is electrically connected to the second interconnection structure 131, and the other end is electrically connected to the first chip 15, the second chip 16, the third chip 17 and the fourth chip 18, respectively. Through the second rewiring layer 10 and the plurality of first connection structures 14, the interconnection between the plurality of chips and the plurality of adapter boards is realized, and the interconnection between the plurality of chips is also realized.

[0039] At least one of the first adapter board 11 and the second adapter board 12 is an active adapter board. For example, the first adapter board 11 can be an active adapter board, and the second adapter board 12 can be a passive adapter board, wherein the "passive adapter board" includes a silicon wafer, a through hole (TSV) penetrating the silicon wafer, and a wiring arranged on the silicon wafer, and the "active adapter board" includes not only a silicon wafer, a through hole penetrating the silicon wafer, and a wiring arranged on the silicon wafer, but also includes active devices arranged on the silicon wafer, and the active devices are used to form a functional circuit that meets the design requirements. For another example, the first adapter board 11 can be a passive adapter board, and the second adapter board 12 can be an active adapter board. For another example, the first adapter board 11 and the second adapter board 12 are both active adapter boards.

[0040] Compared with passive silicon bridges, active adapter board interconnection can better optimize signal integrity performance and signal conditioning functions. The chip packaging structure constructed with multiple interconnection relationships can better realize horizontal and vertical high-density interconnection between chips, with strong flexibility, and realize horizontal and three-dimensional integrated interconnection between multiple chips, which improves the integration of the packaging structure and eliminates the need to re-design the interconnection between the multiple chips on the circuit board.

[0041] The adapter boards provided in the embodiment of the present application are not limited to two, but may be three, four, five, etc., and at least one of the multiple adapter boards is an active adapter board. Multiple adapter boards can form an interwoven interconnection network, provide more interconnection points and higher interconnection density, and can easily expand the functions and performance of the system, and in some cases can also improve the fault tolerance of the system.

[0042] The chips provided in the embodiment of the present application are not limited to four, but can also be five, six, seven, etc. Multiple chips are integrated in the chip packaging structure 100, which can improve the integration level and reduce the communication time between chips, without the need to re-design the interconnection between the multiple chips on the circuit board.

[0043] In some embodiments, Figure 1 As shown, the chip packaging structure 100 further includes a plurality of second connection structures 19 , one end of the plurality of second connection structures 19 is electrically connected to the first interconnection structure 101 , and the other end thereof is electrically connected to the second interconnection structure 131 .

[0044] The electrical connection between the first interconnection structure 101 and the second interconnection structure 131 is realized through the second connection structure 19, thereby forming an interwoven interconnection network, so that the chip packaging structure 100 realizes a variety of interconnection relationships, such as the interconnection between the first chip 15 and the second chip 16, the interconnection between the third chip 17 and the fourth chip 18, and the interconnection between the first chip 15 and the third chip 17. The two interconnected chips can communicate directly without going through the active adapter board or other channels on the system circuit board, which can reduce the delay of data transmission. In tasks that require a large amount of parallel processing, the computing power of the control chip can be more efficiently utilized. The interwoven interconnection network realizes horizontal and three-dimensional integrated interconnection between multiple chips, improves the integration of the packaging structure, and there is no need to re-design the interconnection between multiple chips on the circuit board.

[0045] In some embodiments, Figure 1 As shown, the first chip 15 and the third chip 17 are control chips, and the second chip 16 and the fourth chip 18 are storage chips.

[0046] Exemplarily, the first chip 15 and the third chip 17 may be high-computing power chips. Through the interwoven interconnection network, high-density interconnection between the high-computing power chip and the storage chip is achieved, thereby improving system integration.

[0047] In some embodiments, Figure 1 As shown, the first chip 15 is a central processing unit chip (CPU), the second chip 16 is a dynamic random access memory chip (DRAM), the third chip 17 is a graphics processing unit chip (GPU), and the fourth chip 18 is a high bandwidth memory chip (HBM).

[0048] The first chip 15 and the second chip 16 can be interconnected through the first adapter board 11, or directly through the second interconnection structure 131 and the first connection structure 14 instead of the first adapter board 11. The third chip 17 and the fourth chip 18 can be interconnected through the second adapter board 12, or directly through the second interconnection structure 131 and the first connection structure 14 instead of the second adapter board 12. The redundant interconnection structure improves the connection density and fault tolerance of the system. The first adapter board 11 and the second adapter board 12 can both provide higher bandwidth interconnection and optimize the signal path, so that the data transmission between the central processing unit chip and the dynamic random access memory chip, and the graphics processing unit chip and the high-bandwidth memory chip is faster, reducing the attenuation and interference of the signal during the transmission process, thereby improving the integrity of the signal. Similarly, the first chip 15 and the third chip 17 can be interconnected through the first adapter board 11 or the second adapter board 12, or through a passive first interconnection structure 101, a second interconnection structure 131 and a second connection structure 19, which can reduce the delay in data transmission, and in tasks that require a large amount of parallel processing, can more efficiently utilize the computing power of the control chip and is conducive to improving the system's fault tolerance.

[0049] In some embodiments, Figure 1 As shown, the first rewiring layer 10 includes a bottom surface P1 away from the first adapter board 11. The first adapter board 11 and the second adapter board 12 are arranged in a flat pattern in a direction parallel to the bottom surface P1 of the first rewiring layer 10, that is, the first adapter board 11 and the second adapter board 12 do not overlap. The first chip 15, the second chip 16, the third chip 17 and the fourth chip 18 are arranged in a flat pattern in a direction parallel to the bottom surface P1 of the first rewiring layer 10.

[0050] In some embodiments, Figure 1 As shown, the chip packaging structure 100 also includes a first packaging layer 20 and a second packaging layer 21, wherein the first packaging layer 20 wraps the first adapter board 11 and the second adapter board 12, and the second packaging layer 21 wraps the first chip 15, the second chip 16, the third chip 17 and the fourth chip 18 to ensure the stability of the first chip 15, the second chip 16, the third chip 17 and the fourth chip 18 bridging the first adapter board 11 and the second adapter board 12 through the second interconnect structure 131. The first packaging layer 20 and the second packaging layer 21 provide physical protection for the internal electronic components, respectively, to prevent mechanical damage, dust, moisture and other environmental factors from damaging sensitive semiconductor materials. Exemplarily, the materials of the first packaging layer 20 and the second packaging layer 21 both include epoxy molding compound (EMC).

[0051] On the other hand, the present application also provides a method for preparing a chip packaging structure, such as Figure 2As shown, Figure 2 A flow chart of a chip packaging structure preparation method provided in an embodiment of the present application, Figure 3 to Figure 13 A step diagram of the preparation method provided in the embodiments of the present application.

[0052] Specifically, the preparation method includes the following steps S1 to S6:

[0053] Step S1: Figure 3-4 As shown, the first adapter board 11 and the second adapter board 12 are disposed on the carrier board L01 , and at least one of the first adapter board 11 and the second adapter board 12 is an active adapter board.

[0054] Exemplarily, before step S1, Figure 3 As shown, the preparation method further includes forming a second connection structure 19 on the carrier L01. The carrier L01 includes a temporary carrier L02 and a temporary bonding adhesive L03 coated on the upper surface of the carrier L02. Then, the second connection structure 19 is prepared on the carrier L01 by an electroplating process, and the material of the second connection structure 19 may include copper.

[0055] Afterwards, if Figure 4 As shown, through the patch process, the active adapter board is connected to the carrier board L01 to form a first adapter board 11 and a second adapter board 12. The active adapter board can also be an active silicon bridge.

[0056] Step S2: Figure 5 to Figure 7 As shown, a second rewiring layer 13 is formed, and the second rewiring layer 13 includes a second interconnect structure 131. The second rewiring layer 13 is located on a side of the first adapter board 11 away from the carrier board L01, and is located on a side of the second adapter board 12 away from the carrier board L01. The first adapter board 11 and the second adapter board 12 are electrically connected to the second interconnect structure 131 respectively.

[0057] Exemplarily, before step S2, as Figure 5 As shown, the preparation method further includes forming a first packaging layer 20 on the carrier L01, the first packaging layer 20 wraps the first adapter board 11 and the second adapter board 12, the material of the first packaging layer 20 includes epoxy molding compound (EMC), and the process adopts a wafer-level molding process.

[0058] Afterwards, if Figure 6 As shown, grinding, thinning and chemical mechanical polishing are performed to reduce the package volume and achieve surface flatness, so that the first package layer 20 exposes the surface of the first adapter board 11 away from the carrier board L01, and exposes the surface of the second adapter board 12 away from the carrier board L01, and at the same time, exposes the second connection structure 19.

[0059] Then, if Figure 7As shown, a second rewiring layer 13 is formed on the upper surface of the first adapter board 11 and the second adapter board 12, that is, on the side of the first adapter board 11 and the second adapter board 12 away from the carrier board L01, and the electrical connection between the first adapter board 11 and the second adapter board 12 is achieved by using a second interconnect structure 131.

[0060] After the second rewiring layer 13 is formed, one end of the plurality of second connection structures 19 is electrically connected to the second interconnection structure 131 .

[0061] Step S3: Figure 8 As shown, a plurality of first connection structures 14 are formed, and one end of the plurality of first connection structures 14 is electrically connected to the second interconnection structure 131 .

[0062] Exemplarily, the process of completing step S3 adopts a micro-bump manufacturing process to form a high-density interconnection structure.

[0063] Step S4: Fig. 9 As shown, the first chip 15 , the second chip 16 , the third chip 17 and the fourth chip 18 are electrically connected to the other ends of the plurality of first connection structures 14 , respectively.

[0064] For example, Fig. 9 As shown, the first chip 15, the second chip 16, the third chip 17 and the fourth chip 18 are respectively bonded to the multiple first connection structures 14, so that the first chip 15, the second chip 16, the third chip 17 and the fourth chip 18 are respectively electrically connected to the second interconnection structure 131 through the multiple first connection structures 14.

[0065] Step S5: Figure 10-11 As shown, the carrier board L01 is removed.

[0066] For example, Fig.10 As shown, before step S5, the preparation method further includes forming a second encapsulation layer 21, and the second encapsulation layer 21 encapsulates the first chip 15, the second chip 16, the third chip 17 and the fourth chip 18. The material of the second encapsulation layer 21 includes epoxy molding compound (EMC), and the process adopts a wafer-level molding process. In addition, grinding and thinning and chemical mechanical polishing are performed to reduce the package volume and achieve surface flatness.

[0067] Afterwards, if Fig.11 As shown, the temporary bonding glue L03 is removed by the debonding process, and as the temporary bonding glue L03 is peeled off and removed, the temporary carrier L02 is also removed. After removing the carrier L01, the lower surface of the first adapter plate 11 and the second adapter plate 12 is exposed, that is, the side away from the first chip 15 and the third chip 17.

[0068] Step S6: Figure 12-13 As shown, a first rewiring layer 10 is formed, and the first rewiring layer 10 includes a first interconnect structure 101. The first rewiring layer 10 is located on a side of the first adapter board 11 away from the second rewiring layer 13, and is located on a side of the second adapter board 12 away from the second rewiring layer 13. The first interconnect structure 131 is electrically connected to the first adapter board 11 and the second adapter board 12.

[0069] For example, Fig.12 As shown, a first rewiring layer 10 is formed on the lower surface of the first adapter board 11 and the lower surface of the second adapter board 12, that is, the side of the first adapter board 11 away from the second rewiring layer 13 and the side of the second adapter board 12 away from the second rewiring layer 13, and the first interconnection structure 101 of the first rewiring layer 10 is used to realize the electrical connection between the first adapter board 11 and the second adapter board 12. After the first rewiring layer 10 is formed, the other ends of the plurality of second connection structures 19 are electrically connected to the first interconnection structure 101.

[0070] In some embodiments, Fig.13 As shown, after completing step S6, a micro-bump manufacturing process is adopted on a side of the first rewiring layer 10 away from the first adapter board 11 and the second adapter board 12 to form solder balls 22 for subsequent electrical connection with the circuit board.

[0071] The above preparation method combines the micro-bump manufacturing process with the wafer-level fan-out packaging process, and integrates it into the molding, grinding, thinning and chemical mechanical polishing processes. It does not require a silicon adapter plate, which can reduce packaging costs and improve packaging reliability.

[0072] In a third aspect, the present application also provides an electronic device 200, such as Fig.14 As shown, Fig.14 An electronic device provided in an embodiment of the present application includes the chip packaging structure 100 mentioned above, and a circuit board 201, wherein the chip packaging structure 200 is electrically connected to the circuit board 201. The chip packaging structure 100 in the electronic device 200 realizes horizontal and three-dimensional integrated interconnection between multiple chips, improves the integration of the packaging structure, and does not need to perform interconnection design again on the circuit board 201.

[0073] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A chip packaging structure, characterized in that: include: a first rewiring layer including a first interconnect structure; A first adapter plate and a second adapter plate, which are disposed on the first rewiring layer and are electrically connected to the first interconnect structure respectively, and at least one of the first adapter plate and the second adapter plate is an active adapter plate; a second rewiring layer, comprising a second interconnect structure, the second rewiring layer being arranged on a side of the first adapter plate away from the first rewiring layer, and being arranged on a side of the second adapter plate away from the first rewiring layer, the first adapter plate and the second adapter plate being electrically connected to the second interconnect structure respectively; a plurality of first connection structures, one end of each of the plurality of first connection structures being electrically connected to the second interconnection structure; A first chip, a second chip, a third chip and a fourth chip, wherein the first chip, the second chip, the third chip and the fourth chip are electrically connected to the other ends of the plurality of first connection structures respectively.

2. The chip packaging structure according to claim 1, characterized in that: The chip packaging structure further includes a plurality of second connection structures, one end of each of the plurality of second connection structures is electrically connected to the first interconnection structure, and the other end of each of the plurality of second connection structures is electrically connected to the second interconnection structure.

3. The chip packaging structure according to claim 1, characterized in that: The first chip and the third chip are control chips, and the second chip and the fourth chip are storage chips.

4. The chip packaging structure according to claim 3, characterized in that: The first chip is a central processing unit chip, the second chip is a dynamic random access memory chip, the third chip is a graphics processing unit chip, and the fourth chip is a high bandwidth memory chip.

5. The chip packaging structure according to claim 1, characterized in that: The first adapter plate and the second adapter plate are arranged in parallel along a direction parallel to the bottom surface of the first rewiring layer; The first chip, the second chip, the third chip and the fourth chip are arranged in a tiled manner along a direction parallel to a bottom surface of the first rewiring layer.

6. The chip packaging structure according to claim 1, characterized in that: The chip packaging structure further includes a first packaging layer and a second packaging layer, the first packaging layer wraps the first adapter board and the second adapter board, and the second packaging layer wraps the first chip, the second chip, the third chip and the fourth chip.

7. A method for preparing a chip packaging structure, characterized in that: include: Disposing a first adapter board and a second adapter board on a carrier board, wherein at least one of the first adapter board and the second adapter board is an active adapter board; forming a second rewiring layer, the second rewiring layer comprising a second interconnect structure; the second rewiring layer is located on a side of the first adapter plate away from the carrier plate, and is located on a side of the second adapter plate away from the carrier plate; the first adapter plate and the second adapter plate are electrically connected to the second interconnect structure respectively; forming a plurality of first connection structures, one end of each of the plurality of first connection structures being electrically connected to the second interconnection structure; electrically connecting the first chip, the second chip, the third chip and the fourth chip to the other ends of the plurality of first connection structures respectively; removing the carrier plate; A first rewiring layer is formed, wherein the first rewiring layer includes a first interconnect structure; the first rewiring layer is located on a side of the first adapter board away from the second rewiring layer, and is located on a side of the second adapter board away from the second rewiring layer; the first interconnect structure is electrically connected to the first adapter board and the second adapter board.

8. The preparation method according to claim 7, characterized in that: Before forming the first adapter plate and the second adapter plate, the preparation method further includes: forming a plurality of second connection structures on the carrier; After forming the second rewiring layer, one end of the plurality of second connection structures is electrically connected to the second interconnect structure; After the first rewiring layer is formed, the other ends of the plurality of second connection structures are electrically connected to the first interconnection structure.

9. The preparation method according to claim 7, characterized in that: After forming the first adapter plate and the second adapter plate and before forming the second rewiring layer, the preparation method further includes: forming a first packaging layer on the carrier, wherein the first packaging layer exposes a surface of the first adapter plate away from the carrier, and exposes a surface of the second adapter plate away from the carrier; Before removing the carrier plate, the preparation method further comprises: A second packaging layer is formed, wherein the second packaging layer encapsulates the first chip, the second chip, the third chip, and the fourth chip.

10. An electronic device, characterized in that: include: The chip packaging structure according to any one of claims 1 to 5; A circuit board, the chip packaging structure is electrically connected to the circuit board.

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