Semiconductor structure and detection method thereof

Abstract

The embodiment of the invention provides a semiconductor structure and a detection method thereof. The semiconductor structure comprises a first region arranged on a substrate and a second region arranged on one side of the first region, a storage structure is arranged in the first area; a detection structure which is separated from the storage structure and is vertical to the substrate is arranged in the second region; and the detection structure comprises a first detection unit in a floating state and a second detection unit coupled to ground voltage.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, including but not limited to a semiconductor structure and a detection method thereof. Background Art

[0002] Three-dimensional phase change memory (PCM) is considered to be one of the most promising next-generation semiconductor storage technologies due to its advantages such as high density, fast writing and low power consumption. In three-dimensional phase change memory, data is stored by using the difference in conductivity when the phase change layer transforms between the crystalline state and the amorphous state.

[0003] In order to improve the process window of the three-dimensional phase change memory, dummy cells are usually added during the layout design and process, and the dummy structures are subsequently removed. However, in the process of removing the dummy structures, it is easy to cause the residue of conductive materials in the dummy area, for example, the residue of word line materials (for example, metal tungsten) exists in the dummy area.

[0004] Current detection methods have difficulty detecting minute residues of conductive materials. Summary of the invention

[0005] In view of this, an embodiment of the present disclosure provides a semiconductor structure and a detection method thereof.

[0006] In a first aspect, an embodiment of the present disclosure provides a semiconductor structure, comprising: a first region arranged on a substrate and a second region arranged on one side of the first region; a storage structure is arranged in the first region; a detection structure is arranged in the second region, which is spaced from the storage structure and perpendicular to the substrate, and the detection structure comprises: a first detection unit in a floating state and a second detection unit coupled to a ground voltage.

[0007] In some embodiments, the structure of the first detection unit and the structure of the second detection unit are arranged identically, the minimum distance between the first detection unit and the substrate is less than or equal to the minimum distance between the storage structure and the substrate, and the maximum distance between the first detection unit and the substrate is greater than or equal to the maximum distance between the storage structure and the substrate.

[0008] In some embodiments, the semiconductor structure further includes: a conductive block disposed between the substrate and the second detection unit, and the second detection unit is connected to the substrate through the conductive block so as to be coupled to a ground voltage.

[0009] In some embodiments, the semiconductor structure also includes: a conductive layer disposed on the storage structure away from the substrate side, the second detection unit includes a first end and a second end opposite to each other in a direction perpendicular to the substrate, the first end is coupled to the conductive layer, and the second end is coupled to the conductive block.

[0010] In some embodiments, the storage structure includes a top electrode away from the substrate side, the second detection unit includes a first subunit, and the first subunit and the top electrode are prepared by the same process.

[0011] In some embodiments, the first subunit includes a second end and a third end opposite to each other in a direction perpendicular to the substrate, and the second end is coupled to a conductive block.

[0012] In some embodiments, the second detection unit further includes a second subunit, the second subunit including a first end and a fourth end opposite to each other in a direction perpendicular to the substrate, the first end is coupled to the conductive layer, and the fourth end is coupled to the third end.

[0013] In some embodiments, the first area is a storage array area, and the second area is a dummy area.

[0014] In a second aspect, an embodiment of the present disclosure provides a method for detecting a semiconductor structure, and the detection method is applied to a semiconductor structure as in the above-mentioned technical solution; the detection method comprises: performing electron beam detection on a detection structure of the semiconductor structure to obtain a detection image; the detection image comprises a first sub-image obtained after detecting the first detection unit and a second sub-image obtained after detecting the second detection unit; determining that the semiconductor structure has a defect based on the same brightness of the first sub-image and the second sub-image; determining that the semiconductor structure has no defect based on the different brightness of the first sub-image and the second sub-image.

[0015] In some embodiments, determining that the semiconductor structure has a defect based on the first sub-image and the second sub-image having the same brightness includes: determining that the first detection unit and the second detection unit have a short circuit defect based on the first sub-image and the second sub-image having a first brightness value. Determining that the first detection unit and the second detection unit have an open circuit defect based on the first sub-image and the second sub-image having a second brightness value; wherein the first brightness value is greater than the second brightness value.

[0016] The present disclosure provides a semiconductor structure and a detection method thereof. In the present disclosure, the detection structure disposed in the second region includes a first detection unit in a floating state and a second detection unit coupled to a ground voltage; an electron beam detection is performed on the detection structure to obtain a detection image; the defect status of the semiconductor structure can be determined based on the first sub-image and the second sub-image in the detection image, thereby determining whether there is a short circuit defect between the first detection unit and the second detection unit, and further determining whether conductive material residue is generated in the process of removing the dummy structure in the second region. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A cross-sectional view of a phase change memory cell provided for some embodiments;

[0018] Figure 2A and Figure 2B A cross-sectional view of a phase change memory during manufacturing provided in some embodiments;

[0019] Figure 3 A cross-sectional view of a conductive structure provided in some embodiments under normal conditions;

[0020] Figure 4 Cross-sectional view of a conductive structure under abnormal conditions provided for some embodiments Figure 1 ;

[0021] Figure 5 A second cross-sectional view of a conductive structure provided in some embodiments under abnormal conditions;

[0022] Fig. 6A and Figure 6B A cross-sectional view of a conductive structure during manufacturing provided for some embodiments;

[0023] Figure 7 A schematic flow chart of a method for manufacturing a semiconductor structure provided in some embodiments;

[0024] FIG. 8A to FIG. 8D A cross-sectional view of a semiconductor structure during manufacturing provided for some embodiments;

[0025] 9A to 9E Cross-sectional views of semiconductor structures during manufacturing processes provided for other embodiments;

[0026] Fig.10 A schematic diagram of a process flow of a semiconductor structure detection method provided by an embodiment of the present disclosure;

[0027] Fig.11 Schematic diagram of detection images in different situations. DETAILED DESCRIPTION

[0028] The following will be combined with the embodiments of the present disclosure and the accompanying drawings to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0029] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0030] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0031] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.

[0032] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0033] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0034] In order to thoroughly understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below, but in addition to these detailed descriptions, the present disclosure may also have other implementations.

[0035] Before introducing the embodiments of the present disclosure, various directions that may be involved in the following text are defined. The arrangement direction of the bottom memory cell (or, the top memory cell) in the three-dimensional phase change memory is defined as the intersecting first direction (i.e., D1 direction) and the second direction (i.e., D2 direction), and the stacking direction of the bottom memory cell and the top memory cell is defined as the third direction (i.e., D3 direction), and any two of the first direction, the second direction, and the third direction intersect. Among them, the direction in which the bit line in the three-dimensional phase change memory extends is the first direction, and the direction in which the word line extends is the second direction. In some embodiments, any two of the first direction, the second direction, and the third direction are perpendicular to each other. The following will be described by taking the example that any two of the first direction, the second direction, and the third direction are perpendicular to each other.

[0036] refer to Figure 1 , Figure 1 A cross-sectional view of a phase change memory cell provided in some embodiments. Figure 1As shown, the phase change memory unit 106 includes: a first electrode layer 108, a selection layer 110, a second electrode layer 112, a phase change layer 114 and a third electrode layer 116 stacked in sequence along the D3 direction; the first electrode layer 108 in the phase change memory unit 106 can be coupled to the bit line 102, and the third electrode layer 116 in the phase change memory unit 106 can be coupled to the word line 104.

[0037] Here, the first electrode layer 108, the second electrode layer 112 and the third electrode layer 116 can be used to transmit electrical signals and can include conductive materials, such as metal materials, metal nitrides or any combination thereof. The metal material can be, for example, platinum (Pt), tungsten (W), aluminum (Al), copper (Cu) or titanium (Ti). In some embodiments, the first electrode layer 108, the second electrode layer 112 and the third electrode layer 116 can include carbon electrodes.

[0038] Here, the gating layer 110 may include a threshold switch material, such as an Ovonic Threshold Switching (OTS) material. The OTS material may be a chalcogenide material, such as GeSeAs, GeTeAs, GeSeTeSe, GeSe, SeAs, GeTe, SiTe, etc. The bidirectional threshold switch uses an electrical signal to control the switch of the gating device. When the applied electrical signal is higher than the threshold voltage, the OTS material changes from a high resistance state to a low resistance state, and the OTS is in an on state; when the electrical signal is removed, the OTS material changes from a low resistance state to a high resistance state, and the OTS is in an off state. The gating layer 110 is used to control the current flowing through the phase change layer 114, and remains in an on state when the phase change layer 114 is erased and written, and remains in a off state after the erase and write operation is completed, so as to avoid read-write crosstalk between phase change memory cells.

[0039] Here, the phase change layer 114 may include a phase change material. The phase change material may be an alloy of a chalcogenide compound, for example, a germanium antimony telluride compound (Ge-Sb-Te compound, GST), a germanium antimony compound, an indium germanium telluride compound, an aluminum selenide telluride compound, an indium selenide telluride compound, an aluminum indium selenide telluride compound, etc. In this embodiment, taking the material of the phase change layer 114 as GST as an example, the GST material can realize a reversible transition between an amorphous state and a crystalline state. In the amorphous state, the GST material has a short-range atomic energy level and a low free electron density, so that it has a high resistivity; in the crystalline state, the GST material has a long-range atomic energy level and a high free electron density, so that it has a low resistivity. The memory uses the resistance difference between different phases of phase change materials to realize information storage. By applying different voltage or current pulse signals to the phase change layer, the phase change material undergoes a physical phase change, that is, a reversible phase change occurs between the crystalline state (low resistance state) and the amorphous state (high resistance state), thereby realizing the writing and erasing operations of information to store data.

[0040] Here, the cross-sectional shape of the phase-change memory unit 106 perpendicular to the direction D3 may be circular, quadrilateral or other shapes. The present disclosure has no special limitation on the orthographic projection shape (or cross-sectional shape) of the phase-change memory unit 106 .

[0041] refer to Figure 2A and Figure 2B , Figure 2A and Figure 2B A cross-sectional view of a phase change memory during the manufacturing process provided in some embodiments. Figure 2A As shown, the semiconductor structure may include: a first region 202 and a second region 204 arranged on one side of the first region 202, wherein the first region 202 is provided with a first conductive line 206, a first storage unit 208, a second conductive line 210, a third conductive line 214, and a second storage stack bar 218 stacked in sequence along the D3 direction, and the second region 204 is provided with a virtual second conductive line 212, a virtual third conductive line 216, and a virtual second storage stack bar 220 stacked in sequence along the D3 direction; wherein, a plurality of first conductive lines 206 extend along the D1 direction and are arranged at intervals along the D2 direction, the first storage unit 208 is arranged at intervals along the D1 direction and the D2 direction, and a plurality of second conductive lines 210, virtual second conductive lines 212, third conductive lines 214, virtual third conductive lines 216, second storage stack bars 218, and virtual second storage stack bars 220 extend along the D2 direction and are arranged at intervals along the D1 direction. Here, the second conductive line 210 and the dummy second conductive line 212 are formed in the same process, and the third conductive line 214, the dummy third conductive line 216, the second storage stack bar 218 and the dummy second storage stack bar 220 are formed in the same process.

[0042] like Figure 2B As shown, the dummy second storage stack bar 220, the dummy third conductive line 216, and the dummy second conductive line 212 in the second region 204 are removed. Here, in the process of etching and removing the dummy second storage stack bar 220, the dummy third conductive line 216, and the dummy second conductive line 212 in the second region 204, it may cause the material residue of the dummy second conductive line 212 in the second region 204, that is, there is a conductive material residue in the second region (such as Figure 2B (shown in the dotted circle).

[0043] Thus, it is difficult to detect extremely fine (eg, less than 5 nm) residual conductive material using only an online inspection method, such as a bright field inspection (BFI) or a dark field inspection (DFI).

[0044] refer to Figure 3 , Figure 3 FIG. 1 is a cross-sectional view of a conductive structure provided in some embodiments under normal conditions. Figure 3 As shown, the semiconductor structure may include: a substrate 306; a first region 302 disposed on the substrate 306 and a second region 304 disposed on one side of the first region 302; a storage structure 310 (such as Figure 3 In the second region 304, a conductive structure 312 may be provided, and the conductive structure 312 may be coupled to the substrate 306 through the metal layer 308 and the via structure 314, that is, the conductive structure 312 may be coupled to the ground voltage. Here, the conductive structure 312 may also be referred to as a top via (TV) structure, and the top via structure is coupled to the substrate 306, that is, the top via structure is coupled to the ground voltage (TV grounding).

[0045] refer to Figure 4 , Figure 4 Cross-sectional view of a conductive structure under abnormal conditions provided for some embodiments Figure 1 .like Figure 4 As shown, the conductive structure 312 has an under-etch problem, that is, the bottom of the conductive structure 312 is not coupled to the metal layer 308 (eg, Figure 4 Therefore, the conductive structure 312 is not coupled to the substrate 306, that is, the conductive structure 312 is not coupled to the ground voltage.

[0046] refer to Figure 5 , Figure 5 FIG2 is a cross-sectional view of a conductive structure provided in some embodiments under abnormal conditions. Figure 5As shown, the conductive structure 312 has a surface void problem, that is, a void morphology appears on the surface of the conductive structure 312 (eg, Figure 5 (shown in the dotted circle).

[0047] Combination Figure 3 , Figure 4 and Figure 5 , Figure 3 A cross-sectional view of the conductive structure 312 in a normal condition is shown. By performing electron beam inspection (Electrons Beam inspection, EBI) on the conductive structure 312 in a normal condition (Noraml), the conductive structure 312 is displayed as bright voltage contrast (BVC) in the inspection image. Figure 4 The cross-sectional view of the conductive structure 312 when there is an insufficient etching problem is shown. By performing electron beam detection on the abnormal conductive structure 312, the conductive structure 312 is displayed as a dark voltage contrast (DVC) in the detection image. Therefore, the detection image obtained by the electron beam detection can identify that the conductive structure 312 has an insufficient etching problem. Figure 5 The cross-sectional view of the conductive structure 312 when there are surface holes is shown. The surface holes of the conductive structure 312 can be identified by bright field detection or scanning electron microscope (SEM).

[0048] In summary, for the process of removing the dummy structure, the bright field detection method in the current detection method can detect the surface holes or other abnormal morphology of the conductive structure 312, and the electron beam detection can detect the insufficient etching problem of the conductive structure 312. However, the current detection method is difficult to detect the residual of fine conductive material.

[0049] Return to reference Figure 2A and Figure 2B As shown, during the process of etching away the dummy second storage stack strip, the dummy third conductive line and the dummy second conductive line in the second region, conductive material residue may exist in the second region. Fig. 6A A cross-sectional view of the semiconductor structure along the direction D1 is shown, and Figure 6B The cross-sectional view of the semiconductor structure along the D2 direction is shown. Subsequently, the second conductive structure 312 is formed in the second region 304. The residual conductive material may cause interconnection between different conductive structures 312, thereby causing short circuit connection between different conductive structures 312 and electrical failure. However, the current detection method is difficult to detect the problem of interconnection between different conductive structures 312 caused by the slight residual conductive material.

[0050] In view of this, an embodiment of the present disclosure provides a semiconductor structure and a detection method thereof.

[0051] refer to Figure 7 , Figure 7 A schematic diagram of a method for manufacturing a semiconductor structure provided in some embodiments. Figure 7 As shown, an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, the semiconductor structure comprising: a first region disposed on a substrate and a second region disposed on one side of the first region along any direction parallel to the substrate; the manufacturing method comprises:

[0052] Step S710: forming a storage structure in the first region;

[0053] Step S720: forming a detection structure in the second region that is spaced apart from the storage structure and perpendicular to the substrate, wherein the detection structure includes a first detection unit in a floating state and a second detection unit coupled to a ground voltage.

[0054] In the embodiment of the present disclosure, the detection structure provided in the second area includes a first detection unit in a floating state and a second detection unit coupled to a ground voltage; an electron beam detection is performed on the detection structure to obtain a detection image; the defect condition of the semiconductor structure can be determined based on the first sub-image and the second sub-image in the detection image, thereby determining whether there is a short circuit defect between the first detection unit and the second detection unit, and further determining whether conductive material residue is generated in the process of removing the dummy structure in the second area.

[0055] refer to FIG. 8A to FIG. 8D , FIG. 8A to FIG. 8D The cross-sectional view of the semiconductor structure during the manufacturing process provided by some embodiments. Figure 7 as well as FIG. 8A to FIG. 8D , describing in detail the manufacturing methods of the semiconductor structures provided by some embodiments.

[0056] refer to Fig. 8A As shown, in some embodiments, the first region 402 is provided with a first conductive line 408, a first storage unit 410, a second conductive line 412, a third conductive line 414, and a second storage stack bar 416 stacked along the D3 direction, and the second region 404 is provided with a first dielectric sublayer 430, a virtual second conductive line 418, a virtual third conductive line 420, and a virtual second storage stack bar 422 stacked along the D3 direction; wherein the first storage unit 410 is arranged at intervals along the D1 direction and the D2 direction, the first conductive line 408 extends along the D1 direction, and the second conductive line 412, the third conductive line 414, the second storage stack bar 416, the virtual second conductive line 418, the virtual third conductive line 420, and the virtual second storage stack bar 422 all extend along the D2 direction.

[0057] Exemplarily, before forming the storage structure, the manufacturing method may include the following steps: forming an interconnection layer on the substrate 406, wherein the interconnection layer may include a conductive layer extending along the D1 direction and a conductive block extending along the D3 direction. Different conductive layers and different conductive blocks may be separated by an insulating layer. The present disclosure does not specifically limit the number of conductive layers and conductive blocks in the interconnection layer, and can be flexibly selected according to actual conditions.

[0058] Still refer to Fig. 8A As shown, the semiconductor structure also includes: a first conductive layer 462, a second conductive layer 464 and a third conductive layer 466; wherein the first conductive layer 462 is not coupled to the substrate 406; the second conductive layer 464 is coupled to the third conductive layer 466 through the first conductive block 468, and the third conductive layer 466 is coupled to the substrate 406 through the second conductive block 470.

[0059] Here, the first distance between the first conductive layer 462 and the substrate 406 and the second distance between the second conductive layer 464 and the substrate 406 are the same, and the first distance and the second distance are both greater than the third distance between the third conductive layer 466 and the substrate 406. The first conductive layer 462, the second conductive layer 464 and the third conductive layer 466 can be, for example, metal layers, wherein the first conductive layer 462 and the second conductive layer 464 are formed in the same process, that is, the first conductive layer 462 and the second conductive layer 464 can be metal layers located at the same layer. The first conductive block 468 and the second conductive block 470 can be, for example, via structures. Fig. 8A The number of conductive layers and conductive blocks shown is only for illustrative purposes and does not constitute a limitation on the scope of protection of the present disclosure.

[0060] Exemplarily, forming the above-mentioned interconnection layer may include the following steps: forming a first insulating layer on a substrate; etching the first insulating layer along the Z direction to form a first through hole exposing the substrate; filling a conductive material in the first through hole to form a second conductive block 470; forming a second insulating layer on the first insulating layer; etching the second insulating layer along the Z direction to form a first groove exposing the second conductive block; filling a conductive material in the first groove to form a third conductive layer 466; forming a third insulating layer on the second insulating layer; etching the third insulating layer along the Z direction to form a second through hole exposing the third conductive layer 466; filling a conductive material in the second through hole to form a first conductive block 468; forming a fourth insulating layer on the third insulating layer; etching the fourth insulating layer along the Z direction to form a second groove exposing the first conductive block 468 and a third groove exposing the third insulating layer; filling a conductive material in the second groove and the third groove to form a second conductive layer 464 and a first conductive layer 462, respectively.

[0061] Exemplarily, forming a storage structure may include the following steps: forming a first conductive material layer and a first storage stack layer in a first region 402 and a second region 404; etching the first storage stack layer and the first conductive material layer along a D3 direction to form a first groove extending along a D1 direction in the first region 402 and removing the first storage stack layer and the first conductive material layer in the second region 404, wherein the etched first storage stack layer in the first region 402 forms a first storage stack strip, and the etched first conductive material layer in the first region 402 forms a first conductive line 408; filling a first isolation material in the first groove to form a first isolation layer; and filling a first dielectric material in the second region to form a first dielectric sublayer 430.

[0062] Here, the first dielectric sublayer 430 is used to fill the space removed from the first conductive material layer and the first storage stack layer in the second region 404 . Therefore, the first dielectric sublayer 430 in the second region and the first conductive line 408 and the first storage stack strip in the first region 402 are arranged adjacent to each other.

[0063] Here, the first memory stack layer may include a first electrode layer, a gate layer, a second electrode layer, a phase change layer, and a third electrode layer which are sequentially stacked along a D3 direction.

[0064] Exemplarily, forming a storage structure may also include the following steps: forming a second conductive material layer in the first region 402 and the second region 404; etching the second conductive material layer and the first storage stack strip along the D3 direction to form a second groove extending along the D2 direction, wherein the first storage stack strip etched in the first region 402 forms a first storage unit 410, the second conductive material layer etched in the first region 402 forms a second conductive line 412, and the second conductive material layer etched in the second region 404 forms a virtual second conductive line 418; and filling the second groove with a second isolation material to form a second isolation layer.

[0065] Here, the first memory cell 410 may also be referred to as a bottom memory cell, and the bottom memory cells are arranged at intervals along the D1 direction and the D2 direction. The first conductive line 408 may also be referred to as a bottom bit line, the second conductive line 412 may also be referred to as a bottom word line, and the dummy second conductive line 418 may also be referred to as a dummy bottom word line.

[0066] Exemplarily, forming a storage structure may also include the following steps: forming a third conductive material layer and a second storage stack layer in the first region 402 and the second region 404, etching the second storage stack layer and the third conductive material layer along the D3 direction to form a third groove extending along the D2 direction, the second storage stack layer after etching in the first region 402 forms a second storage stack bar, the third conductive material layer after etching in the first region 402 forms a third conductive line 414, the third conductive material layer after etching in the second region 404 forms a virtual third conductive line 420, and the second storage stack layer after etching in the second region 404 forms a virtual second storage stack bar 422; filling the third isolation material in the third groove to form a third isolation layer.

[0067] Here, the second memory stack layer may also include a first electrode layer, a gate layer, a second electrode layer, a phase change layer, and a third electrode layer which are sequentially stacked along the direction D3.

[0068] Here, the second storage stack bar 416 can subsequently form a second storage unit, which can also be referred to as a top storage unit, and the top storage units are arranged at intervals along the D1 direction and the D2 direction. The third conductive line 414 can also be referred to as a top word line, and the dummy third conductive line 420 can also be referred to as a dummy top word line. The bottom word line and the top word line can be connected in a one-to-one correspondence, and the dummy bottom word line and the dummy top word line can also be connected in a one-to-one correspondence.

[0069] Here, the materials of the first conductive line 408, the second conductive line 412, the third conductive line 414, the dummy second conductive line 418, and the dummy third conductive line 420 may all include conductive materials, such as metal materials. In some embodiments, the first conductive line 408, the second conductive line 412, the third conductive line 414, the dummy second conductive line 418, and the dummy third conductive line 420 may include metal tungsten.

[0070] refer to Fig. 8A As shown, a mask layer 424 is further provided in the first region 402 and the second region 404, and the mask layer 424 includes a first sublayer 426 and a second sublayer 428. Here, the first sublayer 426 can be, for example, a mask layer for etching to form a third groove. The dummy second conductive line 418, the dummy third conductive line 420 and the dummy second storage stack bar 422 in the second region 404 are all dummy structures.

[0071] refer to Figure 8BAs shown, the dummy second storage stack bar 422, the dummy third conductive line 420 and the dummy second conductive line 418 in the second region 404 are removed. For example, the first region 402 can be shielded and the dummy structure in the second region 404 can be etched away. Due to the large etching depth, the process of etching away the dummy structure in the second region 404 may result in residual conductive material in the second region 404 (such as Figure 8B and Figure 8C (shown in the dotted circle).

[0072] Here, the etching depth for removing the dummy structure in the second region 404 includes the sum of the thickness of the dummy second storage stack bar 422 along the D3 direction, the thickness of the dummy third conductive line 420 along the D3 direction, and the thickness of the dummy second conductive line 418 along the D3 direction.

[0073] refer to Figure 8C As shown, a second dielectric sublayer 450 is formed in the second region 404, and the first dielectric sublayer 430 and the second dielectric sublayer 450 together form a first dielectric layer 452. Here, the second dielectric sublayer 450 is used to fill the space formed by removing the dummy structure in the second region 404. Therefore, the second dielectric sublayer 450 in the second region 404 and the second conductive line 412, the third conductive line 414, and the second storage stack bar 416 in the first region 402 are arranged adjacent to each other.

[0074] Exemplarily, the first dielectric material can be filled in the space formed by removing the dummy structure in the second region 404 to form a first dielectric material layer that fills the above-mentioned space in the second region 404 and covers the mask layer 424 in the first region 402; the first dielectric material layer is planarized to expose the surface of the mask layer 424 in the first region 402, and the remaining first dielectric material layer forms the second dielectric sublayer 450.

[0075] Here, the materials of the first dielectric sub-layer 430 and the second dielectric sub-layer 450 may be the same. The first dielectric sub-layer 430 and the second dielectric sub-layer 450 may include, but are not limited to, silicon oxide materials.

[0076] Here, the process of forming the first dielectric sublayer 430 and the second dielectric sublayer 450 may include but is not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0077] refer to Fig.8DAs shown, a fourth conductive line 432 extending along the direction D1 is formed in the first region 402, and the second memory stack strip 416 is etched to form a second memory cell 434 (eg, Fig.8D The second storage units 434 are arranged at intervals along the D1 direction and the D2 direction.

[0078] Exemplarily, forming a storage structure may also include the following steps: forming a fourth conductive material layer in the first region 402 and the second region 404; etching the fourth conductive material layer and the second storage stack bar 416 along the D3 direction to form a fourth groove extending along the D1 direction in the first region 402 and removing the fourth conductive material layer in the second region 404, the second storage stack bar after etching in the first region 402 forms a second storage unit 434, and the fourth conductive material layer after etching in the first region 402 forms a fourth conductive line 432; filling the fourth groove with a fourth isolation material to form a fourth isolation layer.

[0079] Here, the second memory cells 434 may also be referred to as top memory cells, and the top memory cells are arranged at intervals along the D1 direction and the D2 direction. The fourth conductive line 432 may also be referred to as a top bit line.

[0080] Here, the material of the fourth conductive line 432 may include a conductive material, such as a metal material. In some embodiments, the fourth conductive line 432 may include metal tungsten.

[0081] refer to Fig.8D As shown, the storage structure 436 (such as Fig.8D The present invention further includes a first conductive line 408, a first storage unit 410, a second conductive line 412, a third conductive line 414, a second storage unit 434 and a fourth conductive line 432 which are sequentially stacked along the D3 direction; wherein the first storage unit 410 and the second storage unit 434 are arranged at intervals along the D1 direction and the D2 direction, the first conductive line 408 and the fourth conductive line 432 extend along the D1 direction, and the second conductive line 412 and the third conductive line 414 extend along the D2 direction.

[0082] refer to Fig.8D As shown, in some embodiments, step S720 includes: forming a second dielectric layer 438 in the first region 402 and the second region 404. Here, the storage structure 436 in the first region 402 is disposed between the substrate 406 and the second dielectric layer 438, and the first dielectric layer 452 (including the first dielectric sublayer 430 and the second dielectric sublayer 450) in the second region 404 is disposed between the substrate 406 and the second dielectric layer 438.

[0083] Here, the second dielectric layer 438 may include but is not limited to silicon oxide material.

[0084] Here, the process of forming the second dielectric layer 438 may include but is not limited to CVD, PVD, ALD or any combination thereof.

[0085] refer to Fig.8D As shown, the second dielectric layer 438 and the first dielectric layer 452 are etched along the D3 direction in the second region 404 to form a first etching hole exposing the first conductive layer 462 and a second etching hole exposing the second conductive layer 464; the first etching hole and the second etching hole in the second region 404 are filled with conductive materials to respectively form a first conductive column 440 and a second conductive column 442. Here, the first conductive column 440 and the second conductive column 442 both extend along the D3 direction, the first conductive column 440 is in a floating state, and can be used as a first detection unit 446; the second conductive column 442 is coupled to the ground voltage, and can be used as a second detection unit 448.

[0086] In some embodiments, the first region 402 is a storage array region, and the second region 404 is a dummy region. Here, the first region 402 can be used to form a storage structure 436, and the second region 404 can be used to form a dummy structure first and then used to form a detection structure.

[0087] The present disclosure provides a semiconductor structure, referring to Fig.8D As shown, the semiconductor structure 400 includes: a first region 402 disposed on a substrate 406 and a second region 404 disposed on one side of the first region 402; a storage structure 436 is disposed in the first region 402; a detection structure 444 is disposed in the second region 404 and is spaced from the storage structure 436 and perpendicular to the substrate 406, and the detection structure 444 includes: a first detection unit 446 in a floating state, and a second detection unit 448 coupled to a ground voltage.

[0088] In some embodiments, the semiconductor structure 400 also includes: a first conductive layer 462, a first detection unit 446 (i.e., a first conductive column 440) is coupled to the first conductive layer 462, and the first conductive layer 462 is not coupled to the substrate 406; a second conductive layer 464, a second detection unit 448 (i.e., a second conductive column 442) is coupled to the second conductive layer 464; a first conductive block 468, one end of the first conductive block 468 is coupled to the second conductive layer 464, and the other end of the first conductive block 468 is coupled to the third conductive layer 466; a second conductive block 470, one end of the second conductive block 470 is coupled to the third conductive layer 466, and the other end of the second conductive block 470 is coupled to the substrate 406.

[0089] Here, the first detection unit 446 is coupled to the first conductive layer 462 , which is not coupled to the substrate 406 ; the second detection unit 448 is coupled to the substrate 406 through the second conductive layer 464 , the first conductive block 468 , the third conductive layer 466 and the second conductive block 470 .

[0090] In some embodiments, the semiconductor structure 400 also includes: a first dielectric layer 452 disposed in the second region 404 and adjacent to the storage structure 436; a second dielectric layer 438 disposed in the first region 402 and the second region 404, the storage structure 436 in the first region 402 is disposed between the substrate 406 and the second dielectric layer 438, and the first dielectric layer 452 in the second region 404 is disposed between the substrate 406 and the second dielectric layer 438.

[0091] In some embodiments, the semiconductor structure 400 also includes: a first conductive column 440 and a second conductive column 442 disposed in the first dielectric layer 452 and the second dielectric layer 438 and extending along the D3 direction, the first conductive column 440 is in a floating state, and the second conductive column 442 is coupled to the substrate 406; wherein the first conductive column 440 serves as a first detection unit 446, and the second conductive column 442 serves as a second detection unit 448.

[0092] In some embodiments, the structure of the first detection unit 446 and the structure of the second detection unit 448 are set the same, the minimum distance between the first detection unit 446 (or, the second detection unit 448) and the substrate 406 is less than or equal to the minimum distance between the storage structure 436 and the substrate 406, and the maximum distance between the first detection unit 446 (or, the second detection unit 448) and the substrate 406 is greater than or equal to the maximum distance between the storage structure 436 and the substrate 406.

[0093] Here, the first detection unit 446 and the second detection unit 448 have the same structure, including the first detection unit 446 and the second detection unit 448 having the same manufacturing process, the same size, and the same manufacturing material. The first detection unit 446 may include a first end and a second end opposite to each other along the D3 direction, the first end of the first detection unit 446 is coupled to the top conductive layer 472, and the second end of the first detection unit 446 is coupled to the first conductive layer 462. Among them, the minimum distance between the first detection unit 446 and the substrate 406 is the distance between the second end of the first detection unit 446 and the substrate 406, and the maximum distance between the first detection unit 446 and the substrate 406 is the distance between the first end of the first detection unit 446 and the substrate 406. The first detection unit extends along the D3 direction and passes through the area where the virtual second conductive line and the virtual third conductive line were previously formed. Similarly, the second detection unit 448 extends along the D3 direction and passes through the area where the virtual second conductive line and the virtual third conductive line were previously formed.

[0094] In some embodiments, the semiconductor structure 400 further includes a conductive block (eg, a first conductive block 468 and a second conductive block 470 ) disposed between the substrate 406 and the second detection unit 448 , and the second detection unit 448 is connected to the substrate 406 through the conductive block and thus coupled to the ground voltage. Fig.8D The first conductive block 468 and the second conductive block 470 are illustrated for exemplary purposes only, and the present disclosure does not specifically limit the specific number of conductive layers and conductive blocks, as long as the second detection unit 448 can be coupled to the substrate 406 through the conductive layers and the conductive blocks.

[0095] In some embodiments, the semiconductor structure 400 also includes: a top conductive layer 472 disposed on the side of the storage structure 436 away from the substrate 406, and the second detection unit 448 includes a first end and a second end opposite to each other along the D3 direction, the first end is coupled to the top conductive layer 472, and the second end is coupled to the conductive block.

[0096] In addition, it should be noted that the reference Fig.8D As shown, the first conductive line (i.e., the bottom bit line) can be coupled to the fourth conductive layer through the bottom contact structure (Bottom Contact, BCT), and the size of the bottom contact structure along the D3 direction is the distance between the first conductive line and the fourth conductive layer. The second conductive line (i.e., the bottom word line) and the third conductive line (i.e., the top word line) can be coupled to the fifth conductive layer through the word line contact structure (Word Line Contact, WLCT) and the bottom contact structure in turn, and the size of the word line contact structure along the D3 direction is the distance between the second conductive line and the bottom contact structure. The fourth conductive line (i.e., the top bit line) can be coupled to the sixth conductive layer through the top contact structure (Top Contact, TCT), the word line contact structure and the bottom contact structure in turn. Among them, the fourth conductive layer, the fifth conductive layer and the sixth conductive layer can be metal layers located at the same layer. The peripheral circuit can apply electrical signals to the different conductive layers to which it is coupled through the pad, and then apply electrical signals to the bottom bit line, the word line and the top bit line. Fig.8D It is also illustrated that the fourth conductive layer, the fifth conductive layer, the sixth conductive layer and the first conductive layer 462 and the second conductive layer 464 are metal layers of the same layer.

[0097] It should be noted that the first conductive material layer, the second conductive material layer, the third conductive material layer and the fourth conductive material layer are used to form the first conductive wire, the second conductive wire, the third conductive wire and the fourth conductive wire, respectively. The first conductive material layer, the second conductive material layer, the third conductive material layer and the fourth conductive material layer here are different from the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, the fifth conductive layer and the sixth conductive layer used as the interconnect layer.

[0098] refer to 9A to 9E , 9A to 9E The cross-sectional views of the semiconductor structures during the manufacturing process are provided for other embodiments. Figure 7 as well as 9A to 9E , describing in detail the manufacturing methods of the semiconductor structures provided in other embodiments.

[0099] refer to Fig.9A As shown, in some embodiments, a first conductive line 508, a first storage unit 510, a second conductive line 512, a third conductive line 514, and a second storage stack bar 516 stacked along the D3 direction are provided in the first region 502, and a first dielectric sublayer 530, a virtual second conductive line 518, a virtual third conductive line 520, and a virtual second storage stack bar 522 stacked along the D3 direction are provided in the second region 504; wherein the first storage unit 510 is arranged at intervals along the D1 direction and the D2 direction, the first conductive line 508 extends along the D1 direction, and the second conductive line 512, the third conductive line 514, the second storage stack bar 516, the virtual second conductive line 518, the virtual third conductive line 520, and the virtual second storage stack bar 522 all extend along the D2 direction.

[0100] Still refer to Fig.9A As shown, the semiconductor structure further includes: a first conductive layer 562, a second conductive layer 564 and a third conductive layer 566; wherein the first conductive layer 562 is not coupled to the substrate 506; the second conductive layer 564 is coupled to the third conductive layer 566 through the first conductive block 568, and the third conductive layer 566 is coupled to the substrate 506 through the second conductive block 570. The first conductive layer 562 and the second conductive layer 564 can be metal layers located at the same layer.

[0101] Still refer to Fig.9A As shown, a mask layer 524 is further provided in the first region 502 and the second region 504, and the mask layer 524 includes a first sublayer 526 and a second sublayer 528. Here, the dummy second conductive line 518, the dummy third conductive line 520 and the dummy second storage stack bar 522 in the second region 504 are all dummy structures.

[0102] refer to Fig. 9B As shown, the dummy second storage stack bar 522, the dummy third conductive line 520 and the dummy second conductive line 518 in the second region 504 are etched away. Due to the large etching depth, during the process of etching away the dummy structure in the second region 504, conductive material residues (such as Fig. 9B and Fig. 9C (shown in the dotted circle).

[0103] refer to Fig. 9CAs shown, in some embodiments, a second dielectric sublayer 550 is formed in the second region 504, and the first dielectric sublayer 530 and the second dielectric sublayer 550 together form a first dielectric layer 552. Here, the first dielectric sublayer 530 in the second region 504 and the first conductive line 508 and the first storage unit 510 in the first region 502 are disposed adjacently, and the second dielectric sublayer 550 in the second region and the second conductive line 512, the third conductive line 514 and the second storage stack strip 516 in the first region 502 are disposed adjacently.

[0104] refer to Fig.9D As shown, the first dielectric layer 552 is etched along the D3 direction in the second region 504 to form a first etched sub-hole exposing the first conductive layer 562 and a second etched sub-hole exposing the second conductive layer 564; the first etched sub-hole and the second etched sub-hole in the second region 504 are filled with conductive materials to respectively form a third sub-conductive pillar 558 and a first sub-conductive pillar 554. Here, the third sub-conductive pillar 558 and the first sub-conductive pillar 554 both extend along the D3 direction, and the third sub-conductive pillar 558 is in a floating state; the first sub-conductive pillar 554 is coupled to the ground voltage.

[0105] refer to Fig.9E As shown, in some embodiments, the manufacturing method further includes: forming a fourth conductive line 532 extending along the direction D1 in the first region 502, and etching the second memory stack strip to form a second memory cell 534 (such as Fig.9E The second storage units 534 are arranged at intervals along the D1 direction and the D2 direction.

[0106] In other embodiments, while depositing the fourth conductive material layer for forming the fourth conductive line 532 in the first region 502, a conductive material may be deposited in the first etched sub-hole and the second etched sub-hole in the second region 504 to respectively form the third sub-conductive pillar 558 and the first sub-conductive pillar 554. Here, the fourth conductive line 532 may also be referred to as a top electrode, and the third sub-conductive pillar 558, the first sub-conductive pillar 554, and the top electrode may be formed by the same process, that is, the third sub-unit 578, the first sub-unit 574, and the top electrode may be formed by the same process.

[0107] Here, the storage structure 536 may include: a first conductive line 508, a first storage unit 510, a second conductive line 512, a third conductive line 514, a second storage unit 534 and a fourth conductive line 532 stacked in sequence along the D3 direction; wherein the first storage unit 510 and the second storage unit 534 are arranged at intervals along the D1 direction and the D2 direction, the first conductive line 508 and the fourth conductive line 532 extend along the D1 direction, and the second conductive line 512 and the third conductive line 514 extend along the D2 direction.

[0108] Still refer to Fig.9E As shown, a second dielectric layer 538 is formed in the first region 502 and the second region 504. The second dielectric layer 538 is etched in the second region 504 along the D3 direction to form a third etched sub-hole exposing the third sub-conductive pillar 558 and a fourth etched sub-hole exposing the first sub-conductive pillar 554; the third etched sub-hole and the fourth etched sub-hole in the second region 504 are filled with conductive material to form a fourth sub-conductive pillar 560 and a second sub-conductive pillar 556, respectively. Here, the third sub-conductive pillar 558 and the fourth sub-conductive pillar 560 are connected to each other to form a first conductive pillar 540, and the first conductive pillar 540 serves as a first detection unit 546; the first sub-conductive pillar 554 and the second sub-conductive pillar 556 are connected to each other to form a second conductive pillar 542, and the second conductive pillar 542 serves as a second detection unit 548.

[0109] In some embodiments, the first region 502 is a storage array region, and the second region 504 is a dummy region. Here, the first region 502 can be used to form a storage structure 536, and the second region 504 can be used to form a dummy structure first, and then remove the dummy structure, and the second region 504 is used to form a detection structure.

[0110] The present disclosure provides a semiconductor structure, such as Fig.9E As shown, the semiconductor structure 500 includes: a first region 502 disposed on a substrate 506 and a second region 504 disposed on one side of the first region 502; a storage structure 536 is disposed in the first region 502; a detection structure 544 is disposed in the second region 504 and is spaced from the storage structure 536 and is perpendicular to the substrate 506, including: a first detection unit 546 in a floating state, and a second detection unit 548 coupled to a ground voltage.

[0111] In some embodiments, the semiconductor structure 500 also includes: a first conductive layer 562, a first detection unit 546 (i.e., a first conductive column 540) is coupled to the first conductive layer 562, and the first conductive layer 562 is not coupled to the substrate 506; a second conductive layer 564, a second detection unit 548 (i.e., a second conductive column 542) is coupled to the second conductive layer 564; a first conductive block 568, one end of the first conductive block 568 is coupled to the second conductive layer 564, and the other end of the first conductive block 568 is coupled to the third conductive layer 566; a second conductive block 570, one end of the second conductive block 570 is coupled to the third conductive layer 566, and the other end of the second conductive block 570 is coupled to the substrate 506.

[0112] Here, the first detection unit 546 is coupled to the first conductive layer 562 , which is not coupled to the substrate 506 ; the second detection unit 548 is coupled to the substrate 506 through the second conductive layer 564 , the first conductive block 568 , the third conductive layer 566 and the second conductive block 570 .

[0113] In some embodiments, the semiconductor structure 500 also includes: a first dielectric layer 552 disposed in the second region 504 and adjacent to the storage structure 536; a second dielectric layer 538 disposed in the first region 502 and the second region 504, the storage structure 536 in the first region 502 is disposed between the substrate 506 and the second dielectric layer 538, and the first dielectric layer 552 in the second region 504 is disposed between the substrate 506 and the second dielectric layer 538.

[0114] In some embodiments, the semiconductor structure 500 further includes: a third sub-conductive column 558 and a first sub-conductive column 554 disposed in the first dielectric layer 552 and extending along the D3 direction, the third sub-conductive column 558 being in a floating state, and the first sub-conductive column 554 being coupled to the substrate 506; a fourth sub-conductive column 560 and a second sub-conductive column 556 disposed in the second dielectric layer 538 and extending along the D3 direction, the axes of the third sub-conductive column 558 and the fourth sub-conductive column 560 being coincident and interconnected to form a first conductive column 540 together, the axes of the first sub-conductive column 554 and the second sub-conductive column 556 being coincident and interconnected to form a second conductive column 542 together; wherein the first conductive column 540 serves as a first detection unit 546, and the second conductive column 542 serves as a second detection unit 548.

[0115] In some embodiments, the structure of the first detection unit 546 and the structure of the second detection unit 548 are set the same, the minimum distance between the first detection unit 546 (or, the second detection unit 548) and the substrate 506 is less than or equal to the minimum distance between the storage structure 536 and the substrate 506, and the maximum distance between the first detection unit 546 (or, the second detection unit 548) and the substrate 506 is greater than or equal to the maximum distance between the storage structure 536 and the substrate 506.

[0116] Here, the first detection unit 546 and the second detection unit 548 have the same structure, including the first detection unit 546 and the second detection unit 548 having the same manufacturing process, the same size, and the same manufacturing material. The first detection unit 546 may include a first end and a second end opposite to each other along the D3 direction, the first end of the first detection unit 546 is coupled to the top conductive layer 572, and the second end of the first detection unit 546 is coupled to the first conductive layer 562. Among them, the minimum distance between the first detection unit 546 and the substrate 506 is the distance between the second end of the first detection unit 546 and the substrate 506, and the maximum distance between the first detection unit 546 and the substrate 506 is the distance between the first end of the first detection unit 546 and the substrate 506. The first detection unit 546 extends along the D3 direction and passes through the area where the virtual second conductive line and the virtual third conductive line were previously formed. Similarly, the second detection unit 548 extends along the D3 direction and passes through the area where the virtual second conductive line and the virtual third conductive line were previously formed.

[0117] In some embodiments, the semiconductor structure 500 further includes a conductive block (ie, a first conductive block 568 and a second conductive block 570 ) disposed between the substrate 506 and the second detection unit 548 , and the second detection unit 548 is connected to the substrate 506 through the conductive block and thus coupled to the ground voltage. Fig.9E The first conductive block 568 and the second conductive block 570 are illustrated for exemplary purposes only, and the present disclosure does not specifically limit the specific number of conductive layers and conductive blocks, as long as the second detection unit 548 can be coupled to the substrate 506 through the conductive layers and the conductive blocks.

[0118] In some embodiments, the semiconductor structure 500 also includes: a top conductive layer 572 disposed on the side of the storage structure 536 away from the substrate 506, the second detection unit 548 includes a first end and a second end opposite to each other along the direction D3, the first end is coupled to the top conductive layer 572, and the second end is coupled to the conductive block.

[0119] In some embodiments, the second detection unit 548 (i.e., the second conductive pillar 542) includes a first sub-unit 574 (i.e., the first sub-conductive pillar 554) and a second sub-unit 576 (i.e., the second sub-conductive pillar 556), wherein the first sub-unit 574 is disposed between the substrate 506 and the second sub-unit 576. The first sub-unit 574 includes a second end and a third end opposite to each other along the direction D3, and the second sub-unit 576 includes a first end and a fourth end opposite to each other along the direction D3, wherein the first end is coupled to the top conductive layer 572, the second end is coupled to the second conductive layer 564, and the third end is coupled to the fourth end.

[0120] In some embodiments, the first detection unit 546 (i.e., the first conductive pillar 540) includes a third sub-unit 578 (i.e., the third sub-conductive pillar 558) and a fourth sub-unit 580 (i.e., the fourth sub-conductive pillar 560), and the third sub-unit 578 is disposed between the substrate 506 and the fourth sub-unit 580. The third sub-unit 578 includes a second end and a third end opposite to each other along the direction D3, and the fourth sub-unit 580 includes a first end and a fourth end opposite to each other along the direction D3, the first end is coupled to the top conductive layer 572, the second end is coupled to the first conductive layer 562, and the third end is coupled to the fourth end.

[0121] In the embodiment of the present disclosure, a first detection unit in a floating state is additionally provided, so that a detection structure is formed by the first detection unit in a floating state and a second detection unit coupled to a ground voltage.

[0122] FIG. 8A to FIG. 8D In the manufacturing process of the semiconductor structure provided in some of the illustrated embodiments, the first conductive pillar is used as the first detection unit, and the second conductive pillar is used as the second detection unit. In other words, in the process of forming the second conductive pillar, the first conductive pillar in a floating state is formed at the same time, and the electron beam detection can be performed after the first conductive pillar and the second conductive pillar are formed without modifying the process flow.

[0123] 9A to 9E In the manufacturing process of the semiconductor structure provided by some other embodiments shown, the process of the second conductive column (or the first conductive column) is performed twice, the process flow of forming the second conductive column is divided into forming the first sub-conductive column (i.e., the third sub-conductive column) and the second sub-conductive column (i.e., the fourth sub-conductive column), and the process flow of forming the second conductive column is divided into forming the first sub-conductive column and the second sub-conductive column. In this way, electron beam detection can be performed after the first sub-conductive column and the third sub-conductive column are formed, and the detection is more timely.

[0124] refer to Fig.10 , Fig.10 The following is a flow chart of a method for detecting a semiconductor structure provided by an embodiment of the present disclosure. Fig.10 As shown, an embodiment of the present disclosure provides a method for detecting a semiconductor structure, and the detection method is applied to the semiconductor structure in the above technical solution; the detection method includes:

[0125] Step S1010: performing electron beam detection on the detection structure of the semiconductor structure to obtain a detection image; the detection image includes a first sub-image obtained after the first detection unit is detected and a second sub-image obtained after the second detection unit is detected;

[0126] Step S1020: determining that the semiconductor structure has defects according to the same brightness of the first sub-image and the second sub-image;

[0127] Step S1030: Determine that the semiconductor structure has no defects according to the different brightness between the first sub-image and the second sub-image.

[0128] Here, during the electron beam inspection, the floating structure is displayed as a dark field image in the inspection image. If the floating structure is displayed as a dark field image in the inspection image, it is determined that the floating structure has no defects; if the floating structure is displayed as a bright field image in the inspection image, it is determined that the floating structure has a short circuit defect.

[0129] Here, during the electron beam inspection, the grounding structure is displayed as a bright field image in the inspection image. If the grounding structure is displayed as a bright field image in the inspection image, it is determined that the grounding structure has no defects; if the grounding structure is displayed as a dark field image in the inspection image, it is determined that the grounding structure has a circuit breaker defect.

[0130] In the embodiment of the present disclosure, the first detection unit in the detection structure is in a floating state, belonging to a floating structure, and the first sub-image in the detection image is displayed as a dark field image; the second detection unit in the detection structure is coupled to a ground voltage, belonging to a grounded structure, and the second sub-image in the detection image is displayed as a bright field image. According to the first sub-image and the second sub-image, the defect status of the semiconductor structure can be determined.

[0131] In some embodiments, step S1020 includes: determining that the first detection unit and the second detection unit have a short circuit defect according to the first sub-image and the second sub-image both having a first brightness value; determining that the first detection unit and the second detection unit have an open circuit defect according to the first sub-image and the second sub-image both having a second brightness value; wherein the first brightness value is greater than the second brightness value. Here, if the first sub-image and the second sub-image are both bright field images, it means that the first detection unit and the second detection unit are both grounded structures, and then it is determined that the first detection unit and the second detection unit have a short circuit defect; if the first sub-image and the second sub-image are both dark field images, it means that the first detection unit and the second detection unit are both floating structures, and then it is determined that the first detection unit and the second detection unit have an open circuit defect.

[0132] Further analysis shows that if there is a short circuit defect between the first detection unit and the second detection unit, there may be residual conductive material in the process of removing the dummy structure in the second region, and the residual conductive material causes a short circuit connection between the first detection unit and the second detection unit. If there is an open circuit defect between the first detection unit and the second detection unit, there may be an insufficient etching problem in the process of forming the first detection unit and the second detection unit, and the insufficient etching problem causes the first detection unit and the second detection unit to have an open circuit defect.

[0133] In some embodiments, step S1030 includes: determining that both the first detection unit and the second detection unit do not have defects according to the first sub-image having the second brightness value and the second sub-image having the first brightness value; wherein the first brightness value is greater than the second brightness value. Here, the first sub-image is displayed as a dark field image, indicating that the first detection unit is a floating structure; the second sub-image is displayed as a bright field image, indicating that the second detection unit is a grounded structure, and then determining that both the first detection unit and the second detection unit do not have defects.

[0134] refer to Fig.11 , Fig.11 Schematic diagram of the detection image under different conditions. Fig.11 As shown in Figure (a), for two ground structures without defects, after electron beam testing, the test image shows two bright field images. Fig.11 As shown in Figure (b), for the first detection unit and the second detection unit without defects, the first sub-image is displayed as a dark field image, and the second sub-image is displayed as a bright field image. Fig.11 As shown in Figure (c), for the first detection unit and the second detection unit with short circuit defects, the first sub-image and the second sub-image are both displayed as bright field images. Therefore, after the electron beam test, if the test image is as follows Fig.11 As shown in Figure (c), it is determined that there is a short circuit defect between the first detection unit and the second detection unit, and further it can be determined that there is residual conductive material in the process of removing the dummy structure in the second area. Fig.11 As shown in Figure (d), for the first detection unit and the second detection unit with disconnection defects, the first sub-image and the second sub-image are both displayed as dark field images. Therefore, after the electron beam test, if the test image is as follows Fig.11 As shown in FIG. 5( d ), it is determined that the first detection unit and the second detection unit have short circuit defects, and further it can be determined that insufficient etching exists in the process of forming the first detection unit and the second detection unit.

[0135] The present disclosure provides a semiconductor structure and a detection method thereof. In the present disclosure, the detection structure disposed in the second region includes a first detection unit in a floating state and a second detection unit coupled to a ground voltage; an electron beam detection is performed on the detection structure to obtain a detection image; based on the first sub-image and the second sub-image in the detection image, it can be determined whether the semiconductor structure has defects, thereby determining the defect status between the first detection unit and the second detection unit, and further determining whether conductive material residues are generated in the process of removing the dummy structure in the second region.

[0136] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0137] The above description is only a preferred embodiment of the present disclosure, and does not limit the patent scope of the present disclosure. All equivalent structural changes made by using the contents of the present disclosure and the drawings under the inventive concept of the present disclosure, or directly / indirectly applied in other related technical fields are included in the patent protection scope of the present disclosure.

Claims

1. A semiconductor structure, characterized in that: The semiconductor structure comprises: a first region disposed on a substrate and a second region disposed on one side of the first region; A storage structure is provided in the first area; A detection structure is disposed in the second region and is spaced apart from the storage structure and perpendicular to the substrate. The detection structure includes a first detection unit in a floating state and a second detection unit coupled to a ground voltage.

2. The semiconductor structure according to claim 1, characterized in that: The structure of the first detection unit is the same as the structure of the second detection unit, the minimum distance between the first detection unit and the substrate is less than or equal to the minimum distance between the storage structure and the substrate, and the maximum distance between the first detection unit and the substrate is greater than or equal to the maximum distance between the storage structure and the substrate.

3. The semiconductor structure according to claim 2, characterized in that: The semiconductor structure further includes a conductive block disposed between the substrate and the second detection unit, and the second detection unit is connected to the substrate through the conductive block so as to be coupled to a ground voltage.

4. The semiconductor structure according to claim 3, characterized in that: The semiconductor structure also includes: a conductive layer arranged on the side of the storage structure away from the substrate, the second detection unit includes a first end and a second end opposite to each other in a direction perpendicular to the substrate, the first end is coupled to the conductive layer, and the second end is coupled to the conductive block.

5. The semiconductor structure according to any one of claims 2 to 4, characterized in that: The storage structure includes a top electrode away from the substrate side, the second detection unit includes a first subunit, and the first subunit and the top electrode are prepared by the same process.

6. The semiconductor structure according to claim 5, characterized in that: The first subunit includes a second end and a third end opposite to each other in a direction perpendicular to the substrate, and the second end is coupled to the conductive block.

7. The semiconductor structure according to claim 6, characterized in that: The second detection unit further includes a second subunit, the second subunit includes a first end and a fourth end opposite to each other in a direction perpendicular to the substrate, the first end is coupled to the conductive layer, and the fourth end is coupled to the third end.

8. The semiconductor structure according to claim 1, characterized in that: The first area is a storage array area, and the second area is a dummy area.

9. A method for detecting a semiconductor structure, characterized in that: The detection method is applied to the semiconductor structure according to any one of claims 1 to 8; the detection method comprises: Performing electron beam detection on the detection structure of the semiconductor structure to obtain a detection image; the detection image includes a first sub-image obtained after the first detection unit is detected and a second sub-image obtained after the second detection unit is detected; Determining that the semiconductor structure has a defect according to the same brightness of the first sub-image and the second sub-image; According to the difference in brightness between the first sub-image and the second sub-image, it is determined that the semiconductor structure has no defects.

10. The detection method according to claim 9, characterized in that: The step of determining that the semiconductor structure has a defect according to the brightness of the first sub-image and the brightness of the second sub-image being the same includes: According to the first sub-image and the second sub-image both having the first brightness value, determining that the first detection unit and the second detection unit have a short circuit defect; According to the first sub-image and the second sub-image both having the second brightness value, it is determined that the first detection unit and the second detection unit have open circuit defects; wherein the first brightness value is greater than the second brightness value.

Images