Negative pressure protection circuit

Abstract

The present invention provides a negative voltage protection circuit, which includes a voltage clamping module, which is arranged between the gate terminal and the drain terminal of an NMOS tube, and is used to clamp the voltage between the drain terminal and the source terminal of the NMOS tube to a protection threshold voltage when the NMOS tube is turned off, so that the voltage between the drain terminal and the source terminal of the NMOS tube can be clamped within a safe range, avoiding the problem that the NMOS tube is broken down due to excessive current between its source terminal and the drain terminal. In this process, the power supply voltage for the inductive load, the NMOS tube and the inductive load form a demagnetization path, so that the inductive load can be demagnetized faster. On this basis, since the protection threshold voltage of the voltage clamping module is negatively correlated with the temperature of the voltage clamping module, when the NMOS tube is overheated during demagnetization, the voltage between the drain terminal and the source terminal of the NMOS tube will decrease, so that the NMOS tube will not produce thermal failure during demagnetization.

Description

Technical Field

[0001] The invention relates to the field of electronic circuit design, and in particular to a negative voltage protection circuit. Background Art

[0002] A high-side switch chip is an intelligent power switch chip that integrates a high-voltage power tube, a driver, and a control. In the application scenario where the high-side switch chip drives an inductive load, when the power tube in the high-side switch chip changes from the on state to the off state, the power tube in the high-side switch chip will be broken down due to excessive current between the source terminal and the drain terminal, and even cause the chip latch to burn out.

[0003] Therefore, connecting a protection circuit to assist in demagnetizing the inductive load is a common method for protecting the power tube from breakdown. However, the demagnetization rate of the existing protection circuit is relatively slow. Summary of the invention

[0004] The present invention provides a negative voltage protection circuit to solve the problem of slow demagnetization rate of inductive load after a high-side switch chip is connected to the protection circuit.

[0005] The present invention provides a negative voltage protection circuit for protecting an NMOS tube in a high-side switch chip, wherein the NMOS tube is used to drive an inductive load. The negative voltage protection circuit comprises:

[0006] A voltage clamping module, wherein a first end of the voltage clamping module is coupled to the drain end of the NMOS tube, a second end of the voltage clamping module is coupled to the gate end of the NMOS tube, a voltage between the first end and the second end of the voltage clamping module is a protection threshold voltage, the protection threshold voltage is negatively correlated with the temperature of the voltage clamping module, and the voltage clamping module is used to clamp the voltage between the drain end and the source end of the NMOS tube to the protection threshold voltage.

[0007] Optionally, the voltage clamping module includes a first negative pressure detection unit and a second negative pressure detection unit, the first end of the first negative pressure detection unit serves as the first end of the voltage clamping module, the second end of the first negative pressure detection unit is connected to the first end of the second negative pressure detection unit, the second end of the second negative pressure detection unit serves as the second end of the voltage clamping module, the voltage between the first end and the second end of the first negative pressure detection unit is a first threshold voltage, and the first threshold voltage is negatively correlated with the temperature of the first negative pressure detection unit, the voltage between the first end and the second end of the second negative pressure detection unit is, and the second threshold voltage is positively correlated with the temperature of the second negative pressure detection unit.

[0008] Optionally, the second negative voltage detection unit includes several Zener diodes connected in series, the cathode of the first Zener diode serves as the first end of the second negative voltage detection unit, the anode of each Zener diode is connected to the cathode of the next Zener diode, and the anode of the last Zener diode serves as the second end of the second negative voltage detection unit.

[0009] Optionally, the voltage clamping module includes a first negative pressure detection module, the first end of the first negative pressure detection unit serves as the first end of the voltage clamping module, the second end of the first negative pressure detection unit serves as the second end of the voltage clamping module, the voltage between the first end and the second end of the first negative pressure detection unit is a first threshold voltage, and the first threshold voltage is negatively correlated with the temperature of the first negative pressure detection unit.

[0010] Optionally, the first negative pressure detection unit includes several diodes connected in series, the anode of the first diode serves as the first end of the first negative pressure detection unit, the cathode of each diode is connected to the anode of the next diode, and the cathode of the last diode serves as the second end of the first negative pressure detection module.

[0011] Optionally, the first negative voltage detection unit includes a PNP transistor, a first resistor and a second resistor, the emitter of the PNP transistor is connected to the first end of the first resistor to serve as the first end of the first negative voltage detection unit, the base of the PNP transistor is connected to the second end of the first resistor and the first end of the second resistor, and the collector of the PNP transistor is connected to the second end of the second resistor to serve as the second end of the first negative voltage detection unit;

[0012] The first threshold voltage Among them, V BE It is used to characterize the voltage between the base and the emitter of the PNP transistor, R1 is used to characterize the resistance value of the first resistor, and R2 is used to characterize the resistance value of the second resistor.

[0013] Optionally, the voltage between the base and the emitter of the PNP transistor is negatively correlated with the temperature of the first negative pressure detection unit.

[0014] Optionally, the first negative voltage detection unit includes a PMOS tube, a third resistor and a fourth resistor, the source terminal of the PMOS tube is connected to the first end of the third resistor to serve as the first end of the first negative voltage detection unit, the gate terminal of the PMOS tube is connected to the second end of the third resistor and the first end of the fourth resistor, and the drain terminal of the PMOS tube is connected to the second end of the fourth resistor to serve as the second end of the first negative voltage detection unit;

[0015] The first threshold voltage Among them, V GS It is used to characterize the voltage between the gate and the source of the PMOS tube, R3 is used to characterize the resistance value of the third resistor, and R4 is used to characterize the resistance value of the fourth resistor.

[0016] Optionally, the voltage between the gate and the source of the PMOS tube is negatively correlated with the temperature of the first negative pressure detection unit.

[0017] Optionally, the voltage between the source terminal and the drain terminal of the NMOS tube is less than the source-drain withstand voltage value of the NMOS tube, and the gate-drain withstand voltage value of the NMOS tube is used to characterize the maximum voltage value between the source terminal and the drain terminal of the NMOS tube.

[0018] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0019] In the negative voltage protection circuit provided by the technical solution of the present invention, the first end of the voltage clamping module is coupled to the drain end of the NMOS tube, the second end of the voltage clamping module is coupled to the gate end of the NMOS tube, and the voltage clamping module is used to clamp the voltage between the drain end and the source end of the NMOS tube to the protection threshold voltage when the NMOS tube is turned off. Therefore, when the NMOS tube is turned off and the voltage between the drain end and the source end of the NMOS tube is greater than the protection threshold voltage, the voltage clamping module starts to work, clamping the voltage between the drain end and the gate end of the NMOS tube at the protection threshold voltage, so that the gate end voltage of the NMOS tube is increased, thereby slowing down the turn-off speed of the NMOS tube, and then the voltage between the drain end and the source end of the NMOS tube can be clamped within a safe range, avoiding the problem of the NMOS tube being broken down due to excessive current between its source end and drain end. In this process, since the gate terminal voltage of the NMOS tube increases, the NMOS tube is not turned off at this time, so that the power supply voltage for the inductive load, the NMOS tube and the inductive load form a demagnetization path, so that the inductive load can be demagnetized faster. On this basis, since the protection threshold voltage of the voltage clamping module is negatively correlated with the temperature of the voltage clamping module, when the NMOS tube is overheated during demagnetization, the protection threshold voltage of the voltage clamping module will decrease, so that the voltage between the drain terminal and the source terminal of the NMOS tube will also decrease, so that the NMOS tube will not produce thermal failure during demagnetization.

[0020] Furthermore, the voltage clamping module includes a first negative pressure detection unit and a second negative pressure detection unit, the voltage across the first negative pressure detection unit as a first threshold voltage is negatively correlated with the temperature of the first negative pressure detection unit, and the voltage across the second negative pressure detection unit as a second threshold voltage is positively correlated with the temperature of the second negative pressure detection unit, so that by jointly adjusting the first negative pressure detection unit and the second negative pressure detection unit, the coefficient of variation between the protection threshold voltage and temperature of the voltage clamping module can be adjusted. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 The circuit frame of the negative voltage protection circuit provided by the embodiment of the present invention is Figure 1 ;

[0022] Figure 2 The circuit frame of the negative voltage protection circuit provided by the embodiment of the present invention is Figure 2 ;

[0023] Figure 3 The circuit frame of the negative voltage protection circuit provided by the embodiment of the present invention is Figure 3 ;

[0024] Figure 4 The circuit structure of the negative voltage protection circuit provided by the embodiment of the present invention is shown in FIG. Figure 1 ;

[0025] Figure 5 The circuit structure of the negative voltage protection circuit provided by the embodiment of the present invention is shown in FIG. Figure 2 ;

[0026] Figure 6 The circuit structure of the negative voltage protection circuit provided by the embodiment of the present invention is shown in FIG. Figure 3 ;

[0027] Figure 7 It is a working timing diagram of the negative voltage protection circuit provided by an embodiment of the present invention.

[0028] Reference numerals:

[0029] 1- Voltage clamp module;

[0030] 11-a first negative pressure detection unit;

[0031] 12- second negative pressure detection unit;

[0032] 2- Inductive load;

[0033] VIN-drive signal;

[0034] VCC-power supply voltage signal;

[0035] VOUT-NMOS tube source terminal voltage;

[0036] Q1-NMOS tube;

[0037] Q2-PMOS tube;

[0038] M1-PNP transistor;

[0039] R1-first resistor R1;

[0040] R2-second resistor R2;

[0041] R3-the third resistor R3;

[0042] R4-the fourth resistor R4;

[0043] I L -The current flowing through the inductive load. DETAILED DESCRIPTION

[0044] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the embodiments in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present invention. The terms "first", "second", "third", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0045] As described in the background art, in order to prevent the power transistor in the high-side switch chip from being broken down when the high-side switch chip drives an inductive load, the high-side switch chip is usually externally connected to a protection circuit.

[0046] Specifically, a common protection circuit solution currently is to connect a freewheeling diode in parallel at both ends of the inductive load. This method has a simple circuit, but requires an external circuit that consumes area. In addition, the speed at which the charge is discharged in this way is limited by the tube voltage of the freewheeling diode, so that the attenuation rate of the discharge current of the inductive load is limited. In addition, the protection circuit is affected by the reverse recovery characteristics of the freewheeling diode, so that the stability of the protection circuit is not high.

[0047] In view of this, the present invention creatively proposes a negative voltage protection circuit.

[0048] Figure 1 The circuit frame of the negative voltage protection circuit provided by the embodiment of the present invention is Figure 1 .

[0049] Please refer to Figure 1 An embodiment of the present invention provides a negative voltage protection circuit for protecting an NMOS transistor Q1 in a high-side switch chip, wherein the NMOS transistor Q1 is used to drive an inductive load 2. The negative voltage protection circuit includes:

[0050] A voltage clamping module 1, wherein a first end of the voltage clamping module 1 is coupled to a drain end of the NMOS tube Q1, and a second end of the voltage clamping module 1 is coupled to a gate end of the NMOS tube Q1. A voltage between the first end and the second end of the voltage clamping module 1 is a protection threshold voltage, and the protection threshold voltage is negatively correlated with a temperature of the voltage clamping module 1. The voltage clamping module 1 is used to clamp a voltage between a drain end and a source end of the NMOS tube Q1 to the protection threshold voltage.

[0051] Through the above technical means, the embodiment of the present invention can provide a negative voltage protection circuit that assists in the demagnetization of the inductive load 2 and has a fast demagnetization speed. The specific principle is as follows:

[0052] In the negative voltage protection circuit provided in the embodiment of the present invention, a voltage clamping module 1 is provided. When the NMOS tube Q1 is turned from the on state to the off state, due to the freewheeling characteristic of the inductive load 2, the source terminal voltage of the NMOS tube Q1 will be pulled into a negative voltage, so that the voltage between the drain terminal and the source terminal of the NMOS tube Q1 is too large. When the voltage between the drain terminal and the source terminal of the NMOS tube Q1 is greater than the protection threshold voltage of the voltage clamping module 1, the voltage clamping module 1 starts to work, clamping the voltage between the drain terminal and the gate terminal of the NMOS tube Q1 at the protection threshold voltage, so that the gate terminal voltage of the NMOS tube Q1 is increased, thereby slowing down the turn-off speed of the NMOS tube Q1, reducing the negative voltage generated by the source terminal of the NMOS tube Q1, and then the voltage between the drain terminal and the source terminal of the NMOS tube Q1 can be clamped within a safe range, avoiding the problem of the NMOS tube Q1 being broken down due to the excessive voltage between its source terminal and the drain terminal.

[0053] In this process, since the gate terminal voltage of the NMOS tube Q1 increases, the NMOS tube Q1 is not turned off at this time, so that the power supply voltage for the inductive load 2, the NMOS tube Q1 and the inductive load 2 form a demagnetization path, so that the inductive load 2 can be demagnetized faster.

[0054] On this basis, since the protection threshold voltage of the voltage clamping module 1 is negatively correlated with the temperature of the voltage clamping module 1, when the NMOS tube Q1 is overheated during demagnetization, the protection threshold voltage of the voltage clamping module 1 will decrease, so that the voltage between the drain terminal and the source terminal of the NMOS tube Q1 will also decrease, so that the NMOS tube Q1 will not produce thermal failure during demagnetization.

[0055] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0056] Figure 2 The circuit frame of the negative voltage protection circuit provided by the embodiment of the present invention is Figure 2 ; Figure 3 The circuit frame of the negative voltage protection circuit provided by the embodiment of the present invention is Figure 3 ; Figure 4 The circuit structure of the negative voltage protection circuit provided by the embodiment of the present invention is shown in FIG. Figure 1 ; Figure 5 The circuit structure of the negative voltage protection circuit provided by the embodiment of the present invention is shown in FIG. Figure 2 ; Figure 6 The circuit structure of the negative voltage protection circuit provided by the embodiment of the present invention is shown in FIG. Figure 3 ; Figure 7 It is a working timing diagram of the negative voltage protection circuit provided by an embodiment of the present invention.

[0057] As an example, please refer to Figure 3 The voltage clamping module 1 includes a first negative pressure detection unit 11 and a second negative pressure detection unit 12, the first end of the first negative pressure detection unit 11 serves as the first end of the voltage clamping module 1, the second end of the first negative pressure detection unit 11 is connected to the first end of the second negative pressure detection unit 12, the second end of the second negative pressure detection unit 12 serves as the second end of the voltage clamping module 1, the voltage between the first end and the second end of the first negative pressure detection unit 11 is a first threshold voltage, the first threshold voltage is negatively correlated with the temperature of the first negative pressure detection unit 11, the voltage between the first end and the second end of the second negative pressure detection unit 12 is, the second threshold voltage is positively correlated with the temperature of the second negative pressure detection unit 12.

[0058] Specifically, the protection threshold voltage is equal to the sum of the first threshold voltage and the second threshold voltage.

[0059] Among them, the first threshold voltage is negatively correlated with the temperature of the first negative pressure detection unit 11, and the second threshold voltage is positively correlated with the temperature of the second negative pressure detection unit 12, so that technicians in this field can adjust the coefficient of variation between the protection threshold voltage and temperature of the voltage clamping module 1 by jointly adjusting the first negative pressure detection unit 11 and the second negative pressure detection unit 12 according to actual conditions, thereby better avoiding thermal failure of the NMOS tube Q1.

[0060] In this embodiment, please refer to Figure 4 , Figure 5 or Figure 6 The second negative voltage detection unit 12 includes several Zener diodes connected in series, the cathode of the first Zener diode serves as the first end of the second negative voltage detection unit 12, the anode of each Zener diode is connected to the cathode of the next Zener diode, and the anode of the last Zener diode serves as the second end of the second negative voltage detection unit 12.

[0061] Specifically, the second threshold voltage is equal to the reverse breakdown voltage V of a plurality of Zener diodes in the second negative voltage detection unit 12. Z sum.

[0062] As another example, please refer to Figure 2 The negative pressure protection circuit includes a first negative pressure detection module, the first negative pressure detection unit 11, the first end of the first negative pressure detection unit 11 serves as the first end of the voltage clamping module 1, the second end of the first negative pressure detection unit 11 serves as the second end of the voltage clamping module 1, the voltage between the first end and the second end of the first negative pressure detection unit 11 is a first threshold voltage, and the first threshold voltage is negatively correlated with the temperature of the first negative pressure detection unit 11.

[0063] Specifically, the first threshold voltage is equal to the protection threshold voltage, and at this time, the protection threshold voltage is negatively correlated with the temperature of the first negative pressure detection unit 11.

[0064] As a first specific implementation method of this embodiment and the previous embodiment, please refer to Figure 4 The first negative pressure detection unit 11 includes several diodes connected in series, the anode of the first diode serves as the first end of the first negative pressure detection unit 11, the cathode of each diode is connected to the anode of the next diode, and the cathode of the last diode serves as the second end of the first negative pressure detection module.

[0065] In this embodiment, the first threshold voltage is equal to the sum of the conduction voltages of a plurality of diodes in the first negative pressure detection unit 11, and the conduction voltage V of each diode is DIt is negatively correlated with the temperature of each diode, so the first threshold voltage is negatively correlated with the temperature of the first negative pressure detection unit 11.

[0066] As a second specific implementation method of this embodiment and the previous embodiment, please refer to Figure 5 The first negative pressure detection unit 11 includes a PNP transistor M1, a first resistor R1 and a second resistor R2. The emitter of the PNP transistor M1 is connected to the first end of the first resistor R1 to serve as the first end of the first negative pressure detection unit 11. The base of the PNP transistor M1 is connected to the second end of the first resistor R1 and the first end of the second resistor R2. The collector of the PNP transistor M1 is connected to the second end of the second resistor R2 to serve as the second end of the first negative pressure detection unit 11.

[0067] In this embodiment, the first threshold voltage Among them, V BE It is used to characterize the voltage between the base and the emitter of the PNP transistor M1, R1 is used to characterize the resistance value of the first resistor, and R2 is used to characterize the resistance value of the second resistor.

[0068] In this embodiment, the voltage between the base and the emitter of the PNP transistor M1 is negatively correlated with the temperature of the first negative pressure detection unit 11 , so that the first threshold voltage is negatively correlated with the temperature of the first negative pressure detection unit 11 .

[0069] Please continue to refer to Figure 5 If the voltage clamping module 1 includes the first negative voltage detection unit 11 and the second negative voltage detection unit 12, and the first negative voltage detection unit 11 includes the PNP transistor M1, the first resistor R1 and the second resistor R2, and the second negative voltage detection unit 12 includes a plurality of Zener diodes connected in series, then the second negative voltage detection unit 12 can be used to avoid energy loss caused by current flowing through the first resistor R1 and the second resistor R2 when the NMOS tube Q1 is turned on.

[0070] As a third specific implementation method of this embodiment and the previous embodiment, please refer to Figure 6 The first negative voltage detection unit 11 includes a PMOS tube Q2, a third resistor R3 and a fourth resistor R4. The source terminal of the PMOS tube Q2 is connected to the first end of the third resistor R3 to serve as the first end of the first negative voltage detection unit 11. The gate terminal of the PMOS tube Q2 is connected to the second end of the third resistor R3 and the first end of the fourth resistor R4. The drain terminal of the PMOS tube Q2 is connected to the second end of the fourth resistor R4 to serve as the second end of the first negative voltage detection unit 11.

[0071] In this embodiment, the first threshold voltage Among them, V GS It is used to characterize the voltage between the gate and the source of the PMOS tube Q2, R3 is used to characterize the resistance value of the third resistor, and R4 is used to characterize the resistance value of the fourth resistor.

[0072] The voltage between the gate and the source of the PMOS tube Q2 is negatively correlated with the temperature of the first negative pressure detection unit 11 , so that the first threshold voltage is negatively correlated with the temperature of the first negative pressure detection unit 11 .

[0073] Please continue to refer to Figure 6 If the voltage clamping module 1 includes the first negative voltage detection unit 11 and the second negative voltage detection unit 12, and the first negative voltage detection unit 11 includes the PMOS tube Q2, the third resistor R3 and the fourth resistor R4, and the second negative voltage detection unit 12 includes a plurality of Zener diodes connected in series, then the second negative voltage detection unit 12 can be used to avoid energy loss caused by current flowing through the third resistor R3 and the fourth resistor R4 when the NMOS tube Q1 is turned on.

[0074] Here, please refer to the second and third embodiments, NMOS transistors and NPN transistors can also be used in the first negative pressure detection unit 11. Of course, those skilled in the art should be aware that there are many circuits and devices that are negatively correlated with temperature, and the present invention is not limited thereto.

[0075] The following Figure 1 Take the circuit diagram shown as an example, and combine Figure 7 , the working process of the negative pressure protection circuit provided by the embodiment of the present invention is described:

[0076] The gate terminal of the NMOS transistor Q1 is connected to the driving signal VIN, the drain terminal of the NMOS transistor Q1 is connected to the power supply voltage signal VCC, and the source terminal of the NMOS transistor Q1 is connected to the inductive load 2 .

[0077] 0-t 0 When the driving signal VIN connected to the gate terminal of the NMOS tube Q1 is at a high level, the NMOS tube Q1 is turned on, and the power supply voltage VCC is connected to the inductive load 2 through the NMOS tube Q1. The inductive load 2 has an energy storage function, so that the current I flowing through the inductive load 2 L At this time, since the NMOS tube Q1 is turned on, the voltage between the drain terminal and the source terminal of the NMOS tube Q1 is constant, so the source terminal voltage VOUT of the NMOS tube Q1 is constant.

[0078] t 0 When the driving signal VIN connected to the gate terminal of the NMOS tube Q1 changes from a high level to a low level, the NMOS tube Q1 is disconnected, and the source terminal voltage VOUT of the NMOS tube Q1 will be pulled to a negative voltage due to the freewheeling characteristics of the inductive load 2. However, when the voltage between the drain terminal and the source terminal of the NMOS tube Q1 is greater than the protection threshold voltage, the voltage clamping module 1 starts to work, clamping the voltage between the drain terminal and the gate terminal of the NMOS tube Q1 at the protection threshold voltage, so that the gate terminal voltage of the NMOS tube Q1 is increased, thereby slowing down the turn-off speed of the NMOS tube Q1, and then the voltage between the drain terminal and the source terminal of the NMOS tube Q1 can be clamped within a safe range, avoiding the problem of the NMOS tube Q1 being broken down due to excessive current between its source terminal and drain terminal.

[0079] t 0 -t 1 When the voltage clamp module 1 increases the gate voltage, the NMOS tube Q1 is not turned off at this time, so the power supply voltage VCC, the NMOS tube Q1 and the inductive load 2 form a demagnetization path, so that the inductive load 2 can be demagnetized faster, thereby making the current I flowing through the inductive load 2 L On this basis, since the protection threshold voltage of the voltage clamping module 1 is negatively correlated with the temperature of the voltage clamping module 1, when the NMOS tube Q1 is overheated during demagnetization, the protection threshold voltage of the voltage clamping module 1 will decrease, so that the voltage between the drain terminal and the source terminal of the NMOS tube Q1 will also decrease, so that the NMOS tube Q1 will not produce thermal failure during demagnetization.

[0080] t 1 , the current flowing through the inductive load 2 decreases to 0, indicating that the demagnetization of the inductive load 2 is completed.

[0081] t 1 After the inductive load 2 is demagnetized, due to the current I L If the discharge is not complete, the source terminal voltage of the NMOS tube Q1 will oscillate slightly. After oscillating for a period of time, when the drain terminal and source terminal voltage of the NMOS tube Q1 are less than the protection threshold voltage, the voltage clamping module 1 stops working, and the gate terminal voltage of the NMOS tube Q1 returns to a low level, so that the NMOS tube Q1 is disconnected. Because the demagnetization of the inductive load 2 has ended at this time, the source terminal voltage of the NMOS tube Q1 is 0.

[0082] In summary, in the negative voltage protection circuit provided by the technical solution of the present invention, the voltage clamping module is arranged between the gate terminal and the drain terminal of the NMOS tube, and is used to clamp the voltage between the drain terminal and the source terminal of the NMOS tube to the protection threshold voltage when the NMOS tube is turned off, so that the voltage between the drain terminal and the source terminal of the NMOS tube can be clamped within a safe range, avoiding the problem of the NMOS tube being broken down due to excessive current between its source terminal and the drain terminal. In this process, the power supply voltage, the NMOS tube and the inductive load that supply power to the inductive load form a demagnetization path, so that the inductive load can be demagnetized faster. On this basis, since the protection threshold voltage of the voltage clamping module is negatively correlated with the temperature of the voltage clamping module, when the NMOS tube is overheated during demagnetization, the voltage between the drain terminal and the source terminal of the NMOS tube will decrease, so that the NMOS tube will not produce thermal failure during demagnetization.

[0083] Furthermore, the voltage clamping module includes a first negative pressure detection unit and a second negative pressure detection unit, the voltage across the first negative pressure detection unit as a first threshold voltage is negatively correlated with the temperature of the first negative pressure detection unit, and the voltage across the second negative pressure detection unit as a second threshold voltage is positively correlated with the temperature of the second negative pressure detection unit, so that by jointly adjusting the first negative pressure detection unit and the second negative pressure detection unit, the coefficient of variation between the protection threshold voltage and temperature of the voltage clamping module can be adjusted.

[0084] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A negative voltage protection circuit for protecting an NMOS tube in a high-side switch chip, wherein the NMOS tube is used to drive an inductive load, characterized in that: The negative voltage protection circuit comprises: A voltage clamping module, wherein a first end of the voltage clamping module is coupled to the drain end of the NMOS tube, a second end of the voltage clamping module is coupled to the gate end of the NMOS tube, a voltage between the first end and the second end of the voltage clamping module is a protection threshold voltage, the protection threshold voltage is negatively correlated with the temperature of the voltage clamping module, and the voltage clamping module is used to clamp the voltage between the drain end and the source end of the NMOS tube to the protection threshold voltage.

2. The negative voltage protection circuit according to claim 1, characterized in that: The voltage clamping module includes a first negative pressure detection unit and a second negative pressure detection unit, the first end of the first negative pressure detection unit serves as the first end of the voltage clamping module, the second end of the first negative pressure detection unit is connected to the first end of the second negative pressure detection unit, the second end of the second negative pressure detection unit serves as the second end of the voltage clamping module, the voltage between the first end and the second end of the first negative pressure detection unit is a first threshold voltage, the first threshold voltage is negatively correlated with the temperature of the first negative pressure detection unit, the voltage between the first end and the second end of the second negative pressure detection unit is, the second threshold voltage is positively correlated with the temperature of the second negative pressure detection unit.

3. The negative voltage protection circuit according to claim 2, characterized in that: The second negative voltage detection unit includes several Zener diodes connected in series, the cathode of the first Zener diode serves as the first end of the second negative voltage detection unit, the anode of each Zener diode is connected to the cathode of the next Zener diode, and the anode of the last Zener diode serves as the second end of the second negative voltage detection unit.

4. The negative voltage protection circuit according to claim 1, characterized in that: The voltage clamping module includes a first negative pressure detection unit, the first end of the first negative pressure detection unit serves as the first end of the voltage clamping module, the second end of the first negative pressure detection unit serves as the second end of the voltage clamping module, the voltage between the first end and the second end of the first negative pressure detection unit is a first threshold voltage, and the first threshold voltage is negatively correlated with the temperature of the first negative pressure detection unit.

5. The negative voltage protection circuit according to any one of claims 2 to 4, characterized in that: The first negative pressure detection unit includes several diodes connected in series, the anode of the first diode serves as the first end of the first negative pressure detection unit, the cathode of each diode is connected to the anode of the next diode, and the cathode of the last diode serves as the second end of the first negative pressure detection module.

6. The negative voltage protection circuit according to any one of claims 2 to 4, characterized in that: The first negative voltage detection unit includes a PNP transistor, a first resistor and a second resistor, the emitter of the PNP transistor is connected to the first end of the first resistor to serve as the first end of the first negative voltage detection unit, the base of the PNP transistor is connected to the second end of the first resistor and the first end of the second resistor, and the collector of the PNP transistor is connected to the second end of the second resistor to serve as the second end of the first negative voltage detection unit; The first threshold voltage Among them, V BE It is used to characterize the voltage between the base and the emitter of the PNP transistor, R1 is used to characterize the resistance value of the first resistor, and R2 is used to characterize the resistance value of the second resistor.

7. The negative voltage protection circuit according to claim 6, characterized in that: The voltage between the base and the emitter of the PNP transistor is negatively correlated with the temperature of the first negative pressure detection unit.

8. The negative voltage protection circuit according to any one of claims 2 to 4, characterized in that: The first negative voltage detection unit includes a PMOS tube, a third resistor and a fourth resistor, the source terminal of the PMOS tube is connected to the first end of the third resistor to serve as the first end of the first negative voltage detection unit, the gate terminal of the PMOS tube is connected to the second end of the third resistor and the first end of the fourth resistor, and the drain terminal of the PMOS tube is connected to the second end of the fourth resistor to serve as the second end of the first negative voltage detection unit; The first threshold voltage Among them, V GS It is used to characterize the voltage between the gate and the source of the PMOS tube, R3 is used to characterize the resistance value of the third resistor, and R4 is used to characterize the resistance value of the fourth resistor.

9. The negative voltage protection circuit according to claim 8, characterized in that: The voltage between the gate and the source of the PMOS tube is negatively correlated with the temperature of the first negative pressure detection unit.

10. The negative voltage protection circuit according to claim 1, characterized in that: The voltage between the source terminal and the drain terminal of the NMOS tube is less than the source-drain withstand voltage value of the NMOS tube, and the gate-drain withstand voltage value of the NMOS tube is used to characterize the maximum voltage value between the source terminal and the drain terminal of the NMOS tube.

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