High-voltage substrate selection circuit and charging device

Abstract

The application provides a high-voltage substrate selection circuit and a charging device. The high-voltage substrate selection circuit comprises a charging power tube, a charging judgment circuit and a substrate voltage switching circuit. The charging judgment circuit judges the charging state through the voltage state of a VCC voltage and a VBAT voltage. When the circuit charging state is that the VCC voltage is not connected or the VCC voltage is lower than the VBAT voltage, the enable signal output by the charging judgment circuit is a low-level signal, so that the substrate voltage bulk voltage of the charging power tube is equal to the VBAT voltage. The first switching circuit output end of the substrate voltage switching circuit outputs a first voltage, and the first voltage is the VBAT voltage, so that the voltage switching is completed and the charging function is closed. The substrate voltage switching circuit outputs the VBAT voltage, so that the normal discharge demand when the circuit charging state is that the VCC voltage is not connected or the VCC voltage is lower than the VBAT voltage is realized, and the voltage backflow situation is avoided.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power management chip, in particular to a high-voltage substrate selection circuit and a charging device. BACKGROUND

[0002] The power management chip generally has two voltage sources, namely a charging power source and a battery power source, wherein the charging power source provides a VCC voltage and the battery provides a VBAT voltage. In the case that the charging device is lower than the battery voltage VBAT or is not connected, the power management chip is still in a normal discharging working state, but there may be a battery voltage backflow situation, therefore, it is necessary to timely switch the charging power tube substrate voltage and close the charging module.

[0003] The existing substrate switching circuit, as shown in the figure, is composed of two diodes, the VCC input end and the VBAT input end are respectively connected to the positive ends of the two diodes, and the negative ends of the two diodes are connected together to form an output end, and the output substrate voltage is output. Figure 1

[0004] However, the defects of this structure are also obvious, because the substrate voltage is always lower than the highest voltage by one PN junction threshold voltage Vth. When the VCC voltage and the VBAT voltage are close, the pressure difference is easy to be lower than the threshold voltage Vth of the PN junction, and the substrate switching circuit cannot complete the voltage switching function, and even can cause a latch effect. SUMMARY

[0005] In view of the defects in the prior art, the present application provides a high-voltage substrate selection circuit and a charging device, which solves the problem that the circuit structure of the substrate switching circuit in the prior art cannot complete the voltage switching function when the voltages provided by the charging power source and the battery are close, and even can cause a latch effect.

[0006] According to the embodiment of the present application, a high-voltage substrate selection circuit is provided, comprising:

[0007] A charging power tube, the source of the charging power tube is connected to the VBAT voltage, the drain of the charging power tube is connected to the VCC voltage, the gate of the charging power tube is connected to an enable signal, and the substrate of the charging power tube is connected to a substrate voltage;

[0008] A charging judgment circuit, the charging judgment circuit comprises a first judgment circuit input end connected to the VBAT voltage, a second judgment circuit input end connected to the VCC voltage, a third judgment circuit input end and a fourth judgment circuit input end connected to an external power source, and the charging judgment circuit outputs the enable signal;

[0009] ​a substrate voltage switching circuit, comprising a first switching circuit input end connected with an enable signal, a second switching circuit input end connected with a substrate voltage, a first switching circuit output end outputting a first voltage;

[0010] The charging judgment circuit judges the circuit charging state through the VCC voltage and the VBAT voltage, and when the circuit charging state is that the VCC voltage is not connected or the VCC voltage is lower than the VBAT voltage, the enable signal output by the charging judgment circuit is a low-level signal, so that the substrate voltage connected with the charging power tube substrate is equal to the VBAT voltage, the first voltage is output by the first switching circuit output end of the substrate voltage switching circuit, and the first voltage is the VBAT voltage.

[0011] Optionally, the substrate voltage switching circuit further comprises a second switching circuit output end outputting a second voltage.

[0012] When the circuit charging state is a normal charging state, the enable signal output by the charging judgment circuit is a high-level signal, the substrate voltage connected with the charging power tube substrate is equal to the VCC voltage, the second voltage is output by the second switching circuit output end of the substrate voltage switching circuit, and the second voltage is the VCC voltage.

[0013] Optionally, in the charging judgment circuit, the sixth PMOS tube and the seventh PMOS tube are high-voltage P-type diodes formed by N wells of high-voltage PMOS tubes.

[0014] Optionally, the charging judgment circuit comprises a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, a first resistor, a second resistor, a driver and a Schmitt trigger.

[0015] The source of the first NMOS tube is grounded, the drain of the first NMOS tube is connected with a current, the gate of the first NMOS tube is connected with the gate of the second NMOS tube, the source of the second NMOS tube is grounded, the drain of the second NMOS tube is connected with the source of the third NMOS tube, the drain of the third NMOS tube is connected with the source of the sixth PMOS tube, and the gate of the third NMOS tube is connected with an external power supply.

[0016] The drain of the sixth PMOS tube is connected with the drain of the second PMOS tube, the drain of the second PMOS tube is connected with the gate of the second PMOS tube, the gate of the second PMOS tube is also connected with the gate of the third PMOS tube, the source of the second PMOS tube and the source of the third PMOS are connected with one end of the first resistor, the other end of the first resistor is connected with VBAT voltage, the drain of the third PMOS tube is connected with the drain of the eighth NMOS tube;

[0017] The gate of the sixth PMOS tube is connected with the gate of the seventh PMOS tube, the source of the sixth PMOS tube is also connected with the source of the seventh PMOS tube, the gate of the sixth PMOS tube and the gate of the seventh PMOS tube are also connected with the source of the sixth PMOS tube and the source of the seventh PMOS tube;

[0018] The drain of the seventh PMOS tube is connected with the drain of the fourth PMOS tube, the gate of the fourth PMOS tube is connected with the drain of the fourth PMOS tube, the gate of the fourth PMOS tube is also connected with the gate of the fifth PMOS tube, the source of the fourth PMOS tube and the source of the fifth PMOS are connected with one end of the second resistor, the other end of the second resistor is connected with VCC voltage;

[0019] The drain of the fifth PMOS tube is connected with the drain of the fourth NMOS tube, the gate of the fourth NMOS tube is connected with an external power supply, the source of the fourth NMOS tube is connected with the drain of the fifth NMOS tube, the gate of the sixth NMOS tube, the gate of the seventh NMOS tube and the gate of the eighth NMOS tube, the source of the fifth NMOS tube is connected with the drain of the sixth NMOS tube, the source of the sixth NMOS tube is grounded, the gate of the fifth NMOS tube is connected with one end of a driver, the other end of the driver is connected with the input end of a Schmitt trigger; the source of the fourth NMOS tube is also connected with the drain of the seventh NMOS tube, the source of the seventh NMOS tube is grounded, the gate of the seventh NMOS tube is connected with the gate of the eighth NMOS tube, the source of the eighth NMOS tube is grounded, the drain of the eighth NMOS tube and the drain of the third PMOS tube are connected with the input end of the Schmitt trigger.

[0020] Optionally, the charging judgment circuit further comprises a first current source, the first current source is connected with the drain of the first NMOS tube, and provides a current.

[0021] Optionally, the third NMOS transistor, the fourth NMOS transistor, the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor, the fifth PMOS transistor, the sixth PMOS transistor and the seventh PMOS transistor are 40V high-voltage transistors, and the first NMOS transistor, the second NMOS transistor, the fifth NMOS transistor, the sixth NMOS transistor, the seventh NMOS transistor and the eighth NMOS transistor are 5V low-voltage transistors.

[0022] Optionally, the substrate voltage switching circuit comprises a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, a third resistor and a fourth resistor.

[0023] The drain of the eleventh NMOS transistor is connected to a current, the source of the eleventh NMOS transistor is grounded, the gate of the eleventh NMOS transistor is connected to the drain of the eleventh NMOS transistor, the gate of the eleventh NMOS transistor is connected to the gate of the tenth NMOS transistor, the source of the tenth NMOS transistor is grounded, the drain of the tenth NMOS transistor is connected to the source of the ninth NMOS transistor, the substrate of the ninth NMOS transistor is grounded, the gate of the ninth NMOS transistor is connected to an enable signal, the drain of the ninth NMOS transistor is connected to the gate of the tenth PMOS transistor and one end of the third resistor, the other end of the third resistor is connected to the source of the tenth PMOS transistor and the source of the ninth PMOS transistor, the drain of the tenth PMOS transistor is connected to the gate of the ninth PMOS transistor and one end of the fourth resistor, the other end of the fourth resistor is grounded, and the drain of the ninth PMOS transistor is connected to a VBAT voltage.

[0024] The source of the ninth PMOS transistor and the source of the eighth PMOS transistor are further connected to a BLUK voltage, the drain of the eighth PMOS transistor is connected to a VCC voltage, and the potential of the gate of the eighth PMOS transistor is the same as the potential of the gate of the tenth PMOS transistor.

[0025] Optionally, the substrate voltage switching circuit further comprises a second current source, the second current source is connected to the drain of the eleventh NMOS transistor and provides a current.

[0026] The current of the MN11 is provided by the second current source.

[0027] Optionally, the ninth NMOS transistor, the eighth PMOS transistor, the ninth PMOS transistor and the tenth PMOS transistor are 40V high-voltage transistors, and the tenth NMOS transistor, the eleventh NMOS transistor, the twelfth NMOS transistor and the thirteenth NMOS transistor are 5V low-voltage transistors.

[0028] In another aspect, according to an embodiment of the present application, a charging device is also provided, comprising a charger shell and a power management chip arranged in the charger shell.

[0029] The power management chip comprises a charging power supply, a battery power supply and the high-voltage substrate selection circuit as described above, wherein the charging power supply outputs a VCC voltage, and the battery power supply outputs a VBAT voltage.

[0030] The technical principle of the present application is that the charging judgment circuit judges the charging state through the voltage state judgment circuit of the VCC voltage and the VBAT voltage, and the circuit charging state indicates that the VCC voltage is not connected or the VCC voltage is lower than the battery voltage VBAT, the enable signal output by the charging judgment circuit is a low-level signal, so that the substrate voltage connected to the charging power tube substrate is equal to the VBAT voltage, the first switching circuit output end of the substrate voltage switching circuit outputs the first voltage, and the first voltage is the VBAT voltage, thereby completing the voltage switching and closing the charging function, and the substrate voltage switching circuit outputs the VBAT voltage, thereby realizing the normal discharge demand when the circuit charging state is that the VCC voltage is not connected or the VCC voltage is lower than the VBAT voltage, and avoiding the voltage backflow situation.

[0031] Compared with the prior art, the present application has the following beneficial effects: by increasing the charging judgment circuit, an enable signal for charging judgment is generated, the substrate voltage switching circuit makes the substrate voltage equal to the maximum value of the VCC voltage and the VBAT voltage according to the enable signal, thereby avoiding the problem that the substrate voltage cannot be normally switched when the VCC voltage and the VBAT voltage are close, and in addition, the charging judgment circuit increases the hysteresis of the substrate voltage switching circuit, thereby avoiding the phenomenon that the substrate voltage is repeatedly switched when the VCC voltage and the VBAT voltage are close and the VCC voltage appears a small peak. BRIEF DESCRIPTION OF DRAWINGS

[0032] Figure 1 It is a structural schematic diagram of the existing substrate switching circuit;

[0033] Figure 2 It is a structural schematic diagram of the high-voltage substrate selection circuit of the embodiment of the present application;

[0034] Figure 3 It is a circuit structural schematic diagram of the high-voltage substrate selection circuit of the embodiment of the present application. DETAILED DESCRIPTION

[0035] The technical solutions in the present application will be further described below in combination with the drawings and embodiments.

[0036] As shown in the drawings, Figure 2 The embodiment of the present application proposes a high-voltage substrate selection circuit, which comprises a charging power tube 1, a charging judgment circuit 2 and a substrate voltage switching circuit 3. The connection relationship of each part of the embodiment of the present application is described as follows:

[0037] The charging power tube is a PMOS tube, and in Figure 2 The charging power tube 1 is a PMOS tube MP1, the source of the PMOS tube MP1 is connected with the VBAT voltage, the drain is connected with the VCC voltage, the gate is connected with the enable signal ch_en, and the substrate of the charging power tube 1 is connected with the bulk voltage. The charging judgment circuit 2 comprises a first judgment circuit input end 21 connected with the VBAT voltage, a second judgment circuit input end 22 connected with the VCC voltage, a second judgment circuit input end 23 and a fourth judgment circuit input end 24 connected with an external power supply, and an output enable signal ch_en of the charging judgment circuit 2. The substrate voltage switching circuit 3 comprises a first switching circuit input end 31 connected with the enable signal ch_en, a second switching circuit input end 32 connected with the bulk voltage, and a first switching circuit output end 33 outputting a first voltage.

[0038] It should be noted that the high-voltage substrate selection circuit provided by the embodiment of the present application is applied to a power management chip, the VCC voltage is provided for a charging power supply of the power management chip, and the VBAT voltage is provided for a battery power supply of the power management chip.

[0039] Therefore, the output of the charging judgment circuit 2 is connected with the gate of the charging power tube 1 and the first switching circuit input end 31 of the substrate voltage switching circuit 3, and the output of the charging power tube 1 is connected with the second switching circuit input end 32 of the substrate voltage switching circuit 3.

[0040] The detailed working process of the embodiment of the present application is as follows:

[0041] The charging judgment circuit 2 judges the charging state through the VCC voltage and the VBAT voltage, and when the circuit charging state is that the VCC voltage is not connected or the VCC voltage is lower than the VBAT voltage, the enable signal ch_en output by the charging judgment circuit 2 is a low-level signal, so that the bulk voltage output by the charging power tube 1 is equal to the VBAT voltage, the first switching circuit output end 33 of the substrate voltage switching circuit 3 outputs the first voltage, the first voltage is the VBAT voltage, thereby completing the voltage switching and closing the charging function, and the substrate voltage switching circuit 3 outputs the VBAT voltage, thereby realizing the normal discharging demand when the circuit charging state is that the VCC voltage is not connected or the VCC voltage is lower than the VBAT voltage, avoiding the voltage backflow situation and affecting the charging power supply.

[0042] Since the charging judgment circuit 2 is added, the charging judgment circuit 2 generates the enable signal ch_en for charging judgment, and the substrate voltage switching circuit 3 makes the bulk voltage equal to the maximum value of the VCC voltage and the VBAT voltage according to the enable signal ch_en, thereby avoiding the repeated switching phenomenon of the bulk voltage when the VCC voltage and the VBAT voltage are close and the VCC voltage appears a small peak.

[0043] like Figure 2 As shown, in one embodiment, the substrate voltage switching circuit 3 further includes a second switching circuit output terminal 34 that outputs a second voltage; when the charging judgment circuit 2 is in the normal charging state, the enabled signal ch_en output by the charging power transistor 1 is a high-level signal, the bulk voltage output by the charging power transistor 1 is equal to the VCC voltage, and the second switching circuit output terminal 34 of the substrate voltage switching circuit 3 outputs a second voltage, which is the VCC voltage. During the above process, the substrate voltage switching circuit 3 completes voltage switching and enables the charging function, and finally the charging power supply outputs the charging voltage required by the load, i.e., the VCC voltage.

[0044] It should be noted that when the circuit charging state is VCC voltage not connected or VCC voltage is lower than VBAT voltage, it refers to the internal circuit state of a device including a power management chip, such as a charging device. In this case, there is no external power supply connected or the external power supply connected is lower than the battery voltage VBAT. At this time, the charging device needs to be in a normal discharge working state. When the circuit charging state is normal charging state, it means that the charging device can output the charging voltage required by the load.

[0045] like Figure 3As shown, the embodiment of the present application provides a detailed circuit structure of the charging judgment circuit 2, wherein the charging judgment circuit 2 comprises: a first NMOS tube MN1, a second NMOS tube MN2, a third NMOS tube MN3, a fourth NMOS tube MN4, a fifth NMOS tube MN5, a sixth NMOS tube MN6, a seventh NMOS tube MN7, an eighth NMOS tube MN8, a second PMOS tube MP2, a third PMOS tube MP3, a fourth PMOS tube MP4, a fifth PMOS tube MP5, a sixth PMOS tube MP6, a seventh PMOS tube MP7, a first resistor R1, a second resistor R2, a driver buffer and a Schmitt trigger SMT; the source of the first NMOS tube MN1 is grounded, the drain of the first NMOS tube MN1 is connected to a current, the gate of the first NMOS tube MN1 is connected to the gate of the second NMOS tube MN2, the source of the second NMOS tube MN2 is grounded, the drain of the second NMOS tube MN2 is connected to the source of the third NMOS tube MN3, the drain of the third NMOS tube MN3 is connected to the source of the sixth PMOS tube MP6, the gate of the third NMOS tube MN3 is connected to an external power supply VDDA; the drain of the sixth PMOS tube MP6 is connected to the drain of the second PMOS tube MP2, the drain of the second PMOS tube MP2 is connected to the gate of the second PMOS tube MP2, the gate of the second PMOS tube MP2 is also connected to the gate of the third PMOS tube MP3, the source of the second PMOS tube MP2 and the source of the third PMOS tube MP3 are connected to one end of the first resistor R1, the other end of the first resistor R1 is connected to a VBAT voltage, the drain of the third PMOS tube MP3 is connected to the drain of the eighth NMOS tube MN8; the gate of the sixth PMOS tube MP6 is connected to the gate of the seventh PMOS tube MP7, the source of the sixth PMOS tube MP6 is also connected to the source of the seventh PMOS tube MP7, the gate of the sixth PMOS tube MP6 and the gate of the seventh PMOS tube MP7 are also connected to the source of the sixth PMOS tube MP6 and the source of the seventh PMOS tube MP7; the drain of the seventh PMOS tube MP7 is connected to the drain of the fourth PMOS tube MP4, the gate of the fourth PMOS tube MP4 is connected to the drain of the fourth PMOS tube MP4, the gate of the fourth PMOS tube MP4 is also connected to the gate of the fifth PMOS tube MP5, the source of the fourth PMOS tube MP4 and the source of the fifth PMOS tube MP5 are connected to one end of the second resistor R2, the other end of the second resistor R2 is connected to a VCC voltage.The drain of the fifth PMOS transistor MP5 is connected with the drain of the fourth NMOS transistor MN4, the gate of the fourth NMOS transistor MN4 is connected with an external power supply VDDA, the source of the fourth NMOS transistor MN4 is connected with the drain of the fifth NMOS transistor MN5, the gate of the sixth NMOS transistor MN6, the gate of the seventh NMOS transistor MN7 and the gate of the eighth NMOS transistor MN8, the source of the fifth NMOS transistor MN5 is connected with the drain of the sixth NMOS transistor MN6, the source of the sixth NMOS transistor MN6 is grounded, the gate of the fifth NMOS transistor MN5 is connected with one end of a driver buffer, the other end of the driver buffer is connected with the input end of a Schmitt trigger SMT; the source of the fourth NMOS transistor MN4 is also connected with the drain of the seventh NMOS transistor MN7, the source of the seventh NMOS transistor MN7 is grounded, the gate of the seventh NMOS transistor MN7 is connected with the gate of the eighth NMOS transistor MN8, the source of the eighth NMOS transistor MN8 is grounded, and the drain of the eighth NMOS transistor MN8 and the drain of the third PMOS transistor MP3 are connected with the input end of the Schmitt trigger SMT.

[0046] In a preferable implementation, in the charging judgment circuit 2, the sixth PMOS transistor MP6 and the seventh PMOS transistor MP7 use the N well of the high-voltage PMOS transistor to form a parasitic high-voltage P-type diode, thereby obtaining a high-voltage resistant diode. Through the above circuit, on the one hand, the charging power supply can be a wide range of voltage input, i.e., the VCC voltage is a wide range of voltage input; on the other hand, the path between VCC and VBAT can be avoided when VBAT is reversely connected for charging, thereby preventing the chip from being burned out. In a specific application, if there is no such diode, in the charging judgment circuit 2, the potentials at the nodes N1 and N2 are equal, when VBAT is reversely connected, the parasitic diode between the N well and the drain of MP2 is turned on at the moment of power-on of VCC, the path between VCC and VBAT is formed, and the chip is burned out.

[0047] In an embodiment, the charging judgment circuit 2 further comprises a first current source idc1 connected with the drain of the first NMOS transistor MN1 to provide a current. The first current source idc1 and a second current source idc2 in the following substrate voltage switching circuit 3 to provide a current realize current mirroring.

[0048] In a better implementation, the third NMOS transistor MN3, the fourth NMOS transistor MN4, the second PMOS transistor MP2, the third PMOS transistor MP3, the fourth PMOS transistor MP4, the fifth PMOS transistor MP5, the sixth PMOS transistor MP6 and the seventh PMOS transistor MP7 are 40V high-voltage transistors, and the first NMOS transistor MN1, the second NMOS transistor MN2, the fifth NMOS transistor MN5, the sixth NMOS transistor MN6, the seventh NMOS transistor MN7 and the eighth NMOS transistor MN8 are 5V low-voltage transistors. Thus, the embodiment of the application adds two normally-on high-voltage transistors MN3 and MN4 to isolate high voltage from the VCC terminal, so that the first NMOS transistor MN1, the second NMOS transistor MN2, the fifth NMOS transistor MN5, the sixth NMOS transistor MN6, the seventh NMOS transistor MN7 and the eighth NMOS transistor MN8 are designed as low-voltage transistors to save layout area.

[0049] It should be noted that in the embodiment of the application, the high-voltage and low-voltage are defined in the common BCD process, and the high-voltage device is greater than 7V and less than 40V, and the low-voltage device is less than 5V.

[0050] According to the charging judgment circuit 2, the fifth NMOS transistor MN5, the sixth NMOS transistor MN6 and the driver buffer constitute a charging judgment enable ch_en feedback loop. By setting the size ratio of the sixth NMOS transistor MN6 and the seventh NMOS transistor MN7, especially the W / L size ratio, the size of the ch_en flip voltage hysteresis is changed. Thus, by setting a certain hysteresis voltage, the phenomenon of repeated switching of the bulk voltage when the VCC voltage and the VBAT voltage are close and the VCC appears a small peak can be avoided.

[0051] As Figure 3As shown, the embodiment of the present application provides a detailed circuit structure of the substrate voltage switching circuit 3, wherein the substrate voltage switching circuit 3 comprises a ninth NMOS transistor MN9, a tenth NMOS transistor MN10, an eleventh NMOS transistor MN11, an eighth PMOS transistor MP8, a ninth PMOS transistor MP9, a tenth PMOS transistor MP10, a third resistor R3 and a fourth resistor R4; the drain of the eleventh NMOS transistor MN11 is connected to a current, the source of the eleventh NMOS transistor MN11 is grounded, the gate of the eleventh NMOS transistor MN11 is connected to the drain of the eleventh NMOS transistor MN11, the gate of the eleventh NMOS transistor MN11 is connected to the gate of the tenth NMOS transistor MN10, the source of the tenth NMOS transistor MN10 is grounded, the drain of the tenth NMOS transistor MN10 is connected to the source of the ninth NMOS transistor MN9, the substrate of the ninth NMOS transistor MN9 is grounded, the gate of the ninth NMOS transistor MN9 is connected to an enable signal ch_en, the drain of the ninth NMOS transistor MN9 is connected to the gate of the tenth PMOS transistor MP10 and one end of the third resistor R3, the other end of the third resistor R3 is connected to the source of the tenth PMOS transistor MP10 and the source of the ninth PMOS transistor MP9, the drain of the tenth PMOS transistor MP10 is connected to the gate of the ninth PMOS transistor MP9 and one end of the fourth resistor R4, the other end of the fourth resistor R4 is grounded, and the drain of the ninth PMOS transistor MP9 is connected to a VBAT voltage; the source of the ninth PMOS transistor MP9 and the source of the eighth PMOS transistor MP8 are also connected to a BLUK voltage, the drain of the eighth PMOS transistor MP8 is connected to a VCC voltage, and the potential of the gate of the eighth PMOS transistor MP8 is the same as the potential of the gate of the tenth PMOS transistor MP10.

[0052] In one embodiment, the substrate voltage switching circuit 3 further comprises a second current source idc2, the second current source idc2 is connected to the drain of the eleventh NMOS transistor MN11 to provide a current. The first current source idc1 in the above-mentioned charging judgment circuit 2 provides a current to realize a current mirror, thereby avoiding a large current path between VCC, VBAT, bulk and ground when the third NMOS transistor MN3 and the ninth NMOS transistor MN9 are turned on.

[0053] In a better implementation, the ninth NMOS transistor MN9, the eighth PMOS transistor MP8, the ninth PMOS transistor MP9 and the tenth PMOS transistor MP10 are 40V high-voltage tubes, and the tenth NMOS transistor MN10, the eleventh NMOS transistor MN11, the twelfth NMOS transistor and the thirteenth NMOS transistor MN13 are 5V low-voltage tubes.

[0054] Based on Figure 3The embodiment of the present application also describes the working principles of the charging judgment circuit 2 and the substrate voltage switching circuit 3 in two circuit charging states, i.e., when the VCC voltage is not connected or the VCC voltage is lower than the VBAT voltage, and in a normal charging state.

[0055] According to Figure 3 When the circuit charging state is normal charging, the VCC voltage is greater than the VBAT voltage, and the current flowing through the MP6 is less than the current flowing through the MP7, so the MN8 is turned on and the N5 node voltage is pulled down to a low level, and after passing through the Schmidt trigger SMT, the enable signal ch_en is high, the ninth NMOS tube MN9 is turned on, the gate potential of the tenth NMOS tube MN10, i.e., the enn node, is low, so the first PMOS tube, the eighth PMOS tube MP8 and the tenth PMOS tube MP10 are turned on, and the bulk voltage is equal to the VCC voltage, and the N6 node based on the drain of the tenth PMOS tube is equal to the VCC voltage, so the ninth PMOS tube MP9 is turned off, thereby completing the voltage switching and starting the charging function.

[0056] When the circuit charging state is that the VCC voltage is not connected or the VCC voltage is lower than the VBAT voltage, since the VCC voltage is less than the VBAT voltage, the current flowing through the MP6 is greater than the current flowing through the MP7, so the MP3 is turned on and the N5 node voltage is pulled up to a high level, and at the same time, the N5 node passes through the Schmidt trigger SMT, the enable signal ch_en is low, and at this time, the N3 node is low, the ninth PMOS tube MP9 is turned on, the bulk voltage is equal to the VBAT voltage, the gate potential of the eighth PMOS tube MP8, i.e., the enn node, is high, so the eighth PMOS tube MP8 and the tenth PMOS tube MP10 are cut off, the charging power supply does not charge the battery, the VBAT voltage is output by the ninth PMOS tube MP9, thereby completing the voltage switching and closing the charging function, and finally the battery power supply outputs the VBAT voltage, achieving the normal discharging demand when the circuit charging state is that the VCC voltage is not connected or the VCC voltage is lower than the VBAT voltage, avoiding the voltage backflow and affecting the charging power supply.

[0057] Another embodiment of the present application provides a charging device, which comprises a charger shell and a power management chip placed in the charger shell; the power management chip comprises a charging power supply, a battery power supply and a high-voltage substrate selection circuit as in the above embodiment, the charging power supply outputs the VCC voltage, and the battery power supply outputs the VBAT voltage.

[0058] Finally, it is to be explained that the above embodiments are only used to illustrate the technical solutions of the present application but not to limit the present application. Although the present application has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present application can be modified or equivalently replaced without departing from the purpose and scope of the present application, and all of them should be covered in the scope of the claims of the present application.

Claims

1. A high voltage substrate selection circuit, characterized by, The application relates to a charging power tube, a charging judgment circuit and a charging power supply circuit. The application relates to a charging power tube, a charging judgment circuit and a charging power supply circuit. The source electrode of the first NMOS tube is connected with ground, the drain electrode of the first NMOS tube is connected with current, the gate electrode of the first NMOS tube is connected with the gate electrode of the second NMOS tube, the source electrode of the second NMOS tube is connected with ground, the drain electrode of the second NMOS tube is connected with the source electrode of the third NMOS tube, the drain electrode of the third NMOS tube is connected with the source electrode of the sixth PMOS tube, and the gate electrode of the third NMOS tube is connected with an external power supply. The drain electrode of the sixth PMOS tube is connected with the drain electrode of the second PMOS tube, the drain electrode of the second PMOS tube is connected with the gate electrode of the second PMOS tube, the gate electrode of the second PMOS tube is also connected with the gate electrode of the third PMOS tube, the source electrode of the second PMOS tube and the source electrode of the third PMOS are connected with one end of the first resistor, the other end of the first resistor is connected with a VBAT voltage, and the drain electrode of the third PMOS tube is connected with the drain electrode of the eighth NMOS tube. The gate electrode of the sixth PMOS tube is connected with the gate electrode of the seventh PMOS tube, the source electrode of the sixth PMOS tube is also connected with the source electrode of the seventh PMOS tube, and the gate electrode of the sixth PMOS tube and the gate electrode of the seventh PMOS tube are also connected with the source electrode of the sixth PMOS tube and the source electrode of the seventh PMOS tube. The drain electrode of the seventh PMOS tube is connected with the drain electrode of the fourth PMOS tube, the gate electrode of the fourth PMOS tube is connected with the drain electrode of the fourth PMOS tube, the gate electrode of the fourth PMOS tube is also connected with the gate electrode of the fifth PMOS tube, the source electrode of the fourth PMOS tube and the source electrode of the fifth PMOS tube are connected with one end of the second resistor, and the other end of the second resistor is connected with a VCC voltage. ​ The drain of the fifth PMOS is connected with the drain of the fourth NMOS, the gate of the fourth NMOS is connected with an external power supply, the source of the fourth NMOS is connected with the drain of the fifth NMOS, the gate of the sixth NMOS, the gate of the seventh NMOS and the gate of the eighth NMOS, the source of the fifth NMOS is connected with the drain of the sixth NMOS, the source of the sixth NMOS is grounded, the gate of the fifth NMOS is connected with one end of a driver, the other end of the driver is connected with the input end of a Schmitt trigger; the source of the fourth NMOS is also connected with the drain of the seventh NMOS, the source of the seventh NMOS is grounded, the gate of the seventh NMOS is connected with the gate of the eighth NMOS, the source of the eighth NMOS is grounded, the drain of the eighth NMOS and the drain of the third PMOS are connected with the input end of the Schmitt trigger; The substrate voltage switching circuit comprises a first switching circuit input end connected with an enable signal, a second switching circuit input end connected with a substrate voltage, and a first switching circuit output end outputting a first voltage; The charging judgment circuit judges the circuit charging state through the VCC voltage and the VBAT voltage, and when the circuit charging state is that the VCC voltage is not connected or the VCC voltage is lower than the VBAT voltage, the enable signal output by the charging judgment circuit is a low-level signal, so that the substrate voltage connected with the substrate of the charging power tube is equal to the VBAT voltage, and the first switching circuit output end of the substrate voltage switching circuit outputs the first voltage which is the VBAT voltage.

2. The high voltage substrate selection circuit of claim 1, wherein, The substrate voltage switching circuit further comprises a second switching circuit output end outputting a second voltage; When the circuit charging state is a normal charging state, the enable signal output by the charging judgment circuit is a high-level signal, the substrate voltage connected with the substrate of the charging power tube is equal to the VCC voltage, the second switching circuit output end of the substrate voltage switching circuit outputs the second voltage which is the VCC voltage.

3. The high voltage substrate selection circuit of claim 1, wherein, In the charging judgment circuit, the sixth PMOS and the seventh PMOS are high-voltage P-type diodes formed by N wells of high-voltage PMOS.

4. The high voltage substrate selection circuit of claim 3, wherein, The charging judgment circuit further comprises a first current source connected with the drain of the first NMOS and providing a current.

5. The high voltage substrate selection circuit of claim 3, wherein, The third NMOS, the fourth NMOS, the second PMOS, the third PMOS, the fourth PMOS, the fifth PMOS, the sixth PMOS and the seventh PMOS are 40V high-voltage tubes, and the first NMOS, the second NMOS, the fifth NMOS, the sixth NMOS, the seventh NMOS and the eighth NMOS are 5V low-voltage tubes.

6. The high voltage substrate selection circuit of claim 1, wherein, The substrate voltage switching circuit comprises a ninth NMOS, a tenth NMOS, an eleventh NMOS, an eighth PMOS, a ninth PMOS, a tenth PMOS, a third resistor and a fourth resistor. The drain of the eleventh NMOS is connected to a current, the source of the eleventh NMOS is grounded, the gate of the eleventh NMOS is connected to the drain of the eleventh NMOS, the gate of the eleventh NMOS is connected to the gate of the tenth NMOS, the source of the tenth NMOS is grounded, the drain of the tenth NMOS is connected to the source of the ninth NMOS, the substrate of the ninth NMOS is grounded, the gate of the ninth NMOS is connected to an enable signal, the drain of the ninth NMOS is connected to the gate of the tenth PMOS and one end of a third resistor, the other end of the third resistor is connected to the source of the tenth PMOS and the source of the ninth PMOS, the drain of the tenth PMOS is connected to the gate of the ninth PMOS and one end of a fourth resistor, the other end of the fourth resistor is grounded, and the drain of the ninth PMOS is connected to a VBAT voltage. The source of the ninth PMOS and the source of the eighth PMOS are also connected to a BLUK voltage, the drain of the eighth PMOS is connected to a VCC voltage, and the potential of the gate of the eighth PMOS is the same as the potential of the gate of the tenth PMOS.

7. The high voltage substrate selection circuit of claim 6, wherein, The substrate voltage switching circuit further comprises a second current source connected to the drain of the eleventh NMOS to provide a current. The current of the eleventh NMOS is provided by the second current source.

8. The high voltage substrate selection circuit of claim 7, wherein, The ninth NMOS, the eighth PMOS, the ninth PMOS, and the tenth PMOS are 40V high-voltage tubes, and the tenth NMOS, the eleventh NMOS, the twelfth NMOS, and the thirteenth NMOS are 5V low-voltage tubes.

9. A charging device, characterized by It comprises: a charger shell and a power management chip placed in the charger shell; The power management chip comprises a charging power supply, a battery power supply, and a high-voltage substrate selection circuit as claimed in any one of claims 1 to 8, wherein the charging power supply outputs a VCC voltage, and the battery power supply outputs a VBAT voltage. The drain of the eleventh NMOS is connected to a current, the source of the eleventh NMOS is grounded, the gate of the eleventh NMOS is connected to the drain of the eleventh NMOS, the gate of the eleventh NMOS is connected to the gate of the tenth NMOS, the source of the tenth NMOS is grounded, the drain of the tenth NMOS is connected to the source of the ninth NMOS, the substrate of the ninth NMOS is grounded, the gate of the ninth NMOS is connected to an enable signal, the drain of the ninth NMOS is connected to the gate of the tenth PMOS and one end of a third resistor, the other end of the third resistor is connected to the source of the tenth PMOS and the source of the ninth PMOS, the drain of the tenth PMOS is connected to the gate of the ninth PMOS and one end of a fourth resistor, the other end of the fourth resistor is grounded, and the drain of the ninth PMOS is connected to a VBAT voltage. The source of the ninth PMOS and the source of the eighth PMOS are also connected to a BLUK voltage, the drain of the eighth PMOS is connected to a VCC voltage, and the potential of the gate of the eighth PMOS is the same as the potential of the gate of the tenth PMOS. The substrate voltage switching circuit further comprises a second current source connected to the drain of the eleventh NMOS to provide a current. The current of the eleventh NMOS is provided by the second current source. The ninth NMOS, the eighth PMOS, the ninth PMOS, and the tenth PMOS are 40V high-voltage tubes, and the tenth NMOS, the eleventh NMOS, the twelfth NMOS, and the thirteenth NMOS are 5V low-voltage tubes. It comprises: a charger shell and a power management chip placed in the charger shell; The power management chip comprises a charging power supply, a battery power supply, and a high-voltage substrate selection circuit as claimed in any one of claims 1 to 8, wherein the charging power supply outputs a VCC voltage, and the battery power supply outputs a VBAT voltage.

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