Impedance adjustment circuit, power amplifier circuit and electronic equipment

Abstract

The embodiment of the present invention discloses an impedance adjustment circuit for a power amplifier tube, a power amplifier circuit, and an electronic device. The power amplifier circuit includes a power amplifier tube and an impedance adjustment circuit. The impedance adjustment circuit includes an LC resonant circuit and a first capacitor. The first capacitor is connected between a first node and ground. The LC resonant circuit is connected between the first node and an input end or an output end of the power amplifier tube. The first node is coupled to a bias voltage terminal, for example. The impedance adjustment circuit makes the external impedance of the input end or the output end of the power amplifier tube short-circuit low resistance at the second harmonic 2F0, achieves an ideal working state, and reduces the circuit area.

Description

Technical Field

[0001] The present invention relates to a power amplifier, and in particular to an impedance adjustment circuit for a power amplifier tube, a power amplifier circuit and an electronic device. Background Art

[0002] Power amplifiers (PA) are widely used in radars, communication base stations, wireless terminals and other wireless signal transmitters, as well as audio playback and other fields. For example, the RF power amplifier circuit in a communication base station needs to amplify the signal to a specific power according to the receiving requirements of the device terminal, so that the final output signal maintains a specific coverage range and meets specific data transmission rate requirements. Therefore, the RF power amplifier is a very important component in communication equipment. In the power amplifier circuit, the power supply bias circuit is required to provide a suitable static operating point. The power supply bias circuit also affects the power amplifier efficiency and stability of the power amplifier circuit. At the same time, the miniaturization of the power amplifier circuit is also significantly affected by the circuit area of ​​the power supply bias circuit. Summary of the invention

[0003] In view of this, an embodiment of the present invention provides an impedance adjustment circuit for a power amplifier tube, a power amplifier circuit, and an electronic device. The circuit can improve the efficiency of the power amplifier circuit.

[0004] One aspect of an embodiment of the present invention provides an impedance adjustment circuit. The impedance adjustment circuit includes: an LC resonant circuit and a first capacitor, wherein the first capacitor is connected between the first node and ground, and the LC resonant circuit is connected between the first node and the input end or the output end of the power amplifier tube to adjust the external impedance of the input end or the output end of the power amplifier tube.

[0005] In some embodiments, the impedance adjustment circuit further includes a first resistor, and the LC resonant circuit and the first resistor are connected in series between the first node and an input end or an output end of the power amplifier tube.

[0006] In some embodiments, the impedance adjustment circuit further includes a first inductor, and the LC resonant circuit and the first inductor are connected in series between the first node and an input end or an output end of the power amplifier tube.

[0007] In some embodiments, the impedance adjustment circuit further includes a first resistor and a first inductor, and the LC resonant circuit, the first resistor and the first inductor are connected in series between the first node and the input or output end of the power amplifier tube.

[0008] In some embodiments, the LC resonant circuit includes a second capacitor and a second inductor connected in parallel.

[0009] In some embodiments, the impedance of the LC resonant circuit is maximum at frequency F0. Wherein, L is the inductance value of the second inductor, and C is the capacitance value of the second capacitor.

[0010] In some embodiments, the first node is also connected to a bias voltage terminal.

[0011] Another aspect of an embodiment of the present invention provides a power amplifier circuit. The power amplifier circuit includes: a power amplifier tube and an impedance adjustment circuit. The impedance adjustment circuit includes an LC resonant circuit and a first capacitor, wherein the first capacitor is connected between the first node and the ground, and the LC resonant circuit is connected between the first node and the input end or the output end of the power amplifier tube to adjust the external impedance of the input end or the output end of the power amplifier tube.

[0012] In some embodiments, the impedance adjustment circuit further includes a first resistor, and the LC resonant circuit and the first resistor are connected in series between the first node and an input end or an output end of the power amplifier tube.

[0013] In some embodiments, the impedance adjustment circuit further includes a first inductor, and the LC resonant circuit and the first inductor are connected in series between the first node and an input end or an output end of the power amplifier tube.

[0014] In some embodiments, the impedance adjustment circuit further includes a first resistor and a first inductor, and the LC resonant circuit, the first resistor and the first inductor are connected in series between the first node and the input or output end of the power amplifier tube.

[0015] In some embodiments, the LC resonant circuit includes a second capacitor and a second inductor connected in parallel.

[0016] In some embodiments, the impedance of the LC resonant circuit is maximum at frequency F0. Wherein, L is the inductance value of the second inductor, and C is the capacitance value of the second capacitor.

[0017] In some embodiments, the first node is also connected to a bias voltage terminal.

[0018] In some embodiments, the power amplifier circuit includes two impedance adjustment circuits, and the two impedance adjustment circuits include a first impedance adjustment circuit and a second impedance adjustment circuit. The first impedance adjustment circuit is connected to the input end of the power amplifier tube, and the second impedance adjustment circuit is connected to the output end of the power amplifier tube.

[0019] In some embodiments, the first node of the first impedance adjustment circuit is connected to the first bias voltage terminal, and the first node of the second impedance adjustment circuit is connected to the second bias voltage terminal; or, the first node of the first impedance adjustment circuit is not connected to the first bias voltage terminal, and the first node of the second impedance adjustment circuit is connected to the second bias voltage terminal; or, the first node of the first impedance adjustment circuit is connected to the first bias voltage terminal, and the first node of the second impedance adjustment circuit is not connected to the second bias voltage terminal; or, the first node of the first impedance adjustment circuit is not connected to the first bias voltage terminal, and the first node of the second impedance adjustment circuit is not connected to the second bias voltage terminal.

[0020] In some embodiments, the power amplifier tube includes a gate, a source and a drain, the gate is the input end of the power amplifier tube, and the drain is the output end of the power amplifier tube; or, the power amplifier tube includes a base, an emitter and a collector, the base is the input end of the power amplifier tube, and the collector is the output end of the power amplifier tube.

[0021] In some embodiments, the power amplifier tube is fabricated on a gallium nitride, silicon, silicon germanium, gallium arsenide, or indium phosphide epitaxial layer.

[0022] Another aspect of the embodiments of the present invention provides an electronic device, comprising the above-mentioned power amplifier circuit.

[0023] The impedance adjustment circuit of the embodiment of the present invention is connected to the input end or the output end of the power amplifier tube, the impedance of the impedance adjustment circuit is an open circuit high impedance at the fundamental wave F0, and a short circuit low impedance at the second harmonic 2F0, and the external impedance of the input end or the output end of the power amplifier tube is adjusted so that the external impedance of the input end or the output end of the power amplifier tube is not affected at the fundamental wave F0, and is a short circuit low impedance at the second harmonic 2F0, thereby improving the efficiency of the power amplifier circuit. When the first node in the impedance adjustment circuit is connected to the bias voltage terminal, when the impedance adjustment circuit is used as the input end power supply bias circuit or the output end power supply bias circuit of the power amplifier tube, the area of ​​the power supply bias circuit is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0025] Figure 1 is a schematic diagram of a power supply bias circuit in the related art;

[0026] Figure 2 Shows the use of Figure 1 The frequency response curve of the gate impedance of the power amplifier tube of the power supply bias circuit;

[0027] Figure 3 is a schematic diagram of another power supply bias circuit in the related art;

[0028] Figure 4 Shows the use of Figure 3 The frequency response curve of the gate impedance of the power amplifier tube of the power supply bias circuit;

[0029] Figure 5 is a schematic diagram of a power amplifier circuit according to an embodiment of the present invention;

[0030] Figure 6 is a schematic diagram of a power amplifier tube according to an embodiment of the present invention;

[0031] Figure 7 is a schematic diagram of another power amplifier tube according to an embodiment of the present invention;

[0032] Figure 8 is a schematic diagram of an impedance adjustment circuit according to an embodiment of the present invention;

[0033] Fig. 9 is a schematic diagram of an impedance adjustment circuit according to an embodiment of the present invention;

[0034] Fig.10 is a schematic diagram of an impedance adjustment circuit according to an embodiment of the present invention;

[0035] Fig.11 is a schematic diagram of an impedance adjustment circuit according to an embodiment of the present invention;

[0036] Fig.12 is a schematic diagram of an impedance adjustment circuit according to an embodiment of the present invention;

[0037] Fig.13 is a schematic diagram of an impedance adjustment circuit according to an embodiment of the present invention;

[0038] Fig.14 is a schematic diagram of an LC resonant circuit according to an embodiment of the present invention;

[0039] Fig.15 Shows the use of Fig.11 The impedance adjustment circuit is used as the frequency response curve of the gate impedance of the power amplifier tube of the power supply bias circuit;

[0040] Fig.16 Shows Figure 1 , Figure 3 and Fig.12 The circuit layout;

[0041] Fig.17 is a schematic diagram of another power amplifier circuit according to an embodiment of the present invention;

[0042] Fig.18Shows Fig.17 The impedance adjustment circuit 10 and the impedance adjustment circuit 20;

[0043] Fig.19 is a schematic diagram of another power amplifier circuit according to an embodiment of the present invention;

[0044] Fig. 20 is a schematic diagram of an exemplary electronic device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0045] The present application is described below based on embodiments, but the present application is not limited to these embodiments. In the detailed description of the present application below, some specific details are described in detail. It is possible for those skilled in the art to fully understand the present application without the description of these details. In order to avoid confusing the essence of the present application, known methods, processes, flows, components and circuits are not described in detail.

[0046] In addition, persons of ordinary skill in the art will appreciate that the drawings provided herein are for illustration purposes and are not necessarily drawn to scale.

[0047] Unless the context clearly requires otherwise, the words "include", "comprising" and similar words throughout the application should be interpreted as including rather than exclusive or exhaustive; that is, the meaning is "including but not limited to".

[0048] In the description of this application, it should be understood that the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of this application, unless otherwise specified, the meaning of "plurality" is two or more.

[0049] The input and output ends of the power amplifier tube require a power supply bias circuit to provide a bias voltage or a bias current. Figure 1 This is a schematic diagram of a power supply bias circuit in the related art. The power supply bias circuit provides a bias voltage for the input end of a power amplifier tube, for example. The power supply bias circuit includes a microstrip line MLIN1, a stabilizing resistor Rg1, a microstrip line MLIN2, and a bypass capacitor C1. The length of the microstrip line MLIN2 is λ / 4, where λ is the wavelength corresponding to the fundamental wave F0. When the fundamental wave F0 = 3.5 GHz, Figure 1 The frequency response curve of the input end of the power amplifier tube is shown as Figure 2 As shown. Figure 2In the figure, Z0=50 ohms indicates that the impedance is normalized to Z0. By adjusting the values ​​of MLIN1, Rg1, MLIN2, and C1, at the fundamental wave F0, the impedance of the input end of the power amplifier is in an open circuit position, and the impedance at the second harmonic 2F0 is at Gamma=0.96, Angle=153deg in the Smith chart. For power amplifiers of CMOS and LDMOS processes, this network characteristic is ideal. For power amplifiers of GaN processes, the impedance of the input end of the power amplifier at the fundamental wave F0 is in the optimal position, but the impedance at the second harmonic 2F0 is not in the optimal position. In addition, the area of ​​the microstrip line MLIN2 is large, especially in designs that are sensitive to layout area such as radio frequency integrated circuits (RFIC) / monolithic microwave integrated circuits (MMIC), this disadvantage is more prominent.

[0050] Figure 3 Schematic diagram of another power supply bias circuit in the related art. The power supply bias circuit, for example, provides a bias voltage for the input terminal of a power amplifier tube. The power supply bias circuit includes inductors Lg1 and Lg2, a resistor Rg1, and a bypass capacitor C1. The inductor Lg1, the resistor Rg1, and the inductor Lg2 are connected in series between the bias voltage terminal and the input terminal of the power amplifier tube. Taking the fundamental wave F0 as 3.5GHz as an example, Figure 3 The frequency response curve of the input end of the power amplifier tube is shown as Figure 4 As shown. By adjusting the values ​​of inductors Lg1 and Lg2, resistor Rg1 and bypass capacitor C1, the impedance of the input end of the power amplifier at the fundamental wave F0 is close to the open circuit position, and the impedance of the input end of the power amplifier at the second harmonic 2F0 is closer to the open circuit position than the impedance at F0. For power amplifiers made in VDMOS, CMOS and LDMOS processes, this network characteristic is ideal. For GaN power amplifiers, the impedance of the input end of the power amplifier at the fundamental wave F0 is also ideal, but the impedance at the second harmonic 2F0 is quite different from the ideal impedance, which will cause a significant decrease in the power amplifier efficiency. For GaN power amplifiers, Figure 3 The power supply bias circuit also needs to add an additional harmonic control circuit, which increases the circuit area and increases the complexity of the circuit design.

[0051] Figure 5 Schematic diagram of a power amplifier circuit according to an embodiment of the present invention. Figure 5 As shown, the power amplifier circuit includes: a power amplifier tube, an input matching network, an output matching network, an impedance adjustment circuit 10 and an impedance adjustment circuit 20. Figure 5In the corresponding embodiment, the impedance adjustment circuit 10 serves as an input power supply bias circuit, and the impedance adjustment circuit 20 serves as an output power supply bias circuit. The input end of the input matching network is connected to the RF signal input end RFin for receiving the RF input signal, and the output end of the input matching network is connected to the input end IN of the power amplifier tube. The output end OUT of the power amplifier tube is connected to the input end of the output matching network, and the output end of the output matching network serves as the RF amplified signal output end RFout. The input matching network and the output matching network are used for impedance matching adjustment, for example, a network composed of at least one of an inductor, a resistor and a capacitor. The input matching network receives the input RF signal, the power amplifier tube amplifies the RF signal, and the output matching network outputs the amplified signal.

[0052] The power amplifier tube can be made on an epitaxial layer of gallium nitride (GaN), silicon, silicon germanium (SiGe), gallium arsenide (GaAs), or indium phosphide (InP) and a substrate of a corresponding material. The power amplifier tube is, for example, a chip made on an epitaxial layer and a substrate of the above-mentioned material, and has a plurality of pads, which are respectively used to connect an input matching network, an output matching network, an input power supply bias circuit, an output power supply bias circuit and a ground. The input matching network and the output matching network are, for example, composed of discrete resistors, inductors, and capacitors. In some embodiments, the input matching network and the input power supply bias circuit are connected to the same pad, and / or the output matching network and the output power supply bias circuit are connected to the same pad. In some embodiments, the power amplifier circuit includes a multi-stage amplifier, each stage of the amplifier includes a power amplifier tube, and an inter-stage matching network is provided between the multi-stage amplifiers. In one embodiment, the input matching network, the output matching network, the input power supply bias circuit, and the output power supply bias circuit can be separated on different chips, or two or more of them are respectively integrated on one chip. In another embodiment, one or more of the input matching network, the output matching network, the input power supply bias circuit, and the output power supply bias circuit are implemented on a PCB board. In one embodiment, the power amplifier tube, the input matching network, the output matching network, the input power supply bias circuit, and the output power supply bias circuit are integrated on a chip with multiple pads, for example, the pads are configured as: a radio frequency signal input terminal RFin, a radio frequency amplified signal output terminal RFout, a first bias voltage terminal, a second bias voltage terminal, etc., and its epitaxial layer and substrate can be the above-mentioned materials.

[0053] In some embodiments, the power amplifier is a field effect transistor (Field Effect Transistor), such as a high electron mobility transistor (HEMT), a laterally diffused metal oxide semiconductor (LDMOS) transistor, a vertically diffused metal oxide semiconductor (VDMOS) transistor, a complementary metal oxide semiconductor (CMOS) transistor, etc. Figure 6 As shown, the power amplifier tube includes a gate G, a source S, and a drain D. The gate G is the input end of the power amplifier tube, the drain D is the output end of the power amplifier tube, and the source S is grounded.

[0054] In some embodiments, the power amplifier is a bipolar transistor (Bipolar Junction Transistor, BJT), such as a heterojunction bipolar transistor (Heterojunction Bipolar Transistor, HBT). Figure 7 As shown, the power amplifier tube includes a base B, a collector C, and an emitter E. The base B is the input end of the power amplifier tube, the collector C is the output end of the power amplifier tube, and the emitter E is grounded.

[0055] The input end of the input power supply bias circuit is connected to a first bias voltage terminal, which is a terminal for providing a voltage VCC, and the output end of the input power supply bias circuit is connected to the input end IN of the power amplifier tube. The input end of the output power supply bias circuit is connected to a second bias voltage terminal, which is a terminal for providing a voltage VCC, and the output end of the output power supply bias circuit is connected to the output end OUT of the power amplifier tube. The input power supply bias circuit and the output power supply bias circuit are used to provide a static operating point for the power amplifier tube. In one embodiment, the first bias voltage terminal and the second bias voltage terminal are the same terminal. In another embodiment, the first bias voltage terminal and the second bias voltage terminal are different terminals. In one embodiment, the voltage VCC provided by the first bias voltage terminal and the second bias voltage terminal are equal. In another embodiment, the voltage VCC provided by the first bias voltage terminal and the second bias voltage terminal are not equal. The voltage VCC (DC) can be the voltage provided by a DC power supply, or the voltage provided by a DC power supply after being processed by a DC-DC conversion circuit or a low dropout regulator, or the voltage provided by an AC power supply after being processed by an AC-DC conversion circuit. The DC-DC conversion circuit and the low dropout regulator can make the DC voltage more stable and eliminate fluctuations. The input power supply bias circuit and the output power supply bias circuit provide DC feed to the power amplifier tube, ensuring that the power amplifier tube has an appropriate DC bias point to achieve efficient amplification of the RF signal.

[0056] The impedance of the impedance adjustment circuit is an open circuit high impedance at the fundamental wave F0, and a short circuit low impedance at the second harmonic 2F0. When the impedance adjustment circuit is coupled to the input end or the output end of the power amplifier tube, the external impedance of the input end or the output end of the power amplifier tube is adjusted so that the external impedance of the input end or the output end of the power amplifier tube is not affected at the fundamental wave F0, and is a short circuit low impedance at the second harmonic 2F0, thereby improving the efficiency of the power amplifier circuit.

[0057] For GaN HEMTs fabricated on a substrate of a gallium nitride epitaxial layer and corresponding materials, the gate capacitance Cgs varies nonlinearly with the gate voltage Vgs. Therefore, the external impedance of the gate G of the power amplifier tube needs to be realized as a low impedance at the second harmonic 2F0, and the short circuit is optimal to provide the output efficiency of the power amplifier circuit. Specifically, the external impedance of the input end (e.g., gate G) of the power amplifier tube refers to the source impedance of the input end of the power amplifier tube, specifically the impedance from the end face of the input end IN of the power amplifier tube to the RF signal input end RFin, which depends on the input matching network and the input end power supply bias circuit. The external impedance of the output end (e.g., gate G) of the power amplifier tube refers to the load impedance of the output end of the power amplifier tube, specifically the impedance from the end face of the output end OUT of the power amplifier tube to the RF signal output end Rout, which depends on the output matching network and the output end power supply bias circuit.

[0058] Figure 8 1 is a schematic diagram of an impedance adjustment circuit 10 or an impedance adjustment circuit 20 for a power amplifier tube according to an embodiment of the present invention. Figure 8 The circuit in the embodiment can be applied to the input end and / or the output end of the power amplifier tube as an input end power supply bias circuit and / or an output end power supply bias circuit. Figure 8 As shown, the impedance adjustment circuit includes an LC resonant circuit and a first capacitor C1. The first capacitor C1 is a bypass capacitor connected between the first node N1 and the ground. The first node N1 is connected to a bias voltage terminal that provides a voltage VCC. The first capacitor C1 is used to short-circuit the radio frequency signal to prevent the radio frequency signal from being fed into the power module coupled to the bias voltage terminal. The LC resonant circuit is connected between the first node N1 and the input terminal IN or the output terminal OUT of the power amplifier tube.

[0059] Fig. 9 is a circuit diagram of an exemplary LC resonant circuit. The LC resonant circuit includes a second capacitor C2 and a second inductor L2 connected in parallel. The impedance of the LC resonant circuit is set to be a maximum value at a frequency F0, Wherein, L is the inductance value of the second inductor L2, and C is the capacitance value of the second capacitor C2.

[0060] exist Figure 8In the corresponding embodiment, the first node N1 is connected to the bias voltage terminal, the impedance adjustment circuit 10 is used as the input end power supply bias circuit, and the impedance adjustment circuit 20 is used as the output end power supply bias circuit. When the frequency of the power supply bias circuit is lower than F0, the equivalent impedance of the second capacitor C2 increases, the equivalent impedance of the second inductor L2 decreases, the second inductor L2 plays a major role, and the impedance of the parallel network decreases. Therefore, the power supply bias circuit also has a certain effect on expanding the video bandwidth (VBW) of the RF power amplifier circuit. When the frequency is higher than F0, the equivalent impedance of the second inductor L2 increases, the equivalent impedance of the second capacitor C2 decreases, the second capacitor C2 plays a major role, and the impedance of the parallel network decreases. At 2F0, it presents a nearly ideal short-circuit direct state. The first capacitor C1 and the second capacitor C2 provide a path to the ground for the 2F0 frequency signal.

[0061] The power supply bias circuit includes an LC resonant circuit. The power supply bias circuit makes the external impedance of the input end or the output end of the power amplifier tube unaffected at the fundamental wave F0, and presents a short-circuit low impedance at the second harmonic 2F0. If the short-circuit low impedance is not presented at the second harmonic 2F0, the amplification efficiency of the power amplifier tube will be affected. The power supply bias circuit achieves a better distribution of the fundamental wave F0 and the second harmonic 2F0 impedance with a smaller circuit area.

[0062] Fig.10 1 is a schematic diagram of another impedance adjustment circuit 10 or impedance adjustment circuit 20 for a power amplifier tube according to an embodiment of the present invention. Fig.10 The circuit in the figure can be applied to the input end or the output end of the power amplifier tube. Fig.10 As shown, the circuit includes an LC resonant circuit, a first inductor L1 and a first capacitor C1. The first capacitor C1 is a bypass capacitor connected between the first node N1 and the ground. The first node N1 is connected to a bias voltage terminal that provides a voltage VCC. The first capacitor C1 is used to short-circuit the radio frequency signal to prevent the radio frequency signal from being fed into the power module connected to the bias terminal. The LC resonant circuit and the first inductor L1 are connected in series between the first node N1 and the input terminal IN or the output terminal OUT of the power amplifier tube. The first inductor L1 is a fine-tuning inductor, which generally has a smaller value. When the values ​​of other components are determined, by adjusting the inductance value of the first inductor L1, the impedance at the second harmonic 2F0 can be adjusted without changing the impedance at the fundamental wave F0. The angle of the circle with a relatively high Gamma value in the Smith chart is adjusted to pursue the best radio frequency performance. The positions of the LC resonant circuit and the first inductor L1 can be interchanged.

[0063] Fig.11 It is a schematic diagram of another impedance adjustment circuit 10 or impedance adjustment circuit 20 for a power amplifier tube according to an embodiment of the present invention. Fig.11The circuit in the figure can be applied to the input end or the output end of the power amplifier tube. Fig.11 As shown, the impedance adjustment circuit includes an LC resonant circuit, a first resistor R1 and a first capacitor C1. The first capacitor C1 is a bypass capacitor connected between the first node N1 and the ground. The first node N1 is connected to a bias voltage terminal that provides a voltage VCC. The first capacitor C1 is used to short-circuit the radio frequency signal to prevent the radio frequency signal from being fed into the power module connected to the bias terminal. The LC resonant circuit and the first resistor R1 are connected in series between the first node N1 and the input terminal IN or the output terminal OUT of the power amplifier tube. The first resistor R1 is used as a stabilizing resistor to adjust the gain and stability of the power amplifier. The positions of the LC resonant circuit and the first resistor R1 can be interchanged.

[0064] Figure 12-14 It is a schematic diagram of another impedance adjustment circuit 10 or impedance adjustment circuit 20 for a power amplifier tube according to an embodiment of the present invention. Figure 12-14 The circuit in the figure can be applied to the input end or the output end of the power amplifier tube. Figure 12-14 As shown, the circuit includes an LC resonant circuit, a first resistor R1, a first inductor L1 and a first capacitor C1. The first capacitor C1 is a bypass capacitor connected between the first node N1 and the ground. The first node N1 is connected to a bias voltage terminal that provides a voltage VCC. The first capacitor C1 is used to short-circuit the radio frequency signal to prevent the radio frequency signal from being fed into the power module connected to the bias terminal. The LC resonant circuit, the first inductor L1 and the first resistor R1 are connected in series between the first node N1 and the input terminal IN or the output terminal OUT of the power amplifier tube. The order of the LC resonant circuit, the first inductor L1 and the first resistor R1 in the series path is not limited. For example, in Fig.12 In the embodiment shown, the LC resonant circuit, the first resistor R1 and the first inductor L1 are connected in series in sequence. Fig.13 In the embodiment shown, the LC resonant circuit, the first inductor L1 and the first resistor R1 are connected in series in sequence. Fig.14 In the illustrated embodiment, the first inductor L1 , the LC resonant circuit and the first resistor R1 are sequentially connected in series.

[0065] The first inductor L1 is a fine-tuning inductor, which is generally smaller in value. When the values ​​of other components are determined, by adjusting the inductance of the first inductor L1, the angle of the impedance at the second harmonic 2F0 on the circle with a relatively high Gamma value in the Smith chart can be adjusted without changing the impedance at the fundamental wave F0, so as to pursue the best RF performance.

[0066] The first resistor R1 is used as a stabilizing resistor to adjust the gain and stability of the power amplifier. When the power amplifier tube is a GaN HEMT transistor, the first resistor R1 can also adjust the Gamma value of the impedance at the second harmonic 2F0 to better meet the requirements of GaN HEMT transistors with different gate widths for the input second harmonic 2F0 impedance position.

[0067] Figure 10-14 The LC resonant circuit in can refer to Fig. 9 , no more details.

[0068] exist Figure 5-Figure 14 In the corresponding embodiment, the first node N1 of the impedance adjustment circuit 10 is connected to the first bias voltage terminal, the first node N1 of the impedance adjustment circuit 20 is connected to the second bias voltage terminal, the impedance adjustment circuit 10 is used as the input end power supply bias circuit of the power amplifier tube, and the impedance adjustment circuit 20 is used as the output end power supply bias circuit of the power amplifier tube. The voltages provided by the first bias voltage terminal and the second bias voltage terminal can be the same or different. The impedance adjustment circuit 10 can be selected according to the needs. Figure 8 , one of the circuit topologies in 10-14, the impedance adjustment circuit 20 can be selected according to the requirements Figure 8 , one of the circuit topologies in 10 to 14. The circuit topology of the impedance adjustment circuit 10 and the circuit topology of the impedance adjustment circuit 20 may be the same or different.

[0069] The impedance adjustment circuit 20 of the present invention may not include the first resistor R1, or may include the first resistor R1. When the impedance adjustment circuit 20 includes the first resistor R1, the resistance value and power capacity of the first resistor R1 need to be accurately considered, otherwise, the first resistor R1 will consume power, reduce the efficiency of the power amplifier circuit, and even burn out the first resistor R1.

[0070] In the present invention, the first inductor L1, the second inductor L2, the first capacitor C1, the second capacitor C2 and the first resistor R1 are all schematic, which can represent an element, or a module formed by connecting multiple elements in series or / and in parallel. For example, the first inductor L1 is a plurality of inductors in series or / and in parallel, and the first capacitor C1 is a plurality of capacitors in series or / and in parallel. In this way, inductors with various inductance values ​​and capacitors with various capacitance values ​​can be obtained. For example, the target value of the fundamental wave F0 is determined according to the application scenario of the power amplifier circuit, and the target values ​​of the first inductor L1, the second inductor L2, the first capacitor C1, the second capacitor C2 and the first resistor R1 are determined according to the fundamental wave F0. The target values ​​of the first inductor L1, the second inductor L2, the first capacitor C1, the second capacitor C2 and the first resistor R1 are achieved by connecting in series and / or in parallel.

[0071] Fig.15 Shows the use of Fig.12When the circuit is used as the gate power supply bias circuit of the power amplifier tube, the frequency response curve of the impedance of the impedance adjustment circuit. By setting the values ​​of the first resistor R1, the first inductor L1, the first capacitor C1, the second inductor L2 and the second capacitor C2, as shown in FIG. Fig.15 As shown, the impedance of the impedance adjustment circuit at the fundamental wave F0 is at the open circuit point, and the impedance at the second harmonic 2F0 is at the short circuit point. Regardless of the power amplifier tube of VDMOS, CMOS, LDMOS, or GaN process, the frequency response characteristics of this power supply bias circuit are very ideal.

[0072] Fig.16 Shows Figure 1 , Figure 3 and Fig.12 The layout of the three power supply bias circuits in . Fig.16 In the Figure 1 The layout of the power supply bias circuit in B is Figure 3 The layout of the power supply bias circuit in the figure, C is Fig.12 Based on the GaN monolithic microwave integrated circuit (MMIC) process epitaxial layer and the corresponding substrate, Figure 1 The layout area of ​​the power supply bias circuit is normalized. At the fundamental frequency F0 = 3.5 GHz, Fig.12 In the power supply bias circuit, optionally, the inductance value of the first inductor L1 is 0.58nH, the resistance value of the resistor R1 is 1Ω, the inductance value of the second inductor L2 is 1.48nH, the capacitance value of the second capacitor C2 is 1.4pF, and the capacitance value of the first capacitor C1 is 5.6pF. Figure 1 The layout area of ​​the power supply bias circuit is normalized as the basis. Fig.12 The normalized area of ​​the power supply bias circuit layout is 8%, compared to Figure 1 The power supply bias circuit has been reduced by 92%. The most important thing is that the inductor area is reduced, which reduces the chip area.

[0073] Fig.12 The power supply bias circuit can be applied to the input end (gate) of the power amplifier tube. Based on the GaN HEMT process, a unit cell with uWg = 250um and Fingers No. = 4 is selected to perform loadpull simulation. The results show that the use of Fig.12 The gate supply bias circuit is different from the Figure 1 The power supply bias circuit, when the gain of the power amplifier circuit is compressed by 3dB, the maximum drain efficiency is improved by 5%, compared with the Figure 3 The power supply bias circuit has a 3dB compression maximum drain efficiency improvement of 15%.

[0074] The present application utilizes the frequency response characteristics of the LC resonant circuit. The impedance adjustment circuit is coupled to the input or output end of the power amplifier tube to adjust the external impedance of the input or output end of the power amplifier tube, so that the external impedance of the input or output end of the power amplifier tube is not affected at the fundamental wave F0, and is a short circuit low resistance at the second harmonic 2F0, thereby improving the efficiency of the power amplifier circuit and meeting the electrical requirements of the input power supply bias circuit of RF power amplifier tubes such as VDMOS, CMOS, LDMOS and GaN. In addition, the inductance value of the LC resonant circuit used to generate high impedance at the fundamental wave F0 is less than Figure 3 The inductance value of the second inductor of the power supply bias circuit. Therefore, Fig.12 The layout area of ​​the power supply bias circuit is also significantly reduced.

[0075] In some embodiments, the power amplifier circuit includes an impedance adjustment circuit 10 (a first impedance adjustment circuit) and an impedance adjustment circuit 20 (a second impedance adjustment circuit). The impedance adjustment circuit 10 is connected to the input end of the power amplifier tube, and the impedance adjustment circuit 20 is connected to the output end of the power amplifier tube.

[0076] The first node N1 of the impedance adjustment circuit 10 is connected to the first bias voltage terminal, which is reused as the input power supply bias circuit of the power amplifier tube, and the first node N1 of the impedance adjustment circuit 20 is connected to the second bias voltage terminal, which is reused as the output power supply bias circuit of the power amplifier tube. Alternatively, the first node N1 of the impedance adjustment circuit 10 is not connected to the first bias voltage terminal (for example, the first capacitor C1 and the LC resonant circuit are connected in series between the ground and the input end of the power amplifier tube), and the first node N1 of the impedance adjustment circuit 20 is connected to the second bias voltage terminal. Alternatively, the first node N1 of the impedance adjustment circuit 10 is connected to the first bias voltage terminal, and the first node N1 of the impedance adjustment circuit 20 is not connected to the second bias voltage terminal (for example, the first capacitor C1 and the LC resonant circuit are connected in series between the ground and the output end of the power amplifier tube). Alternatively, the first node N1 of the impedance adjustment circuit 10 is not connected to the first bias voltage terminal, and the first node N1 of the impedance adjustment circuit 20 is not connected to the second bias voltage terminal.

[0077] Fig.17 is a schematic diagram of another power amplifier circuit according to an embodiment of the present invention. Fig.17 As shown, the power amplifier circuit includes: a power amplifier tube, an input matching network, an output matching network, an input power supply bias circuit, an output power supply bias circuit, an impedance adjustment circuit 10 and an impedance adjustment circuit 20. The input end of the input power supply bias circuit is connected to the first bias voltage terminal, and the output end is connected to the input end IN of the power amplifier tube. The input end of the output power supply bias circuit is connected to the second bias voltage terminal, and the output end is connected to the output end OUT of the power amplifier tube. The input power supply bias circuit and the output power supply bias circuit provide a static operating point for the power amplifier tube.

[0078] The impedance adjustment circuit 10 is used to adjust the external impedance of the input terminal IN of the power amplifier tube, so that the external impedance of the input terminal IN of the power amplifier tube is not affected at the fundamental wave F0, and has a low impedance characteristic (preferably a short circuit) at the second harmonic 2F0. The impedance adjustment circuit 20 is used to adjust the external impedance of the output terminal OUT of the power amplifier tube, so that the external impedance of the output terminal OUT of the power amplifier tube is not affected at the fundamental wave F0, and has a low impedance characteristic (preferably a short circuit) at the second harmonic 2F0.

[0079] The impedance adjustment circuit 10 can be selected according to the requirements. Figure 8 , one of the circuit topologies in 10-14, the impedance adjustment circuit 20 can be selected according to the requirements Figure 8 , one of the circuit topologies in 10-14, but the difference is that Figure 8 , the circuit topology in 10-14 is applied in Fig.17 When the first node N1 is in the state of being connected to the bias voltage terminal, the first node N1 is no longer connected to the bias voltage terminal. Figure 8 The topological application in Fig.17 For the impedance adjustment circuit 10, the first node N1 is no longer connected to the bias voltage terminal, and the first capacitor C1 and the LC resonant circuit are connected in series between the ground and the input terminal IN of the power amplifier tube; for the circuit 20, the first node N1 is no longer connected to the bias voltage terminal, and the first capacitor C1 and the LC resonant circuit are connected in series between the ground and the output terminal OUT of the power amplifier tube.

[0080] The circuit topology of the impedance adjustment circuit 10 and the circuit topology of the impedance adjustment circuit 20 may be the same or different.

[0081] Fig.18 Shows Fig.17 The exemplary impedance adjustment circuit 10 and the impedance adjustment circuit 20 in the embodiment of the present invention are shown in FIG. The exemplary impedance adjustment circuit 10 includes a first capacitor C1, an LC resonant circuit, a first inductor L1 and a first resistor R1. The exemplary impedance adjustment circuit 20 includes a first capacitor C1, an LC resonant circuit and a first inductor L1.

[0082] In the first embodiment, the input power supply bias circuit and the output power supply bias circuit are, for example, fabricated on the same chip as the power amplifier tube, and the chip and the input matching network, the output matching network, the impedance adjustment circuit 10, and the impedance adjustment circuit 20 are arranged on a PCB board. In the second embodiment, the input power supply bias circuit, the output power supply bias circuit, the power amplifier tube, the input matching network, the output matching network, the impedance adjustment circuit 10, and the impedance adjustment circuit 20 are all integrated on one chip. In the third embodiment, the power amplifier tube is fabricated separately on a chip, and one or more of the input power supply bias circuit, the output power supply bias circuit, the input matching network, the output matching network, the impedance adjustment circuit 10, and the impedance adjustment circuit 20 are fabricated on one chip, or one or more of the input power supply bias circuit, the output power supply bias circuit, the input matching network, the output matching network, the impedance adjustment circuit 10, and the impedance adjustment circuit 20 are fabricated on a PCB board. The input power supply bias circuit and the output power supply bias circuit can be, for example, fabricated using Figure 1 and Figure 3 The circuits in which the impedance adjustment circuit 10 and the impedance adjustment circuit 20 can overcome Figure 1 and Figure 3 The circuit in has a disadvantage at the second harmonic 2F0.

[0083] exist Fig.17 In the corresponding embodiment, the power amplifier circuit includes both the impedance adjustment circuit 10 and the impedance adjustment circuit 20. In other embodiments, the power amplifier circuit may include only one of the impedance adjustment circuit 10 and the impedance adjustment circuit 20.

[0084] Fig.19 is a schematic diagram of another power amplifier circuit according to an embodiment of the present invention. Fig.19 As shown, the power amplifier circuit includes: a power amplifier tube, an input matching network, an output matching network, an output power supply bias circuit, an impedance adjustment circuit 10 and an impedance adjustment circuit 20. The impedance adjustment circuit 10 is used as an input power supply bias circuit of the power amplifier tube. The impedance adjustment circuit 20 is used to adjust the external impedance of the output end OUT of the power amplifier tube, so that the external impedance of the output end OUT of the power amplifier tube is not affected at the fundamental wave F0, and has a low impedance characteristic (preferably short circuit) at the second harmonic 2F0.

[0085] In some other embodiments, the power amplifier circuit includes: a power amplifier tube, an input matching network, an output matching network, an input power supply bias circuit, an impedance adjustment circuit 10 and an impedance adjustment circuit 20. The impedance adjustment circuit 20 is used as an output power supply bias circuit of the power amplifier tube. The impedance adjustment circuit 10 is used to adjust the external impedance of the input terminal IN of the power amplifier tube, so that the external impedance of the input terminal IN of the power amplifier tube is not affected at the fundamental wave F0, and has a low impedance characteristic (preferably short circuit) at the second harmonic 2F0.

[0086] Fig. 20 : is a schematic diagram of an electronic device of an embodiment of the present invention. The electronic device is capable of accessing a wireless communication network and receiving and transmitting services from a wireless communication network. The electronic device is configured as an electronic product containing a wireless transmission function, such as a radar, a wireless base station, a repeater and a mobile terminal, including but not limited to a portable computer, an image capture terminal device (such as a digital camera), a game terminal device, a music storage and playback device, a mobile phone, a cellular phone, a smart phone, a tablet computer, a wearable device, a personal digital assistant PDA, a vehicle, etc. The electronic device includes a digital circuit, an analog-to-digital converter DAC, an oscillator OSC, a mixer, a power amplifier circuit, a bandpass filter and an antenna. The mixer, the power amplifier circuit, the bandpass filter and the antenna constitute the transmission link of the electronic device. The power amplifier circuit amplifies the radio frequency signal so that the radio frequency signal is transmitted through the antenna, thereby realizing wireless communication.

[0087] Although the embodiments are described and illustrated separately above, some common technologies are involved. It is the opinion of ordinary technicians in this field that the embodiments can be replaced and integrated. If the content is not clearly recorded in one of the embodiments, reference can be made to another recorded embodiment.

[0088] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. An impedance adjustment circuit, comprising: An LC resonant circuit and a first capacitor, wherein the first capacitor is connected between a first node and ground, and the LC resonant circuit is connected between the first node and an input end or an output end of a power amplifier tube to adjust the external impedance of the input end or the output end of the power amplifier tube.

2. The impedance adjustment circuit according to claim 1, further comprising a first resistor, wherein: The LC resonant circuit and the first resistor are connected in series between the first node and the input end or the output end of the power amplifier tube.

3. The impedance adjustment circuit according to claim 1, further comprising a first inductor, wherein: The LC resonant circuit and the first inductor are connected in series between the first node and the input end or the output end of the power amplifier tube.

4. The impedance adjustment circuit according to claim 1, further comprising a first resistor and a first inductor, wherein: The LC resonant circuit, the first resistor and the first inductor are connected in series between the first node and the input end or the output end of the power amplifier tube.

5. The impedance adjustment circuit according to any one of claims 1 to 4, wherein: The LC resonant circuit includes a second capacitor and a second inductor connected in parallel.

6. The impedance adjustment circuit according to claim 5, wherein: The impedance of the LC resonant circuit is maximum at frequency F0. Wherein, L is the inductance value of the second inductor, and C is the capacitance value of the second capacitor.

7. The impedance adjustment circuit according to any one of claims 1 to 4, wherein: The first node is also connected to a bias voltage terminal.

8. A power amplifier circuit, comprising: A power amplifier tube and an impedance adjustment circuit, wherein the impedance adjustment circuit comprises: an LC resonant circuit and a first capacitor, the first capacitor is connected between a first node and ground, and the LC resonant circuit is connected between the first node and an input end or an output end of the power amplifier tube to adjust the external impedance of the input end or the output end of the power amplifier tube.

9. The power amplifier circuit according to claim 8, wherein: The impedance adjustment circuit also includes a first resistor, wherein the LC resonant circuit and the first resistor are connected in series between the first node and the input end or the output end of the power amplifier tube.

10. The power amplifier circuit according to claim 8, wherein: The impedance adjustment circuit also includes a first inductor, wherein the LC resonant circuit and the first inductor are connected in series between the first node and the input end or the output end of the power amplifier tube.

11. The power amplifier circuit according to claim 8, wherein: The impedance adjustment circuit also includes a first resistor and a first inductor, wherein the LC resonant circuit, the first resistor and the first inductor are connected in series between the first node and the input end or the output end of the power amplifier tube.

12. The power amplifier circuit according to any one of claims 8 to 11, wherein: The LC resonant circuit includes a second capacitor and a second inductor connected in parallel.

13. The power amplifier circuit according to claim 12, wherein: The impedance of the LC resonant circuit is maximum at frequency F0. Wherein, L is the inductance value of the second inductor, and C is the capacitance value of the second capacitor.

14. The power amplifier circuit according to any one of claims 8 to 11, wherein: The first node is also connected to a bias voltage terminal.

15. The power amplifier circuit according to claim 8, wherein: The power amplifier circuit includes two impedance adjustment circuits, which include a first impedance adjustment circuit and a second impedance adjustment circuit. The first impedance adjustment circuit is connected to the input end of the power amplifier tube, and the second impedance adjustment circuit is connected to the output end of the power amplifier tube.

16. The power amplifier circuit according to claim 15, wherein: The first node of the first impedance adjustment circuit is connected to a first bias voltage terminal, and the first node of the second impedance adjustment circuit is connected to a second bias voltage terminal; Alternatively, the first node of the first impedance adjustment circuit is not connected to the first bias voltage terminal, and the first node of the second impedance adjustment circuit is connected to the second bias voltage terminal; Alternatively, the first node of the first impedance adjustment circuit is connected to a first bias voltage terminal, and the first node of the second impedance adjustment circuit is not connected to a second bias voltage terminal; Alternatively, the first node of the first impedance adjustment circuit is not connected to the first bias voltage terminal, and the first node of the second impedance adjustment circuit is not connected to the second bias voltage terminal.

17. The power amplifier circuit according to claim 8, wherein: The power amplifier tube comprises a gate, a source and a drain, the gate is the input end of the power amplifier tube, and the drain is the output end of the power amplifier tube; or The power amplifier tube comprises a base, an emitter and a collector, wherein the base is the input end of the power amplifier tube and the collector is the output end of the power amplifier tube.

18. The power amplifier circuit according to claim 8, wherein: The power amplifier tube is made on a gallium nitride, silicon, silicon germanium, gallium arsenide, or indium phosphide epitaxial layer.

19. An electronic device comprising the power amplifier circuit according to any one of claims 8 to 18.

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