Piezoelectric MEMS resonator and electronic component

Abstract

The invention relates to the field of semiconductor devices and provides a piezoelectric MEMS resonator and an electronic component. The resonator comprises a cap wafer and a device wafer, the cap wafer comprises a cap layer, and the device wafer comprises a substrate layer; the resonance cavity is arranged on the substrate layer; the device silicon layer is positioned on the upper side of the resonant cavity; the piezoelectric layer is positioned on the upper side of the device silicon layer; the top electrode is positioned on the upper side of the piezoelectric layer; the first dielectric layer is located on the upper side of the top electrode and covers the top electrode, the first dielectric layer is in bonding connection with the cap layer, and the projection of at least one part, bonded with the cap layer, of the first dielectric layer in the vertical direction is overlapped with the projection of the top electrode in the vertical direction; and at least the upper surface of the part, bonded with the cap layer, of the first dielectric layer is in the same plane. Therefore, the bonding characteristics of the cap wafer and the device wafer are improved by flattening the surface of the dielectric layer covering the top electrode, and a good bonding effect is ensured.

Description

Technical Field

[0001] The present application relates to the field of semiconductor devices, and in particular to a piezoelectric MEMS resonator and an electronic component. Background Art

[0002] The resonator is the core component of the oscillator. Since the electrostatically driven silicon-based MEMS resonator has a smaller size, lower manufacturing cost and higher reliability, the MEMS oscillator with the electrostatically driven silicon-based MEMS resonator as the core component is expected to become a substitute for the traditional quartz oscillator as the technology becomes more mature.

[0003] With the development of piezoelectric thin film materials, compared with electrostatically driven silicon-based MEMS resonators, piezoelectrically driven silicon-based MEMS resonators (referred to as "piezoelectrically driven silicon-based MEMS resonators") show excellent performance such as lower motional impedance and higher electromechanical coupling coefficient, which is more conducive to reducing the power consumption and phase noise of the oscillator.

[0004] Since piezoelectrically driven silicon-based MEMS resonators do not require the application of electrostatic bias voltage, the error term caused by power supply jitter on the output signal is reduced; in addition, piezoelectrically driven silicon-based MEMS resonators do not require the formation of sub-micron silicon layer slits during processing, which reduces the difficulty of the process, is beneficial to improving the device yield, and is also conducive to further miniaturization of the device.

[0005] Piezoelectrically driven silicon-based MEMS resonators often adopt a wafer-level packaging structure. In order to ensure that the piezoelectrically driven silicon-based MEMS resonator has a smaller size, the device wafer signal is usually led out through a conductive through-hole structure in the cap wafer, that is, a conductive through-hole structure for leading out the signal is formed in the silicon cap, thereby leading the electrode in the device layer to the outside of the package.

[0006] This section is intended to provide a background or context to the embodiments of the present application as recited in the claims. No admission is made that the description herein is prior art by inclusion in this section. Summary of the invention

[0007] The inventors have found that in the above-mentioned packaging structure, the process of processing the silicon cap with the conductive through hole is relatively complicated and involves many steps, resulting in high manufacturing cost and low yield, thereby increasing the cost of a single chip.

[0008] In addition, by using the conductive via structure in the cap wafer to lead out the device wafer signal, the device performance before and after bonding will be affected by the conductive via, thereby having a significant impact on the device frequency, impedance characteristics and other performance, which is not conducive to controlling these performances and maintaining consistency in device performance during production, and increases the on-chip fluctuation of device performance.

[0009] In addition, due to the presence of a patterned electrode layer in the device wafer, the surface of the dielectric layer deposited on the electrode layer is usually uneven, which affects the bonding characteristics of the cap wafer and the device wafer.

[0010] In order to solve at least one of the above problems or other similar problems, embodiments of the present application provide a piezoelectric MEMS resonator and an electronic component.

[0011] According to one aspect of an embodiment of the present application, a piezoelectric MEMS resonator is provided, the resonator comprising a cap wafer and a device wafer, the cap wafer comprising a cap layer,

[0012] The device wafer comprises:

[0013] substrate layer;

[0014] A resonant cavity disposed on the substrate layer;

[0015] A device silicon layer located on the upper side of the resonant cavity;

[0016] a piezoelectric layer located on the upper side of the device silicon layer;

[0017] a top electrode located on an upper side of the piezoelectric layer; and

[0018] a first dielectric layer located on the upper side of the top electrode and covering the top electrode,

[0019] The first dielectric layer is bonded to the cap layer, a projection of at least a portion of the first dielectric layer bonded to the cap layer in the vertical direction overlaps with a projection of the top electrode in the vertical direction, and an upper surface of at least a portion of the first dielectric layer bonded to the cap layer is in the same plane.

[0020] According to another aspect of an embodiment of the present application, an electronic component is provided, wherein the electronic component includes the resonator described in the above embodiment.

[0021] One of the beneficial effects of the embodiments of the present application is that the bonding characteristics of the cap wafer and the device wafer are improved by planarizing the surface of the dielectric layer covering the top electrode, thereby ensuring a good bonding effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0023] Figure 1FIG. 4 is a schematic top view of a piezoelectric MEMS resonator according to an embodiment of the present application.

[0024] Figure 2 yes Figure 1 The piezoelectric MEMS resonator is shown in a cross-sectional view along the AA' direction.

[0025] Figure 3 FIG. 4 is a cross-sectional view of another embodiment of the piezoelectric MEMS resonator according to the embodiment of the present application.

[0026] Figure 4 FIG. 4 is a cross-sectional view of another embodiment of the piezoelectric MEMS resonator according to the embodiment of the present application.

[0027] Figure 5 FIG. 4 is a cross-sectional view of another embodiment of the piezoelectric MEMS resonator according to the embodiment of the present application.

[0028] Figure 6 FIG. 4 is a cross-sectional view of another embodiment of the piezoelectric MEMS resonator according to the embodiment of the present application.

[0029] Figure 7 FIG. 4 is a cross-sectional view of another embodiment of the piezoelectric MEMS resonator according to the embodiment of the present application.

[0030] Figure 8 FIG. 4 is a cross-sectional view of another embodiment of the piezoelectric MEMS resonator according to the embodiment of the present application.

[0031] Fig. 9 FIG. 4 is a cross-sectional view of another embodiment of the piezoelectric MEMS resonator according to the embodiment of the present application.

[0032] Fig.10 FIG. 4 is a cross-sectional view of another embodiment of the piezoelectric MEMS resonator according to the embodiment of the present application.

[0033] Fig.11 FIG. 4 is a cross-sectional view of another embodiment of the piezoelectric MEMS resonator according to the embodiment of the present application.

[0034] Fig.12 FIG. 4 is a schematic diagram of another embodiment of the piezoelectric MEMS resonator of the present application.

[0035] Fig.13 yes Fig.12 The piezoelectric MEMS resonator is shown in a cross-sectional view along the AA' direction.

[0036] Fig.14 FIG. 4 is a cross-sectional view of another embodiment of the piezoelectric MEMS resonator according to the embodiment of the present application.

[0037] Fig.15 FIG. 4 is a cross-sectional view of another embodiment of the piezoelectric MEMS resonator according to the embodiment of the present application.

[0038] Fig.16 1 is a schematic top view of another embodiment of the piezoelectric MEMS resonator of the embodiment of the present application.

[0039] Fig.17 yes Fig.16 The piezoelectric MEMS resonator is shown as a cross-sectional view along the BB' direction. DETAILED DESCRIPTION

[0040] In order to make the purpose, technical solution and advantages of the embodiments of the present application more clear, the embodiments of the present application are further described in detail below in conjunction with the accompanying drawings. Here, the illustrative embodiments of the present application and their descriptions are used to explain the present application, but are not intended to limit the present application.

[0041] In the embodiments of the present application, the terms "first", "second", "upper", "lower", etc. are used to distinguish different elements in terms of title, but do not indicate the spatial arrangement or time order of these elements, etc., and these elements should not be limited by these terms. The term "and / or" includes any one and all combinations of one or more of the associated listed terms. The terms "comprising", "including", "having", etc. refer to the presence of the stated features, elements, components or components, but do not exclude the presence or addition of one or more other features, elements, components or components.

[0042] In the embodiments of the present application, the singular forms "a", "the", etc. include plural forms and should be broadly understood as "a kind" or "a type" rather than being limited to the meaning of "one"; in addition, the term "said" should be understood to include both singular and plural forms, unless the context clearly indicates otherwise. In addition, the term "according to" should be understood as "at least in part according to...", and the term "based on" should be understood as "at least in part based on...", unless the context clearly indicates otherwise.

[0043] The embodiments of the present application are described below with reference to the accompanying drawings.

[0044] The embodiment of the present application provides a piezoelectric MEMS resonator, which may be a silicon-based MEMS resonator based on piezoelectric drive, but the embodiment of the present application is not limited to this. The piezoelectric MEMS resonator of the present application is described below using a silicon-based MEMS resonator based on piezoelectric drive as an example.

[0045] Figure 1 is a top view schematic diagram of a piezoelectric MEMS resonator according to an embodiment of the present application, Figure 2 yes Figure 1 The piezoelectric MEMS resonator is shown in a cross-sectional view along the AA' direction.

[0046] like Figure 2As shown, the piezoelectric MEMS resonator (hereinafter referred to as "resonator") 1 includes a cap wafer 30 and a device wafer 20, the cap wafer 30 includes a cap layer 301, and the device wafer 20 includes a substrate layer 101, a resonant cavity 102 arranged on the substrate layer, a piezoelectric layer 202 located on the upper side of the resonant cavity 102, a top electrode 203 located on the upper side of the piezoelectric layer 202; and a first dielectric layer 204 located on the upper side of the top electrode 203 and covering the top electrode 203. In addition, in the case of no ambiguity, sometimes for the convenience of explanation, other layers in the device wafer 20 except the substrate layer 101 are collectively referred to as "device layers".

[0047] In some embodiments, Figure 2 As shown, the first dielectric layer 204 is bonded to the cap layer 301, the projection of at least a portion of the first dielectric layer 204 bonded to the cap layer 301 in the vertical direction overlaps with the projection of the top electrode 203 in the vertical direction, and the upper surface of at least the portion of the first dielectric layer 301 bonded to the cap layer 301 is in the same plane. It can also be said that at least the region of the upper surface of the first dielectric layer 301 bonded to the cap layer 301 is flat.

[0048] Thus, the bonding characteristics between the cap wafer and the device wafer are improved by planarizing the surface of the dielectric layer covering the top electrode, thereby ensuring a good bonding effect.

[0049] like Figure 1 As shown, the cap wafer 30 and the device wafer 20 are bonded in the first direction z. In the embodiment of the present application, the first direction z, the second direction x and the third direction y are perpendicular to each other. In addition, in the case of no ambiguity, the first direction z is sometimes referred to as the "vertical direction", and the second direction x and the third direction y are referred to as the "horizontal direction". In addition, for the convenience of description below, unless otherwise specified, the dimension in the first direction z is referred to as "thickness", the dimension in the second direction x is referred to as "width", and the dimension in the third direction y is referred to as "length"; for the first direction z, the direction from the device wafer 20 to the cap wafer 30 is referred to as "up", the direction from the cap wafer 30 to the device wafer 20 is referred to as "down", the surface located on the "upper" side is referred to as the "upper surface", and the surface located on the "lower" side is referred to as the "lower surface".

[0050] In some embodiments, the cap layer 301 of the cap wafer 30 may be formed of materials such as silicon or glass to protect the device active area of ​​the device wafer 20. In addition, for the convenience of description, the "cap layer" is sometimes referred to as a "silicon cap".

[0051] In some embodiments, the “device effective area” refers to, for example, an area where the resonant cavity 102 and the effective acoustic area of ​​the piezoelectric layer 202 overlap in the first direction z, for example, Figure 2As shown, the effective acoustic area of ​​the piezoelectric layer 202 is, for example, the area of ​​the piezoelectric layer 202 covered by the top electrode 203, and the "device effective area" is, for example, the portion of the resonant cavity 102 overlapping with the top electrode 203 in the first direction z.

[0052] In some embodiments, the substrate layer 101 may be formed of a semiconductor material, or may be formed of a composite of multiple layers of materials, which is not limited in the embodiments of the present application. For example, the substrate layer 101 may be formed of single crystal silicon, for example, formed of a high-resistance silicon material, the resistivity of the silicon material is, for example, greater than 1000Ω·cm, for example, the resistivity>5000Ω·cm, which is not limited in the embodiments of the present application. For example, the substrate layer 101 may also be formed of materials such as lithium niobate, lithium tantalate, silicon carbide (SiC), sapphire, quartz, etc. In addition, the substrate layer 101 may also be formed of semiconductor materials such as silicon dioxide, silicon nitride, polycrystalline silicon, amorphous silicon, etc., which is not limited in the embodiments of the present application.

[0053] In some embodiments, the resonant cavity 102 is a recess formed in the substrate layer 101, and the embodiments of the present application do not limit its formation process. In addition, although the word "cavity" is used for description, it can also be a Bragg reflection layer or other sound reflection layer with close or similar acoustic impedance characteristics to the "cavity". The embodiments of the present application do not limit the selection of the sound reflection structure, and can be designed according to actual needs. For example, when the Q value of the resonator is required to be high, the cavity can be selected as the sound reflection layer; when the heat dissipation performance or power of the resonator is required to be high, the Bragg reflection layer can be selected as the sound reflection layer. The following description takes the cavity as an example, and those skilled in the art should know that the embodiments of the present application are also applicable to sound reflection layers of other structures.

[0054] In some embodiments, the piezoelectric layer 202 can be formed of a piezoelectric film, for example, a piezoelectric film can be formed of a single crystal piezoelectric material. The embodiments of the present application do not limit the specific materials, and can be selected according to actual needs or performance requirements, for example, a material with a larger piezoelectric coupling coefficient corresponding to the transverse electric field excitation is selected, for example, a single crystal piezoelectric material such as lithium niobate or lithium tantalate is selected. The embodiments of the present application can make lithium niobate or lithium tantalate have larger d11 (or e11), d15 (or e15), d16 (or e16) piezoelectric coupling coefficients by selecting a suitable cut type and an angle between the in-plane interdigitated electrode and the crystal axis, thereby respectively enabling the resonator to excite a zero-order symmetric Lamb Wave mode, referred to as S0 mode, a first-order antisymmetric Lamb Wave mode, referred to as A1 mode, a zero-order horizontal shear mode, referred to as SH0 mode, and higher-order or lower-order modes of the above modes.

[0055] In addition, the wafer-level packaging structure of the embodiment of the present application is suitable for piezoelectrically driven silicon-based MEMS resonators with different vibration modes. There can be multiple planar structures of piezoelectrically driven silicon-based MEMS resonators, and the corresponding electrode arrangement structures are also different. There can also be multiple vibration modes, such as: in-plane flexural vibration mode (in-plane flexural mode), out-of-plane flexural vibration mode (out-of-plane flexural mode), width extension mode (Width extensional mode, referred to as WE mode), length extension mode (Length extensional mode, referred to as LE mode), Lamé mode, etc., but not limited to the above vibration modes. In addition, the resonant frequency that can be achieved by the resonator of the embodiment of the present application can, for example, cover a range from more than ten kHz to hundreds of MHz.

[0056] In some embodiments, the material forming the top electrode 203 may be a metal, for example, a single metal such as molybdenum (Mo), aluminum (Al), copper (Cu), platinum (Pt), tantalum (Ta), tungsten (W), palladium (Pd), ruthenium (Ru), gold (Au), titanium (Ti), chromium (Cr), or an alloy thereof, or a composite stack thereof; the material of the top electrode 203 may also be doped polysilicon, and the doping element may be boron (B), phosphorus (P), arsenic (As), or the like, and the doping concentration may be, for example, 10 19 cm -3 As mentioned above, the higher the doping concentration, the lower the sheet resistance of the electrode made of polysilicon will be, and the lower the electrical loss will be. The material selected to form the top electrode 203 can be determined according to actual needs, and the embodiment of the present application does not limit this.

[0057] In some embodiments, the material forming the first dielectric layer 204 can be silicon dioxide, fluorine-doped silicon dioxide, silicon nitride, silicon oxynitride, aluminum nitride, aluminum oxide, titanium oxide, tantalum pentoxide, etc., and can be a single layer or a combination of multiple layers of different dielectric materials. The first dielectric layer 204 can serve as a passivation layer of the resonator 1 and as an isolation layer between the signal line and the cap.

[0058] When the first dielectric layer 204 covers the surface of the resonant cavity, the first dielectric layer 204 also participates in the vibration of the resonant cavity. Therefore, the first dielectric layer 204 will affect the frequency, temperature drift characteristics and quality factor of the resonator. For example, the first dielectric layer 204 is formed of silicon dioxide material, which can also play a temperature compensation role on the resonator performance.

[0059] In some embodiments, a first dielectric layer 204 can be formed on the upper surface of the piezoelectric layer 202 including the top electrode 203 by a deposition process. At the location where the metal lead is located, the surface of the first dielectric layer 204 will be higher than other locations. If the thickness of the top electrode 203 is less than 1000A, the height difference will basically not affect the bonding characteristics. If the thickness of the top electrode 203 is greater than 1000A, the height difference will affect the bonding characteristics. Therefore, after the first dielectric layer 204 is deposited, a chemical mechanical polishing (CMP) can be performed on the first dielectric layer 204 to eliminate the surface height difference and ensure a good subsequent bonding effect. For example, the entire upper surface of the first dielectric layer 204 is flat.

[0060] In some embodiments, Figure 1 As shown, at least a portion of the projection of the top electrode 203 in the vertical direction z does not overlap with the projection of the cap layer 301 in the vertical direction z. Figure 2 As shown, the device wafer 20 also includes at least one first lead-out electrode P1 electrically connected to the top electrode 203, and at least one first lead-out electrode P1 passes through the first dielectric layer 204 from the portion of the top electrode 203 that does not overlap with the cap layer 301 and covers the area on the upper surface of the first dielectric layer 204 that is not covered by the cap layer.

[0061] Thus, it is possible to avoid processing a complex conductive through-hole structure in the silicon cap, thereby reducing the manufacturing cost and improving the chip manufacturing yield, thereby obtaining a low-cost resonator chip.

[0062] On the other hand, since the electrodes are led out laterally, the test pins and leads will not be changed before and after the cap wafer and the device wafer are bonded, so the performance of the device will hardly be affected by the bonding, which can improve the on-chip stability of the device performance. In the traditional structure, the device layer signal is led out through the conductive via structure in the cap wafer, and the device performance before and after bonding will be affected by the process of forming the conductive via. The process of forming the conductive via will have a great impact on the frequency and impedance characteristics of the device, which is not conducive to controlling the performance of the device to maintain good consistency, thereby increasing the on-chip fluctuation of the device performance.

[0063] In some embodiments, the first extraction electrode P1 is formed of a material such as gold, aluminum, copper, or an aluminum-copper alloy or an aluminum-silicon-copper alloy, which is not limited in the present embodiment of the application.

[0064] In some embodiments, Figure 2As shown, the device wafer 20 further includes a device silicon layer 201 located between the piezoelectric layer 202 and the substrate layer, and the device silicon layer 201 is a doped silicon layer. Thus, the device frequency-temperature characteristics can be improved. The device silicon layer 201 can be, for example, single crystal silicon or polycrystalline silicon. At the same time, in order to further improve the device frequency-temperature characteristics, the device silicon layer 201 can be heavily doped silicon, and the doping elements can be boron (B), phosphorus (P), arsenic (As), etc., and the doping concentration can be, for example, 10 19 cm -3 Above, optionally, the doping concentration is 10 20 cm -3 above, thereby making the resistivity lower than 1 mΩ·cm.

[0065] In some embodiments, at least a portion of the projection of the device silicon layer 201 in the vertical direction z does not overlap with the projection of the cap layer 301 in the vertical direction z. Figure 2 As shown, the device wafer 20 further includes a second extraction electrode P2 electrically connected to the upper surface of the device silicon layer 201, and the second extraction electrode P1 passes through the piezoelectric layer 202 and the first dielectric layer 204 from the portion of the device silicon layer 201 that does not overlap with the cap layer 301 and covers the area of ​​the upper surface of the first dielectric layer 204 that is not covered by the cap layer 301. Thus, the function of the bottom electrode of the piezoelectric layer 202 is realized through the device silicon layer 201. In addition, the forming material of the second extraction electrode P2 may be the same as or different from the forming material of the first extraction electrode P1, and the embodiment of the present application does not limit this.

[0066] Figure 3 FIG. 4 is a cross-sectional view of another embodiment of the piezoelectric MEMS resonator according to the embodiment of the present application.

[0067] In some embodiments, Figure 2 As shown, the device wafer 20 further includes a silicon oxide layer 207 located between the device silicon layer 201 and the substrate layer 101, and a portion of the silicon oxide layer 207 corresponding to the resonant cavity 102 is located on the lower surface of the device silicon layer 201. In addition, optionally, as Figure 3 As shown, a portion of the silicon oxide layer 103 corresponding to the resonant cavity 102 is formed on the upper surface of the substrate layer 101 .

[0068] For example, when forming a SOI wafer with a preset cavity (Cavity SOI, CSOI for short), a silicon oxide layer 207 used for bonding is formed below the device silicon layer 201. At this time, the silicon oxide layer 207 exists below the suspended area of ​​the device that is finally formed; optionally, when forming CSOI, a silicon oxide layer 103 used for bonding is formed on the surface of the substrate 101. At this time, there is no silicon oxide layer 103 below the suspended area of ​​the device that is finally formed.

[0069] In addition, the silicon oxide layer 207 or the silicon oxide layer 103 can be formed by a thermal oxidation method, or by other methods such as low-pressure chemical vapor deposition (LPCVD) and plasma enhanced chemical vapor deposition (PECVD). The specific formation method can refer to the relevant technology, and the embodiments of the present application are not limited to this.

[0070] Figure 4 FIG. 4 is a cross-sectional view of another embodiment of the piezoelectric MEMS resonator according to the embodiment of the present application.

[0071] In some embodiments, Figure 4 As shown, the device wafer 20 also includes a bottom electrode 208 located on the lower side of the piezoelectric layer 202 and at least one second lead-out electrode P2 electrically connected to the bottom electrode 208, at least a portion of the projection of the bottom electrode 202 in the vertical direction z does not overlap with the projection of the cap layer 301 in the vertical direction z, and at least one second lead-out electrode P2 passes through the piezoelectric layer 202 and the first dielectric layer 204 from the portion of the bottom electrode 208 that does not overlap with the cap layer 301 and covers the upper surface of the first dielectric layer 204.

[0072] For example, the bottom electrode 208 is located between the piezoelectric layer 202 and the device silicon layer 201 , thereby further reducing the motion impedance of the device and improving the reliability of the connection between the second lead electrode P2 and the device silicon layer 201 .

[0073] In addition, the bottom electrode 208 is, for example, a metal layer, for example, it can be made of a single metal such as molybdenum (Mo), aluminum (Al), copper (Cu), platinum (Pt), tantalum (Ta), tungsten (W), palladium (Pd), ruthenium (Ru), gold (Au), titanium (Ti), chromium (Cr), or an alloy thereof, or a composite stack thereof, and the embodiments of the present application are not limited to this.

[0074] In addition, Figure 3 The structure of the cap wafer 30 shown is different. Figure 4 The edge of the cap wafer 30 shown is formed with an eaves structure protruding outward in the horizontal direction, which is formed by different processing techniques and is not limited in the embodiment of the present application.

[0075] In some embodiments, Figure 2As shown, the device wafer also includes a sealing ring 205, and the first dielectric layer 204 is bonded to the cap layer 301 through the sealing ring 205. The sealing ring 205 is formed by at least one layer of metal material and / or dielectric material. For example, the metal material can be gold, aluminum, germanium, tin, copper and other metals, which are used to form metal-silicon bonding or metal-metal bonding, and can also include at least one layer of adhesion layer or barrier layer material, such as titanium (Ti), titanium tungsten (TiW), chromium (Cr) and other materials; the dielectric material can be silicon dioxide, glass paste (glass frit), etc., which can be used to bond with silicon wafers and glass wafers respectively. In addition, the material forming the sealing ring 205 can be the same as the material of the first electrode P1 or the second electrode P2. For example, the sealing ring 205 and the first electrode P1 or the second electrode P2 can be formed simultaneously by the same process. In addition, the material forming the sealing ring 205 can also be different from the material of the first electrode P1 or the second electrode P2, and the embodiment of the present application is not limited to this.

[0076] Figure 5 FIG. 4 is a cross-sectional view of another embodiment of the piezoelectric MEMS resonator according to the embodiment of the present application.

[0077] In some embodiments, Figure 5 As shown, the thickness of the portion of the first dielectric layer 204 bonded to the cap layer 301 is thicker than the thickness of the portion not bonded to the cap layer 301 .

[0078] For example, the first dielectric layer 204 is bonded to the cap layer 301 through the sealing ring 205, and the cap wafer 30 and the device wafer 20 can be bonded together by gold-silicon bonding. After the device layer is manufactured and before bonding with the cap wafer), sometimes in order to adjust the frequency of the resonator, it is necessary to adjust the thickness of the first dielectric layer 204. For example, the first dielectric layer 204 is silicon dioxide or aluminum nitride, or a stacked combination of the two materials. The first dielectric layer 204 can be subjected to ion beam frequency correction treatment, that is, the first dielectric layer 204 is thinned by ion beam bombardment. At this time, the first dielectric layer 204 below the sealing ring 205 is protected by the sealing ring 205, and its thickness remains unchanged, and the thickness of the first dielectric layer 204 not covered by the sealing ring 205 is thinned.

[0079] In some embodiments, Figures 1 to 5 As shown, the cap layer 301 and the first dielectric layer 204 form an upper cavity 302. The upper cavity 302 can be a cavity, or can include multiple sub-cavities, and the size (or "depth") of the upper cavity 302 in the first direction z can be set according to the vibration amplitude of the resonator, which is not limited in the embodiment of the present application.

[0080] In addition, if Figures 1 to 5As shown, the resonator 1 has a groove H that runs through the upper cavity 302 and the resonant cavity 102, thereby realizing the sealed package of the resonator 1. In addition, the sealing vacuum degree can be adjusted by adjusting the bonding parameters to realize packages of different pressures, for example, to realize normal pressure packaging, that is, consistent with the external atmospheric pressure or slightly less than the atmospheric pressure; or to realize high vacuum packaging, for example, less than 10Pa, or less than 1Pa, less than 0.1Pa, etc.; or to realize general vacuum packaging, for example, less than 100Pa, or less than 1kPa, etc. The corresponding vacuum degree can be selected according to actual needs, and the embodiment of the present application is not limited to this.

[0081] Figure 6 FIG. 4 is a cross-sectional view of another embodiment of the piezoelectric MEMS resonator according to the embodiment of the present application.

[0082] and Figure 4 The structure of the resonator shown is different in that Figure 6 The piezoelectric layer 202 or the first dielectric layer 204 of the resonator 1 shown is located in different planes from the end surface of the device silicon layer 201 on the groove H side, that is, the piezoelectric layer 202 or the first dielectric layer 204 is not flush with the end surface of the device silicon layer 201 on the groove H side.

[0083] In some embodiments, Figure 6 As shown, the end surfaces of the first dielectric layer 204 and the piezoelectric layer 202 on the groove H side can be flush, for example, the end surfaces of the first dielectric layer 204 and the piezoelectric layer 202 on the groove H side can be parallel to the vertical direction or inclined relative to the vertical direction; the end surfaces of the device silicon layer 201 and the silicon oxide layer 207 on the groove H side can also be flush, for example, parallel to the vertical direction; the end surface of the bottom electrode 208 on the groove H side is not flush with the end surfaces of the piezoelectric layer 202 and the device silicon layer 201 on its upper and lower sides.

[0084] For example, when the groove H is formed by an etching process, a distributed shell etching method can be used. For example, the piezoelectric layer 202 and the first dielectric layer 204 are formed by the same photolithography, and the bottom electrode 208 is formed by wet etching, which is 0 to 5 um smaller inward than the piezoelectric layer 202. Optionally, it is 1 to 2.5 um smaller inward than the piezoelectric layer 202. Finally, the device silicon layer 201 and the silicon oxide layer 207 are etched by a Bosch deep silicon etching process, so that the device silicon layer 201 and the silicon oxide layer 207 have a high verticality feature of nearly 90° on the end face of the groove H.

[0085] In addition, the embodiments of the present application are not limited thereto. For example, the first dielectric layer 204 and the piezoelectric layer 202 may not be flush at the end faces of the trench H, and the device silicon layer 201 and the silicon oxide layer 207 may not be flush at the end faces of the trench H. In addition, for example, Figures 2 to 5As shown, all layer structures may also be flush at the end surface of the trench H. For example, the trench H may be formed by a continuous etching method. This embodiment of the present application is not limited to this.

[0086] Figure 7 and Figure 8 They are cross-sectional views of another embodiment of the piezoelectric MEMS resonator according to the embodiment of the present application.

[0087] In some embodiments, the first dielectric layer 204 located in the active area of ​​the device can be removed by etching, thereby preventing the first dielectric layer 204 from affecting the device performance and only serving as an isolation layer between the signal line and the cap. Figure 7 and Figure 2 The difference is that, Figure 7 As shown, the first dielectric layer 204 corresponding to the device active area, for example, at least the suspended portion of the device layer, is etched and removed.

[0088] In some embodiments, Figure 8 As shown, the resonator 1 also has a second dielectric layer 209 located between the first dielectric layer 204 and the top electrode 203, and the second dielectric layer 209 and the first dielectric layer 204 may be formed of different materials. Therefore, the second dielectric layer 209 can be used as a passivation layer for the top electrode 203 and a barrier layer for etching the first dielectric layer 204, and can also be used as a temperature compensation layer for the resonator. For example, the first dielectric layer 204 is formed of silicon dioxide, and the second dielectric layer 209 is formed of aluminum nitride. In this case, the second dielectric layer 209 can be used as a passivation layer for the top electrode 203 to protect the metal, and the second dielectric layer 209 can be used as a barrier layer when etching the first dielectric layer 204. For another example, the first dielectric layer 204 is formed of silicon nitride, and the second dielectric layer 209 is formed of silicon dioxide. In this case, in addition to achieving the above-mentioned functions, the second dielectric layer 209 can also be used as a temperature compensation layer for the resonator. The embodiments of the present application are not limited to this.

[0089] Fig. 9 FIG. 4 is a cross-sectional view of another embodiment of the piezoelectric MEMS resonator according to the embodiment of the present application.

[0090] In some embodiments, the first dielectric layer 204 located in the active region of the device can be patterned by etching, thereby achieving simultaneous adjustment of the temperature coefficient and the frequency characteristic.

[0091] For example, Fig. 9 and Figure 8 The difference is that, Fig. 9As shown, the first dielectric layer 204 is etched into a predetermined pattern in the effective area of ​​the device, for example, at least the suspended part of the device layer, and the predetermined pattern can be set according to the required temperature coefficient and frequency characteristics. For example, the material density, stiffness, and temperature coefficient of the first dielectric layer 204 are different from those of the second dielectric layer 209, and the removal rates of the two are different during ion beam bombardment, so it is beneficial to achieve simultaneous adjustment of the temperature coefficient and frequency characteristics by ion beam bombardment.

[0092] Fig.10 FIG. 4 is a cross-sectional view of another embodiment of the piezoelectric MEMS resonator according to the embodiment of the present application.

[0093] In some embodiments, Fig.10 As shown, the cap wafer 30 further includes a metal layer 304, through which the cap layer 301 is bonded to the sealing ring 205, and the metal layer 304 is formed of at least one layer of metal material, thereby realizing a metal-metal bonding method, such as gold-gold bonding, aluminum-germanium bonding, gold-tin-copper bonding, etc.

[0094] In some embodiments, Fig.10 As shown, the cap wafer 30 further includes a first insulating layer 303 covering the outer surface of the cap layer 301, and the metal layer 304 is formed on the lower surface of the first insulating layer 303. For example, the cap wafer 30 is formed of single crystal silicon, and the first insulating layer 303 can be a silicon dioxide layer formed by thermal oxidation, thereby further reducing the parasitic capacitance generated by the cap wafer, or improving the bonding reliability and extending the device life.

[0095] Fig.11 FIG. 4 is a cross-sectional view of another embodiment of the piezoelectric MEMS resonator according to the embodiment of the present application.

[0096] In some embodiments, the device wafer 20 further includes a second insulating layer 215 located on the lower surface of the bottom electrode 208. Fig.11 As shown, Figure 4 Compared with the resonator shown in FIG. 1 , a second insulating layer 215 is added below the bottom electrode 208. The second insulating layer 215 can be formed of materials such as silicon dioxide, doped silicon oxide, silicon oxynitride, silicon nitride, aluminum oxide, aluminum nitride, titanium oxide, and tantalum pentoxide. The second insulating layer 215 can be a single layer or a combination of multiple layers of different dielectric materials. Since the bottom electrode 208 is insulated from the device silicon layer 201 by the second insulating layer 215, the bottom electrode 208 can be patterned into multiple electrode shapes to connect electrical signals of different polarities.

[0097] Fig.12 is a schematic diagram of another embodiment of the piezoelectric MEMS resonator of the embodiment of the present application, Fig.13 yes Fig.12A cross-sectional view of the piezoelectric MEMS resonator along the AA' direction is shown. Fig.14 and Fig.15 They are cross-sectional views of another embodiment of the piezoelectric MEMS resonator according to the embodiment of the present application.

[0098] In some embodiments, Fig.13 As shown, the device silicon layer 201 further includes a trench-shaped isolation layer 210 penetrating the device silicon layer 201 . The isolation layer 210 extends from a portion of the device silicon layer 201 located in the device active region to a portion corresponding to the second extraction electrode P2 .

[0099] like Fig.13 As shown, the isolation layer 210 includes a third insulating layer 211 filled in the groove. For example, a groove structure is etched in the device silicon layer 201, and the groove structure is filled with insulating materials such as silicon dioxide or a combination of silicon dioxide and polysilicon. Finally, the redundant insulating layer is removed by etching or CMP. For example, by CMP, only the Fig.13 The third insulating layer 211 is shown in the trench, but no insulating layer is retained on the surface of the device silicon layer 201.

[0100] like Fig.14 and Fig.15 As shown, the isolation layer 210 may also include a fourth insulating layer 212 located on the upper surface of the device silicon layer 201 , and the fourth insulating layer 212 is located on the portion of the upper surface of the device silicon layer 201 not covered by the second extraction electrode P2 and the piezoelectric layer 202 .

[0101] For example, after the insulating material is filled in the groove, the insulating layer on the surface of the device silicon layer 201 where the piezoelectric layer 202 needs to be grown and the insulating layer on the position where the second extraction electrode P2 needs to be connected is etched away by an etching method, while the insulating layer on other areas of the surface of the device silicon layer 201 is retained, thereby forming Fig.14 The fourth insulating layer 212 is shown.

[0102] For another example, after the insulating material is filled in the groove, the insulating layer at the position where the piezoelectric layer 202 needs to be grown on the surface of the device silicon layer 201 is etched away by an etching method, while the insulating layer in other areas of the surface of the device silicon layer 201 is retained. When the second lead electrode P2 is formed to connect to the bottom electrode, the first dielectric layer 204 and the piezoelectric layer 202 are etched, and then the insulating layer at the exposed position is etched away to expose the device silicon layer 201 or the bottom electrode.

[0103] Fig.16 is a schematic top view of another embodiment of the piezoelectric MEMS resonator of the embodiment of the present application, Fig.17 yes Fig.16 The piezoelectric MEMS resonator is shown as a cross-sectional view along the BB' direction.

[0104] In some embodiments, the sealing ring 205 may also be electrically connected to the bottom electrode of the piezoelectric layer 202 , thereby reducing the effect of the parasitic capacitance of the metal sealing ring 205 and the cap wafer 30 on the resonator, thereby improving the performance of the resonator.

[0105] For example, when the device silicon layer 201 is used as the bottom electrode of the piezoelectric layer 202, the sealing ring 205 can be electrically connected to the device silicon layer 201 through at least one conductive hole. Fig.17 As shown, the conductive hole P3 at least passes through the first dielectric layer 204 and the piezoelectric layer 202 and is electrically connected to the upper surface of the device silicon layer 201 . Fig.16 and 17 Only one conductive hole is shown, but the embodiment of the present application is not limited thereto, and multiple conductive holes may be provided according to actual needs.

[0106] In addition, optionally, in the case where the device wafer 20 includes a bottom electrode 208, the sealing ring 205 can be electrically connected to the bottom electrode 208 through at least one conductive hole, and the at least one conductive hole at least passes through the first dielectric layer 204 and the piezoelectric layer 202 to be electrically connected to the upper surface of the bottom electrode 208, or the at least one conductive hole can also pass through the first dielectric layer 204, the piezoelectric layer 202 and the bottom electrode 208 to be electrically connected to the device silicon layer 201.

[0107] In addition, the projection of the above-mentioned conductive hole in the vertical direction can overlap with the sealing ring 205, or can be located inside the annular area of ​​the sealing ring 205, or can be located outside the annular area of ​​the sealing ring 205. The embodiment of the present application does not limit the setting position of the conductive hole.

[0108] It can be seen from the above embodiments that the bonding characteristics of the cap wafer and the device wafer are improved by planarizing the surface of the dielectric layer covering the top electrode, thereby ensuring a good bonding effect.

[0109] An embodiment of the present application also provides an electronic component, which includes the piezoelectric MEMS resonator described in the above embodiment. Since the structure and characteristics of the piezoelectric MEMS resonator have been described in detail in the above embodiment, its content is incorporated here and the description is omitted here.

[0110] The electronic component of the embodiment of the present application is, for example, an oscillator, which includes the piezoelectric MEMS resonator described in any of the aforementioned embodiments, the contents of which are incorporated herein and the description thereof is omitted here.

[0111] In addition, the electronic components of the embodiments of the present application may be applied to a communication device that complies with the fifth-generation mobile communication standard or may be included in the communication device. For details, reference may be made to the relevant technology, and the embodiments of the present application are not limited to this.

[0112] The specific embodiments described above further illustrate the purpose, technical solutions and beneficial effects of the present application. It should be understood that the above description is only a specific embodiment of the present application and is not intended to limit the scope of protection of the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A piezoelectric MEMS resonator, comprising a cap wafer and a device wafer, characterized in that: The cap wafer comprises a cap layer, The device wafer comprises: substrate layer; A resonant cavity disposed on the substrate layer; A device silicon layer located on the upper side of the resonant cavity; a piezoelectric layer located on the upper side of the device silicon layer; a top electrode located on an upper side of the piezoelectric layer; and a first dielectric layer located on the upper side of the top electrode and covering the top electrode, The first dielectric layer is bonded to the cap layer, a projection of at least a portion of the first dielectric layer bonded to the cap layer in the vertical direction overlaps with a projection of the top electrode in the vertical direction, and an upper surface of at least a portion of the first dielectric layer bonded to the cap layer is in the same plane.

2. The resonator according to claim 1, characterized in that The upper surface of the first dielectric layer is flat.

3. The resonator according to claim 1, characterized in that The device wafer further includes at least one first extraction electrode electrically connected to the top electrode, At least a portion of a projection of the top electrode in the vertical direction does not overlap with a projection of the cap layer in the vertical direction, The at least one first extraction electrode passes through the first dielectric layer from a portion of the top electrode that does not overlap with the cap layer and covers a region of the upper surface of the first dielectric layer that is not covered by the cap layer.

4. The resonator according to claim 1, characterized in that The device wafer further includes a bottom electrode made of a metal material located at the lower side of the piezoelectric layer and at least one second extraction electrode electrically connected to the bottom electrode. At least a portion of the projection of the bottom electrode in the vertical direction does not overlap with the projection of the cap layer in the vertical direction, The at least one second extraction electrode passes through the piezoelectric layer and the first dielectric layer from a portion of the bottom electrode that does not overlap with the cap layer and covers an upper surface of the first dielectric layer.

5. The resonator according to claim 1, characterized in that The device silicon layer is a doped silicon layer, and the doping concentration of the device silicon layer is 10 19 cm -3 above.

6. The resonator according to claim 1, characterized in that The cap layer and the first dielectric layer form an upper cavity, The resonator has a groove penetrating the upper cavity and the resonant cavity.

7. The resonator according to claim 6, characterized in that The piezoelectric layer or the first dielectric layer and the end surface of the device silicon layer on the groove side are located in different planes.

8. The resonator according to claim 1, characterized in that The device wafer further includes a silicon oxide layer located between the device silicon layer and the substrate layer. The portion of the silicon oxide layer corresponding to the resonant cavity is located on the lower surface of the device silicon layer, or, A portion of the silicon oxide layer corresponding to the resonant cavity is formed on an upper surface of the substrate layer.

9. The resonator according to claim 1, characterized in that The resonator also has a second dielectric layer located between the first dielectric layer and the top electrode.

10. The resonator according to claim 1 or 9, characterized in that: The first dielectric layer located in the active region of the device is removed.

11. The resonator according to claim 1 or 9, characterized in that: The first dielectric layer located in the active area of ​​the device is patterned.

12. The resonator according to claim 1, characterized in that The device wafer further includes a sealing ring, the first dielectric layer is bonded to the cap layer via the sealing ring, and the sealing ring is formed by at least one layer of metal material and / or dielectric material.

13. The resonator according to claim 12, characterized in that A portion of the first dielectric layer bonded to the cap layer is thicker than a portion of the first dielectric layer not bonded to the cap layer.

14. The resonator according to claim 12, characterized in that The cap wafer further includes a metal layer, the cap layer is bonded to the sealing ring through the metal layer, and the metal layer is formed by at least one layer of metal material.

15. The resonator according to claim 14, characterized in that The cap wafer further includes a first insulating layer covering an outer surface of the cap layer, and the metal layer is formed on a lower surface of the first insulating layer.

16. The resonator according to claim 4, characterized in that The device wafer further includes a second insulating layer located on the lower surface of the bottom electrode.

17. The resonator according to claim 1 or 5, characterized in that The device wafer further includes a second extraction electrode electrically connected to the upper surface of the device silicon layer. At least a portion of a projection of the device silicon layer in the vertical direction does not overlap with a projection of the cap layer in the vertical direction, The second extraction electrode passes through the piezoelectric layer and the first dielectric layer from a portion of the device silicon layer that does not overlap with the cap layer and covers a region of the upper surface of the first dielectric layer that is not covered by the cap layer.

18. The resonator according to claim 17, characterized in that The device silicon layer further includes a trench-shaped isolation layer penetrating the device silicon layer, wherein the isolation layer extends from a portion of the device silicon layer located in the device active region to a portion corresponding to the second extraction electrode.

19. The resonator according to claim 18, characterized in that The isolation layer includes a third insulating layer filled in the trench.

20. The resonator according to claim 19, characterized in that The isolation layer further includes a fourth insulating layer located on the upper surface of the device silicon layer, The fourth insulating layer is located on a portion of the upper surface of the device silicon layer other than that covered by the second extraction electrode and the piezoelectric layer.

21. The resonator according to claim 12, characterized in that The sealing ring is electrically connected to the device silicon layer through at least one conductive hole.

22. The resonator according to claim 4, characterized in that The device wafer further includes a sealing ring, the first dielectric layer is bonded to the cap layer via the sealing ring, and the sealing ring is formed by at least one layer of metal material and / or dielectric material. The sealing ring is electrically connected to the bottom electrode through at least one conductive hole.

23. An electronic component, characterized in that: The electronic component comprises the resonator according to any one of claims 1 to 22.

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