Parallel error correction method based on FFT parallel period time-varying filter

Abstract

The invention discloses a parallel error correction method based on an FFT (Fast Fourier Transform) parallel period time-varying filter, which comprises the following steps that: a user can firstly select a sampling mode of a signal and then realize parallel error correction of an input signal through the FFT parallel period time-varying filter according to different sampling modes; in the error correction process, by means of optimization multiplexing of an FFT butterfly operation structure and optimization processing of the frequency domain data operation process, the operation speed is increased to the maximum extent, resources are saved, and meanwhile high-precision and high-real-time correction of the frequency response mismatch error is achieved.

Description

Technical Field

[0001] The present invention belongs to the technical field of error correction, and more specifically, relates to a parallel error correction method based on FFT parallel periodic time-varying filter. Background Art

[0002] The data acquisition system is a key module for realizing the digitization of analog signals. It has been widely used in the fields of communications, nuclear physics, deep space exploration, and measuring instruments. With the continuous advancement of technology, the signals in these fields are becoming more complex, with wider bandwidths and more obvious transient characteristics, which puts higher requirements on the performance of data acquisition systems. However, due to the limitations of existing integrated circuit processes, single-chip analog to digital converters (ADCs) are difficult to meet the various indicators of data acquisition systems, especially the sampling rate requirements.

[0003] Therefore, the acquisition system under the parallel architecture proposes a time-interleaved (TI) sampling architecture and a digital bandwidth interleaving (DBI) to achieve a sampling rate performance far exceeding that of a single-chip ADC, which has become the focus of current research.

[0004] However, in the actual acquisition system based on TI architecture, it is difficult to ensure that the parameters of the front-end circuits of each quantizer are completely consistent. Factors such as power dividers, circuit board layout and wiring, and mismatch of ADC internal parameters will lead to differences in the quantization signals of each sampling channel. These quantization differences will inevitably introduce errors when the final data is stitched together, which will appear as additional error spectra in the frequency domain. Fundamentally, these quantization differences are caused by the mismatch of frequency responses between sampling channels. In order to make the stitching result as close as possible to the ideal single ADC data acquisition system output, the frequency response mismatch error must be corrected.

[0005] Similar to the TI architecture, the actual acquisition system of the DBI architecture also faces the problem of inconsistent parameters between sub-band channels. Factors such as circuit layout, gain deviation, and characteristic differences of ADC sub-bands of different channels will lead to frequency response mismatch between sub-bands, resulting in phase inconsistency errors and amplitude distortion errors. These errors appear as additional noise and distortion in the frequency domain, affecting the accuracy of data after splicing. Especially under the requirements of high bandwidth and high sampling rate, the frequency overlap area between sub-bands has more stringent requirements for synchronization and matching. How to effectively correct the frequency response mismatch error has become a key technical challenge of the DBI architecture.

[0006] Among the existing error correction methods, patent CN110557122A uses multiple cascaded filter groups to correct the frequency response inconsistency error, but its resource consumption is large and it is difficult to apply to time-interleaved acquisition systems with more than 4 channels; at the same time, the implementation of IIR filters in FPGA cannot meet the real-time data processing requirements, which may lead to data accumulation problems during continuous sampling. Patent US7978104 uses frequency domain polynomials to approximate the frequency response of the sampling channel, but this method is only applicable to cases where the frequency response is relatively regular. Patent CN113114241B proposes a solution based on cascaded overlapping FFT, which can accurately correct the frequency response mismatch error under any number of channels and continuous data input. However, this method is first implemented serially, with low data throughput. Secondly, it processes data in the frequency domain, with high latency, which will greatly increase the dead time and reduce the waveform capture rate. At the same time, the frequency domain method will consume a lot of LUT resources in FPGA implementation. Finally, after IFFT, the method performs extraction, which consumes a lot of resources.

[0007] From the above analysis, it can be seen that there is currently a lack of a general error correction method that can effectively correct frequency response mismatch errors in parallel architecture acquisition systems while taking into account high throughput, low latency, low resource consumption, wide applicability and high real-time performance. Summary of the invention

[0008] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a parallel error correction method based on FFT parallel periodic time-varying filter, which realizes high-precision and high-real-time correction of frequency response mismatch error based on frequency domain FFT parallel filtering structure. The entire correction process relies entirely on hardware implementation, and maximizes the computing speed and saves resources.

[0009] To achieve the above-mentioned object of the invention, the present invention provides a parallel error correction method based on FFT parallel periodic time-varying filter, characterized in that it includes the following steps:

[0010] (1) Power on the digital oscilloscope and then connect it to any input signal, such as a sine signal, a multi-tone signal, etc.

[0011] (2) The user selects an acquisition mode of the acquisition system in the digital oscilloscope, including: an interleaved sampling mode and a non-interleaved sampling mode; if the interleaved sampling mode is selected, proceed to step (3); otherwise, proceed to step (4);

[0012] (3) Implement parallel error correction of input signals through FFT parallel periodic time-varying filters in interleaved sampling mode;

[0013] (4) Parallel error correction of the input signal is achieved through FFT parallel periodic time-varying filter in non-interleaved sampling mode.

[0014] The object of the invention of the present invention is achieved in this way:

[0015] The present invention is based on a parallel error correction method of an FFT parallel periodic time-varying filter. The user can first select a sampling mode of the signal, and then implement parallel error correction of the input signal through the FFT parallel periodic time-varying filter according to different sampling modes. In the error correction process, the present invention optimizes the reuse of the FFT butterfly operation structure and optimizes the frequency domain data operation process to maximize the operation speed and save resources while meeting the requirements of high-precision and high-real-time correction of frequency response mismatch errors.

[0016] At the same time, the parallel error correction method based on FFT parallel periodic time-varying filter of the present invention also has the following beneficial effects:

[0017] (1) The present invention proposes a universal FFT parallel error correction architecture based on FPGA, which has high universality. It only needs to adjust the filter working mode and configuration parameters (such as interleaved / non-interleaved mode, filter coefficient, etc.) according to the different requirements of the data acquisition system to achieve frequency response mismatch error correction under different acquisition architectures, thereby adapting to a variety of broadband data acquisition application scenarios.

[0018] (2) The present invention has remarkable high efficiency. Through the design of the FFT parallel filtering module, the system realizes full parallel processing in hardware, avoiding the serial calculation bottleneck of frequency domain data. Compared with the serial method, the present invention significantly improves the operation speed and is very suitable for data acquisition scenarios with high real-time requirements. At the same time, by optimizing the frequency domain filtering strategy and utilizing operations such as frequency domain averaging and parallel spectrum folding, storage resources are saved while reducing data correction delay and improving operation efficiency.

[0019] (3) The hardware design of the present invention has good scalability and is applicable to a wide range of real-time data processing needs. By optimizing the parallel design of the complex multiplier and the frequency domain filtering structure and the data splicing strategy and the frequency domain data processing algorithm, the filtering processing performance is improved and the back pressure control of the data stream is increased to reduce the possibility of data loss in a high-speed environment. In addition, the signal averaging process in the interleaved mode is the frequency domain averaging, which saves storage resources and reduces data correction delay. At the same time, a parallel spectrum folding method is used in the frequency domain filtering process to reduce the number of parallel paths in the IFFT process and save computing resources. The present invention provides a low-latency, high-throughput, high-stability, and resource-saving correction method. These design ideas can be used in data processing systems with other parallel filtering requirements, and provide reference and guidance for other high-performance data acquisition and error correction. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1It is a flow chart of a parallel error correction method based on FFT parallel periodic time-varying filter of the present invention;

[0021] Figure 2 It is a structural diagram of the FFT-based parallel periodic time-varying filter in interleaved mode;

[0022] Figure 3 This is the principle diagram of point loss and frame splicing;

[0023] Figure 4 This is a diagram of the parallel FFT butterfly structure in interleaved mode;

[0024] Figure 5 It is a complex multiplier structure diagram;

[0025] Figure 6 This is a structural diagram of a FFT-based parallel periodic time-varying filter in non-interleaved mode;

[0026] Figure 7 This is a diagram of the parallel FFT butterfly structure in non-interleaved mode. DETAILED DESCRIPTION

[0027] The specific implementation of the present invention is described below in conjunction with the accompanying drawings so that those skilled in the art can better understand the present invention. It should be noted that in the following description, when the detailed description of known functions and designs may dilute the main content of the present invention, these descriptions will be omitted here.

[0028] Example

[0029] In this embodiment, if Figure 1 As shown, the present invention provides a parallel error correction method based on FFT parallel periodic time-varying filter, comprising the following steps:

[0030] (1) Power on the digital oscilloscope and then connect it to any input signal, such as a sine signal, a multi-tone signal, etc.

[0031] (2) The user selects an acquisition mode of the acquisition system in the digital oscilloscope, including: an interleaved sampling mode and a non-interleaved sampling mode; if the interleaved sampling mode is selected, proceed to step (3); otherwise, proceed to step (4);

[0032] (3) Figure 2 As shown, in the interleaved sampling mode, the parallel error correction of the input signal is realized by the FFT parallel periodic time-varying filter;

[0033] (3.1) The FPGA in the digital oscilloscope configures the filter coefficients of the FFT parallel periodic time-varying filter in the interleaved sampling mode, and completes the initialization configuration of the FFT parallel periodic time-varying filter;

[0034] (3.2) The acquisition system in the digital oscilloscope acquires the input signal to obtain 8 parallel sampling data, and then inputs the 8 parallel sampling data into the FFT parallel periodic time-varying filter;

[0035] (3.3) In the FFT parallel periodic time-varying filter, the FIFO backpressure control module is used to control the 8-way parallel sampling data to be written into the front-stage FIFO in a fixed-length data frame. After the front-stage FIFO is full of a frame of data, the front-stage FIFO turns on the read enable and starts to read the data frame to the loss point module for subsequent processing, and finally writes it into the back-stage FIFO;

[0036] At this time, the front-stage FIFO is in the read and write states at the same time. If the number of frames written into the front-stage FIFO reaches the pre-full state, the FIFO backpressure control module controls the front-stage FIFO to turn off the write enable, and then continue to read the data frame under the read enable. After continuing to read a frame of data frame, the write enable is turned on to input the data frame;

[0037] When the number of data frames written into the subsequent FIFO reaches the pre-full state, the FIFO back pressure control module controls the previous FIFO to turn off the read enable, and then turns on the read enable of the previous FIFO after the subsequent FIFO continues to read a frame of data, and continues to read data frames, and so on;

[0038] (3.4), let the length of the data frame be N; each data frame is copied into a master and slave data frame after passing through the point loss module, wherein the master data frame is directly forwarded to the master frequency domain filtering module after passing through the point loss module; Figure 3 As shown, in the slave data frame, the point dropping module drops the first N / 2 points of the first frame data and then forms a new data frame with the first N / 2 points of the second frame data, the last N / 2 points of the second frame and the first N / 2 points of the third frame data form a new data frame, and so on, and then the data frames are forwarded to the frequency domain filtering module of the slave in sequence; in this embodiment, taking N equal to 2048 as an example, the main data frame is directly forwarded to the frequency domain filtering module of the main road after passing through the point dropping module, and in the slave data frame, the point dropping module drops the first 1024 points of the first frame data and then forms a new data frame with the first 1024 points of the second frame data, the last 1024 points of the second frame and the first 1024 points of the third frame data form a new data frame, and so on, and then the data frames are forwarded to the frequency domain filtering module of the slave in sequence;

[0039] (3.5) Perform frequency domain filtering on each data frame through the main frequency domain filtering module;

[0040] (3.5.1) In the main frequency domain filtering module, the 8rth point of each data frame is sent to the 0th FFT unit, the 8r+4th point is sent to the 1st FFT unit, the 8r+2th point is sent to the 2nd FFT unit, the 8r+6th point is sent to the 3rd FFT unit, the 8r+1th point is sent to the 4th FFT unit, the 8r+5th point is sent to the 5th FFT unit, the 8r+3th point is sent to the 6th FFT unit, and the 8r+7th point is sent to the 7th FFT unit, and then 8-way N / 8-point parallel FFT transformation is performed respectively to obtain the transformed spectrum:

[0041]

[0042] Among them, x(8r+i) represents the 8r+ith data point in the data frame, and the rotation factor r is the coefficient, i represents the number of the i-th time domain data before FFT transformation, and k represents the number of each frequency point in the spectrum after FFT transformation;

[0043] (3.5.2), such as Figure 4 As shown, the spectrum obtained by transforming each FFT unit is subjected to butterfly operation to obtain the final output spectrum of each FFT unit;

[0044]

[0045] Where m represents the mth frequency domain output after butterfly operation, m = 0, 1, 2, ..., 7; the intermediate quantity

[0046]

[0047] (3.5.3) Perform frequency domain averaging on the 0th FFT unit output spectrum X(k), that is, cache the 0th frequency point in the output spectrum X(k) and assign the spectrum value to 0;

[0048] Perform path delay processing on the output spectra of the remaining 7 FFT units to align the timing of the output spectrum data of the 8 FFT units;

[0049] (3.5.4), such as Figure 5 As shown, the 8-channel spectrum data after time sequence alignment are sent to the master and slave complex multipliers respectively, wherein the master complex multiplier directly multiplies the 8-channel spectrum data with the filter coefficients at the corresponding frequency points, and the result is input to the main spectrum folding unit; in the slave complex multiplier, the filter coefficients at each frequency point are first multiplied by the rotation factor Then, the complex number is multiplied with the 8-channel spectrum data, and the result is input into the main spectrum folding unit;

[0050] (3.5.5) The main spectrum folding unit performs odd-numbered folding processing on the 8-channel spectrum data output by the main complex multiplier, and outputs even-numbered spectrum data; the even-numbered spectrum data is then input into the merging unit after being subjected to 4-channel N / 8-point parallel inverse transformation of the main IFFT unit;

[0051] The spectrum folding unit performs even-channel folding processing on the 8-channel spectrum data output from the complex multiplier, and outputs odd-channel spectrum data; the odd-channel spectrum data is then input to the merging unit after being inversely transformed by 4-channel N / 8 points of parallel inversion from the IFFT unit;

[0052] Finally, the merging unit merges the odd-path and even-path data to obtain the filtering output of the main-path frequency domain filtering module;

[0053] (3.6) Similarly, by performing frequency domain filtering on each data frame from the frequency domain filtering module, a filtering output of the frequency domain filtering module from the path is obtained;

[0054] (3.7), such as Figure 3 In the middle gray part, the output data of the master and slave frequency domain filter modules are overlapped and spliced, and then sent to the post-stage FIFO, and the data frame is written into the post-stage FIFO through the FIFO backpressure control module. When the post-stage FIFO is full of a frame of data, the post-stage FIFO turns on the read enable and starts to read the data frame as the output data of the FFT parallel periodic time-varying filter;

[0055] At this time, the subsequent FIFO is in the reading and writing states at the same time. If the number of data frames written by the subsequent FIFO reaches the pre-full state, the FIFO back pressure control module controls the previous FIFO to turn off the read enable, and the subsequent FIFO continues to read the data frame under the read enable. After continuing to read one frame of data frame, the read enable of the previous FIFO is turned on, and so on.

[0056] (4) Figure 6 As shown, parallel error correction of the input signal is implemented by FFT parallel periodic time-varying filter in non-interleaved sampling mode;

[0057] (4.1) The FPGA in the digital oscilloscope configures the filter coefficients of the FFT parallel periodic time-varying filter in the non-interleaved sampling mode, and completes the initialization configuration of the FFT parallel periodic time-varying filter;

[0058] (4.2) The acquisition system in the digital oscilloscope acquires input signals and obtains two sets of non-interleaved 4-way parallel sampling data of two acquisition channels ch1 and ch2, and then inputs these 8-way parallel sampling data into the FFT parallel periodic time-varying filter;

[0059] (4.3) In the FFT parallel periodic time-varying filter, the FIFO backpressure control module is used to control the 8-way parallel sampling data to be written into the front-stage FIFO in a fixed-length data frame. After the front-stage FIFO is full of a frame of data, the front-stage FIFO turns on the read enable and starts to read the data frame to the loss point module for subsequent processing, and finally writes it into the back-stage FIFO;

[0060] At this time, the front-stage FIFO is in the read and write states at the same time. If the number of frames written into the front-stage FIFO reaches the pre-full state, the FIFO backpressure control module controls the front-stage FIFO to turn off the write enable, and then continue to read the data frame under the read enable. After continuing to read a frame of data frame, the write enable is turned on to input the data frame;

[0061] When the number of data frames written into the subsequent FIFO reaches the pre-full state, the FIFO back pressure control module controls the previous FIFO to turn off the read enable, and then turns on the read enable of the previous FIFO after the subsequent FIFO continues to read a frame of data, and continues to read data frames, and so on;

[0062] (4.4) Assume that the length of the data frames of channels ch1 and ch2 are both M=N / 2; each data frame is copied into a master and a slave data frame after passing through the point dropping module, wherein the master data frame is directly forwarded to the master frequency domain filtering module after passing through the point dropping module; in the slave data frame, the point dropping module drops the first M / 2 points of the first frame data and then forms a new data frame with the first M / 2 points of the second frame data, the last M / 2 points of the second frame and the first M / 2 points of the third frame data form a new data frame, and so on, and then the data frame is The data frames are forwarded to the frequency domain filtering module of the slave road in sequence; in this embodiment, N is equal to 2048 as an example, then M is equal to 1024, the master road data frame is directly forwarded to the frequency domain filtering module of the master road after passing through the point dropping module, in the slave road data frame, the point dropping module drops the first 512 points of the first frame data and then forms a new data frame with the first 512 points of the second frame data, the last 512 points of the second frame and the first 512 points of the third frame data form a new data frame, and so on, and then the data frames are forwarded to the frequency domain filtering module of the slave road in sequence;

[0063] (4.5) Perform frequency domain filtering on each data frame through the main frequency domain filtering module;

[0064] (4.5.1) In the main frequency domain filtering module, the 4r1th point of each data frame of channel ch1 is sent to the 0th FFT unit, the 4r1+2th point is sent to the 1st FFT unit, the 4r1+1th point is sent to the 2nd FFT unit, and the 4r1+3th point is sent to the 3rd FFT unit, and a 4-way M / 4-point parallel FFT transformation is performed to obtain the transformed spectrum:

[0065]

[0066] Among them, x(4r1+i1) represents the 4r1+i1th data point in each data frame of channel ch1, and the rotation factor r1 is the coefficient, i1 represents the number of the i1th time domain data of channel ch1 before FFT transformation, and k1 represents the number of each frequency point in the spectrum after FFT transformation;

[0067] The 4r2th point of each data frame of channel ch2 is sent to the 4th FFT unit, the 4r2+2th point is sent to the 5th FFT unit, the 4r2+1th point is sent to the 6th FFT unit, and the 4r2+3th point is sent to the 7th FFT unit, and a 4-way M / 4-point parallel FFT transformation is performed to obtain the transformed spectrum:

[0068]

[0069] Among them, x(4r2+i2) represents the 4r2+i2th data point in each data frame of channel ch2, and the rotation factor r2 is the coefficient, i2 represents the i2th time domain data of channel ch2 before FFT transformation, and k2 represents the number of each frequency point in the spectrum after FFT transformation;

[0070] (4.5.2), such as Figure 7 As shown, the spectrum obtained by transforming the four FFT units corresponding to channel ch1 and channel ch2 is subjected to butterfly operation to obtain the final output spectrum of the four FFT units:

[0071]

[0072] The parameter j represents the number of the acquisition channel, j = 1, 2; the parameter m j Indicates the mth channel j corresponding to the butterfly operation j Frequency domain output, m j =0,1,2,3;B ji (k j ) is an intermediate variable,

[0073] (4.5.3) Send the spectrum outputs of the 4 FFT units corresponding to channel ch1 to the master complex multiplier, and send the spectrum outputs of the 4 FFT units corresponding to channel ch2 to the slave complex multiplier, wherein the master complex multiplier directly multiplies the 4-channel spectrum data with the filter coefficients at the corresponding frequency points, and the result data are then respectively input through the 4-channel M / 4-point parallel inverse transformation of the master and slave IFFT units to obtain the filter output of the main frequency domain filter module;

[0074] (4.6) Similarly, by performing frequency domain filtering on each data frame from the frequency domain filtering module, a filtering output of the frequency domain filtering module from the path is obtained;

[0075] (4.7) The output data of the master and slave frequency domain filter modules are overlapped and spliced, and then sent to the post-stage FIFO, and the data frame is written into the post-stage FIFO through the FIFO backpressure control module. When the post-stage FIFO is full of a frame of data, the post-stage FIFO turns on the read enable and starts to read the data frame as the output data of the FFT parallel periodic time-varying filter;

[0076] At this time, the subsequent FIFO is in the reading and writing states at the same time. If the number of data frames written by the subsequent FIFO reaches the pre-full state, the FIFO back pressure control module controls the previous FIFO to turn off the read enable, and the subsequent FIFO continues to read the data frame under the read enable. After continuing to read one frame of data frame, the read enable of the previous FIFO is turned on, and so on.

[0077] Although the above describes the illustrative specific embodiments of the present invention to facilitate those skilled in the art to understand the present invention, it should be clear that the present invention is not limited to the scope of the specific embodiments. For those of ordinary skill in the art, as long as various changes are within the spirit and scope of the present invention as defined and determined by the attached claims, these changes are obvious, and all inventions and creations using the concept of the present invention are protected.

Claims

1. A parallel error correction method based on FFT parallel periodic time-varying filter, characterized in that: The following steps are involved: (1) Power on the digital oscilloscope and connect it to the input signal; (2) The user selects an acquisition mode of the acquisition system in the digital oscilloscope, including: an interleaved sampling mode and a non-interleaved sampling mode; if the interleaved sampling mode is selected, proceed to step (3); otherwise, proceed to step (4); (3) Implement parallel error correction of input signals through FFT parallel periodic time-varying filters in interleaved sampling mode; (4) Parallel error correction of the input signal is achieved through FFT parallel periodic time-varying filter in non-interleaved sampling mode.

2. The parallel error correction method based on FFT parallel periodic time-varying filter according to claim 1 is characterized in that: The method for implementing parallel error correction of input signals by using FFT parallel periodic time-varying filters in the interleaved sampling mode is: (2.1) The FPGA in the digital oscilloscope configures the filter coefficients of the FFT parallel periodic time-varying filter in the interleaved sampling mode, and completes the initialization configuration of the FFT parallel periodic time-varying filter; (2.2) The acquisition system in the digital oscilloscope acquires the input signal to obtain 8 parallel sampling data, and then inputs the 8 parallel sampling data into the FFT parallel periodic time-varying filter; (2.3) In the FFT parallel periodic time-varying filter, the 8-way parallel sampling data is first controlled by the FIFO backpressure control module to be written into the front-stage FIFO in a fixed-length data frame. After the front-stage FIFO is full of a frame of data, the front-stage FIFO turns on the read enable and starts to read the data frame to the loss point module for subsequent processing, and finally writes it into the back-stage FIFO; At this time, the front-stage FIFO is in the read and write states at the same time. If the number of frames written into the front-stage FIFO reaches the pre-full state, the FIFO backpressure control module controls the front-stage FIFO to turn off the write enable, and then continue to read the data frame under the read enable. After continuing to read a frame of data frame, the write enable is turned on to input the data frame; When the number of data frames written into the subsequent FIFO reaches the pre-full state, the FIFO back pressure control module controls the previous FIFO to turn off the read enable, and then turns on the read enable of the previous FIFO after the subsequent FIFO continues to read a frame of data, and continues to read data frames, and so on; (2.4) Let the length of the data frame be N; Each data frame is copied into two data frames, the master and slave, after passing through the point dropping module. The master data frame is directly forwarded to the frequency domain filtering module of the master after passing through the point dropping module. In the slave data frame, the point dropping module drops the first N / 2 points of the first frame data and then forms a new data frame with the first N / 2 points of the second frame data. The last N / 2 points of the second frame and the first N / 2 points of the third frame data form a new data frame, and so on. The data frames are then forwarded to the frequency domain filtering module of the slave in sequence. (2.5) Perform frequency domain filtering on each data frame through the main frequency domain filtering module; (2.5.1) In the main frequency domain filtering module, the 8rth point of each data frame is sent to the 0th FFT unit, the 8r+4th point is sent to the 1st FFT unit, the 8r+2th point is sent to the 2nd FFT unit, the 8r+6th point is sent to the 3rd FFT unit, the 8r+1th point is sent to the 4th FFT unit, the 8r+5th point is sent to the 5th FFT unit, the 8r+3th point is sent to the 6th FFT unit, and the 8r+7th point is sent to the 7th FFT unit, and then 8-way N / 8-point parallel FFT transformation is performed respectively to obtain the transformed spectrum: Among them, x(8r+i) represents the 8r+ith data point in the data frame, and the rotation factor r is the coefficient, i represents the number of the i-th time domain data before FFT transformation, and k represents the number of each frequency point in the spectrum after FFT transformation; (2.5.2) Perform butterfly operation on the spectrum obtained by transforming each FFT unit to obtain the final output spectrum of each FFT unit; Where m represents the mth frequency domain output after butterfly operation, m = 0, 1, 2, ..., 7; the intermediate quantity (2.5.3) Perform frequency domain averaging on the 0th FFT unit output spectrum X(k), that is, cache the 0th frequency point in the output spectrum X(k) and assign the spectrum value to 0; Perform path delay processing on the output spectra of the remaining 7 FFT units to align the timing of the output spectrum data of the 8 FFT units; (2.5.4) The 8-channel spectrum data after time alignment are sent to the master and slave complex multipliers respectively. In the master complex multiplier, the 8-channel spectrum data is directly multiplied by the filter coefficients at the corresponding frequency points, and the result is input to the main spectrum folding unit; in the slave complex multiplier, the filter coefficients at each frequency point are first multiplied by the rotation factor Then, the complex number is multiplied with the 8-channel spectrum data, and the result is input into the main spectrum folding unit; (2.5.5) The main spectrum folding unit performs odd-numbered ... The spectrum folding unit performs even-channel folding processing on the 8-channel spectrum data output from the complex multiplier, and outputs odd-channel spectrum data; the odd-channel spectrum data is then input to the merging unit after being inversely transformed by 4-channel N / 8 points of parallel inversion from the IFFT unit; Finally, the merging unit merges the odd-path and even-path data to obtain the filtering output of the main-path frequency domain filtering module; (2.6) Similarly, by performing frequency domain filtering on each data frame from the frequency domain filtering module, a filtering output of the frequency domain filtering module from the path is obtained; (2.7) The output data of the master and slave frequency domain filter modules are overlapped and spliced, and then sent to the post-stage FIFO, and the data frame is written into the post-stage FIFO through the FIFO backpressure control module. When the post-stage FIFO is full of a frame of data, the post-stage FIFO turns on the read enable and starts to read the data frame as the output data of the FFT parallel periodic time-varying filter; At this time, the subsequent FIFO is in the reading and writing states at the same time. If the number of data frames written by the subsequent FIFO reaches the pre-full state, the FIFO back pressure control module controls the previous FIFO to turn off the read enable, and the subsequent FIFO continues to read the data frame under the read enable. After continuing to read one frame of data frame, the read enable of the previous FIFO is turned on, and so on.

3. The parallel error correction method based on FFT parallel periodic time-varying filter according to claim 1 is characterized in that: The method for implementing parallel error correction of input signals by using FFT parallel periodic time-varying filters in the non-interleaved sampling mode is: (3.1) The FPGA in the digital oscilloscope configures the filter coefficients of the FFT parallel periodic time-varying filter in the non-interleaved sampling mode, and completes the initialization configuration of the FFT parallel periodic time-varying filter; (3.2) The acquisition system in the digital oscilloscope acquires the input signal and obtains two sets of non-interleaved 4-way parallel sampling data of two acquisition channels ch1 and ch2, and then inputs these 8-way parallel sampling data into the FFT parallel periodic time-varying filter; (3.3) In the FFT parallel periodic time-varying filter, the FIFO backpressure control module is used to control the 8-way parallel sampling data to be written into the front-stage FIFO in a fixed-length data frame. After the front-stage FIFO is full of a frame of data, the front-stage FIFO turns on the read enable and starts to read the data frame to the loss point module for subsequent processing, and finally writes it into the back-stage FIFO; At this time, the front-stage FIFO is in the read and write states at the same time. If the number of frames written into the front-stage FIFO reaches the pre-full state, the FIFO backpressure control module controls the front-stage FIFO to turn off the write enable, and then continue to read the data frame under the read enable. After continuing to read a frame of data frame, the write enable is turned on to input the data frame; When the number of data frames written into the subsequent FIFO reaches the pre-full state, the FIFO back pressure control module controls the previous FIFO to turn off the read enable, and then turns on the read enable of the previous FIFO after the subsequent FIFO continues to read a frame of data, and continues to read data frames, and so on; (3.4) Assume that the length of the data frames of channels ch1 and ch2 are both M=N / 2; Each data frame is copied into two data frames, the master and slave, after passing through the point dropping module. The master data frame is directly forwarded to the frequency domain filtering module of the master after passing through the point dropping module. In the slave data frame, the point dropping module drops the first M / 2 points of the first frame data and then forms a new data frame with the first M / 2 points of the second frame data, and the last M / 2 points of the second frame and the first M / 2 points of the third frame data form a new data frame, and so on. Then the data frames are forwarded to the frequency domain filtering module of the slave in sequence. (3.5) Perform frequency domain filtering on each data frame through the main frequency domain filtering module; (3.5.1) In the main frequency domain filtering module, the 4r1th point of each data frame of channel ch1 is sent to the 0th FFT unit, the 4r1+2th point is sent to the 1st FFT unit, the 4r1+1th point is sent to the 2nd FFT unit, and the 4r1+3th point is sent to the 3rd FFT unit, and a 4-way M / 4-point parallel FFT transformation is performed to obtain the transformed spectrum: Among them, x(4r1+i1) represents the 4r1+i1th data point in each data frame of channel ch1, and the rotation factor r1 is the coefficient, i1 represents the number of the i1th time domain data of channel ch1 before FFT transformation, and k1 represents the number of each frequency point in the spectrum after FFT transformation; The 4r2th point of each data frame of channel ch2 is sent to the 4th FFT unit, the 4r2+2th point is sent to the 5th FFT unit, the 4r2+1th point is sent to the 6th FFT unit, and the 4r2+3th point is sent to the 7th FFT unit, and a 4-way M / 4-point parallel FFT transformation is performed to obtain the transformed spectrum: Among them, x(4r2+i2) represents the 4r2+i2th data point in each data frame of channel ch2, and the rotation factor r2 is the coefficient, i2 represents the i2th time domain data of channel ch2 before FFT transformation, and k2 represents the number of each frequency point in the spectrum after FFT transformation; (3.5.2) Perform butterfly operation on the spectrum obtained by transforming the four FFT units corresponding to channel ch1 and channel ch2, and obtain the final output spectrum of the four FFT units: The parameter j represents the number of the acquisition channel, j = 1, 2; the parameter m j Indicates the mth channel j corresponding to the butterfly operation j Frequency domain output, m j =0,1,2,3;B ji (k j ) is an intermediate variable, (3.5.3) Send the spectrum outputs of the 4 FFT units corresponding to channel ch1 to the master complex multiplier, and send the spectrum outputs of the 4 FFT units corresponding to channel ch2 to the slave complex multiplier, wherein the master complex multiplier directly multiplies the 4-channel spectrum data with the filter coefficients at the corresponding frequency points, and the result data are then respectively input through the 4-channel M / 4-point parallel inverse transformation of the master and slave IFFT units to obtain the filter output of the main frequency domain filter module; (3.6) Similarly, by performing frequency domain filtering on each data frame from the frequency domain filtering module, a filtering output of the frequency domain filtering module from the path is obtained; (3.7) The output data of the master and slave frequency domain filter modules are overlapped and spliced, and then sent to the post-stage FIFO, and the data frame is written into the post-stage FIFO through the FIFO backpressure control module. When the post-stage FIFO is full of a frame of data, the post-stage FIFO turns on the read enable and starts to read the data frame as the output data of the FFT parallel periodic time-varying filter; At this time, the subsequent FIFO is in the reading and writing states at the same time. If the number of data frames written by the subsequent FIFO reaches the pre-full state, the FIFO back pressure control module controls the previous FIFO to turn off the read enable, and the subsequent FIFO continues to read the data frame under the read enable. After continuing to read one frame of data frame, the read enable of the previous FIFO is turned on, and so on.

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