High-sensitivity delay unit and circuit for detecting threshold voltage

Abstract

A circuit configured to detect a threshold voltage includes a first delay circuit, a second delay circuit, and a controller. The first delay circuit has a first sensitivity to a threshold voltage of a transistor value. The first delay circuit may be configured to generate a first output signal delayed by a first delay time relative to the input signal, the first delay time changing in accordance with the digital control code. The second delay circuit has a second sensitivity higher than the first sensitivity. The second delay circuit may be configured to generate a second output signal delayed by a second delay time relative to the input signal. The controller may compare the first output signal to the second output signal and generate a digital output code corresponding to the digital control code to indicate a threshold voltage of the transistor when the first delay time is equal to the second delay time.

Description

Technical Field

[0001] The present disclosure relates generally to semiconductor integrated circuits, and more particularly to a high-sensitivity delay cell and a circuit for detecting a threshold voltage of a transistor using the high-sensitivity delay cell. Background Art

[0002] As process miniaturization continues to advance according to Moore's Law, variables such as threshold voltage and channel length of transistors such as metal oxide semiconductor field effect transistors (MOSFETs) also become smaller. During this miniaturization process, the impact of process variations increases. Because these process variations can be critical (and can be very critical) to the performance of the integrated circuit, designers of semiconductor integrated circuits must take them into account.

[0003] Among the variables that vary according to the process, the threshold voltage can have a relatively large impact on the performance and power of the integrated circuit, so the design of the integrated circuit must take into account the change in the threshold voltage. In addition, as semiconductor chips become more and more complex, on-chip calibration becomes more and more important, so the need for circuits to detect the threshold voltage inside the semiconductor chip is increasing. The threshold voltage detection circuit may need to be able to operate in a variety of environments in order to perform on-chip operations. As reducing power consumption becomes more and more important, many circuits operating at low voltages are increasingly expected. The threshold voltage detection circuit must be designed to operate in such an environment.

[0004] In addition, dynamic voltage and frequency scaling (DVFS), which can change the operating clock frequency in various circuits such as processors, memory interfaces, etc., is being applied to power management, so the operating clock frequency of the threshold voltage detection circuit can be frequently changed. To operate in such an environment, the threshold voltage detection circuit must be able to operate within a wide frequency range. Summary of the invention

[0005] Some example embodiments may provide a circuit capable of detecting a threshold voltage of a transistor in a relatively efficient manner.

[0006] Some example embodiments may provide a delay unit having high sensitivity to a threshold voltage of a transistor.

[0007] According to some embodiments, a circuit for detecting a threshold voltage may include a first delay circuit, a second delay circuit, and a controller. The first delay circuit may have a first sensitivity to the threshold voltage of a transistor. The first delay circuit may be configured to receive an input signal and a digital control code, and may generate a first output signal delayed by a first delay time relative to the input signal, the first delay time being changed according to the digital control code. The second delay circuit may have a second sensitivity higher than the first sensitivity. The second delay circuit may be configured to receive the input signal and may generate a second output signal delayed by a second delay time relative to the input signal. The controller may compare the first output signal with the second output signal by changing the digital control code, and may generate a digital output code corresponding to the digital control code in response to the first delay time being equal to the second delay time, so that the digital output code indicates the threshold voltage of the transistor.

[0008] According to some embodiments, a circuit for detecting a threshold voltage may include: a pulse generator, which is configured to generate an input pulse signal based on an input clock signal; a first delay circuit, which has a first sensitivity to a threshold voltage of a transistor, and is configured to receive the input pulse signal and a digital control code, and generate a first output signal delayed by a first delay time relative to the input pulse signal, and the first delay time changes according to the digital control code; a second delay circuit, which has a second sensitivity higher than the first sensitivity, and is configured to receive the input pulse signal and generate a second output signal delayed by a second delay time relative to the input pulse signal; a phase detector, which is configured to generate a phase detection signal by comparing the phase of the first output signal with the phase of the second output signal; and a control logic circuit, which is configured to generate a digital control code that increases or decreases according to the logic level of the phase detection signal.

[0009] According to some embodiments, a high-sensitivity delay unit includes: a first P-type metal oxide semiconductor (PMOS) transistor, the first PMOS transistor is connected between a cell input node and a first node and has a gate electrode configured to receive a mode signal; a first N-type metal oxide semiconductor (NMOS) transistor, the first NMOS transistor is connected in parallel with the first PMOS transistor between the cell input node and the first node and has a gate electrode configured to receive the mode signal; a buffer circuit, the buffer circuit is connected between the cell input node and a second node; a boost capacitor, the boost capacitor is connected between the first node and the second node; a second PMOS transistor, the second PMOS transistor is connected between a power supply voltage and a third node and has a gate electrode connected to the first node; a second NMOS transistor, the second NMOS transistor is connected between a ground voltage and the third node and has a gate electrode connected to the first node; a third PMOS transistor, the third PMOS transistor is connected between the power supply voltage and a cell output node and has a gate electrode connected to the third node; and a third NMOS transistor, the third NMOS transistor is connected between the ground voltage and the cell output node and has a gate electrode connected to the third node.

[0010] According to some exemplary embodiments, the high-sensitivity delay cell can reduce area overhead and increase the delay time variation according to the threshold voltage variation of the transistor by increasing the sensitivity to the threshold voltage using a reconfigurable pass transistor. In addition, even at a relatively low operating voltage, the high-sensitivity delay cell can operate by increasing the over-driving voltage using a boost capacitor.

[0011] The circuit for detecting the threshold voltage according to some embodiments can detect (e.g., relatively accurately detect) the threshold voltage of the transistor using a high-sensitivity delay cell and operate even at a relatively low operating voltage. In addition, by adopting a digital delay locked loop scheme, the circuit for detecting the threshold voltage can operate robustly over a wide frequency range despite changes in the operating clock frequency. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Example embodiments of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0013] Figure 1 is a block diagram illustrating a threshold voltage detection circuit according to some embodiments.

[0014] Figure 2 is a diagram illustrating an example embodiment of a first delay circuit included in a threshold voltage detection circuit according to some embodiments.

[0015] Figure 3 It is shown Figure 2 A circuit diagram of an example embodiment of a normal delay unit included in a first delay circuit of FIG.

[0016] Figure 4 and Figure 5 It is shown Figure 3 Timing diagram of the normal delay unit operation and delay time.

[0017] Figure 6 is a timing diagram illustrating delay times of a first delay circuit and a second delay circuit included in a threshold voltage detection circuit according to some embodiments.

[0018] Figure 7 is a diagram illustrating an example embodiment of a second delay circuit included in a threshold voltage detection circuit according to some embodiments.

[0019] Figure 8 is a circuit diagram illustrating a high-sensitivity delay unit according to some embodiments.

[0020] Fig. 9 and Fig.10 It is shown Figure 8 Timing diagram of the operation and delay time of the high sensitivity delay unit.

[0021] Fig.11 is a block diagram illustrating an example embodiment of a controller included in a threshold voltage detection circuit according to some embodiments.

[0022] Fig.12 It is shown Fig.11 A circuit diagram of an example embodiment of a pulse generator included in a controller.

[0023] Fig.13 It is shown Fig.12 Timing diagram of the operation of the pulse generator.

[0024] Fig.14 It is shown Fig.11 Schematic diagram of an example embodiment of a phase detector included in a controller.

[0025] Fig.15A and Fig. 15B It is shown Fig.14 Timing diagram of the operation of the phase detector.

[0026] Fig.16 It is shown Fig.11 Schematic diagram of an example embodiment of a lock signal generator included in a controller.

[0027] Fig.17 and Fig.18 It is shown Fig.16 Timing diagram of the operation of the lock signal generator.

[0028] Fig.19 and Fig. 20 is a timing diagram illustrating the operation of a threshold voltage detection circuit according to some embodiments.

[0029] Fig.21 It is shown Fig.11 A block diagram of an example embodiment of a counter circuit included in a controller.

[0030] Fig. 22 is a block diagram illustrating a computing system according to some example embodiments. DETAILED DESCRIPTION

[0031] Various example embodiments will be described more fully hereinafter with reference to the accompanying drawings showing some example embodiments. In the accompanying drawings, the same reference numerals refer to the same elements throughout. Repeated descriptions may be omitted.

[0032] Figure 1 is a block diagram illustrating a threshold voltage detection circuit according to some example embodiments.

[0033] Reference Figure 1 , the threshold voltage detection circuit 10 may include a first delay circuit ( DLC1 ) 100 , a second delay circuit ( DLC2 ) 200 , and a controller 300 .

[0034] The first delay circuit 100 may have a first sensitivity to the threshold voltage of the transistor, and the second delay circuit 200 may have a second sensitivity greater than the first sensitivity. As used herein, a large or relatively greater sensitivity to the threshold voltage of the transistor does not mean that the threshold voltage itself is large, but may mean that a delay time variation according to a threshold voltage variation is relatively large.

[0035] The first delay circuit 100 can receive an input signal SI and a digital control code DCC, and can generate a first output signal SO1, which is delayed relative to the input signal SI by a first delay time that can be changed according to the digital control code DCC. The second delay circuit 200 can receive an input signal SI, and can generate a second output signal SO2 delayed relative to the input signal SI by a second delay time. The first delay time of the first output signal SO1 can be changed according to or based on the digital control code DCC, but the second delay time of the second output signal SO2 can be constant regardless of the digital control code DCC. Accordingly, in some embodiments, the second delay circuit 200 may not receive (e.g., may not be configured to receive) the digital control code DCC. Below, reference will be made to Figures 2 to 10Some example embodiments of the first delay circuit 100 and the second delay circuit 200 are described in more detail.

[0036] As will be referenced below Figures 7 to 10 As described above, the second delay circuit 200 may include a delay line in which a plurality of high-sensitivity delay cells having the second sensitivity are connected in series.

[0037] The high sensitivity delay cell according to some example embodiments may include a reconfigurable pass transistor to increase sensitivity to a transistor threshold voltage, thereby reducing area overhead and increasing delay time variation due to threshold voltage variation. In addition, the high sensitivity delay cell according to some example embodiments may operate (e.g., operate robustly) even at a low operating voltage by increasing an overdrive voltage using a boost capacitor, as will be described below.

[0038] The controller 300 can compare the first output signal SO1 with the second output signal SO2 by changing the digital control code DCC, and can generate a digital output code DOC corresponding to the digital control code DCC when the first delay time is equal to the second delay time, so that the digital output code DOC indicates the threshold voltage of the transistor. Fig.11 An example embodiment of the controller 300 is described below.

[0039] Conventional threshold voltage detectors use a time-to-digital converter (TDC) to detect changes in the pulse width of a signal generated by a ring oscillator based on a ratio inverter according to changes in the threshold voltage. In addition, conventional threshold voltage detectors are equipped with both N-type and P-type ring oscillators to detect changes in threshold voltages of each type, respectively. In this case, instead of using a typical delay unit (e.g., a CMOS inverter) to reduce area overhead, a diode-connected transistor is used as a load transistor or a ratio transistor. This scheme can increase process sensitivity. However, since there is no device for a low voltage environment, if the swing of the signal is excessively reduced, the threshold voltage detector cannot operate normally. In addition, since TDC is used as a circuit for reading a changed signal, an error occurs when the operating clock frequency changes.

[0040] Another conventional threshold voltage detector consists of a ring oscillator and a controller, the ring oscillator includes a leakage monitoring unit, and the controller can change the mode of the transistor to be detected or control its on / off. In this case, since the threshold voltage is measured using the leakage current, the process sensitivity is high and the area overhead can be reduced. This is because the leakage current is exponentially inversely proportional to the threshold voltage, as shown in Expression 1.

[0041] Expression 1

[0042]

[0043] In Expression 1, Ids represents the drain current of the transistor, Vth represents the threshold voltage of the transistor, and n n and v are constants, and T represents absolute temperature.

[0044] However, in this case, due to leakage current, it may take a relatively long time to generate a signal, and it may be difficult to use in an environment where fast operation is required. This method may be difficult to use in a structure that requires a high sampling rate.

[0045] On the other hand, the threshold voltage detection circuit 10 according to the example embodiment can detect (e.g., relatively more accurately detect) the threshold voltage of the transistor using a high-sensitivity delay cell, and can operate (e.g., robustly operate) even at a relatively low operating voltage. In addition, the threshold voltage detection circuit 10 can adopt a digital delay locked loop scheme, and can operate (e.g., robustly operate) in a relatively wide frequency range despite changes in the operating clock frequency.

[0046] Figure 2 is a diagram illustrating an example embodiment of a first delay circuit included in a threshold voltage detection circuit according to some example embodiments.

[0047] Reference Figure 2 , the first delay circuit 100 may include a first delay line 120 and a selector (MUX) 140 .

[0048] The first delay line 120 may include a plurality of normal delay cells CN having a first sensitivity connected in series. The first delay line 120 may receive an input signal SI and may generate a plurality of delay signals SD1 ˜SDn having different delay times with respect to the input signal SI.

[0049] The selector 140 may select one of the plurality of delayed signals SD1 ˜SDn based on the digital control code DCC and provide the selected delayed signal as the first output signal SO1 .

[0050] Figure 3 It is shown Figure 2 A circuit diagram of an example embodiment of a normal delay unit included in a first delay circuit of FIG.

[0051] Reference Figure 2 and Figure 3 , the normal delay unit CN may include a first PMOS transistor MP11, a first NMOS transistor MN11, a second PMOS transistor MP22, and a second NMOS transistor MN22.

[0052] The first PMOS transistor MP11 and the first NMOS transistor MN11 may form one inverter (eg, a first inverter) and may be connected between a power supply voltage VDD and a ground voltage VSS, and may invert a cell input signal IN to generate an inversion signal OUTb′.

[0053] The second PMOS transistor MP22 and the second NMOS transistor MN22 may form another inverter (eg, a second inverter) and may be connected between the power supply voltage VDD and the ground voltage VSS and may invert the inversion signal OUTb′ to generate a cell output signal OUT′.

[0054] Figure 3 A normal delay unit CN including two normal inverters is shown, but the present disclosure is not limited thereto. According to some embodiments, the normal delay unit CN may have a 2-stage structure, etc., and may include four, six, and other numbers of inverters.

[0055] Figure 4 and Figure 5 It is shown Figure 3 Timing diagram of the normal delay unit operation and delay time.

[0056] Figure 4 The cell input signal IN changes from a logic low level to a logic high level at the rising edge according to Figure 3 The first NMOS transistor MN11 may be a typical transistor TP having a typical threshold voltage, a fast transistor FS having a relatively low threshold voltage, or a slow transistor SL having a relatively high threshold voltage.

[0057] Compared to the falling transition time nt of the inversion signal OUTb′ in the case of the typical transistor TP, the fast transistor FS has a relatively short falling transition time nf, and the slow transistor SL has a relatively long falling transition time ns.

[0058] Thus, as the threshold voltage of the first NMOS transistor MN11 increases, the switching speed of the first NMOS transistor MN11 turning on decreases, and the delay time of the falling edge of the inverting signal OUTb' increases. The high sensitivity of the NMOS transistor indicates that the delay time changes due to the threshold voltage change of the NMOS transistor (e.g., Figure 4 The nt-nf, ns-nt and ns-nf) in the sample are large.

[0059] Figure 5 The following diagram shows the falling edge of the cell input signal IN changing from a logic high level to a logic low level. Figure 3The first PMOS transistor MP11 may be a typical transistor TP having a typical threshold voltage, a fast transistor FS having a relatively low threshold voltage, or a slow transistor SL having a relatively high threshold voltage.

[0060] Compared to the rising transition time Pt ​​of the inversion signal OUTb′ in the case of the typical transistor TP, the fast transistor FS has a relatively short rising transition time pf, and the slow transistor SL has a relatively long rising transition time ps.

[0061] In this way, as the threshold voltage of the first PMOS transistor MP11 increases, the switching speed of turning on the first PMOS transistor MP11 decreases, and the delay time of the rising edge of the inverting signal OUTb' increases. The high sensitivity of the PMOS transistor indicates that the delay time changes due to the threshold voltage change of the PMOS transistor (for example, Figure 5 The pt-pf, ps-pt and ps-pf) in the sample are large.

[0062] Figure 6 is a timing diagram illustrating delay times of a first delay circuit and a second delay circuit included in a threshold voltage detection circuit according to some examples of the embodiments.

[0063] Reference Figures 2 to 6 The first delay line 120 may include a plurality of normal delay units CN having a first sensitivity connected in series, and the first delay line 120 may receive an input signal SI and may generate a plurality of delay signals SD1 ˜SDn having different delay times relative to the input signal SI.

[0064] The selector 140 may select one of the plurality of delayed signals SD1 ˜SDn based on the digital control code DCC and provide the selected delayed signal as the first output signal SO1 .

[0065] For example, when the value of the digital control code DCC is 0, the selector 140 may output a delayed signal SD1 delayed by a first delay time corresponding to d1 relative to the input signal SI as the first output signal SO1. When the value of the digital control code DCC is 1, the selector 140 may output a delayed signal SD2 delayed by a first delay time corresponding to d2 relative to the input signal SI as the first output signal SO1. In this way, when the value of the digital control code DCC is n-1, the selector 140 may output a delayed signal SDn delayed by a first delay time corresponding to dn relative to the input signal SI as the first output signal SO1.

[0066] In this way, the first delay time of the first output signal SO1 can be changed or can be changeable according to the digital control code DCC. For example, whenever the value of the digital control code DCC increases by 1, the first delay time can be increased at regular intervals. On the other hand, whenever the value of the digital control code DCC decreases by 1, the first delay time can be reduced at regular intervals.

[0067] In addition, regardless of the digital control code DCC, the second delay time of the second output signal SO2 can be fixed to tD, such as Figure 6 as shown in .

[0068] As mentioned above, Figure 1 The controller 300 can compare the first output signal SO1 with the second output signal SO2 while changing the digital control code DCC to determine that the first delay time is the same as the second delay time. The digital control code DCC that makes the first delay time equal to the second delay time or substantially the same as the second delay time can be provided as a digital output code DOC representing the transistor threshold voltage.

[0069] The controller 300 may increase the value of the digital control code DCC when the first delay time is less than the second delay time based on the comparison result between the first output signal SO1 and the second output signal SO2, and may decrease the value of the digital control code DCC when the first delay time is greater than the second delay time.

[0070] Figure 7 is a diagram illustrating an example embodiment of a second delay circuit included in a threshold voltage detection circuit according to some example embodiments, and Figure 8 is a circuit diagram illustrating a high-sensitivity delay unit according to some example embodiments.

[0071] Reference Figure 7 , the second delay circuit 200 may include a second delay line 220 including a plurality of high-sensitivity delay cells CHS having a second sensitivity connected in series. The second delay line 220 may receive an input signal SI and may generate a second output signal SO2. The number of high-sensitivity delay cells CHS included in the second delay line 220 may be determined differently.

[0072] Despite Figure 8 Although one high-sensitivity delay cell is shown in FIG. 2 , a plurality of high-sensitivity delay cells CHS included in the second delay line 220 may all have the same configuration.

[0073] Reference Figure 8, each high-sensitivity delay cell CHS may include a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a buffer circuit BF, and a boosting capacitor BC.

[0074] The first PMOS transistor MP1 may be connected between the cell input node NI and the first node N1, and a mode signal MD may be applied to the gate electrode. The first NMOS transistor MN1 may be connected in parallel with the first PMOS transistor MP1 between the cell input node NI and the first node N1, and a mode signal MD may be applied to the gate electrode. The first PMOS transistor MP1 and the first NMOS transistor MN1 may be referred to as pass transistors.

[0075] As will be described below, the mode signal MD may represent an NMOS detection mode for detecting a threshold voltage of an NMOS transistor or a PMOS detection mode for detecting a threshold voltage of a PMOS transistor. When the mode signal MD is at a first logic level (e.g., a logic high level), the first PMOS transistor MP1 may be turned off and the first NMOS transistor MN1 may be turned on to perform the NMOS detection mode. On the other hand, when the mode signal MD is at a second logic level (e.g., a logic low level), the first PMOS transistor MP1 may be turned on and the first NMOS transistor MN1 may be turned off to perform the PMOS detection mode.

[0076] The buffer circuit BF may be connected between the cell input node N1 and the second node N2, and the boost capacitor BC may be connected between the first node N1 and the second node N2. In some example embodiments, the buffer circuit BF may include an even number of inverters connected in series (or cascaded). In some embodiments, the boost capacitor BC may be implemented as a MOS capacitor.

[0077] The second PMOS transistor MP2 may be connected between the power supply voltage VDD and the third node N3, and the gate electrode may be connected to the first node N1. The second NMOS transistor MN2 may be connected between the third node N3 and the ground voltage VSS, and the gate electrode may be connected to the first node N1. The second PMOS transistor MP2 and the second NMOS transistor MN2 together constituting a first inverter may invert a voltage signal of the first node N1 to generate an inverted signal OUTb.

[0078] The third PMOS transistor MP3 may be connected between the power supply voltage VDD and the cell output node NO, and the gate electrode may be connected to the third node N3. The third NMOS transistor MN3 may be connected between the cell output node NO and the ground voltage VSS, and the gate electrode may be connected to the third node N3. The third PMOS transistor MP3 and the third NMOS transistor MN3 constituting the second inverter may generate the cell output signal OUT by inverting the inversion signal (OUTb).

[0079] Fig. 9 and Fig.10 It is shown Figure 8 Timing diagram of the operation and delay time of the high sensitivity delay unit.

[0080] Fig. 9 The following diagram shows the case where the cell input signal IN changes from a logic low level to a logic high level, that is, at the rising edge of the time point t1. Figure 8 The operation is performed by adjusting the threshold voltage of the second NMOS transistor MN2.

[0081] Reference Figure 8 and Fig. 9 , when the cell input signal IN is at a logic high level at time point t2, the first NMOS transistor MN1 may be turned on, and the voltage signal V(N1) of the first node N1 may rise to VDD-VTN. Here, VDD may represent a power supply voltage, and VTN may represent Figure 8 The threshold voltage of the NMOS transistor included in the high-sensitivity delay unit CHS.

[0082] Thereafter, in response to the voltage signal V(N2) of the second node N2 rising to the power supply voltage VDD at time point t3, the voltage level of the first node N1 may increase the boost voltage VBN of the boost capacitor BC. The voltage signal V(N1) may further rise to the over-driving voltage VDD-VTN+VBN. Fig. 9 In FIG. 1 , tn1 represents the delay time due to the buffer circuit BF and the boost capacitor BC.

[0083] Thereafter, at a time point t4 , the second NMOS transistor MN2 may be turned on, and the inversion signal OUTb may drop to the ground voltage VSS.

[0084] The delay of the high-sensitivity delay unit CHS may include (e.g., may consist of) a boost delay tn2 and an inverter delay tn3. At this time, a voltage may be applied to both the second PMOS transistor MP2 and the second NMOS transistor MN2 through the first NMOS transistor MN1 corresponding to the pass transistor to turn off the second PMOS transistor MP2. When the cell input signal NI transitions downward, it may be transmitted through the second NMOS transistor MN2 without any problem (e.g., relatively quickly), but when the input signal SI is as Fig. 9 When the voltage signal V(N1) of the first node N1 is turned upward as shown in , the phenomenon of the threshold voltage drop may occur. Therefore, the voltage signal V(N1) of the first node N1 can become VDD-VTN. In a high power supply voltage environment, the inverter can operate normally even if the input voltage is reduced, but recently, a low voltage environment (e.g., a relatively low voltage environment) near the threshold such as low power is often used, and in such an environment, it may be difficult to use the reduced voltage VDD-VTN. Therefore, when the voltage signal V(N2) of the second node N2 increases after a certain delay time tn1, the voltage signal V(N1) of the first node N1 can be increased using the boost capacitor BC. Using this additional voltage, the post-inverters MP2 and MN2 can be placed within the operating range while maintaining sensitivity to the threshold voltage. The principle of increasing the sensitivity to the threshold voltage is the delay of the inverter, as will be described below. This is because it increases according to the overdrive voltage. The overdrive voltage of the inverters MP2 and MN2 is VDD–2×VTN+VBN. If VBN is regarded as a constant, the amount of change in threshold voltage can be doubled compared to a general inverter, so a larger delay change can occur even if the change in threshold voltage is the same.

[0085] Fig.10 The following diagram shows the falling edge of the cell input signal IN when it changes from a logic high level to a logic low level, that is, at the time point t1. Figure 8 The operation is performed by adjusting the threshold voltage of the second PMOS transistor MP2.

[0086] Reference Figure 8 and Fig.10 , when the cell input signal IN is at a logic low level at time point t2, the first PMOS transistor MP1 may be turned on, and the voltage signal V(N1) of the first node N1 may drop to VDD-VTP. Here, VDD represents a power supply voltage, and VTP represents Figure 8 The threshold voltage of the PMOS transistor included in the high-sensitivity delay unit CHS.

[0087] Thereafter, when the voltage signal V(N2) of the second node N2 drops to the ground voltage VSS at time point t3, the voltage signal V(N1) can further drop to the over-driving voltage (VDD-VTP-VBP) due to the boost voltage VBN of the boost capacitor BC. Fig.10 In FIG. 1 , tp1 represents the delay time due to the buffer circuit BF and the boost capacitor BC.

[0088] Thereafter, at time point t4 , the second PMOS transistor MP2 may be turned on, and the inversion signal OUTb rises to the power supply voltage VDD.

[0089] As reference Fig. 9 As described, the delay of the high-sensitivity delay unit CHS may include (e.g., may be composed of) a boost delay tn2 and an inverter delay tn3. As a result, the overdrive voltage of the inverters MP2 and MN2 becomes VDD-2×VTP-VBP. If VBP is regarded as a constant, the change in threshold voltage is doubled compared to a typical inverter, so a larger delay change may occur for the same threshold voltage change.

[0090] A commonly used delay model alpha-power law model can be expressed as Expression 2.

[0091] Expression 2

[0092]

[0093] In Expression 2, t delay represents the delay time of the delay unit, VDD represents the power supply voltage, Vth represents the threshold voltage of the transistor, and β eff and α are constants.

[0094] According to the delay model, representative variables affecting the delay unit include power supply voltage, transistor threshold voltage, transistor channel length and mobility. Since the threshold voltage can be an independent variable with a very low correlation coefficient with the channel length and mobility, the delay time can be expressed as the product of two different functions using separated variables, as shown in Expression 3.

[0095] Expression 3

[0096] t delay =F(β eff )G(Vth)

[0097] Using Expression 3, the delay time of the first delay line 120 and the delay time of the second delay line 220 having different process sensitivities to the threshold voltage can be expressed as Expression 4 and Expression 5. Expression 4 represents the delay time including the delay time of the first delay line 120 and the delay time of the second delay line 220 having different process sensitivities to the threshold voltage. Figures 3 to 5The first delay time of the first delay line 120 of the normal delay unit CN composed of the inverter described above, and Expression 5 represents the first delay time of the first delay line 120 composed of the reference Figures 7 to 10 The second delay time of the second delay line 220 of the high-sensitivity delay unit CHS composed of a boosting capacitor and a reconfigurable transistor according to some example embodiments is described.

[0098] Expression 4

[0099] t delay1 =F(β eff )G 1 (Vth)

[0100] Expression 5

[0101] t delay2 =F(β eff )G2(Vth)

[0102] In expression 4, t delay1 corresponds to the first delay time mentioned above, and t in Expression 5 delay2 Corresponding to the second delay time mentioned above.

[0103] The sensitivity according to the change of the transconductance coefficient (β coefficient) may be the same, but the sensitivity according to the change of the threshold voltage may be different, so the G function representing the delay change according to the threshold voltage variable may be different. Thereafter, if the delays of the two delay lines are made equal through a digital delay fixing loop, it can be expressed as Expression 6.

[0104] Expression 6

[0105] N=M*G 2 (Vth) / G 1 (Vth)

[0106] In Expression 6, N is the number of normal delay cells CN corresponding to the first output signal SO1, and M is the number of high-sensitivity delay cells CHS corresponding to the second output signal SO2.

[0107] If the number M of high-sensitivity delay cells CHS is fixed to a constant value, the number N of normal delay cells CN corresponding to the first output signal SO1 can be expressed as a function of the threshold voltage. Using this principle, the threshold voltage can be detected using the measured N value.

[0108] Since the swing of the voltage signal V(N1) at the input terminal (ie, the first node N1) of the inverter MP2 and MN2 can be lowered by the threshold voltage through the transistor, the sensitivity due to the threshold voltage change as shown in Expression 7 increases.

[0109] Expression 7

[0110]

[0111] Compared with Expression 2, even for the same threshold voltage change amount, the change amount of the delay time can become relatively large (and can become relatively much larger). However, because the input terminals of the inverters MP2 and MN2 can be lowered from the power supply voltage VDD to the threshold voltage, there may be a problem that the inverters MP2 and MN2 do not operate normally in the low voltage structure.

[0112] The high-sensitivity delay cell CHS according to some example embodiments may use a method of increasing the sensitivity of the delay cell by reducing the swing amplitude by a threshold voltage using a pass transistor, but may add a boost capacitor BC to perform voltage boosting and enable normal operation even in a low voltage environment. This process may be expressed as Expression 8. Therefore, the high-sensitivity delay cell CHS according to some example embodiments may not be constrained by voltage and may be used in various environments such as a low voltage interface.

[0113] Expression 8

[0114]

[0115] In this way, the high-sensitivity delay cell CHS according to some exemplary embodiments can use reconfigurable pass transistors MP1 and MN1 to increase sensitivity to transistor threshold voltages while reducing area overhead. The delay time variation according to the threshold voltage variation can be increased. In addition, by increasing the overdrive voltage using the boost capacitor BC, the high-sensitivity delay cell CHS according to some exemplary embodiments can operate robustly even at a low operating voltage.

[0116] As reference Figures 8 to 10 As described, when the mode signal MD has a logic high level, the first NMOS transistor MN1 may be turned on, and the sensitivity to the threshold voltage of the second NMOS transistor MN2 may be increased. On the other hand, when the mode signal MD has a logic low level, the first PMOS transistor MP1 may be turned on, and the sensitivity to the threshold voltage of the second PMOS transistor MP2 may be increased.

[0117] Fig.11 is a block diagram illustrating an example embodiment of a controller included in a threshold voltage detection circuit according to some example embodiments.

[0118] Reference Fig.11 , the controller 300 may include a phase detector (PSG) 320 , a counter circuit (CNT) 340 , a phase detector (BBPD) 360 , and a control logic circuit (CTRL) 380 .

[0119] The pulse generator 320 may generate an input pulse signal based on the input clock signal ECLK, and may provide the input pulse signal as the input signal SI.

[0120] The phase detector 340 may generate a phase detection signal PD by comparing the phase of the first output signal SO1 with the phase of the second output signal SO2 .

[0121] The counter circuit 340 can increase or decrease the value of the digital control code DCC according to the logic level of the up / down signal UD. Fig.19 and Fig. 20 As described, the counter circuit 340 can increase or decrease (e.g., increment or decrement) the value of the digital control value DCC one by one according to the logic level of the phase detection signal PD in each cycle period of the input clock signal ECLK. In an example embodiment, the counter circuit 340 may include an up-down counter that operates based on the phase detection signal PD. The configuration of the up-down counter can be implemented in various ways.

[0122] The control logic circuit 380 may generate the up-down signal UD based on the phase detection signal PD. The control logic circuit 380 may provide the phase detection signal PD itself as the up-down signal UD, or may generate the up-down signal UD by adjusting the timing of the phase detection signal PD.

[0123] In addition, the control logic circuit 380 may generate an enable signal EN and a reset signal RST that may be used to control the counter circuit 340. The counter circuit 340 may be enabled or disabled based on the enable signal EN. The stored value of the counter circuit 340 may be reset to a predetermined initialization value based on the reset signal RST.

[0124] In addition, the control logic circuit 380 may generate a mode signal MD indicating an NMOS detection mode for detecting a threshold voltage of an NMOS transistor or a PMOS detection mode for detecting a threshold voltage of a PMOS transistor. In some embodiments, when the mode signal MD is at a first logic level (e.g., a logic high level), the mode signal MD may indicate an NMOS detection mode, and when the mode signal MD is at a second logic level (e.g., a logic low level), the mode signal MD indicates a PMOS detection mode.

[0125] Fig.12 It is shown Fig.11 A circuit diagram of an example embodiment of a pulse generator included in a controller, and Fig.13 It is shown Fig.12 Timing diagram of the operation of the pulse generator.

[0126] Reference Fig.12 The pulse generator 320 may include a delay circuit 321, a logic gate 322, and an output circuit. The output circuit may include an inverter 323 and a multiplexer (MX) 324.

[0127] Reference Fig.12 and Fig.13 The delay circuit 321 may be configured to delay the input clock signal ECLK by a certain delay time and invert it to generate an inverted delayed clock signal DCK.

[0128] The logic gate 322 can generate the pulse signal NPLS by performing a logic operation on the input clock signal ECLK and the inverted delayed clock signal DCK. Fig.12 The pulse width PW of the pulse signal NPLS is adjusted according to the delay amount of the buffer 321. Fig.12 An embodiment in which the logic gate 322 is implemented as, for example, a NAND gate is shown, but the present disclosure is not limited thereto.

[0129] The inverter 323 may generate an inverted pulse signal PPLS by inverting the pulse signal NPLS.

[0130] The multiplexer 324 may provide the pulse signal NPLS or the inverted pulse signal PPLS as an input pulse signal based on the mode signal MD.

[0131] In some embodiments, when the mode signal MD is at a logic high level, the mode signal MD may represent an NMOS detection mode for detecting a threshold voltage of an NMOS transistor, and when the mode signal MD is at a logic low level, the mode signal MD may represent a PMOS detection mode for detecting a threshold voltage of a PMOS transistor. In this case, the multiplexer 324 may select a negative pulse signal NPLS activated at a logic low level when the mode signal MD is at a logic high level, and may provide a negative pulse signal as an input signal SI. When the mode signal MD is at a logic low level, the multiplexer 324 may select a positive pulse signal PPLS activated at a logic high level, and may provide a positive pulse signal as an input signal SI.

[0132] As such, the pulse generator 320 may generate a negative pulse signal NPLS activated at a logic low level based on the input clock signal ECLK in the NMOS detection mode, and may generate a positive pulse signal PPLS activated at a logic high level based on the input clock signal ECLK in the PMOS detection mode.

[0133] Fig.14 It is shown Fig.11 A diagram of an example embodiment of a phase detector included in a controller of Fig.15A and Fig. 15B It is shown Fig.14 Timing diagram of the operation of the phase detector.

[0134] Reference Fig.14 , the phase detector 360 may include a bang-bang phase detector that generates a phase detection signal PD by latching the logic level of the first output signal SO1 synchronously with the edge of the second output signal SO2. In some embodiments, the bang-bang phase detector may be implemented as a D flip-flop DFF including an input terminal D, a clock terminal CK, and an output terminal Q. The first output signal SO1 may be applied to the input terminal D of the D flip-flop DFF, the second output signal SO2 may be applied to the clock terminal CK, and the phase signal may be output through the output terminal Q.

[0135] like Fig.15A and Fig. 15B As shown in , the phase detector 360 may latch the logic level of the first output signal SO1 at time points t1 and t2 corresponding to the rising edge of the second output signal SO2, and may generate a phase detection signal PD. Fig.15A As shown in , when the phase of the first output signal SO1 lags behind the phase of the second output signal SO2, the phase detection signal PD may be at a second logic level (eg, a logic low level). Fig. 15B As shown in , when the phase of the first output signal SO1 leads the phase of the second output signal SO2 , the phase detection signal PD may be at a first logic level (eg, a logic high level).

[0136] Fig.11 The counter circuit 340 may increase the value of the digital control code DCC when the phase detection signal PD has a first logic level, and may decrease the value of the digital control code DCC when the phase detection signal PD has a second logic level.

[0137] Fig.16 It is shown Fig.11 A diagram of an example embodiment of a locking signal generator included in a controller of Fig.17 and Fig.18 It is shown Fig.16 Timing diagram of the operation of the lock signal generator.

[0138] Reference Fig.16 , the lock signal generator 382 may include a D flip-flop 384 and a logic gate 386. The phase detection signal PD may be applied to an input terminal D of the D flip-flop 384, the input clock signal ECLK may be applied to a clock terminal CK of the D flip-flop 384, and the previous phase detection signal PD' may be output through an output terminal Q of the D flip-flop 384.

[0139] The logic gate 386 may generate a lock signal LOK by performing a logic operation on the phase detection signal PD and the previous phase detection signal PD′. Fig.16 An example embodiment in which logic gate 386 is implemented as an exclusive OR gate (ie, an XOR gate) is shown, but the present disclosure is not limited thereto.

[0140] like Fig.17 As shown in , when the phase detection signal PD changes from a logic high level to a logic low level at time point t1, the previous phase detection signal PD' may change from a logic high level to a logic low level at time point t2 corresponding to the rising edge of the input clock signal ECLK. As a result, the lock signal LOK may be activated in the form of a pulse during the time interval t1-t2.

[0141] like Fig.18 As shown in , when the phase detection signal PD changes from a logic low level to a logic high level at time point t3, the previous phase detection signal PD' may change from a logic low level to a logic high level at time point t4 corresponding to the rising edge of the input clock signal ECLK. As a result, the lock signal LOK may be activated in the form of a pulse during the time interval t3-t4.

[0142] In this way, Fig.11 The control logic circuit 380 may generate a lock signal LOK activated in response to a transition of the phase detection signal PD. The control logic circuit 380 may provide a digital control code DCC as a digital output code DOC in response to activation of the lock signal LOK. In some embodiments, the controller 380 may deactivate the enable signal EN in response to activation of the lock signal LOK. The counter circuit 340 may be disabled and may stop counting in response to deactivation of the enable signal EN, and at this time, the value stored in the counter circuit 340 may be provided as a digital output code DOC.

[0143] Fig.19 and Fig. 20 is a timing diagram illustrating the operation of a threshold voltage detection circuit according to an example embodiment. Fig.19 and Fig. 20 Shown is a reference Figures 1 to 18 The overall operation of the threshold voltage detection circuit 10 is described. Fig.19 shows an example of the operation of the above-mentioned NMOS detection mode, and Fig. 20 An example of the operation of the above-mentioned PMOS detection mode is shown. Fig.19 and Fig. 20, t1 to t10 represent edges (ie, transition time points) of the input clock signal ECLK, and t11 to t15 represent rising edges (ie, rising transition time points) of the second output signal SO2. Fig.19 and Fig. 20 An example in which the digital control code DCC is 4 bits is shown, but the present disclosure is not limited thereto. According to embodiments, the number of bits of the digital control code DCC may be implemented differently, and as the number of bits of the digital control code DCC increases, the resolution of the threshold voltage detection circuit 10 may increase.

[0144] Reference Fig.19 , in NMOS detection mode, Fig.11 The pulse generator 320 may generate a negative pulse signal NPLS activated at a logic low level based on the input clock signal ECLK, and the negative pulse signal NPLS may be provided as the input signal SI.

[0145] In some embodiments, Fig.11 The counter circuit 340 may be reset to an initial value in response to the reset signal RST, and may output a digital control code DCC corresponding to the initial value at a time point t1. Fig.19 The case where the counter circuit 340 is reset to the intermediate value of the digital control code DCC, that is, 1000 (binary) is shown, but the present disclosure is not limited thereto.

[0146] Since the first output signal SO1 has a relatively small first sensitivity, the pulse width of the first output signal SO1 can be close to the pulse width of the negative pulse signal NPLS corresponding to the input clock signal ECLK. On the other hand, since the second output signal SO2 has a relatively high second sensitivity, the pulse width of the second output signal SO2 can become greater than the pulse width of the negative pulse signal NPLS. Fig. 9 As described, in the NMOS detection mode, the sensitivity of the high-sensitivity delay unit CHS in the figure to the threshold voltage of the NMOS transistor can be increased.

[0147] Fig.14 The phase detector 360 can output the phase detection signal PD having a logic high level at time points t11, t12, t13, and t14 corresponding to the rising edge of the second output signal SO2. Therefore, at time points t3, t5, t7, and t9 corresponding to the rising edge of the input clock signal ECLK, the value of the digital control code DCC can be sequentially increased by 1, such as 1000, 1001, 1010, and 1100.

[0148] At time point t15 corresponding to the rising edge of the second output signal SO2, the phase detector 360 may output the phase detection signal PD having a logic low level. In other words, at time point t15, the phase detection signal PD may transition from a logic high level to a logic low level. Fig.11 The control logic circuit 380 can detect a time point at which the first delay time of the first delay circuit 100 becomes substantially the same as the second delay time of the second delay circuit 200 based on the transition of the phase detection signal PD. For example, the control logic circuit 380 can generate a reference signal as shown in FIG. Fig.16 In other words, in the case of a lock signal LOK described above, the digital control code DCC can be provided as a digital output code DOC in response to activation of the lock signal LOK. Fig.19 In the example of , the digital control code DCC having a value of 1100 at the time point t15 may be provided as the digital output code DOC, and the provided value 1100 may indicate that the threshold voltage of the NMOS transistor is changed.

[0149] Reference Fig. 20 , in PMOS detection mode, Fig.11 The pulse generator 320 may generate a positive pulse signal PPLS activated at a logic high level based on the input clock signal ECLK, and the positive pulse signal PPLS may be provided as the input signal SI.

[0150] In some embodiments, Fig.11 The counter circuit 340 may be reset to an initial value in response to the reset signal RST, and may output a digital control code DCC corresponding to the initial value at a time point t1. Fig. 20 The case where the counter circuit 340 is reset to the intermediate value of the digital control code DCC, that is, 1000 (binary) is shown, but the present disclosure is not limited thereto.

[0151] Since the first output signal SO1 has a relatively small first sensitivity, the pulse width of the first output signal SO1 can be close to the pulse width of the positive pulse signal PPLS corresponding to the input clock signal ECLK. On the other hand, since the second output signal SO2 has a relatively large second sensitivity, the pulse width of the second output signal SO2 can become greater than the pulse width of the positive pulse signal PPLS. Fig.10 As described, in PMOS detection mode, Figure 8 The sensitivity of the high-sensitivity delay cell CHS to the threshold voltage of the PMOS transistor can be increased.

[0152] Fig.14The phase detector 360 can output the phase detection signal PD having a logic low level at time points t11, t12, t13, and t14 corresponding to the rising edge of the second output signal SO2. Therefore, at time points t3, t5, t7, and t9 corresponding to the rising edge of the input clock signal ECLK, the value of the digital control code DCC can be sequentially increased by 1, such as 1000, 1001, 1010, and 1100.

[0153] At time point t15 corresponding to the rising edge of the second output signal SO2, the phase detector 360 outputs the phase detection signal PD having a logic high level. In other words, at time point t15, the phase detection signal PD may transition from a logic low level to a logic high level. Fig.11 The control logic circuit 380 can detect a time point at which the first delay time of the first delay circuit 100 becomes substantially the same as the second delay time of the second delay circuit 200 based on the transition of the phase detection signal PD. For example, the control logic circuit 380 can generate a reference signal as shown in FIG. Fig.16 In other words, in the case of a lock signal LOK described above, the digital control code DCC can be provided as a digital output code DOC in response to activation of the lock signal LOK. Fig. 20 In the example of , the digital control code DCC having a value of 1100 at the time point t15 may be provided as the digital output code DOC, and the provided value 1100 may indicate that the threshold voltage of the PMOS transistor is changed.

[0154] Fig.21 It is shown Fig.11 A block diagram of an example embodiment of a counter circuit included in a controller.

[0155] Reference Fig.21 , the counter circuit 340 may include an NMOS up-down counter (NCNT) 342 and a PMOS up-down counter (PCNT) 344 .

[0156] The NMOS up-down counter 342 may be enabled in the above-mentioned NMOS detection mode, may generate a digital control code DCC, and may store a digital output code DCC representing a threshold voltage of an NMOS transistor.

[0157] The PMOS up-down counter 344 may be enabled in the above-mentioned PMOS detection mode, may generate a digital control code DCC, and may store a digital output code DCC indicating a threshold voltage of a PMOS transistor.

[0158] The NMOS up-down counter 342 may be enabled in response to activation of the first enable signal EN1 , and the PMOS up-down counter 344 may be enabled in response to activation of the second enable signal EN2 . Fig.11 The control logic circuit 380 may activate the first enable signal EN1 and may deactivate the second enable signal EN2 in the NMOS detection mode. On the other hand, in the PMOS detection mode, the control logic circuit 380 may activate the second enable signal EN2 and may deactivate the first enable signal EN1.

[0159] Each of the NMOS up-down counter 342 and the PMOS up-down counter 344 may perform an up-counting operation that may increase the storage value by 1 or a down-counting operation that may decrease the storage value by 1 during each cycle period of the input clock signal ECLK according to the logic level of the up-down signal UD. The NMOS up-down counter 342 and the PMOS up-down counter 344 may reset the storage value to an initial value based on the reset signal RST.

[0160] The NMOS detection mode and the PMOS detection mode are sequentially performed, and a value representing a threshold voltage of an NMOS transistor and a value representing a threshold voltage of a PMOS transistor may be stored in the NMOS up-down counter 342 and the PMOS up-down counter 344 , respectively.

[0161] Fig. 22 is a block diagram illustrating a computing system according to some example embodiments.

[0162] Reference Fig. 22 , the computing system 1000 may include a system on chip (SOC), a working memory 1130, a display device (LCD) 1152, a touch panel 1154, a storage device 1170, a power management integrated circuit (PMIC) 1200, etc. The SOC may include a central processing unit (CPU) 1110, a threshold voltage detection circuit TVD 1115, a DRAM controller 1120, a performance controller (PFMC) 1140, a user interface controller (UI controller) 1150, a storage interface 1160, an accelerator 1180, a power management unit (PMU) 1144, a clock management unit (CMU) 1146, etc. It will be understood that the components of the computing system 1000 are not limited to Fig. 22 For example, the computing system 1000 may further include a hardware codec for processing image data, a security block, and the like.

[0163] The CPU 1110 can execute software (e.g., applications, operating systems (OS), and device drivers) for the computing system 1000. The CPU 1110 can execute the OS that can be loaded into the working memory 1130. The CPU 1110 can execute various applications to be driven on the OS. The CPU 1110 can be configured as a homogeneous multi-core processor or a heterogeneous multi-core processor. A multi-core processor is a computing component that includes at least two independently drivable processors (which can be referred to as "cores" or "processor cores"). Each core can read and execute program instructions independently.

[0164] The processor cores of the CPU 1100 may be grouped into a plurality of clusters that operate with independent drive clocks and independent drive voltages. The processor cores in the same cluster may be included in a clock domain that operates based on the same clock signal and / or a power domain that operates based on the same drive voltage. The drive voltage and / or clock signal provided to each processor core may be cut off or connected in units of a single core.

[0165] The kernel of the OS may monitor the number of tasks in the task queue and the driving voltage and driving clock of the CPU 1110 at specific time intervals to control the CPU 1110. In addition, the kernel of the OS may control hot insertion or hot removal of the CPU 1110 with reference to the monitored information.

[0166] The DRAM controller 1120 may provide an interface between the working memory 1130 and the SOC. The DRAM controller 1120 may access the working memory 1130 according to a request of the CPU 1110 or another intellectual property (IP) block.

[0167] The OS or basic application program may be loaded into the working memory 1130 during a boot operation. For example, an OS image stored in the storage device 1170 may be loaded into the working memory 1130 based on a boot sequence during booting of the computing system 1000. The overall input / output operation of the computing system 1000 may be supported by the OS. The working memory 1130 may be a volatile memory such as a static random access memory (SRAM) and a dynamic random access memory (DRAM) or a non-volatile memory device such as a phase change random access memory (PRAM), a magnetoresistive random access memory (MRAM), a resistive random access memory (ReRAM), a ferroelectric random access memory (FRAM), and a NOR flash memory. In some example embodiments, the working memory 1130 may include a threshold voltage detection circuit 1135 as described above.

[0168] The performance controller 1140 can adjust the operating parameters of the SOC according to the control request provided from the kernel of the OS. For example, the performance controller 1140 can adjust the level of DVFS to enhance the performance of the SOC. Alternatively, the performance controller 1140 can generate a frequency selection signal and can control the frequency of the processor core according to the request of the kernel. In this case, the performance controller 1140 may include a performance table PFMT 1142 to set the frequency of the drive voltage and the drive clock therein. The performance controller 1140 can control the PMU 1144 and CMU 1146 that form a power management circuit together with the PMIC 1200 to provide a determined drive voltage and a determined drive clock to each power domain.

[0169] The user interface controller 1150 may control user input and output from the user interface device. For example, the user interface controller 1150 may display a keyboard screen for inputting data to the LCD 1152 according to the control of the CPU 1110. Alternatively, the user interface controller 1150 may control the LCD 1152 to display data requested by the user. The user interface controller 1150 may decode data provided from a user input device such as a touch panel 1154 into user input data.

[0170] The storage interface 1160 may access the storage device 1170 according to a request of the CPU 1110. For example, the storage interface 1160 may provide a connection between the SOC and the storage device 1170. For example, data processed by the CPU 1110 may be stored in the storage device 1170 through the storage interface 1160. Alternatively, data stored in the storage device 1170 may be provided to the CPU 1110 through the storage interface 1160.

[0171] The storage device 1170 may be provided as a storage medium of the computing system 1000. The storage device 1170 may store applications, OS images, and various types of data. The storage device 170 may be provided as a memory card (e.g., MMC, eMMC, SD, MicroSD, etc.). The storage device 170 may include a NAND-type flash memory having a high-capacity storage capability. Alternatively, the storage device 1170 may include a next-generation non-volatile memory such as PRAM, MRAM, ReRAM, and FRAM, or a NOR-type flash memory. In some example embodiments, the storage device 1170 may include a threshold voltage detection circuit 1175 as described above.

[0172] The accelerator 1180 can be provided as a separate intellectual property (IP) component to increase the processing speed of multimedia or multimedia data. For example, the accelerator 1180 can be provided as an intellectual property (IP) component to enhance the processing performance of text, audio, still images, animation, video, two-dimensional data or three-dimensional data.

[0173] The system interconnector 1190 may be a system bus that provides an on-chip network in the SOC. The system interconnector 1190 may include, for example, a data bus, an address bus, and a control bus. The data bus is a data transmission path. A memory access path to the working memory 1130 or the storage device 1170 may also be provided. The address bus provides an address exchange path between intellectual property rights (IPs). The control bus may provide a path followed by transmission of control signals between intellectual property rights (IPs). However, the configuration of the system interconnector 1190 is not limited to the above description, and the system interconnector 190 may also include an arbitration device for effective management.

[0174] The threshold voltage detection circuits 1115, 1135, and 1177 may be implemented as on-chip circuits to monitor changes in the threshold voltages of transistors in corresponding components. The operation of the computing system 1000 may be effectively controlled based on the digital output codes provided from the threshold voltage detection circuits 1115, 1135, and 1177. The operating conditions and operation timing of the working memory 1130, SOC, and storage device 1170 may be controlled based on the detected threshold voltage changes.

[0175] As described above, the high-sensitivity delay cell according to some exemplary embodiments can reduce area overhead and increase the delay time variation according to the threshold voltage variation of the transistor by increasing the sensitivity to the threshold voltage using a reconfigurable pass transistor. In addition, even at a low operating voltage, the high-sensitivity delay cell can operate robustly by increasing the over-driving voltage using a boost capacitor.

[0176] The circuit for detecting a threshold voltage according to some example embodiments can detect (e.g., more accurately detect) the threshold voltage of a transistor using a high-sensitivity delay cell, and can even operate (e.g., operate robustly) at a low operating voltage. In addition, by adopting a digital delay locked loop scheme, the circuit for detecting a threshold voltage can operate robustly over a wide frequency range despite changes in the operating clock frequency.

[0177] The inventive concept of the present disclosure can be applied to any semiconductor integrated circuit and system including transistors. For example, the inventive concept of the present disclosure can be applied to systems such as memory cards, solid-state drives (SSDs), embedded multimedia cards (eMMCs), universal flash memory (UFS), mobile phones, smart phones, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, video cameras, personal computers (PCs), server computers, workstations, laptop computers, digital TVs, set-top boxes, portable game consoles, navigation systems, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-books, virtual reality (VR) devices, augmented reality (AR) devices, server systems, automotive driving systems, etc.

[0178] The above illustrates some exemplary embodiments and is not to be construed as limiting thereof. Although a few exemplary embodiments have been described, those skilled in the art will readily appreciate that many modifications may be made in the exemplary embodiments without materially departing from the scope of the present disclosure.

Claims

1. A circuit for detecting a threshold voltage, the circuit comprising: a first delay circuit having a first sensitivity to a threshold voltage of a transistor, the first delay circuit being configured to receive an input signal and a digital control code, and being configured to generate a first output signal delayed by a first delay time relative to the input signal, the first delay time being changed based on the digital control code; a second delay circuit having a second sensitivity higher than the first sensitivity, the second delay circuit being configured to receive the input signal and configured to generate a second output signal delayed by a second delay time relative to the input signal; as well as A controller configured to compare the first output signal with the second output signal by changing the digital control code, and configured to generate a digital output code corresponding to the digital control code in response to the first delay time being equal to the second delay time, so that the digital output code indicates a threshold voltage of the transistor.

2. The circuit according to claim 1, wherein The controller comprises: a pulse generator configured to generate an input pulse signal based on an input clock signal and configured to provide the input pulse signal as the input signal; a phase detector configured to generate a phase detection signal by comparing a phase of the first output signal with a phase of the second output signal; a counter circuit configured to increment or decrement the value of the digital control code according to the logic level of the up / down signal; and A control logic circuit is configured to generate the up-down signal based on the phase detection signal.

3. The circuit according to claim 2, wherein: The phase detector comprises: A switch-mode phase detector is configured to generate the phase detection signal based on latching a logic level of the first output signal in synchronization with an edge of the second output signal.

4. The circuit according to claim 2, wherein: The phase detection signal has a first logic level when a phase of the first output signal leads a phase of the second output signal, and has a second logic level when a phase of the first output signal lags a phase of the second output signal.

5. The circuit according to claim 4, wherein: The counter circuit is configured to increase the value of the digital control code when the phase detection signal has the first logic level, and to decrease the value of the digital control code when the phase detection signal has the second logic level.

6. The circuit according to claim 2, wherein: The control logic circuit is configured to generate a lock signal that is activated in response to an edge of the phase detection signal, and is configured to provide the digital control code as the digital output code in response to activation of the lock signal.

7. The circuit according to claim 2, wherein: The counter circuit is configured to increase or decrease a value of the digital control code according to a logic level of the phase detection signal within each cycle period of the input clock signal.

8. The circuit according to claim 2, wherein: The control logic circuit is configured to generate a mode signal, which indicates an NMOS detection mode for detecting a threshold voltage of an NMOS transistor or a PMOS detection mode for detecting a threshold voltage of a PMOS transistor, NMOS (N-type metal oxide semiconductor) and PMOS (P-type metal oxide semiconductor).

9. The circuit according to claim 8, wherein The counter circuit comprises: An NMOS up-down counter configured to be enabled in the NMOS detection mode based on the mode signal to generate the digital control code and store the digital output code indicating the threshold voltage of the NMOS transistor; and A PMOS up-down counter is configured to be enabled in a PMOS detection mode based on the mode signal to generate the digital control code and store the digital output code indicating a threshold voltage of a PMOS transistor.

10. The circuit according to claim 8, wherein The pulse generator is configured to generate a negative pulse signal based on the input clock signal in the NMOS detection mode, so that the negative pulse signal is activated at a logic low level, and is configured to generate a positive pulse signal based on the input clock signal in the PMOS detection mode, so that the positive pulse signal is activated at a logic high level.

11. The circuit according to claim 8, wherein: The pulse generator comprises: a delay circuit configured to generate an inverted delayed clock signal by inverting and delaying the input clock signal; a logic gate configured to generate a pulse signal according to performing a logic operation on the input clock signal and the inverted delayed clock signal; and An output circuit is configured to provide the pulse signal or an inverted signal of the pulse signal as the input pulse signal in response to the mode signal.

12. The circuit of claim 1, wherein: In response to a mode signal indicating an NMOS detection mode for detecting a threshold voltage of an NMOS transistor or a PMOS detection mode for detecting a threshold voltage of a PMOS transistor, the second delay circuit is configured to have the second sensitivity to the threshold voltage of the NMOS transistor in the NMOS detection mode and to have the second sensitivity to the threshold voltage of the PMOS transistor in the PMOS detection mode.

13. The circuit of claim 1, wherein: The first delay circuit comprises: a first delay line including a plurality of normal delay cells connected in series, the plurality of normal delay cells having the first sensitivity and configured to generate a plurality of delay signals having different delay times with respect to the input signal; and A selector is configured to select one of the plurality of delayed signals based on the digital control code and to provide the selected delayed signal as the first output signal.

14. The circuit according to claim 13, wherein: The controller is configured to increase the value of the digital control code when the first delay time is less than the second delay time, and is configured to decrease the value of the digital control code when the first delay time is greater than the second delay time.

15. The circuit of claim 1, wherein: The second delay circuit comprises: A second delay line includes a plurality of high-sensitivity delay cells connected in series and having the second sensitivity and configured to generate the second output signal.

16. The circuit of claim 15, wherein: Each of the plurality of high-sensitivity delay units comprises: a first PMOS transistor connected between the cell input node and the first node and having a gate electrode configured to receive a mode signal; a first NMOS transistor connected in parallel with the first PMOS transistor between the cell input node and the first node and having a gate electrode configured to receive the mode signal; a buffer circuit connected between the cell input node and a second node; a boost capacitor connected between the first node and the second node; a second PMOS transistor connected between the power supply voltage and a third node and having a gate electrode connected to the first node; a second NMOS transistor connected between a ground voltage and the third node and having a gate electrode connected to the first node; a third PMOS transistor connected between the power supply voltage and the cell output node and having a gate electrode connected to the third node; and A third NMOS transistor is connected between the ground voltage and the cell output node and has a gate electrode connected to the third node.

17. The circuit of claim 16, wherein: In response to the mode signal having a logic high level, the first NMOS transistor is turned on and the sensitivity to the threshold voltage of the second NMOS transistor increases, and In response to the mode signal having a logic low level, the first PMOS transistor is turned on and the sensitivity to the threshold voltage of the second PMOS transistor increases.

18. A circuit for detecting a threshold voltage, the circuit comprising: a pulse generator configured to generate an input pulse signal based on an input clock signal; a first delay circuit, the first delay circuit having a first sensitivity to a threshold voltage of a transistor, the first delay circuit being configured to receive the input pulse signal and a digital control code, and being configured to generate a first output signal delayed by a first delay time relative to the input pulse signal, the first delay time being changed according to the digital control code; a second delay circuit having a second sensitivity higher than the first sensitivity, the second delay circuit being configured to receive the input pulse signal and configured to generate a second output signal delayed by a second delay time relative to the input pulse signal; a phase detector configured to generate a phase detection signal by comparing a phase of the first output signal with a phase of the second output signal; as well as A control logic circuit is configured to generate a digital control code whose value increases or decreases according to a logic level of the phase detection signal.

19. A high-sensitivity delay unit, comprising: A first PMOS transistor, the first PMOS transistor is connected between the cell input node and the first node and has a gate electrode configured to receive a mode signal, PMOS being a P-type metal oxide semiconductor; a first NMOS transistor, the first NMOS transistor being connected in parallel with the first PMOS transistor between the cell input node and the first node and having a gate electrode configured to receive the mode signal, wherein the NMOS is an N-type metal oxide semiconductor; a buffer circuit connected between the cell input node and a second node; a boost capacitor connected between the first node and the second node; a second PMOS transistor connected between the power supply voltage and a third node and having a gate electrode connected to the first node; a second NMOS transistor connected between a ground voltage and the third node and having a gate electrode connected to the first node; a third PMOS transistor connected between the power supply voltage and the cell output node and having a gate electrode connected to the third node; as well as A third NMOS transistor is connected between the ground voltage and the cell output node and has a gate electrode connected to the third node.

20. The high-sensitivity delay unit according to claim 19, wherein: In response to the mode signal having a logic high level, sensitivity to threshold voltages of the first NMOS transistor and the second NMOS transistor increases, and In response to the mode signal having a logic low level, sensitivity to threshold voltages of the first PMOS transistor and the second PMOS transistor increases.

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