Level shift circuit used for stepping motor driving
By designing a level shift circuit that assists the upper and lower pull-down circuits in the stepper motor driving circuit, the problem of large transmission delay of the traditional level shift circuit is solved, and the response speed and performance of the driving circuit are improved.
Patent Information
- Application Number
- CN202411834345.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-13
- Publication Date
- 2025-04-08
AI Technical Summary
In stepper motor driving circuit without bootstrap capacitors, the level shift circuit needs to convert the low-voltage power rail output from the internal logic into a high-voltage power rail to control the opening of the power tube on the H bridge, resulting in a large transmission delay and affecting the response speed of the driving circuit.
A level displacement circuit including a main body level displacement structure and an auxiliary up-and-pull-down circuit is designed. The third PMOS tube M9 and the fourth PMOS tube M10 assist in pull-up, and the first NMOS tube M7 and the second NMOS tube M8 assist in pull-down, reducing the rise and fall time of points A and B and reducing the transmission delay.
It effectively reduces the transmission delay of the level shift circuit, improves the response speed and performance of the stepper motor driving circuit, and can work normally at high voltages.
Smart Images
Figure CN119788051A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a level shift circuit for driving a stepping motor. Background Art
[0002] In the stepper motor drive circuit without bootstrap capacitor, there are three power rail conversion issues involved. The first is the low-voltage power rail output by the internal logic, the second is the high-voltage power rail input by the external input, and the third is the high-voltage power rail generated by the internal charge pump. The upper power tube of the H bridge in the stepper motor drive circuit needs the high-voltage power rail generated by the internal charge pump to turn on, so a level shift circuit is required to convert the low-voltage power rail output by the internal logic to the high-voltage power rail, so as to control the subsequent pre-drive circuit to work normally. Reducing the transmission delay of the level shift circuit is conducive to improving the response speed of the drive circuit. Summary of the invention
[0003] In view of the above problems, the present invention provides a level shift circuit which can meet the needs of a high-side pre-driving circuit for driving a stepping motor.
[0004] The technical solution of the present invention is:
[0005] A level shift circuit for driving a stepping motor, comprising a first N-type LDMOS tube M1, a second N-type LDMOS tube M2, a first P-type LDMOS tube M3, a second P-type LDMOS tube M4, a first NMOS tube M7, a second NMOS tube M8, a first PMOS tube M5, a second PMOS tube M6, a third PMOS tube M9, a fourth PMOS tube M10, a first resistor R1, a second resistor R2, a first capacitor C1, a second capacitor C2, a first NAND gate nand1, a second NAND gate nand2, a second NAND gate nand3, a first NAND gate nand4, a second NAND gate nand5, a first NAND gate nand6, a second NAND gate nand7, a first NAND gate nand8, a second NAND gate nand9, a first NAND gate nand10, a second NAND gate nand11, a first NMOS tube M12, a second NMOS tube M13, a first PMOS tube M14, a second PMOS tube M15, a first and2, a first inverter inv1, a second inverter inv2, a third inverter inv3, a fourth inverter inv4, a fifth inverter inv5, a sixth inverter inv6, a seventh inverter inv7, an eighth inverter inv8, a ninth inverter inv9, a tenth inverter inv10, an eleventh inverter inv11, a twelfth inverter inv12, a thirteenth inverter inv13, a fourteenth inverter inv14, a fifteenth inverter inv15, and a sixteenth inverter inv16;
[0006] The gate of the first N-type LDMOS tube M1 is connected to the INP input signal, the drain is connected to the M3 drain, and the source is grounded GND; the gate of the second N-type LDMOS tube M2 is connected to the INN input signal, the drain is connected to the M4 drain, and the source is grounded GND; the gate of the first P-type LDMOS tube M3 is connected to the VM node, and the source is connected to the A node; the gate of the second P-type LDMOS tube M4 is connected to the VM node, and the source is connected to the B node; the gate of the first NMOS tube M7 is connected to the output terminal of the sixteenth inverter inv16, the drain is connected to the A node, and the source is connected to the VM node; the gate of the second NMOS tube M8 is connected to the output terminal of the fifteenth inverter inv15, the drain is connected to the B node, The source is connected to the VM node; the gate of the first PMOS tube M5 is connected to the B node, the drain is connected to the A node, and the source is connected to the power supply VCP; the gate of the second PMOS tube M6 is connected to the A node, the drain is connected to the B node, and the source is connected to the power supply VCP; the gate of the third PMOS tube M9 is connected to the output end of the sixth inverter inv6, the drain is connected to the A node, and the source is connected to the power supply VCP; the gate of the fourth PMOS tube M10 is connected to the output end of inv12, the drain is connected to the B node, and the source is connected to the power supply VCP; one end of the first resistor R1 is connected to the output end of the second inverter inv2, and the other end is connected to the input end of the third inverter inv3 and one end of C1; one end of the second resistor R2 is connected to the eighth inverter inv8 output terminal, the other end is connected to the ninth inverter inv9 input terminal and one end of C2; one end of the first capacitor C1 is connected to one end of the resistor R1 and the third inverter inv3 input terminal, and the other end is connected to the VM node; one end of the second capacitor C2 is connected to one end of the resistor R2 and the ninth inverter inv9 input terminal, and the other end is connected to the VM node; one input end of the first NAND gate nand1 is connected to the first inverter inv1 output terminal, the other input end is connected to the fourth inverter inv4 output terminal, and the output end is connected to the fifth inverter inv5 input terminal; one input end of the second NAND gate nand2 is connected to the inv7 output terminal, the other input end is connected to the inv10 output terminal, and the output end is connected connected to the input end of inv11; the input end of the first inverter inv1 is connected to the B node, and the output end is connected to the input ends of the second inverter inv2, the thirteenth inverter inv13, the sixteenth inverter inv16, and the first NAND gate nand1; the input end of the second inverter inv2 is connected to the output end of the first inverter inv1, and the output end is connected to one end of the first resistor R1; the input end of the third inverter inv3 is connected to one end of the first resistor R1 and one end of the first capacitor C1, and the output end is connected to the input end of the fourth inverter inv4; the input end of the fourth inverter inv4 is connected to the output end of the third inverter inv3, and the output end is connected to one end of the input of the first NAND gate nand1;The input end of the fifth inverter inv5 is connected to the output end of the first NAND gate nand1, and the output end is connected to the input end of the sixth inverter inv6; the input end of the sixth inverter inv6 is connected to the output end of the fifth inverter inv5, and the output end is connected to the gate of the third PMOS tube M9; the input end of the seventh inverter inv7 is connected to the A node, and the output end is connected to the input end of the eighth inverter inv8 and one end of the second NAND gate nand2 input; the input end of the eighth inverter inv8 is connected to the output end of the seventh inverter inv7, and the output end is connected to one end of the second resistor R2; the input end of the ninth inverter inv9 is connected to one end of the second resistor R2 and one end of the second capacitor C2, and the output end is connected to the input end of the tenth inverter inv10; the input end of the tenth inverter inv10 is connected to the output end of the ninth inverter inv9, and the output end is connected to one end of the second NAND gate nand2 input; The input end of the inverter inv11 is connected to the output end of the second NAND gate nand2, and the output end is connected to the input end of the twelfth inverter inv12; the input end of the twelfth inverter inv12 is connected to the output end of the eleventh inverter inv11, and the output end is connected to the gate of the fourth PMOS tube M10; the input end of the thirteenth inverter inv13 is connected to the output end of the eleventh inverter inv1, and the output end is connected to the input end of the fourteenth inverter inv14; the input end of the fourteenth inverter inv14 is connected to the output end of the thirteenth inverter inv13, and the output end is connected to the OUT output signal; the input end of the fifteenth inverter inv15 is connected to the output end of inv16, and the output end is connected to the gate of the second NMOS tube M8; the input end of the sixteenth inverter inv16 is connected to the output end of the first inverter inv1, and the output end is connected to the gate of the first NMOS tube M7 and the input end of the fifteenth inverter inv15. ;
[0007] The beneficial effects of the present invention are as follows: compared with the traditional level shift circuit, the present invention can effectively reduce the transmission delay of the level shift circuit by auxiliary pull-up and pull-down circuits, thereby improving the performance of the stepping motor drive circuit. BRIEF DESCRIPTION OF THE DRAWINGS
[0008] Figure 1 It is a traditional stepper motor level shift circuit diagram.
[0009] Figure 2 The present invention provides a level shift circuit diagram for driving a stepping motor. DETAILED DESCRIPTION
[0010] The present invention will be described in detail below with reference to the accompanying drawings.
[0011] Figure 1 This is a traditional stepper motor level shift circuit diagram, and its specific working process is as follows:
[0012] INN and INP are inverted input signals. When the input INN is low, INP is high, M1 is turned on, M2 is turned off, M1 pulls point A down, and M6 turns on to pull the potential of point B to VCP, realizing the level shift conversion function. This circuit has two disadvantages. The first is that the pull-down speed is slow. Since the gate-source voltage of the transistor is not enough, M3 and M4 are used to limit the voltage. However, the potential of points A and B needs to reach VM. The subthreshold conduction characteristics of M3 and M4 are required. The subthreshold current is small, which limits the pull-down speed; the second is that the potential of points A and B can only be pulled up by M5 and M6, and there will be a very long Miller platform area, which limits the pull-up speed.
[0013] Based on the above problems, the present invention proposes Figure 2 The level shift circuit. The first N-type LDMOS tube M1, the second N-type LDMOS tube M2, the first P-type LDMOS tube M3, the second P-type LDMOS tube M4, the first PMOS tube M5, and the second PMOS tube M6 constitute the main level shift structure; the third PMOS tube M9, the fourth PMOS tube M10, the first resistor R1, the second resistor R2, the first capacitor C1, the second capacitor C2, the first NAND gate nand1, the second NAND gate nand2, the first inverter inv1, the second inverter inv2, the third inverter inv3, The fourth inverter inv4, the fifth inverter inv5, the sixth inverter inv6, the seventh inverter inv7, the eighth inverter inv8, the ninth inverter inv9, the tenth inverter inv10, the eleventh inverter inv11 and the twelfth inverter inv12 constitute an auxiliary pull-up branch; the first NMOS tube M7, the second NMOS tube M8, the fifteenth inverter inv15 and the sixteenth inverter inv16 constitute an auxiliary pull-down branch; the thirteenth inverter inv13 and the fourteenth inverter inv14 provide output levels.
[0014] Specifically, its working principle is as follows: INN and INP are inverted input signals. When the input INN is low, INP is high. At this time, the potential of point A is VM, and the potential of point B is VCP. When the input INN becomes high, INP becomes low, M1 is turned off, and M2 is turned on to provide a pull-down current to pull the potential of point B down. During the process of reducing the potential of point B, inv1, inv15, and inv16 provide a high level for the gate of M8 to turn on M8, and provide a large pull-down current for point B so that point B is quickly pulled down to VM. During the process of pulling point B down, M5 is turned on to provide a pull-up current for point A, pulling point A up. During the process of the potential of point A rising, a delay path is formed through inv8, R2, C2, inv9, and inv10, which will cause nand2 to output a low-level narrow pulse. Through inv11 and inv12, the narrow pulse is output to the gate of M10 to turn on M10, generating a large pull-up current to quickly pull node A up. When the input INN changes from high level to low level, INP changes from low level to high level, M2 turns off, M1 turns on to provide a pull-down current, and pulls down the potential of point A. During the process of reducing the potential of point A, inv1 and inv16 provide a high level for the gate of M7 to turn on M7, providing a large pull-down current for point A so that point A is quickly pulled down to VM. During the process of pulling point A down, M6 turns on to provide a pull-up current for point B, pulling point B up. During the process of the potential of point B rising, a delay path is formed through inv2, R1, C1, inv3, and inv4, which will cause nand1 to output a low-level narrow pulse. Through inv5 and inv6, the narrow pulse is output to the gate of M9 to turn on M9, generating a large pull-up current to quickly pull up node B. The potential of point B is provided with a larger current driving capability through inv1, inv13, and inv14, and then output to the subsequent circuit in an inverted manner.
[0015] In summary, the circuit of the present invention realizes the conversion of 0-5V INP and INN input signals into high-voltage VCP-VM output signals, wherein the VM voltage can reach up to 44V, and VCP is the VM+5V voltage generated by the charge pump of the driving circuit, so M1-M4 use LDMOS with higher voltage resistance. Among them, M9 and M10 are auxiliary pull-up tubes, which can reduce the rise time of points A and B. M7 and M8 are auxiliary pull-down tubes, which can pull the voltage of points A and B down to VM through positive feedback. Compared with the traditional level shift circuit, this circuit has smaller transmission delay, more accurate transmission signal, and can work normally under high voltage.
Claims
1. A level shift circuit for stepping motor driving, characterized in that: The device includes a first N-type LDMOS tube M1, a second N-type LDMOS tube M2, a first P-type LDMOS tube M3, a second P-type LDMOS tube M4, a first NMOS tube M7, a second NMOS tube M8, a first PMOS tube M5, a second PMOS tube M6, a third PMOS tube M9, a fourth PMOS tube M10, a first resistor R1, a second resistor R2, a first capacitor C1, a second capacitor C2, a first NAND gate nand1, a second NAND gate nand2, a first inverting inv1, a second inverter inv2, a third inverter inv3, a fourth inverter inv4, a fifth inverter inv5, a sixth inverter inv6, a seventh inverter inv7, an eighth inverter inv8, a ninth inverter inv9, a tenth inverter inv10, an eleventh inverter inv11, a twelfth inverter inv12, a thirteenth inverter inv13, a fourteenth inverter inv14, a fifteenth inverter inv15, and a sixteenth inverter inv16; The gate of the first N-type LDMOS tube M1 is connected to the INP input signal, the drain is connected to the M3 drain, and the source is grounded GND; the gate of the second N-type LDMOS tube M2 is connected to the INN input signal, the drain is connected to the M4 drain, and the source is grounded GND; the gate of the first P-type LDMOS tube M3 is connected to the VM node, and the source is connected to the A node; the gate of the second P-type LDMOS tube M4 is connected to the VM node, and the source is connected to the B node; the gate of the first NMOS tube M7 is connected to the output end of the sixteenth inverter inv16, the drain is connected to the A node, and the source is connected to the VM node; the gate of the second NMOS tube M8 is connected to the output end of the fifteenth inverter inv15, the drain is connected to the B node, and the source is connected to the VM node; the gate of the first PMOS tube M5 is connected to the B node, the drain is connected to the A node, and the source is connected to the power supply VCP; The gate of the second PMOS tube M6 is connected to the A node, the drain is connected to the B node, and the source is connected to the power supply VCP; The gate of the third PMOS tube M9 is connected to the output end of the sixth inverter inv6, the drain is connected to the A node, and the source is connected to the power supply VCP; The gate of the fourth PMOS tube M10 is connected to the output end of inv12, the drain is connected to the B node, and the source is connected to the power supply VCP; one end of the first resistor R1 is connected to the output end of the second inverter inv2, and the other end is connected to the input end of the third inverter inv3 and one end of C1; one end of the second resistor R2 is connected to the output end of the eighth inverter inv8, and the other end is connected to the input end of the ninth inverter inv9 and one end of C2; one end of the first capacitor C1 is connected to one end of the resistor R1 and the input end of the third inverter inv3, and the other end is connected to the VM node; one end of the second capacitor C2 is connected to one end of the resistor R2 and the input end of the ninth inverter inv9, and the other end is connected to the VM node; one input end of the first NAND gate nand1 is connected to the output end of the first inverter inv1, the other input end is connected to the output end of the fourth inverter inv4, and the output end is connected to the input end of the fifth inverter inv5; one input end of the second NAND gate nand2 is connected to the output end of inv7, and the other input end is connected to the output end of inv10 , the output end is connected to the input end of inv11; the input end of the first inverter inv1 is connected to the B node, and the output end is connected to the input end of the second inverter inv2, the thirteenth inverter inv13, the sixteenth inverter inv16, and the first NAND gate nand1; the input end of the second inverter inv2 is connected to the output end of the first inverter inv1, and the output end is connected to one end of the first resistor R1; the input end of the third inverter inv3 is connected to one end of the first resistor R1 and one end of the first capacitor C1, and the output end is connected to the input end of the fourth inverter inv4; the input end of the fourth inverter inv4 is connected to the output end of the third inverter inv3, and the output end is connected to one end of the first NAND gate nand1 input; the input end of the fifth inverter inv5 is connected to the output end of the first NAND gate nand1, and the output end is connected to the input end of the sixth inverter inv6; the input end of the sixth inverter inv6 is connected to the output end of the fifth inverter inv5, and the output end is connected to the gate of the third PMOS tube M9; The input end of the seventh inverter inv7 is connected to the A node, and the output end is connected to the input end of the eighth inverter inv8 and one end of the second NAND gate nand2 input; the input end of the eighth inverter inv8 is connected to the output end of the seventh inverter inv7, and the output end is connected to one end of the second resistor R2; the input end of the ninth inverter inv9 is connected to one end of the second resistor R2 and one end of the second capacitor C2, and the output end is connected to the input end of the tenth inverter inv10; the input end of the tenth inverter inv10 is connected to the output end of the ninth inverter inv9, and the output end is connected to one end of the second NAND gate nand2 input; the input end of the eleventh inverter inv11 is connected to the output end of the second NAND gate nand2, and the output end is connected to the input end of the twelfth inverter inv12 The input end of the twelfth inverter inv12 is connected to the output end of the eleventh inverter inv11, and the output end is connected to the gate of the fourth PMOS tube M10; the input end of the thirteenth inverter inv13 is connected to the output end of the eleventh inverter inv1, and the output end is connected to the input end of the fourteenth inverter inv14; the input end of the fourteenth inverter inv14 is connected to the output end of the thirteenth inverter inv13, and the output end is connected to the OUT output signal; the input end of the fifteenth inverter inv15 is connected to the output end of inv16, and the output end is connected to the gate of the second NMOS tube M8; the input end of the sixteenth inverter inv16 is connected to the output end of the first inverter inv1, and the output end is connected to the gate of the first NMOS tube M7 and the input end of the fifteenth inverter inv15.