Mode conversion circuit

Abstract

The present invention belongs to the technical field of integrated circuits, and particularly relates to a mode conversion circuit. A mode conversion circuit includes a chip select signal and an initial clock signal, and further includes: a latch configured such that when the levels of the chip select signal and the initial clock signal are the same, the output terminal of the latch is opposite to the level of the initial clock signal, and when the levels of the chip select signal and the initial clock signal are opposite, the output terminal of the latch latches; a first NAND gate, with the first input terminal connected to the output terminal of the latch and the second input terminal connected to the initial clock signal; a first inverter, with the input terminal connected to the output terminal of the first NAND gate and the output terminal serving as the target clock signal. The present invention can convert mode 3 to mode 0, which brings convenience to the clock analysis of digital designs.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and particularly relates to a mode conversion circuit. Background Art

[0002] During the operation of integrated circuits, there are situations where multiple input modes coexist. As shown in Figure 1 , there are two input modes, namely mode 0 and mode 3. In mode 0, after the chip select signal CS is pulled low, data is sampled at the first rising edge of the initial clock signal CLK. In mode 3, after CS is pulled low, data is sampled when CLK falls and then rises, that is, at the second edge of CLK. Since the generation time of the first edge in mode 3 is uncertain, it brings problems to the timing design of digital designs. Summary of the Invention

[0003] Aiming at the technical problem of difficult timing design when multiple input modes coexist during the operation of integrated circuits, the present invention aims to provide a mode conversion circuit.

[0004] A mode conversion circuit includes a chip select signal and an initial clock signal, and further includes:

[0005] A latch configured such that when the levels of the chip select signal and the initial clock signal are the same, the output terminal of the latch is opposite to the level of the initial clock signal, and when the levels of the chip select signal and the initial clock signal are opposite, the output terminal of the latch latches;

[0006] A first NAND gate, with the first input terminal connected to the output terminal of the latch and the second input terminal connected to the initial clock signal;

[0007] A first inverter, with the input terminal connected to the output terminal of the first NAND gate and the output terminal serving as the target clock signal.

[0008] As a preferred solution, the latch may include:

[0009] A second inverter, with the input terminal connected to the chip select signal;

[0010] A second NAND gate, with the first input terminal connected to the output terminal of the second inverter;

[0011] A first two-way data selector, with the first input terminal connected to the chip select signal, the second input terminal connected to the output terminal of the second NAND gate, and the data selection terminal connected to the initial clock signal;

[0012] A third inverter, with the input terminal connected to the output terminal of the first two-way data selector and the output terminal respectively connected to the second input terminal of the second NAND gate and the first input terminal of the first NAND gate.

[0013] As a preferred solution, the latch may include:

[0014] A fourth inverter, the input end of which is connected to the chip select signal;

[0015] A first AND gate, the first input end of which is connected to the output end of the fourth inverter;

[0016] A second two-way data selector, the first input end of which is connected to the output end of the fourth inverter, the second input end of which is connected to the output end of the first AND gate, the data selection end of which is connected to the initial clock signal, and the output end of which is respectively connected to the second input end of the first AND gate and the first input end of the first NAND gate.

[0017] As a preferred solution, the latch may further include:

[0018] A fifth inverter, the input end of which is connected to the initial clock signal;

[0019] A third NAND gate, the first input end of which is connected to the initial clock signal;

[0020] A third two-way data selector, the first input end of which is connected to the output end of the third NAND gate, the second input end of which is connected to the chip select signal, and the data selection end of which is connected to the output end of the fifth inverter;

[0021] A first NOR gate, the first input end of which is connected to the chip select signal, the second input end of which is connected to the output end of the third two-way data selector, and the output end of which is respectively connected to the second input end of the third NAND gate and the first input end of the first NAND gate.

[0022] The positive and progressive effects of the present invention are as follows: The present invention adopts a mode conversion circuit, which can convert mode 3 into mode 0, bringing convenience to the clock analysis of digital design. Description of the Drawings

[0023] Figure 1 Is a timing diagram of mode 0 and mode 3;

[0024] Figure 2 Is a logic circuit diagram of the present invention;

[0025] Figure 3 Is a timing diagram of the present invention;

[0026] Figure 4 Is a logic circuit diagram of Embodiment 1 of the present invention;

[0027] Figure 5 Is a logic circuit diagram of Embodiment 2 of the present invention;

[0028] Figure 6A logic circuit diagram for Embodiment 3 of the present invention. Detailed implementation manners

[0029] In order to make the technical means, creative features, achieved purposes and effects of the present invention easy to understand, the present invention will be further described below with reference to specific illustrations.

[0030] Refer to Figure 2 and Figure 3 , a mode conversion circuit, including a chip select signal CS, an initial clock signal CLK, a latch U1, a first NAND gate F1, a first inverter G1, and a target clock signal CLK_IN.

[0031] The latch U1 is configured such that when the levels of the chip select signal CS and the initial clock signal CLK are the same, the output terminal of the latch U1 is opposite to the level of the initial clock signal CLK. When the levels of the chip select signal CS and the initial clock signal CLK are opposite, the output terminal of the latch U1 is latched, that is, when the levels of the chip select signal CS and the initial clock signal CLK are opposite, the output terminal of the latch U1 maintains the level of the previous state unchanged.

[0032] Refer to Figure 2 , the output terminal of the latch U1 is connected to the first input terminal of the first NAND gate F1. The second input terminal of the first NAND gate F1 is connected to the initial clock signal CLK, the output terminal of the first NAND gate F1 is connected to the input terminal of the first inverter G1, and the output terminal of the first inverter G1 serves as the target clock signal CLK_IN.

[0033] When CS = H (high level) and CLK = H, the output terminal A point of the latch U1 is L (low level), then CLK_IN = L;

[0034] When CS = L and CLK = H, the output terminal A point of the latch U1 maintains the previous state, then CLK_IN = , that is, CLK_IN is the result of the initial clock signal CLK and the previous state of the output terminal A point passing through the first NAND gate F1 and then being inverted by the first inverter G1;

[0035] When CS = L and CLK = L, the output terminal A point of the latch U1 is H, then CLK_IN = CLK.

[0036] Refer to Figure 3 , according to the above principle, in Mode 3, after the chip select signal CS is pulled low, the waveform of the initial clock signal CLK can be converted to CLK_IN. At this time, in the case of Mode 3, data can be collected at the first rising edge of CLK_IN, which is the same as in Mode 0.

[0037] Embodiment 1, the latch U1 of the present invention can adopt the following circuit:

[0038] Reference Figure 4 As shown in Figure 4 , the latch U1 includes a second inverter G2, a second NAND gate F2, a first two-way data selector M1, and a third inverter G3.

[0039] The input terminal of the second inverter G2 is connected to the chip select signal CS, and the output terminal of the second inverter G2 is connected to the first input terminal of the second NAND gate F2. The first input terminal of the first two-way data selector M1 is connected to the chip select signal CS, the second input terminal of the two-way data selector M1 is connected to the output terminal of the second NAND gate F2, and the data selection terminal of the first two-way data selector M1 is connected to the initial clock signal CLK. The input terminal of the third inverter G3 is connected to the output terminal of the first two-way data selector M1, and the output terminal of the third inverter G3 is respectively connected to the second input terminal of the second NAND gate F2 and the first input terminal of the first NAND gate F1.

[0040] Take the output terminal of the latch U1, that is, the output terminal of the third inverter G3, as point A; take the second input terminal of the first two-way data selector M1 as point B; take the first input terminal of the first two-way data selector M1 as point C; take the output terminal of the second inverter G2 as point D;

[0041] Then when CLK = H, A = ; when CLK = L, A = .

[0042] When CS = H and CLK = H, D = = L, B = = H, A = = L, then CLK_IN = L;

[0043] When CS = L and CLK = H, D = = H, A = = keep the previous state, then CLK_IN = ;

[0044] When CS = L and CLK = L, A = = = H, then CLK_IN = CLK.

[0045] Embodiment 2, the latch U1 of the present invention can adopt the following circuit:

[0046] Reference Figure 5 As shown in Figure 5 , the latch U1 includes a fourth inverter G4, a first AND gate F3, and a second two-way data selector M2.

[0047] The input terminal of the fourth inverter G4 is connected to the chip select signal CS. The first input terminal of the first AND gate F3 is connected to the output terminal of the fourth inverter G4. The first input terminal of the second two-way data selector M2 is connected to the output terminal of the fourth inverter G4. The second input terminal of the second two-way data selector M2 is connected to the output terminal of the first AND gate F3. The data selection terminal of the second two-way data selector M2 is connected to the initial clock signal CLK. The output terminals of the second two-way data selector M2 are respectively connected to the second input terminal of the first AND gate F3 and the first input terminal of the first NAND gate F1.

[0048] Take the output terminal of the latch U1, that is, the output terminal of the second two-way data selector M2, as point A; take the output terminal of the fourth inverter G4 as point B; take the output terminal of the first AND gate F3 as point C;

[0049] Then when CLK = H, A = C; when CLK = L, A = B.

[0050] When CS = H and CLK = H, B = = L, C = B * A = L, A = C = L, then CLK_IN = L;

[0051] When CS = L and CLK = H, B = = H, A = C = maintain the previous state of A, then CLK_IN = ;

[0052] When CS = L and CLK = L, A = B = = H, then CLK_IN = CLK.

[0053] Embodiment 3, the latch U1 of the present invention can adopt the following circuit:

[0054] Refer to Figure 6 The latch U1 includes a fifth inverter G5, a third NAND gate F4, a third two-way data selector M3, and a first NOR gate F5.

[0055] The input terminal of the fifth inverter G5 is connected to the initial clock signal CLK. The first input terminal of the third NAND gate F4 is connected to the initial clock signal CLK. The first input terminal of the third two-way data selector M3 is connected to the output terminal of the third NAND gate F4. The second input terminal of the third two-way data selector M3 is connected to the chip select signal CS. The data selection terminal of the third two-way data selector M3 is connected to the output terminal of the fifth inverter G5. The first input terminal of the first NOR gate F5 is connected to the chip select signal CS. The second input terminal of the first NOR gate F5 is connected to the output terminal of the third two-way data selector M3. The output terminal of the first NOR gate F5 is respectively connected to the second input terminal of the third NAND gate F4 and the first input terminal of the first NAND gate F1.

[0056] Take the output terminal of the latch U1, i.e., the output terminal of the first NOR gate F5, as point A; take the output terminal of the third NAND gate F4 as point B; take the output terminal of the third two-way data selector M3 as point C.

[0057] Then when CLK = H, C = B; when CLK = L, C = CS.

[0058] When CS = H and CLK = H, A = = L, then CLK_IN = L;

[0059] When CS = L and CLK = H, B = = , C = B = , A = = = Keep the previous state of A, then CLK_IN = ;

[0060] When CS = L and CLK = L, C = CS, A = = H, then CLK_IN = CLK.

[0061] The above shows and describes the basic principles, main features and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited by the above embodiments. What is described in the above embodiments and the specification only illustrates the principles of the present invention. Without departing from the spirit and scope of the present invention, the present invention will have various changes and improvements, and these changes and improvements all fall within the scope of the present invention claimed. The scope of the present invention claimed is defined by the appended claims and their equivalents.

Claims

1. A mode conversion circuit, comprising a chip select signal and an initial clock signal, characterized in that, Further comprising: A latch configured such that when the level of the chip select signal is the same as that of the initial clock signal, the output of the latch is opposite to the level of the initial clock signal, and when the level of the chip select signal is opposite to that of the initial clock signal, the output of the latch is latched; A first NAND gate, with the first input terminal connected to the output of the latch and the second input terminal connected to the initial clock signal; A first inverter, with the input terminal connected to the output of the first NAND gate and the output terminal serving as the target clock signal; The latch includes: A second inverter, with the input terminal connected to the chip select signal; A second NAND gate, with the first input terminal connected to the output of the second inverter; A first two-way data selector, with the first input terminal connected to the chip select signal, the second input terminal connected to the output of the second NAND gate, and the data selection terminal connected to the initial clock signal; A third inverter, with the input terminal connected to the output of the first two-way data selector and the output terminal respectively connected to the second input terminal of the second NAND gate and the first input terminal of the first NAND gate; Alternatively, the latch includes: A fourth inverter, with the input terminal connected to the chip select signal; A first AND gate, with the first input terminal connected to the output of the fourth inverter; A second two-way data selector, with the first input terminal connected to the output of the fourth inverter, the second input terminal connected to the output of the first AND gate, the data selection terminal connected to the initial clock signal, and the output terminal respectively connected to the second input terminal of the first AND gate and the first input terminal of the first NAND gate; Alternatively, the latch includes: A fifth inverter, with the input terminal connected to the initial clock signal; A third NAND gate, with the first input terminal connected to the initial clock signal; A third two-way data selector, with the first input terminal connected to the output of the third NAND gate, the second input terminal connected to the chip select signal, and the data selection terminal connected to the output of the fifth inverter; A first NOR gate, with the first input terminal connected to the chip select signal, the second input terminal connected to the output of the third two-way data selector, and the output terminal respectively connected to the second input terminal of the third NAND gate and the first input terminal of the first NAND gate.

Images