Continuous time linear equalizer and high-speed serial interface circuit

Abstract

The invention discloses a continuous time linear equalizer and a high-speed serial interface circuit, relates to the technical field of communication, and aims to solve the problems of narrow high-frequency gain adjustment range and unstable peak gain frequency of the continuous time linear equalizer in the prior art. Comprising a high-frequency gain compensation module and an overall gain control module, the high-frequency gain compensation module is cascaded with the overall gain control module; the overall gain control module is used for performing gain control on an output signal of the high-frequency gain compensation module; the high-frequency gain compensation module comprises a plurality of active inductor units, and each active inductor unit comprises an NMOS (N-channel Metal Oxide Semiconductor) tube and a grid resistor; the first end of the grid resistor is connected with the grid electrode of the NMOS tube, and the second end of the grid resistor and the drain electrode of the NMOS tube are connected with power supply voltage. According to the multi-stage equalizer structure based on the active inductor unit, wide-range peak gain adjustment of the equalizer under a stable peak gain frequency can be realized.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a continuous time linear equalizer and a high-speed serial interface circuit. Background Art

[0002] With the rapid development of broadband data communication, high-speed serial interface circuit (serializer / deserializer, SerDes) has gradually become the mainstream technology of high-speed interface due to its advantages of low cost, strong anti-interference and high transmission rate. However, the loss caused by the non-ideal characteristics of the channel leads to inter-symbol interference, which limits the further improvement of data transmission rate.

[0003] The continuous time linear equalizer (CTLE) solution commonly used at the receiving end of the SerDes system can effectively achieve high-frequency boost, thereby compensating for the greater attenuation of the channel to high-frequency signals. However, traditional CTLE usually compresses the low-frequency gain to obtain a greater high-frequency gain compensation. The reduction of low-frequency gain will sacrifice signal swing and reduce sampling margin.

[0004] Figure 1 The existing solution shown achieves the adjustment of high-frequency gain by adjusting the source degeneration capacitance and the transfer function. However, the influence of the parasitic capacitance results in a limited adjustment range of the high-frequency gain.

[0005] Figure 2 The existing solution shown is a CTLE structure based on active inductance, which can effectively widen the bandwidth and has high-frequency gain adjustment capability, but its complex zero-pole coupling relationship causes the peak gain and peak frequency to move simultaneously. At the same time, its adjustment depends on parasitic capacitance, resulting in instability in the frequency corresponding to the high-frequency peak gain, making the technology less practical. Summary of the invention

[0006] The object of the present invention is to provide a continuous-time linear equalizer and a high-speed serial interface circuit, which are used to increase the adjustment range of the high-frequency gain of the continuous-time linear equalizer and improve the stability of the peak gain frequency of the high-frequency signal, so as to realize wide-range peak gain adjustment of the equalizer at a stable peak gain frequency.

[0007] In order to achieve the above object, the present invention provides the following technical solutions:

[0008] In a first aspect, the present invention provides a continuous time linear equalizer, comprising: a high frequency gain compensation module and an overall gain control module;

[0009] The high-frequency gain compensation module is cascaded with the overall gain control module; the overall gain control module is used to perform gain control on the output signal of the high-frequency gain compensation module;

[0010] The high-frequency gain compensation module includes multiple active inductance units, each of which includes an NMOS tube and a gate resistor; the first end of the gate resistor is connected to the gate of the NMOS tube, and the second end of the gate resistor and the drain of the NMOS tube are both connected to the power supply voltage.

[0011] Optionally, the high-frequency gain compensation module includes at least a high-gain adjustment submodule;

[0012] The plurality of active inductor units at least include a first active inductor unit and a second active inductor unit; the first active inductor unit includes a first NMOS transistor; the second active inductor unit includes a second NMOS transistor;

[0013] The high gain adjustment submodule includes the first active inductor unit, the second active inductor unit, a third NMOS transistor, a fourth NMOS transistor, a first resistor, a variable capacitor, a first current sink, and a second current sink;

[0014] Wherein, the drain of the third NMOS tube is connected to the source of the first NMOS tube;

[0015] The drain of the fourth NMOS tube is connected to the source of the second NMOS tube;

[0016] The first end of the variable capacitor, the first end of the first resistor and the first end of the first current sink are all connected to the source of the third NMOS transistor; the second end of the first current sink is grounded;

[0017] The second end of the variable capacitor, the second end of the first resistor and the first end of the second current sink are all connected to the source of the fourth NMOS transistor; the second end of the second current sink is grounded.

[0018] Optionally, the equivalent signal model of the first active inductor unit includes the gate resistor, the first current sink, a gate-drain capacitor, a gate-source capacitor and a drain-source capacitor;

[0019] Wherein, the first end of the gate resistor and the first end of the gate-drain capacitor are both connected to the first end of the gate-source capacitor;

[0020] The second end of the gate resistor and the second end of the gate-drain capacitor are both connected to the first end of the drain-source capacitor;

[0021] The second end of the gate-drain capacitor is also connected to the first end of the first current sink;

[0022] The second end of the gate-source capacitor is connected to the second end of the drain-source capacitor.

[0023] Optionally, the impedance expression of the first active inductor unit is:

[0024]

[0025] Where Z is the impedance; s is a complex variable; R g is the gate resistance; C gd is the gate-drain capacitance; C gs is the gate-source capacitance; C ds is the drain-source capacitance; g m is the equivalent transconductance.

[0026] Optionally, the high-frequency gain compensation module further includes a low-gain adjustment submodule; the low-gain adjustment submodule is cascaded with the high-gain adjustment submodule;

[0027] The plurality of active inductor units further include a third active inductor unit and a fourth active inductor unit; the third active inductor unit includes a fifth NMOS transistor, and the fourth active inductor unit includes a sixth NMOS transistor;

[0028] The low gain adjustment submodule includes the third active inductor unit, the fourth active inductor unit, the seventh NMOS tube and the eighth NMOS tube;

[0029] Wherein, the drain of the seventh NMOS tube is connected to the source of the fifth NMOS tube;

[0030] The drain of the eighth NMOS tube is connected to the source of the sixth NMOS tube.

[0031] Optionally, the overall gain control module includes a buffer submodule, an overall gain setting submodule and an output driving submodule;

[0032] The buffer submodule is cascaded with the overall gain setting submodule, and the overall gain setting submodule is cascaded with the output driving submodule;

[0033] Wherein, the buffer submodule is used to provide a fixed gain;

[0034] The overall gain setting submodule is used to adjust the overall gain;

[0035] The output driver submodule is used to provide gain and improve the load driving capability of the equalizer.

[0036] Optionally, the buffer submodule includes a ninth NMOS transistor, a tenth NMOS transistor, a first inductor and a second inductor;

[0037] Wherein, the first end of the first inductor is connected to the drain of the ninth NMOS tube; the second end of the first inductor is connected to the power supply;

[0038] The first end of the second inductor is connected to the drain of the tenth NMOS tube; the second end of the second inductor is connected to the power supply;

[0039] The gate of the ninth NMOS tube is connected to the first signal output terminal of the high-frequency gain compensation module;

[0040] The gate of the tenth NMOS tube is connected to the second signal output end of the high-frequency gain compensation module.

[0041] Optionally, the overall gain setting submodule includes an eleventh NMOS transistor, a twelfth NMOS transistor, a third inductor, a fourth inductor and a second resistor;

[0042] Wherein, the first end of the third inductor is connected to the drain of the eleventh NMOS tube; the second end of the third inductor is connected to the power supply;

[0043] The first end of the fourth inductor is connected to the drain of the twelfth NMOS tube; the second end of the fourth inductor is connected to the power supply;

[0044] The gate of the eleventh NMOS tube is connected to the drain of the ninth NMOS tube; the gate of the twelfth NMOS tube is connected to the drain of the tenth NMOS tube;

[0045] The first end of the second resistor is connected to the source of the eleventh NMOS transistor; the second end of the second resistor is connected to the source of the twelfth NMOS transistor.

[0046] Optionally, the output driver submodule includes a thirteenth NMOS tube, a fourteenth NMOS tube, a fifth inductor and a sixth inductor;

[0047] Wherein, the first end of the fifth inductor is connected to the drain of the thirteenth NMOS tube; the second end of the fifth inductor is connected to the power supply;

[0048] The first end of the sixth inductor is connected to the drain of the fourteenth NMOS tube; the second end of the sixth inductor is connected to the power supply;

[0049] The gate of the thirteenth NMOS tube is connected to the drain of the eleventh NMOS tube; the gate of the fourteenth NMOS tube is connected to the drain of the twelfth NMOS tube.

[0050] Compared with the prior art, the present invention provides a wide-range continuous-time linear equalizer. In the embodiment of the present invention, firstly, the active inductor unit is changed from the structure in the prior art solution 2 to the structure in which the gate resistor is connected to the AC ground in this embodiment, thereby simplifying the frequency characteristics of the impedance of the active inductor unit; secondly, an active inductor based on an NMOS tube is used to reduce the parasitic capacitance. In this way, the multi-stage equalizer structure based on the active inductor unit in the present invention can achieve a wide range of peak gain adjustment at a stable peak gain frequency.

[0051] In a second aspect, the present invention further provides a high-speed serial interface circuit, comprising any one of the continuous-time linear equalizers described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0053] Figure 1 A circuit schematic diagram of a continuous time linear equalizer provided by the prior art;

[0054] Figure 2 Another circuit schematic diagram of a continuous time linear equalizer provided in the prior art;

[0055] Figure 3 A circuit schematic diagram of a continuous time linear equalizer provided by an embodiment of the present invention;

[0056] Figure 4 One of the circuit principle diagrams of a high frequency gain compensation module provided by one embodiment of the present invention;

[0057] Figure 5 A schematic diagram of an equivalent signal model principle of an active inductor unit provided by an embodiment of the present invention;

[0058] Figure 6 A second circuit schematic diagram of a high frequency gain compensation module provided by an embodiment of the present invention;

[0059] Figure 7 A circuit schematic diagram of an overall gain control module provided by an embodiment of the present invention;

[0060] Figure 8 A circuit principle of a continuous time linear equalizer provided for one embodiment of the present invention;

[0061] Fig. 9 for Figure 1 The simulation result diagram of

[0062] Fig.10A corresponding embodiment of the present invention provides Figure 8 The simulation result diagram of .

[0063] Reference numerals: 10 - high frequency gain compensation module; 20 - overall gain control module; 11 - high gain adjustment submodule; 12 - low gain adjustment submodule; 21 - buffer submodule; 22 - overall gain setting submodule; 23 - output drive submodule;

[0064] 111 - a first active inductor unit; 112 - a second active inductor unit; 113 - a third active inductor unit; 114 - a fourth active inductor unit. DETAILED DESCRIPTION

[0065] In order to clearly describe the technical solutions of the embodiments of the present invention, in the embodiments of the present invention, words such as "first" and "second" are used to distinguish the same items or similar items with basically the same functions and effects. For example, the first threshold and the second threshold are only used to distinguish different thresholds, and their order is not limited. Those skilled in the art can understand that words such as "first" and "second" do not limit the quantity and execution order, and words such as "first" and "second" do not necessarily limit them to be different.

[0066] It should be noted that, in the present invention, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the present invention should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0067] In the present invention, "at least one" means one or more, "more than one" means two or more. "And / or" describes the association relationship of the associated objects, indicating that three types of relationships may exist.

[0068] For a continuous-time linear equalizer, its input signal contains high-frequency components and low-frequency components. In the transmission of the input signal, the ideal expectation is that the channel maintains the same degree of attenuation for signals of different frequencies.

[0069] The reality is that the signal is easily affected by non-ideal factors such as skin effect, dielectric loss and impedance mismatch during transmission, resulting in severe attenuation of the high-frequency components in the input signal. It is understandable that the channel in reality has a low-pass characteristic, which causes the channel to attenuate the low-frequency components less than the high-frequency components.

[0070] One of the main functions of the continuous time linear equalizer is to compensate for the attenuation of the high frequency components of the signal during the transmission process, to compensate for the high frequency components of the signal, and ultimately to ensure the correctness of the signal at the receiving end. Therefore, when designing a continuous time linear equalizer, on the one hand, it is expected that the equalizer can provide sufficient high frequency gain to compensate for the channel, and on the other hand, it is expected that the peak gain of the equalizer can be adjusted over a wide range to meet the application requirements of different channels and different scenarios.

[0071] In order to solve the above problems, the prior art proposes Solution 1 and Solution 2.

[0072] Figure 1 The figure shows the scheme 1 in the prior art. The scheme 1 is a single-stage CTLE structure based on adjusting the high-frequency gain by using the source degeneration capacitor. The high-frequency gain is compensated by adding a resistor and a capacitor to the source of the MOS tube to introduce a zero pole. The overall transfer function based on the scheme is:

[0073]

[0074] Among them, the zero point is |ω z |=1 / (R s C s );

[0075] Pole 1 is

[0076] Pole 2 is |ω p2 |=1 / (R L C L ),

[0077] A0 is the DC gain of the circuit; s is a complex variable; R s is the source resistance; C s is the source capacitance; g m g is the input tube gate transconductance; mb is the input tube substrate transconductance; R L is the load resistance; C L is the load capacitance; the low frequency gain is The high-frequency gain compensation provided by Scheme 1 is |ω p1 | / |ω z |.

[0078] Solution 1 adjusts the high-frequency equalization capability by adjusting the source degeneration resistor to compress the low-frequency gain and by adjusting the source degeneration capacitor to adjust the high-frequency gain.

[0079] The defect of solution 1 in the prior art is that the increase of source degeneration resistance will reduce (i.e., compress) the low-frequency gain, and sacrificing the low-frequency gain will reduce the sampling margin and require an additional broadband amplifier to compensate the low-frequency gain. In addition, due to the existence of parasitic capacitance, the adjustment range of the source degeneration capacitance is limited, so solution 1 further limits the adjustment range of the overall high-frequency gain compensation, which makes the application of solution 1 in high-speed signal transmission have great limitations.

[0080] Figure 2 The figure shows scheme 2 in the prior art. Scheme 2 is a CTLE structure based on active inductance. An additional zero point is provided by introducing active inductance at the load. On the one hand, the bandwidth is broadened, which is conducive to the application of high-speed signals. On the other hand, the active inductance structure also provides a certain adjustment capability.

[0081] Figure 2 The expression for the active inductor impedance in the structure shown is as follows:

[0082]

[0083] Among them, s is a complex variable; C DS for Figure 2 Drain-source capacitance in active inductors; C GD for Figure 2 Gate-drain capacitance in active inductor; C GS for Figure 2 Gate-source capacitance in active inductors; R D for Figure 2 A resistor in an active inductor; R G for Figure 2 Another resistor in the active inductor; g m is the PMOS transconductance in the active inductor; r0 is Figure 2 PMOS characteristic impedance in active inductor.

[0084] From the above formula, it can be concluded that this technology introduces the active inductor as a load into the second-order zero pole, thereby affecting the transfer function of the overall CTLE. By reasonably setting the parameter values, the bandwidth can be widened and a certain range of high-frequency gain compensation can be adjusted.

[0085] The defects of solution 2 in the prior art are: the introduced active inductor load has a relatively complex impedance and introduces a second-order zero pole, which leads to a relatively complex coupling relationship between the high-frequency equalization capability and the frequency of the peak gain, that is, it cannot be adjusted separately. In addition, the adjustment solution of this technology depends on the adjustment of the parasitic capacitance of the transistor, which is less feasible in actual design.

[0086] In order to solve the above problems, Figure 3As shown, an embodiment of the present invention provides a continuous time linear equalizer, including a high frequency gain compensation module 10 and an overall gain control module 20;

[0087] The high-frequency gain compensation module 10 is cascaded with the overall gain control module 20; the overall gain control module 20 is used to perform gain control on the output signal of the high-frequency gain compensation module;

[0088] See also Figure 4 and Figure 5 The high-frequency gain compensation module 10 includes a plurality of active inductance units, each of which includes an NMOS tube and a gate resistor R0, a first end of the gate resistor R0 is connected to the gate of the NMOS tube, and a second end of the gate resistor and a drain of the NMOS tube are both connected to a power supply voltage VDD.

[0089] Regarding cascading, cascading in circuits refers to connecting multiple circuit systems or devices in series in sequence, with the output of the previous system serving as the input of the next system. This connection method allows the signal to be gradually processed or amplified as it passes through each circuit element, ultimately achieving the desired output effect. It is used to implement complex signal processing functions and improve the performance and flexibility of the circuit. At the same time, through reasonable cascade design, the overall layout and wiring of the circuit can be optimized, reducing the cost and complexity of the circuit.

[0090] See also Figure 4 As shown, the high-frequency gain compensation module 10 at least includes a high-gain adjustment submodule 11;

[0091] The plurality of active inductor units at least include a first active inductor unit 111 and a second active inductor unit 112; the first active inductor unit 111 includes a first NMOS transistor N1; the second active inductor unit 112 includes a second NMOS transistor N21;

[0092] The high gain adjustment submodule 11 includes a first active inductor unit 111, a second active inductor unit 112, a third NMOS transistor N3, a fourth NMOS transistor N4, a first resistor R1, a variable capacitor C, a first current sink I1 and a second current sink I2; wherein the first resistor R1 is a variable resistor;

[0093] Wherein, the drain of the third NMOS tube N3 is connected to the source of the first NMOS tube N1;

[0094] The drain of the fourth NMOS tube N4 is connected to the source of the second NMOS tube N2;

[0095] The first end of the variable capacitor C, the first end of the first resistor R1 and the first end of the first current sink I1 are all connected to the source of the third NMOS transistor N3; the second end of the first current sink I1 is grounded;

[0096] The second end of the variable capacitor C, the second end of the first resistor R1 and the first end of the second current sink I2 are all connected to the source of the fourth NMOS transistor N4; the second end of the second current sink I2 is grounded.

[0097] The gate of the third NMOS transistor N3 is used as a first signal input terminal to receive the input signal Vin, and the gate of the fourth NMOS transistor N4 is used as a second signal input terminal to receive the input signal Vip.

[0098] The drain of the third NMOS transistor N3 can also serve as the first signal output terminal Vo1 of the high gain regulating submodule 11 , and the drain of the fourth NMOS transistor N4 can also serve as the second signal output terminal Vo2 of the high gain regulating submodule 11 .

[0099] Further integration Figure 5 For understanding, the equivalent signal model of the first active inductor unit 111 includes a gate resistor R g (i.e., R0 mentioned above), the first current sink I1, the gate-drain capacitor C gd , gate-source capacitance C gs and drain-source capacitance C ds ;

[0100] Among them, the gate resistance R g The first terminal and gate-drain capacitance C gd The first end of the gate-source capacitor C gs connected to the first end of

[0101] Gate resistance R g The second terminal and gate-drain capacitance C gd The second end of the drain-source capacitor C ds connected to the first end of

[0102] Gate-drain capacitance C gd The second end is also connected to the first end of the first current sink I1;

[0103] Gate-source capacitance C gs The second end of the drain-source capacitor C ds The second end is connected to .

[0104] according to Figure 5 It can be seen that the impedance expression of the first active inductor unit 111 is:

[0105]

[0106] Where Z is impedance; s is a complex variable; R g is the gate resistance; C gd is the gate-drain capacitance; C gs is the gate-source capacitance; C ds is the drain-source capacitance; g mis the transconductance of the MOS tube. It is understandable that Figure 5 V g is the gate voltage, V S is the source voltage, g m (V g -V S ) is the current in the voltage-controlled current source (first current sink).

[0107] Beneficial effects: In the embodiments of the present invention, firstly, the active inductor unit is changed from the structure in the prior art solution 2 to the structure in which the gate resistor is connected to the AC ground in this embodiment, thereby simplifying the frequency characteristics of the impedance of the active inductor unit; secondly, an active inductor based on an NMOS tube is used to reduce the parasitic capacitance.

[0108] According to formula (3), by configuring the zero point 1 / (R g ×(C gd +C gs )) is equivalent to adjusting the equivalent inductance value, which can effectively adjust the high-frequency gain.

[0109] Furthermore, the high-frequency gain is further adjusted through multi-stage cascading, thereby broadening the adjustment range of the high-frequency equalization capability in the traditional CTLE structure and achieving wide-range high-frequency equalization capability adjustment at a stable peak frequency.

[0110] In an alternative embodiment, see Figure 6 , the high-frequency gain compensation module 10 further includes a low-gain adjustment submodule 12; the low-gain adjustment submodule 12 is cascaded with the high-gain adjustment submodule 11;

[0111] The plurality of active inductor units further include a third active inductor unit 113 and a fourth active inductor unit 114; the third active inductor unit 113 includes a fifth NMOS transistor N5, and the fourth active inductor unit 114 includes a sixth NMOS transistor N6;

[0112] The low gain adjustment submodule includes a third active inductor unit 113, a fourth active inductor unit 114, a seventh NMOS transistor N7 and an eighth NMOS transistor N8;

[0113] Wherein, the drain of the seventh NMOS tube N7 is connected to the source of the fifth NMOS tube N5;

[0114] The drain of the eighth NMOS transistor N8 is connected to the source of the sixth NMOS transistor N6.

[0115] The low gain adjustment submodule 12 may further include a third current sink I3 , the source of the seventh NMOS transistor N7 and the source of the eighth NMOS transistor N8 are both connected to a first end of the third current sink I3 , and a second end of the third current sink I3 is grounded.

[0116] The drain of the seventh NMOS transistor N7 can also serve as the first signal output terminal Vo3 of the low gain regulating submodule 12 , and the drain of the eighth NMOS transistor N8 can also serve as the second signal output terminal Vo4 of the low gain regulating submodule 12 .

[0117] The first signal output terminal Vo3 of the low gain adjustment submodule 12 and the second signal output terminal Vo4 of the low gain adjustment submodule 12 are connected to the signal input terminal of the following module.

[0118] The gate of the seventh NMOS tube N7 and the gate of the eighth NMOS tube N8 serve as two signal input terminals of the low gain regulating submodule 12. As mentioned above, the drain of the third NMOS tube N3 can also serve as the first signal output terminal Vo1 of the high gain regulating submodule 11, and the drain of the fourth NMOS tube N4 can also serve as the second signal output terminal Vo2 of the high gain regulating submodule 11. Among them, the first signal output terminal Vo1 of the high gain regulating submodule 11 is connected to the gate of the seventh NMOS tube N7, and the second signal output terminal Vo2 of the high gain regulating submodule 11 is connected to the gate of the eighth NMOS tube N8.

[0119] Beneficial effect: In this embodiment, a low gain adjustment submodule 12 is added to the high frequency gain compensation module 10, which can broaden the adjustment range of high frequency gain compensation, and realize wide range gain compensation adjustment in combination with the high gain adjustment submodule.

[0120] In an alternative embodiment, see Figure 7 and Figure 8 , the overall gain control module 20 includes a buffer submodule 21, an overall gain setting submodule 22 and an output driving submodule 23;

[0121] The buffer submodule 21 is cascaded with the overall gain setting submodule 22, and the overall gain setting submodule 22 is cascaded with the output driving submodule 23;

[0122] Wherein, the buffer submodule 21 is used to provide a fixed gain;

[0123] The overall gain setting submodule 22 is used to adjust the overall gain;

[0124] The output driver submodule 23 is used to provide gain and improve the load driving capability of the equalizer.

[0125] Beneficial effects: From the above content, it can be seen that the overall gain control module can further control and adjust the high-frequency signal and the low-frequency signal as a whole, so as to ensure that the output amplitude of the output signal is sufficient.

[0126] In an alternative embodiment, see Figure 7 and Figure 8, the buffer submodule 21 includes a ninth NMOS transistor N9, a tenth NMOS transistor N10, a first inductor L1 and a second inductor L2;

[0127] Wherein, the first end of the first inductor L1 is connected to the drain of the ninth NMOS transistor N9; the second end of the first inductor L1 is connected to the power supply;

[0128] The first end of the second inductor L2 is connected to the drain of the tenth NMOS transistor N10; the second end of the second inductor L2 is connected to the power supply;

[0129] The gate of the ninth NMOS transistor N9 is connected to the first signal output terminal of the high-frequency gain compensation module; for example, the gate of the ninth NMOS transistor N9 is connected to the first signal output terminal Vo3 of the low gain adjustment submodule 12;

[0130] The gate of the tenth NMOS transistor N10 is connected to the second signal output terminal of the high-frequency gain compensation module. For example, the gate of the tenth NMOS transistor N10 is connected to the second signal output terminal Vo4 of the low-gain adjustment submodule 12 .

[0131] The buffer submodule 21 may further include a fourth current sink I4 , the source of the ninth NMOS transistor N9 and the source of the tenth NMOS transistor N10 are both connected to a first end of the fourth current sink I4 ; and a second end of the fourth current sink I4 is grounded.

[0132] Beneficial effect: In this embodiment, the ninth NMOS transistor N9 and the tenth NMOS transistor N10 in the buffer submodule 21 further adjust the signal, the first inductor L1 and the second inductor L2 perform overall amplification of the signal, and further fix the gain peak frequency.

[0133] In an alternative embodiment, see Figure 7 and Figure 8 The overall gain setting submodule 22 includes an eleventh NMOS transistor N11, a twelfth NMOS transistor N12, a third inductor L3, a fourth inductor L4 and a second resistor R2; wherein the second resistor R2 is a variable resistor;

[0134] Wherein, the first end of the third inductor L3 is connected to the drain of the eleventh NMOS transistor N11; the second end of the third inductor L3 is connected to the power supply;

[0135] A first end of the fourth inductor L4 is connected to the drain of the twelfth NMOS transistor N12; a second end of the fourth inductor L4 is connected to a power source;

[0136] The gate of the eleventh NMOS tube N11 is connected to the drain of the ninth NMOS tube N9; the gate of the twelfth NMOS tube N12 is connected to the drain of the tenth NMOS tube N10;

[0137] A first end of the second resistor R2 is connected to the source of the eleventh NMOS transistor N11 ; a second end of the second resistor R2 is connected to the source of the twelfth NMOS transistor N12 .

[0138] The overall gain setting submodule 22 may further include a fifth current sink I5 , the source of the eleventh NMOS transistor N11 and the source of the twelfth NMOS transistor N12 are both connected to a first end of the fifth current sink I5 ; and a second end of the fifth current sink I5 is grounded.

[0139] Beneficial effects: In this embodiment, the overall gain setting submodule 22 can control the overall gain of the signal through the functions of various circuit elements, such as the adjustment of the second resistor R2.

[0140] In an alternative embodiment, see Figure 7 and Figure 8 , the output driver submodule 23 includes a thirteenth NMOS transistor N13, a fourteenth NMOS transistor N14, a fifth inductor L5 and a sixth inductor L6;

[0141] Wherein, the first end of the fifth inductor L5 is connected to the drain of the thirteenth NMOS transistor N13; the second end of the fifth inductor L5 is connected to the power supply;

[0142] A first end of the sixth inductor L6 is connected to the drain of the fourteenth NMOS transistor N14; a second end of the sixth inductor L6 is connected to a power source;

[0143] The gate of the thirteenth NMOS tube N13 is connected to the drain of the eleventh NMOS tube N11 ; the gate of the fourteenth NMOS tube N14 is connected to the drain of the twelfth NMOS tube N12 .

[0144] The output driver submodule 23 may further include a sixth current sink I6 , the source of the thirteenth NMOS transistor N13 and the source of the fourteenth NMOS transistor N14 are both connected to a first end of the sixth current sink I6 ; and a second end of the sixth current sink I6 is grounded.

[0145] Beneficial effect: In this embodiment, the output driver submodule 23 is used to enhance the driving capability of the output load.

[0146] In the first specific implementation, the continuous time linear equalizer is simulated. The first specific implementation is implemented in a 65nm process. The beneficial effect of the technical solution of the present invention is obtained through the AC small signal simulation analysis. Due to the implementation method of the active inductor, it can be miniaturized with the process node, which has advantages over the passive inductor. See Fig. 9 and Fig.10 , Fig. 9 and Fig.10 The frequency responses of the prior art solution 1 and the embodiment of the present invention are respectively given, wherein Fig. 9The figure shows the high-frequency gain adjustment of a single-stage CTLE by adjusting the source degeneration capacitor. Since the source degeneration capacitor adjustment has a certain influence on the pole, Figure 5 The peak gain point frequency in the circuit moves with the change of capacitance. In addition, the adjustment scheme of the prior art scheme 1 shows a limited adjustment range. Due to the influence of parasitic capacitance, the source degeneration capacitor is difficult to provide a larger high-frequency equalization capability adjustment range.

[0147] Fig.10 The frequency response of the embodiment of the present invention shows that a wide range of peak gain adjustment at a fixed peak gain frequency is achieved by combining a multi-stage CTLE structure with an active inductive load. Due to the multi-stage structure, while providing a certain low-frequency gain, a high-frequency equalization capability adjustment range of about 10dB is achieved. This shows the advantages of a wide high-frequency equalization capability adjustment range and stable peak frequency compared to the prior art.

[0148] In summary, in the embodiment of the present invention, an active inductive load is used to adjust the high-frequency gain of the CTLE, and a wide range of peak gain adjustment at a stable peak gain frequency is achieved through a multi-stage CTLE with an active inductive load structure. The circuit reliability is high, so that the CTLE can meet the application requirements of different channels and changing environmental scenarios.

[0149] An embodiment of the present invention further provides a high-speed serial interface circuit, which may include the continuous time linear equalizer in any of the above embodiments.

[0150] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art may understand and implement other variations of the disclosed embodiments by viewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "one" or "an" does not exclude multiple situations. A single processor or other unit may implement several functions listed in the claims. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0151] Although the present invention has been described in conjunction with specific features and embodiments thereof, it is apparent that various modifications and combinations may be made thereto without departing from the spirit and scope of the present invention. Accordingly, this specification and the accompanying drawings are merely exemplary illustrations of the present invention as defined by the appended claims and are deemed to cover any and all modifications, variations, combinations or equivalents within the scope of the present invention. Obviously, those skilled in the art may make various modifications and variations to the present invention without departing from the spirit and scope of the present invention. Thus, the present invention is intended to include such modifications and variations if they fall within the scope of the claims of the present invention and their equivalents.

Claims

1. A continuous time linear equalizer, characterized in that: include: High frequency gain compensation module and overall gain control module; The high-frequency gain compensation module is cascaded with the overall gain control module; the overall gain control module is used to perform overall gain control on the output signal of the high-frequency gain compensation module; The high-frequency gain compensation module includes multiple active inductance units, each of which includes an NMOS tube and a gate resistor; the first end of the gate resistor is connected to the gate of the NMOS tube, and the second end of the gate resistor and the drain of the NMOS tube are both connected to the power supply voltage.

2. The continuous time linear equalizer according to claim 1, characterized in that The high-frequency gain compensation module at least includes a high-gain adjustment submodule; The plurality of active inductor units at least include a first active inductor unit and a second active inductor unit; the first active inductor unit includes a first NMOS transistor; the second active inductor unit includes a second NMOS transistor; The high gain adjustment submodule includes the first active inductor unit, the second active inductor unit, a third NMOS transistor, a fourth NMOS transistor, a first resistor, a variable capacitor, a first current sink, and a second current sink; Wherein, the drain of the third NMOS tube is connected to the source of the first NMOS tube; The drain of the fourth NMOS tube is connected to the source of the second NMOS tube; The first end of the variable capacitor, the first end of the first resistor and the first end of the first current sink are all connected to the source of the third NMOS transistor; the second end of the first current sink is grounded; The second end of the variable capacitor, the second end of the first resistor and the first end of the second current sink are all connected to the source of the fourth NMOS transistor; the second end of the second current sink is grounded.

3. The continuous time linear equalizer according to claim 2, characterized in that The equivalent signal model of the first active inductor unit includes the gate resistor, the first current sink, a gate-drain capacitor, a gate-source capacitor and a drain-source capacitor; Wherein, the first end of the gate resistor and the first end of the gate-drain capacitor are both connected to the first end of the gate-source capacitor; The second end of the gate resistor and the second end of the gate-drain capacitor are both connected to the first end of the drain-source capacitor; The second end of the gate-drain capacitor is also connected to the first end of the first current sink; The second end of the gate-source capacitor is connected to the second end of the drain-source capacitor.

4. The continuous time linear equalizer according to claim 3, characterized in that: The impedance expression of the first active inductor unit is: Wherein, Z is the impedance; s is a complex variable; R g is the gate resistance; C gd is the gate-drain capacitance; C gs is the gate-source capacitance; C ds is the drain-source capacitance; g m is the equivalent transconductance.

5. The continuous time linear equalizer according to claim 2, characterized in that: The high-frequency gain compensation module also includes a low-gain adjustment submodule; the low-gain adjustment submodule is cascaded with the high-gain adjustment submodule; The plurality of active inductor units further include a third active inductor unit and a fourth active inductor unit; The third active inductor unit includes a fifth NMOS transistor, and the fourth active inductor unit includes a sixth NMOS transistor; The low gain adjustment submodule includes the third active inductor unit, the fourth active inductor unit, the seventh NMOS tube and the eighth NMOS tube; Wherein, the drain of the seventh NMOS tube is connected to the source of the fifth NMOS tube; The drain of the eighth NMOS tube is connected to the source of the sixth NMOS tube.

6. The continuous time linear equalizer according to claim 1, characterized in that: The overall gain control module includes a buffer submodule, an overall gain setting submodule and an output drive submodule; The buffer submodule is cascaded with the overall gain setting submodule, and the overall gain setting submodule is cascaded with the output driving submodule; Wherein, the buffer submodule is used to provide a fixed gain; The overall gain setting submodule is used to adjust the overall gain; The output driver submodule is used to provide gain and improve the load driving capability of the equalizer.

7. The continuous time linear equalizer according to claim 6, characterized in that The buffer submodule includes a ninth NMOS tube, a tenth NMOS tube, a first inductor and a second inductor; Wherein, the first end of the first inductor is connected to the drain of the ninth NMOS tube; the second end of the first inductor is connected to the power supply; The first end of the second inductor is connected to the drain of the tenth NMOS tube; the second end of the second inductor is connected to the power supply; The gate of the ninth NMOS tube is connected to the first signal output terminal of the high-frequency gain compensation module; The gate of the tenth NMOS tube is connected to the second signal output end of the high-frequency gain compensation module.

8. The continuous time linear equalizer according to claim 7, characterized in that: The overall gain setting submodule includes an eleventh NMOS tube, a twelfth NMOS tube, a third inductor, a fourth inductor and a second resistor; Wherein, the first end of the third inductor is connected to the drain of the eleventh NMOS tube; the second end of the third inductor is connected to the power supply; The first end of the fourth inductor is connected to the drain of the twelfth NMOS tube; the second end of the fourth inductor is connected to the power supply; The gate of the eleventh NMOS tube is connected to the drain of the ninth NMOS tube; the gate of the twelfth NMOS tube is connected to the drain of the tenth NMOS tube; The first end of the second resistor is connected to the source of the eleventh NMOS transistor; the second end of the second resistor is connected to the source of the twelfth NMOS transistor.

9. The continuous time linear equalizer according to claim 8, characterized in that The output driver submodule includes a thirteenth NMOS tube, a fourteenth NMOS tube, a fifth inductor and a sixth inductor; Wherein, the first end of the fifth inductor is connected to the drain of the thirteenth NMOS tube; the second end of the fifth inductor is connected to the power supply; The first end of the sixth inductor is connected to the drain of the fourteenth NMOS tube; the second end of the sixth inductor is connected to the power supply; The gate of the thirteenth NMOS tube is connected to the drain of the eleventh NMOS tube; the gate of the fourteenth NMOS tube is connected to the drain of the twelfth NMOS tube.

10. A high-speed serial interface circuit, characterized in that: Comprising a continuous time linear equalizer as described in any one of claims 1-9.

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