Level detection circuit, detection method, electronic device and readable medium

Abstract

The present disclosure relates to the field of digital circuit technology, and specifically discloses a level detection circuit, a detection method, an electronic device and a readable medium. The level detection circuit includes: a first detection circuit and a second detection circuit that share the same voltage input terminal and voltage output terminal, wherein the first detection circuit and the second detection circuit both use multiple MOS tubes of the same type for connection, effectively avoiding cross-connections between transistors of different types, and simplifying the layout wiring. In addition, the level detection circuit outputs a voltage to the voltage output terminal through an inverter, so that the MOS tubes in the first detection circuit and the second detection circuit can be in a conducting state when the input voltage drops to less than a first threshold value and the input voltage rises to greater than a second threshold value, respectively, to form positive feedback of the first detection circuit and the second detection circuit, so that even when the input voltage jitters, the voltage output terminal can be driven to output a stable conversion voltage, thereby improving the output stability.

Description

Technical Field

[0001] The present disclosure relates to the technical field of digital circuits, and in particular to a level detection circuit, a detection method, an electronic device, and a readable medium. Background Art

[0002] Level detection refers to outputting a corresponding level signal by detecting whether the input potential is higher or lower than the flip voltage.

[0003] In the prior art, level detection is mainly based on inverters and Schmitt triggers. In the detection method based on the inverter, when the input voltage jitters at the flip voltage, the output voltage will flip repeatedly, resulting in unstable output. In the detection method based on the Schmitt trigger, the layout process is more complicated and requires the consumption of extra metal layers, which will lead to more parasitic effects. Summary of the invention

[0004] To this end, the present disclosure provides a level detection circuit, a detection method, an electronic device and a readable medium to solve the problems of unstable output voltage and complex winding in the layout process in the prior art.

[0005] In order to achieve the above-mentioned object, the present disclosure provides a level detection circuit in a first aspect: comprising: a first detection circuit and a second detection circuit that share the same voltage input terminal and voltage output terminal;

[0006] The first detection circuit comprises: a first PMOS tube and a second PMOS tube connected in series, and a third PMOS tube whose conduction state is controlled according to the output voltage of the voltage output terminal;

[0007] The third PMOS tube is connected to the first PMOS tube and the second PMOS tube, and the first PMOS tube and the third PMOS tube are connected to the power supply voltage terminal;

[0008] The second detection circuit includes: a first NMOS tube and a second NMOS tube connected in series, and a third NMOS tube whose conduction state is controlled according to the output voltage of the voltage output terminal; the third NMOS tube is connected to the first NMOS tube and the second NMOS tube, and the second NMOS tube and the third NMOS tube are connected to the ground terminal;

[0009] When the input voltage of the voltage input terminal drops below the first threshold, the first PMOS transistor and the second PMOS transistor are in a conducting state, and the output voltage of the second PMOS transistor is output to the voltage output terminal through an inverter, so that the third PMOS transistor is in a conducting state, and the first detection circuit forms positive feedback to drive the output voltage of the voltage output terminal to convert from a preset high level to a preset low level;

[0010] When the input voltage of the voltage input terminal rises to be greater than the second threshold value, the first NMOS tube and the second NMOS tube are in the on state, and the output voltage of the first NMOS tube is output to the voltage output terminal through the inverter, so that the third NMOS tube is in the on state, and the second detection circuit forms positive feedback to drive the output voltage of the voltage output terminal to convert from a preset low level to a preset high level.

[0011] In an optional implementation, the first threshold is determined according to a gate voltage value when the second PMOS tube is switched to a conducting state;

[0012] The gate of the first PMOS tube is connected to the voltage input terminal, the source of the first PMOS tube is connected to the power supply voltage terminal, and the drain of the first PMOS tube is connected to the source of the second PMOS tube;

[0013] The gate of the second PMOS tube is connected to the voltage input terminal, the drain of the second PMOS tube is connected to the input terminal of the inverter and the drain of the first NMOS tube, and the source of the second PMOS tube is connected to the drain of the first PMOS tube;

[0014] The gate of the third PMOS tube is connected to the voltage output end, the source of the third PMOS tube is connected to the power supply voltage end, and the drain of the third PMOS tube is connected to the drain of the first PMOS tube and the source of the second PMOS tube.

[0015] In an optional implementation, the second threshold is determined according to a gate voltage value when the first NMOS tube is switched to an on state;

[0016] The gate of the first NMOS tube is connected to the voltage input terminal, the source of the first NMOS tube is connected to the drain of the second NMOS tube, and the drain of the first NMOS tube is connected to the input terminal of the inverter and the drain of the second PMOS tube;

[0017] The gate of the second NMOS tube is connected to the voltage input terminal, the source of the second NMOS tube is connected to the ground terminal, and the drain of the second NMOS tube is connected to the source of the first NMOS tube;

[0018] The gate of the third NMOS tube is connected to the voltage output end, the source of the third NMOS tube is connected to the ground end, and the drain of the third NMOS tube is connected to the source of the first NMOS tube and the drain of the second NMOS tube.

[0019] In an optional implementation, the input end of the inverter is connected to the drain of the second PMOS tube and the drain of the first NMOS tube, and the output end of the inverter is connected to the voltage output end.

[0020] In an optional implementation, the inverter includes a fourth PMOS tube and a fourth NMOS tube;

[0021] The gate of the fourth PMOS tube is connected to the drain of the second PMOS tube and the drain of the first NMOS tube, the source of the fourth PMOS tube is connected to the power supply voltage terminal, and the drain of the fourth PMOS tube is connected to the drain of the fourth NMOS tube and the voltage output terminal;

[0022] The gate of the fourth NMOS tube is connected to the drain of the second PMOS tube and the drain of the first NMOS tube, the source of the fourth NMOS tube is connected to the ground end, and the drain of the fourth NMOS tube is connected to the drain of the fourth PMOS tube and the voltage output end.

[0023] In an optional implementation, the size ratio of the first PMOS tube to the third PMOS tube is in a first ratio range, so that the gate voltage value of the second PMOS tube when it is switched to the on state is less than a first preset voltage value, and the first preset voltage value is determined according to the power supply voltage terminal and the ground terminal.

[0024] In an optional implementation, the size ratio of the second NMOS tube to the third NMOS tube is in a second ratio range, so that the gate voltage value of the first NMOS tube when it is switched to the on state is greater than a second preset voltage value, and the second preset voltage value is determined based on the power supply voltage terminal and the ground terminal.

[0025] A second aspect of the present disclosure provides a level detection method, comprising: in a process where an input voltage is converted from a high level to a low level, when it is detected that the input voltage is less than a first threshold, outputting an output voltage of a preset low level according to a first detection circuit of the level detection circuit;

[0026] During the process of converting the input voltage from a low level to a high level, when it is detected that the input voltage is greater than a second threshold, the second detection circuit of the level detection circuit outputs an output voltage of a preset high level.

[0027] A third aspect of the present disclosure provides an electronic device, including: one or more processors;

[0028] A storage device having one or more programs stored thereon, wherein when the one or more programs are executed by the one or more processors, the one or more processors implement the above-mentioned level detection method;

[0029] One or more I / O interfaces are connected between the processor and the memory and are configured to implement information interaction between the processor and the memory.

[0030] A fourth aspect of the present disclosure provides a computer-readable medium having a computer program stored thereon, wherein the program implements the above-mentioned level detection method when executed by a processor.

[0031] The present disclosure has the following advantages:

[0032] The level detection circuit in the embodiment of the present disclosure is composed of a first detection circuit and a second detection circuit that share the same voltage input terminal and voltage output terminal. The same type of MOS tubes are used in the first detection circuit and the second detection circuit for connection, thereby effectively avoiding cross-connection between transistors of different types and simplifying the layout wiring. Furthermore, the level detection circuit in the embodiment of the present disclosure has two flip thresholds, and through an inverter, the third PMOS tube and the third NMOS tube in the first detection circuit and the second detection circuit can be in a conductive state when the input voltage drops to less than the first threshold and the input voltage rises to greater than the second threshold, respectively, to form positive feedback of the first detection circuit and the second detection circuit. Therefore, even when the input voltage jitters, the voltage output terminal can be driven to output a stable conversion voltage, thereby improving output stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The accompanying drawings are used to provide further understanding of the present disclosure and constitute a part of the specification. They are used to explain the present disclosure together with the following detailed description, but do not constitute a limitation of the present disclosure.

[0034] Figure 1 It is a schematic diagram of application scenarios of the level detection circuit;

[0035] Figure 2 Schematic diagram of the circuit structure of the Schmitt trigger;

[0036] Figure 3 A schematic diagram of a level detection circuit provided by an embodiment of the present disclosure;

[0037] Figure 4 A schematic diagram of a level detection circuit provided by an embodiment of the present disclosure;

[0038] Figure 5 is a schematic diagram for comparing state transition curves in an embodiment of the present disclosure;

[0039] Figure 6A flow chart of a level detection method provided by an embodiment of the present disclosure;

[0040] Figure 7 A block diagram of an electronic device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0041] The specific implementation of the present disclosure is described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation described herein is only used to illustrate and explain the present disclosure, and is not used to limit the present disclosure.

[0042] As used in this disclosure, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0043] The terms used in the present disclosure are only used to describe specific embodiments and are not intended to limit the present disclosure.As used in the present disclosure, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0044] When the terms “comprising” and / or “made of…” are used in the present disclosure, it specifies the existence of the stated features, integers, steps, operations, elements and / or components, but does not exclude the existence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0045] The embodiments described in the present disclosure may be described with reference to plan views and / or cross-sectional views by way of ideal schematic diagrams of the present disclosure. Therefore, the exemplary illustrations may be modified according to manufacturing techniques and / or tolerances.

[0046] Unless otherwise defined, all terms (including technical and scientific terms) used in this disclosure have the same meaning as those commonly understood by those of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning unless explicitly defined in this disclosure.

[0047] In circuit design, some high and low level detection circuits are often designed to output corresponding level signals by detecting whether the input potential is higher or lower than the flip voltage, thereby providing digital signals for subsequent modules.

[0048] Figure 1 This is a schematic diagram of the application scenario of the level detection circuit, refer to Figure 1, where INPUT is a voltage input terminal for inputting a voltage signal to be detected, and OUTPUT is a voltage output terminal for outputting a converted digital signal, such as a high level or a low level. VDD is a power supply voltage terminal for providing a power supply voltage. VSS is a ground terminal for providing a common ground voltage. m and n are voltage divider resistors, and DET is a traditional level detection circuit, such as an inverter.

[0049] Therefore, during the power-on process of VDD, due to the PVT (Process, Voltage, Temperature) state and the unreasonable resistance ratio of m and n, the voltage signal of DET input may jitter at its threshold voltage, such as the middle voltage between VDD and VSS. If the potential is monitored based on a traditional inverter, when the noise signal on the input level continuously crosses the threshold voltage, the level of the inverter output will be repeatedly flipped, making the output unstable.

[0050] Although the Schmitt trigger can solve the problem of unstable output, the wiring is more complicated during the layout process and requires consumption of extra metal layers, which leads to more parasitic effects.

[0051] Figure 2 This is a schematic diagram of the circuit structure of the Schmitt trigger, refer to Figure 2 , where INPUT is a voltage input terminal, used to input the voltage signal to be detected, and OUTPUT is a voltage output terminal, used to output the digital signal converted from the voltage signal. VDD is a power supply voltage terminal, used to provide the power supply voltage for the internal circuit of the Schmitt trigger. VSS is a ground terminal, used to provide a common ground voltage, that is, a reference voltage corresponding to the circuit of the Schmitt trigger.

[0052] from Figure 2 It can be seen that there are cross connections between N-Channel Metal-Oxide-Semiconductor (NMOS) transistors and P-type Metal-Oxide Semiconductor (PMOS) transistors in the Schmitt trigger. For example, the drain of the PMOS transistor M1 and the source of M2 are connected to the drain of the NMOS transistor M6, and the source of the NMOS transistor M4 and the drain of M5 are connected to the drain of the PMOS transistor M3, which makes the wiring more complicated during the layout of the Schmitt trigger.

[0053] In view of this, the embodiments of the present disclosure provide a level detection circuit, a detection method, an electronic device and a readable medium. The level detection circuit in the embodiments of the present disclosure is composed of a first detection circuit and a second detection circuit that share the same voltage input terminal and voltage output terminal. The first detection circuit and the second detection circuit are both connected by the same type of MOS tube, thereby effectively avoiding cross-connection between transistors of different types and simplifying the layout wiring. Furthermore, the level detection circuit of the embodiments of the present disclosure has two flip thresholds, and through an inverter, the third PMOS tube and the third NMOS tube in the first detection circuit and the second detection circuit can be in a conductive state when the input voltage drops to less than the first threshold and the input voltage rises to greater than the second threshold, respectively, to form positive feedback of the first detection circuit and the second detection circuit, so that even when the input voltage jitters, the voltage output terminal can be driven to output a stable conversion voltage, thereby improving the output stability.

[0054] In a first aspect, an embodiment of the present disclosure provides a level detection circuit. Figure 3 A schematic diagram of a level detection circuit provided by an embodiment of the present disclosure, referring to Figure 3 The level detection circuit includes: a first detection circuit 10 and a second detection circuit 11 which share the same voltage input terminal INPUT and voltage output terminal OUTPUT.

[0055] The voltage input terminal INPUT is used to input a voltage signal to be detected, and the voltage output terminal OUTPUT is used to output a digital signal obtained after the voltage signal is converted by the level detection circuit.

[0056] The first detection circuit 10 is used to convert the output digital signal from a preset high level to a preset low level when the input voltage signal drops from a high level to a low level.

[0057] Among them, the preset high level corresponds to logic "1", and the preset low level corresponds to logic "0", and the specific values ​​of the two are determined according to the voltage values ​​corresponding to the power supply voltage terminal VDD and the ground terminal VSS respectively.

[0058] Specifically, the first detection circuit 10 includes: a first PMOS transistor 101 and a second PMOS transistor 102 connected in series, and a third PMOS transistor 103 whose conduction state is controlled according to the output voltage of the voltage output terminal OUTPUT.

[0059] The third PMOS transistor 103 is connected to the first PMOS transistor 101 and the second PMOS transistor 102. The first PMOS transistor 101 and the third PMOS transistor 103 are connected to the power supply voltage terminal VDD. The power supply voltage terminal VDD is used to provide the power supply voltage for the level detection circuit to work.

[0060] It should be noted that, since the third PMOS tube 103 is connected to the first PMOS tube 101 and the second PMOS tube 102 in the first detection circuit 10 of the present application, the output voltage of the second PMOS tube 102 needs to be further output to the voltage output terminal through the inverter 100 .

[0061] The first threshold is the voltage threshold of the input voltage signal corresponding to when the output digital signal is converted from a preset high level to a preset low level, that is, the first threshold is a negative threshold voltage.

[0062] Specifically, in the process of the input voltage signal dropping from a high level to a low level, that is, in the process of the voltage signal dropping from the power supply voltage to 0, when the input voltage signal is the power supply voltage, at this time, the output voltage of the voltage output end is a preset high level, and the first PMOS tube 101, the second PMOS tube 102 and the third PMOS tube 103 are all in the cut-off state.

[0063] As the voltage value of the voltage signal gradually decreases, the first PMOS tube 101 is gradually turned on, and since the first PMOS tube 101 is directly connected to the power supply voltage terminal, and the second PMOS tube 102 is connected in series with the first PMOS tube 101, the second PMOS tube 102 will be turned on later than the first PMOS tube 101, thereby generating hysteresis.

[0064] Correspondingly, when the input voltage drops to less than the first threshold, at this time, the first PMOS tube 101 and the second PMOS tube 102 are both in the on state. After the first PMOS tube 101 and the second PMOS tube 102 are turned on, since the first PMOS tube 101 is connected to the power supply voltage terminal, the potential of the connection terminal of the two will be pulled up. At this time, the output voltage of the second PMOS tube 102 is output to the voltage output terminal after passing through the inverter, so that the output voltage of the voltage output terminal is reduced, so that the third PMOS tube 103 is in the on state.

[0065] Since the third PMOS tube 103 is connected to the power supply voltage terminal VDD, and is connected to the first PMOS tube 101 and the second PMOS tube 102, as the third PMOS tube 103 is turned on, the potential of the connection terminal of the first PMOS tube 101 and the second PMOS tube 102 will be further increased, thereby further increasing the voltage value of the output voltage of the second PMOS tube 102. Accordingly, the output voltage output to the voltage output terminal through the inverter 100 will be further reduced, and at this time, the first detection circuit 10 forms a positive feedback, thereby driving the output voltage of the voltage output terminal to quickly convert from a preset high level to a preset low level.

[0066] The second detection circuit 11 is used to convert the output digital signal from a preset low level to a preset high level when the input voltage signal rises from a low level to a high level.

[0067] Specifically, the second detection circuit 11 includes: a first NMOS transistor 111 and a second NMOS transistor 112 connected in series, and a third NMOS transistor 113 whose conduction state is controlled according to the output voltage of the voltage output terminal.

[0068] The third NMOS transistor 113 is connected to the first NMOS transistor 111 and the second NMOS transistor 112, and the second NMOS transistor 112 and the third NMOS transistor 113 are connected to the ground terminal VSS. The ground terminal VSS is used to provide a common ground terminal voltage, ie, a circuit reference voltage, for the level detection circuit.

[0069] It should be noted that, since the third NMOS tube 113 is connected to the first NMOS tube 111 and the second NMOS tube 112 in the second detection circuit 11 of the present application, the output voltage of the second NMOS tube 112 needs to be further output to the voltage output terminal through the inverter 100 .

[0070] The second threshold is the voltage threshold of the input voltage signal corresponding to when the output digital signal is converted from a preset low level to a preset high level, that is, the second threshold is a positive threshold voltage.

[0071] Specifically, in the process of the input voltage signal rising from a low level to a high level, that is, in the process of the voltage signal rising from 0 to the power supply voltage, when the input voltage signal is 0, at this time, the output voltage of the voltage output end is a preset low level, and the first NMOS tube 111, the second NMOS tube 112 and the third NMOS tube 113 are all in the cut-off state.

[0072] As the voltage value of the voltage signal gradually increases, the second NMOS tube 112 is gradually turned on. Since the second NMOS tube 112 is directly connected to the ground terminal VSS, and the first NMOS tube 111 is connected in series with the second NMOS tube 112, the first NMOS tube 111 will be turned on later than the first NMOS tube 112, thereby generating hysteresis.

[0073] Correspondingly, when the input voltage rises to be greater than the second threshold value, at this time, the first NMOS tube 111 and the second NMOS tube 112 are both in the on state. After the first NMOS tube 111 and the second NMOS tube 112 are turned on, since the second NMOS tube 112 is connected to the ground terminal VSS, the potential of the connection terminal between the two will be pulled down. At this time, the output voltage of the first NMOS tube 111 is output to the voltage output terminal after passing through the inverter, so that the output voltage of the voltage output terminal increases, so that the third NMOS tube 113 is in the on state.

[0074] Since the third NMOS tube 113 is connected to the ground terminal VSS, and is connected to the first NMOS tube 111 and the second NMOS tube 112, as the third NMOS tube 113 is turned on, the potential of the connection terminal of the first NMOS tube 111 and the second NMOS tube 112 will be further lowered, thereby further reducing the voltage value of the output voltage of the first NMOS tube 111. Accordingly, the output voltage output to the voltage output terminal through the inverter 100 will further increase, and at this time, the second detection circuit 11 forms a positive feedback, thereby driving the output voltage of the voltage output terminal to quickly convert from a preset low level to a preset high level.

[0075] It should also be noted that in the embodiment of the present disclosure, the second threshold value must be greater than the first threshold value, so that a hysteresis voltage can be formed between the second threshold value and the first threshold value, so that the level detection circuit can output a stable level when a noisy voltage signal is input, and has a strong anti-interference ability.

[0076] It can be seen that the level detection circuit in the embodiment of the present disclosure avoids the cross-connection phenomenon between different types of MOS tubes, thereby simplifying the layout wiring and reducing the parasitic capacitance between lines to a certain extent. In addition, the level detection circuit in the embodiment of the present disclosure sets two flip thresholds, namely the first threshold and the second threshold, which are respectively used for the output level flip when the input voltage is falling and the output level flip when the input voltage is rising, so that even when the input voltage jitters, a stable level can be output.

[0077] In an optional implementation, in order to realize output level conversion according to a first threshold value when the input voltage is converted from a high level to a low level, the first threshold value needs to be determined according to the gate voltage value when the second PMOS tube 102 is converted to a conducting state.

[0078] Correspondingly, the connection mode of each PMOS tube in the first detection circuit 10 is as follows:

[0079] Reference Figure 3 The gate of the first PMOS tube 101 is connected to the voltage input terminal INPUT, the source of the first PMOS tube 101 is connected to the power supply voltage terminal VDD, and the drain of the first PMOS tube 101 is connected to the source of the second PMOS tube 102.

[0080] The gate of the second PMOS transistor 102 is connected to the voltage input terminal INPUT, the drain of the second PMOS transistor 102 is connected to the input terminal of the inverter 100 and the drain of the first NMOS transistor 111, and the source of the second PMOS transistor 102 is connected to the drain of the first PMOS transistor 101;

[0081] The gate of the third PMOS transistor 103 is connected to the voltage output terminal OUTPUT, the source of the third PMOS transistor 103 is connected to the power supply voltage terminal VDD, and the drain of the third PMOS transistor 103 is connected to the drain of the first PMOS transistor 101 and the source 102 of the second PMOS transistor.

[0082] Therefore, in the process of the input voltage signal decreasing from a high level to a low level, that is, in the process of the voltage signal decreasing from the power supply voltage to 0, as the voltage value of the voltage signal gradually decreases, the gate voltage of the first PMOS tube 101 gradually becomes smaller than the source voltage of the first PMOS tube 101, and the voltage difference between the two is greater than the threshold voltage VTH1 of the first PMOS tube being turned on. At this time, the first PMOS tube 101 is in the turned-on state, and since the source voltage of the second PMOS tube 102 is lower than the power supply voltage, the second PMOS tube is still not turned on at this time.

[0083] As the input voltage drops below the first threshold, the voltage difference between the gate voltage of the second PMOS tube 102 and the source voltage of the second PMOS tube 102 is greater than the threshold voltage VTH2 for the second PMOS tube to be turned on, and the second PMOS tube 102 is turned on.

[0084] As the second PMOS tube 102 is gradually turned on, the output voltage of its drain will be pulled up, so that the output voltage of the drain reduces the output voltage of the voltage output terminal OUTPUT through the inverter 100, thereby gradually reducing the gate voltage of the third PMOS tube 103, and the third PMOS tube 103 is turned on.

[0085] As the third PMOS tube 103 is turned on, since its source voltage is the power supply voltage and its drain is connected to the drain of the first PMOS tube 101 and the source of the second PMOS tube 102, the potential of the connecting end of the first PMOS tube 101 and the second PMOS tube 102 can be further increased, so that the second PMOS tube 102 is turned on faster. Correspondingly, the output voltage of the drain of the second PMOS tube 102 will be quickly increased, so that the output voltage of the voltage output end is quickly converted from a preset high level to a preset low level through the inverter 100.

[0086] It can be seen that the first threshold value needs to be determined according to the gate voltage value when the second PMOS tube is switched to the on state, and only when the first threshold value is not greater than the gate voltage value when the second PMOS tube is switched to the on state, can the second PMOS tube be switched to the on state when the input voltage drops to less than the first threshold value.

[0087] In an optional implementation, in order to improve the stability of the output voltage at the voltage output end when the input voltage jitters, the size ratio of the first PMOS tube 101 and the third PMOS tube 103 can be adjusted so that the gate voltage value when the second PMOS tube is switched to the on state is less than a preset voltage value, thereby making the first threshold determined according to the gate voltage value less than the preset voltage value.

[0088] Accordingly, the size ratio of the first PMOS tube 101 to the third PMOS tube 103 is in a first ratio range, so that the gate voltage value of the second PMOS tube 102 switching to the on state is less than a first preset voltage value, and the first preset voltage value is determined according to the power supply voltage terminal and the ground terminal.

[0089] Since the first threshold is a negative voltage threshold of the level detection circuit, in order to form an effective hysteresis voltage between the first threshold and the second threshold, the first threshold needs to be smaller than the first preset voltage value.

[0090] The size ratio between the first PMOS transistor 101 and the third PMOS transistor 103 refers to the size ratio between the size of the first PMOS transistor and the size of the third PMOS transistor.

[0091] The first preset voltage value may be determined according to the power supply voltage terminal and the ground terminal.

[0092] Specifically, a first proportionality coefficient may be set, so that the first preset voltage value is determined according to a voltage difference between a power supply voltage corresponding to the power supply voltage terminal and a common ground voltage corresponding to the ground terminal and the first proportionality coefficient.

[0093] The value range of the first proportionality coefficient is any value between 0 and 1, and the embodiment of the present disclosure does not limit this.

[0094] In an optional implementation, in order to improve the stability of the output level, the first proportionality coefficient can be set to be less than 1 / 2, so that the gate voltage value when the second PMOS tube 102 is switched to the on state is less than the intermediate voltage value between the power supply voltage corresponding to the power supply voltage terminal and the common ground voltage corresponding to the ground terminal.

[0095] Therefore, the first threshold determined according to the gate voltage value can be smaller than the middle voltage value of the power supply voltage corresponding to the power supply voltage terminal and the common ground voltage corresponding to the ground terminal.

[0096] Exemplarily, the first proportionality coefficient may be set to 1 / 3, so that the first preset voltage value is 1 / 3 (power supply voltage - ground voltage).

[0097] The first ratio interval is used to define a size range within which the size ratio of the first PMOS transistor 101 to the third PMOS transistor 103 lies.

[0098] Specifically, the first ratio interval can be determined according to the conduction thresholds of the first PMOS transistor 101 and the third PMOS transistor 103 , and the first preset voltage value.

[0099] Exemplarily, assume that the turn-on threshold of the first PMOS tube 101 is Vth1, the turn-on threshold of the second PMOS tube 102 is Vth2, the turn-on threshold of the third PMOS tube 103 is Vth3, the first preset voltage value is Vin1, and when the input voltage is the first preset voltage value Vin1, the second PMOS tube 102 is in the on state.

[0100] After the second PMOS tube 102 is turned on, the output voltage is quickly pulled to 0 due to positive feedback. In this process, it can be obtained that:

[0101]

[0102] in, Among them, Un is the channel mobility, Cox is the oxide layer capacitance density, is the size of the first PMOS transistor 101 , ie, the width-to-length ratio. Among them, Un is the channel mobility, Cox is the oxide layer capacitance density, is the size of the third PMOS tube 103, ie, the width-to-length ratio, and Vdd is the power supply voltage.

[0103] Correspondingly, according to formula (1), the size ratio of the first PMOS transistor 101 to the third PMOS transistor 103 can be obtained as follows:

[0104]

[0105] Furthermore, according to the above formula (2), the interval threshold corresponding to the first ratio interval in which the size ratio of the first PMOS transistor to the third PMOS transistor is located can be determined.

[0106] It should be noted that the above-mentioned method for determining the first ratio interval is only a specific example. Those skilled in the art may also adaptively adjust the interval threshold of the first ratio interval according to actual scenario requirements, and the embodiments of the present disclosure are not limited to this.

[0107] In an optional implementation, in order to realize output level conversion according to a second threshold value when the input voltage is converted from a low level to a high level, the second threshold value needs to be determined according to the gate voltage value when the first NMOS transistor 111 is converted to a conducting state.

[0108] Correspondingly, the connection mode of each NMOS transistor in the second detection circuit 11 is as follows:

[0109] Reference Figure 3 The gate of the first NMOS tube 111 is connected to the voltage input terminal INPUT, the source of the first NMOS tube 111 is connected to the drain of the second NMOS tube 112 , and the drain of the first NMOS tube 111 is connected to the input terminal of the inverter 100 and the drain of the second PMOS tube 102 .

[0110] The gate of the second NMOS transistor 112 is connected to the voltage input terminal INPUT, the source of the second NMOS transistor 112 is connected to the ground terminal VSS, and the drain of the second NMOS transistor 112 is connected to the source of the first NMOS transistor 111;

[0111] The gate of the third NMOS transistor 113 is connected to the voltage output terminal OUTPUT, the source of the third NMOS transistor 113 is connected to the ground terminal VSS, and the drain of the third NMOS transistor 113 is connected to the source of the first NMOS transistor 111 and the drain of the second NMOS transistor 112 .

[0112] Therefore, in the process that the input voltage signal rises from a low level to a high level, that is, in the process that the voltage signal rises from 0 to the power supply voltage, as the voltage value of the voltage signal gradually increases, the gate voltage of the second NMOS tube 112 gradually becomes greater than the source voltage of the second NMOS tube 112, and the voltage difference between the two is greater than the threshold voltage VTH5 for the second NMOS tube to be turned on. At this time, the second NMOS tube 112 is in a turned-on state, and because the source voltage of the first NMOS tube 111 is greater than the ground voltage, the first NMOS tube is still not turned on at this time.

[0113] As the input voltage rises to be greater than the second threshold, the voltage difference between the gate voltage of the first NMOS tube 111 and the source voltage of the first NMOS tube 111 is greater than the threshold voltage VTH4 of the first NMOS tube conduction, and the first NMOS tube 111 is turned on.

[0114] As the first NMOS tube 111 is gradually turned on, the output voltage of its drain will be pulled down, so that the output voltage of the drain increases the output voltage of the voltage output terminal OUTPUT through the inverter 100, thereby gradually increasing the gate voltage of the third NMOS tube 113, and the third NMOS tube 113 is turned on.

[0115] As the third NMOS tube 113 is turned on, since its source voltage is the ground voltage and its drain is connected to the source of the first NMOS tube 111 and the drain of the second NMOS tube 112, the potential of the connecting end of the first NMOS tube 111 and the second NMOS tube 112 can be further lowered, so that the first NMOS tube 111 is turned on faster. Correspondingly, the output voltage of the drain of the first NMOS tube 111 will be quickly lowered, so that the output voltage of the voltage output end is quickly converted from a preset low level to a preset high level through the inverter 100.

[0116] It can be seen that the second threshold value needs to be determined according to the gate voltage value when the first NMOS tube is switched to the on state, and only when the second threshold value is not less than the gate voltage value when the first NMOS tube is switched to the on state, can the first NMOS tube be switched to the on state when the input voltage rises to be greater than the second threshold value.

[0117] In an optional implementation, in order to improve the stability of the output voltage at the voltage output end when the input voltage jitters, the size ratio of the second NMOS tube 112 and the third NMOS tube 113 can be adjusted so that the gate voltage value of the first NMOS tube 111 when it is switched to the on state is greater than a preset voltage value, thereby enabling the second threshold determined according to the gate voltage value to be greater than the preset voltage value.

[0118] Correspondingly, the size ratio of the second NMOS tube 112 to the third NMOS tube 113 is in a second ratio range, so that the gate voltage value of the first NMOS tube 111 switching to the on state is greater than the second preset voltage value, and the second preset voltage value is determined according to the power supply voltage terminal and the ground terminal.

[0119] Since the second threshold is the forward voltage threshold of the level detection circuit, in order to form an effective hysteresis voltage between the first threshold and the second threshold, the second threshold needs to be greater than the second preset voltage value.

[0120] The second preset voltage value is determined according to the power supply voltage terminal and the ground terminal.

[0121] Specifically, a second proportionality coefficient may be set, so that the second preset voltage value is determined according to the voltage difference between the power supply voltage corresponding to the power supply voltage terminal and the common ground voltage corresponding to the ground terminal and the second proportionality coefficient.

[0122] It should be noted that the magnitude relationship between the second preset voltage value and the first preset voltage value is: the second preset voltage value needs to be greater than the first preset voltage value, so that a hysteresis voltage can be formed between the second threshold value and the first threshold value.

[0123] Therefore, when determining the second preset voltage value based on the second preset proportional coefficient and the voltage difference between the power supply voltage corresponding to the power supply voltage terminal and the common ground voltage corresponding to the ground terminal, it is necessary to ensure that the second preset proportional coefficient is greater than the above-mentioned first preset proportional coefficient, so that the second preset voltage value can be greater than the first preset voltage value.

[0124] It should also be noted that the value of the second preset proportional coefficient in the embodiment of the present disclosure cannot exceed 1, that is, the second preset voltage value cannot exceed the power supply voltage corresponding to the power supply voltage terminal.

[0125] In an optional implementation, in order to improve the stability of the output level, the second proportional coefficient can be set to be greater than 1 / 2, so that the gate voltage value when the first NMOS tube is switched to the on state is greater than the intermediate voltage value of the power supply voltage corresponding to the power supply voltage terminal and the common ground voltage corresponding to the ground terminal.

[0126] Therefore, the second threshold value determined according to the gate voltage value is greater than the middle voltage value of the power supply voltage corresponding to the power supply voltage terminal and the common ground voltage corresponding to the ground terminal.

[0127] Exemplarily, the first proportionality coefficient may be set to 2 / 3, so that the second preset voltage value is 2 / 3 (power supply voltage - ground voltage).

[0128] The second ratio interval is used to limit the size range of the size ratio of the second NMOS transistor 112 to the third NMOS transistor 113 .

[0129] Specifically, the second ratio interval can be determined according to the conduction thresholds of the second NMOS transistor 112 and the third NMOS transistor 113 , and the second preset voltage value.

[0130] Exemplarily, assume that the turn-on threshold of the first NMOS tube 111 is Vth4, the turn-on threshold of the second NMOS tube 112 is Vth5, the turn-on threshold of the third NMOS tube 113 is Vth6, the second preset voltage value is Vin2, and when the input voltage is the second preset voltage value Vin2, the first NMOS tube 111 is in the on state.

[0131] After the first NMOS tube 111 is turned on, the output voltage is quickly pulled to Vdd due to positive feedback. In this process, it can be obtained that:

[0132]

[0133] in, Among them, Un is the channel mobility, Cox is the oxide layer capacitance density, is the size of the second NMOS transistor 112 , ie, the width-to-length ratio. Among them, Un is the channel mobility, Cox is the oxide layer capacitance density, is the size of the third NMOS transistor 113 , ie, the width-to-length ratio.

[0134] Correspondingly, according to formula (3), the size ratio of the second NMOS transistor 112 to the third NMOS transistor 113 can be obtained as follows:

[0135]

[0136] Furthermore, according to the above formula (4), the interval threshold corresponding to the second ratio interval in which the size ratio of the second NMOS transistor to the third NMOS transistor is located can be determined.

[0137] It should be noted that the above-mentioned method for determining the second ratio interval is only a specific example. Those skilled in the art may also adaptively adjust the interval threshold of the second ratio interval according to actual scenario requirements, and the embodiments of the present disclosure are not limited to this.

[0138] In an optional implementation, in order to enable the output voltage of the voltage output end to drive the third PMOS tube 103 and the third NMOS tube 113 to be in a conducting state, the input end of the inverter 100 needs to be connected to the drain of the second PMOS tube 102 and the drain of the first NMOS tube 111, and the output end of the inverter 100 needs to be connected to the voltage output end OUTPUT.

[0139] Reference Figure 3 When the second PMOS tube 102 is turned on, the output voltage of the second PMOS tube 102 is pulled up to a high level, and then input into the inverter 100, so that the voltage output by the inverter is a low level, thereby driving the third PMOS tube 103 to be turned on.

[0140] When the first NMOS tube 111 is turned on, the output voltage of the first NMOS tube 111 is pulled down to a low level, so as to be input into the inverter 100, so that the voltage output by the inverter is a high level, thereby driving the third NMOS tube 113 to be turned on.

[0141] Furthermore, in order to reduce the structural complexity of the inverter and realize fast voltage inversion conversion, the inverter 100 may be composed of a fourth PMOS transistor and a fourth NMOS transistor.

[0142] For ease of understanding, Figure 4 A schematic diagram of the structure of a level detection circuit in an embodiment of the present disclosure is shown.

[0143] Reference Figure 4 The inverter 100 includes a fourth PMOS transistor 104 and a fourth NMOS transistor 114 .

[0144] Specifically, the gate of the fourth PMOS tube 104 is connected to the drain of the second PMOS tube 102 and the drain of the first NMOS tube 111, the source of the fourth PMOS tube 104 is connected to the power supply voltage terminal VDD, and the drain of the fourth PMOS tube 104 is connected to the drain of the fourth NMOS tube 114 and the voltage output terminal OUTPUT.

[0145] The gate of the fourth NMOS tube 104 is connected to the drain of the second PMOS tube 102 and the drain of the first NMOS tube 111 , the source of the fourth NMOS tube 114 is connected to the ground terminal VSS, and the drain of the fourth NMOS tube 114 is connected to the drain of the fourth PMOS tube 104 and the voltage output terminal OUTPUT.

[0146] Therefore, when the inverter 100 is input with a low level, the fourth PMOS tube 104 is turned on, so that the drain output voltage of the fourth PMOS tube 104 is pulled up to a high level, thereby achieving voltage inversion conversion.

[0147] When the inverter 100 is input with a high level, the fourth NMOS tube 114 is turned on, so that the drain output voltage of the fourth NMOS tube 114 is pulled down to a low level, thereby achieving voltage inversion conversion.

[0148] Further, in order to facilitate understanding of the conversion relationship between the input voltage signal and the output level signal in the embodiment of the present disclosure, Figure 5 A schematic diagram comparing the state transfer curves of the level detection circuit and the Schmitt trigger in the embodiment of the present disclosure is shown.

[0149] Reference Figure 5 ,in, Figure 5 (a) is a state transition curve corresponding to the level detection circuit in the embodiment of the present disclosure, Figure 5 (b) in Figure 2 The state transition curve corresponding to the Schmitt trigger.

[0150] Specifically, refer to Figure 5 (a) in which Vdd is the power supply voltage, Vss is the ground voltage, input is the output voltage, output is the output voltage, VthH is the positive voltage threshold, i.e., the second threshold, and VthL is the negative voltage threshold, i.e., the first threshold.

[0151] Thus, in the process of the input voltage rising from a low level to a high level, the output voltage will be converted from a low level to a high level only when the input voltage is greater than the second threshold value VthH. Correspondingly, in the process of the input voltage falling from a high level to a low level, the output voltage will be converted from a high level to a low level only when the input voltage is less than the first threshold value VthL.

[0152] Reference Figure 5 In (b), when the input voltage rises from a low level to a high level, if the input voltage is greater than the second threshold value VthH, the output voltage is converted from a high level to a low level. Correspondingly, when the input voltage drops from a high level to a low level, if the input voltage is less than the first threshold value VthL, the output voltage is converted from a low level to a high level.

[0153] As can be seen from the figure, the level detection circuit in the embodiment of the present disclosure can realize the positive level detection function, and its state transition curve is Figure 2 The state transfer curve corresponding to the Schmitt trigger is opposite.

[0154] In the disclosed embodiment, the conduction state of the third PMOS tube and the third NMOS tube is changed by the state of the output voltage, thereby adjusting the input level of the inverter. When the output voltage is at a high level, the third NMOS tube is turned on and the third PMOS tube is turned off, thereby lowering the potential of the connection end of the first NMOS tube and the second NMOS tube, thereby increasing the output voltage of the inverter. When the output voltage is at a low level, the third NMOS tube is turned off and the third PMOS tube is turned on, thereby raising the potential of the connection end of the first PMOS tube and the second PMOS tube, thereby reducing the output voltage of the inverter, thereby achieving the output from "0" to "1" when the input voltage is higher than the second threshold value VthH; when the input voltage is lower than the first threshold value VthL, the output changes from "1" to "0", with a positive state transfer curve.

[0155] Furthermore, the level detection circuit in the embodiment of the present disclosure, on the one hand, does not require extra winding on the layout, simplifies the layout wiring, reduces the parasitic capacitance between lines to a certain extent, and reduces the parasitic influence of the layout; on the other hand, it realizes positive level detection, and in some application scenarios, there is no need to add an additional inverter, which provides more options for the detection circuit.

[0156] It should be noted that all modules involved in this embodiment are logic modules. In practical applications, a logic unit may be a physical unit, or a part of a physical unit, or may be implemented as a combination of multiple physical units. In addition, in order to highlight the innovative part of the present disclosure, this embodiment does not introduce units that are not closely related to solving the technical problems proposed by the present disclosure, but this does not mean that there are no other units in this embodiment.

[0157] In a second aspect, an embodiment of the present disclosure provides a level detection method. Figure 6 is a flow chart of the level detection method in the embodiment of the present disclosure, referring to Figure 6 , the method comprising:

[0158] Step S610: During the process of converting the input voltage from a high level to a low level, when it is detected that the input voltage is less than a first threshold, outputting a preset low level output voltage according to the first detection circuit of the level detection circuit.

[0159] Step S620: During the process of the input voltage being converted from a low level to a high level, when it is detected that the input voltage is greater than a second threshold, outputting a preset high level output voltage according to the second detection circuit of the level detection circuit.

[0160] The specific implementation and technical effects of the level detection circuit can refer to the description of the above embodiments, and are not described here for brevity.

[0161] In the process of converting the input voltage from a high level to a low level, when the input voltage is not less than a first threshold, the output voltage of the level detection circuit is a preset high level.

[0162] When it is detected that the input voltage is less than the first threshold, the first detection circuit of the level detection circuit takes effect, and its first PMOS tube, second PMOS tube, and third PMOS tube are in the on state, so that the first detection circuit forms positive feedback, thereby converting the output voltage from a preset high level to a preset low level.

[0163] In the process of converting the input voltage from a low level to a high level, when the input voltage is not greater than the second threshold, the output voltage of the level detection circuit is a preset low level.

[0164] When it is detected that the input voltage is greater than the second threshold, the second detection circuit of the level detection circuit takes effect, and its first NMOS tube, second NMOS tube, and third NMOS tube are in the on state, so that the second detection circuit forms positive feedback, thereby converting the output voltage from a preset low level to a preset high level.

[0165] The step division of the above methods is only for the purpose of clear description. When implemented, they can be combined into one step or some steps can be split and decomposed into multiple steps. As long as they include the same logical relationship, they are all within the scope of protection of this patent; adding insignificant modifications to the algorithm or process or introducing insignificant designs without changing the core design of the algorithm and process are all within the scope of protection of this patent.

[0166] Reference Figure 7 , an embodiment of the present disclosure provides an electronic device, comprising:

[0167] One or more processors 701;

[0168] A memory 702, on which one or more programs are stored. When the one or more programs are executed by one or more processors, the one or more processors implement any one of the above-mentioned level detection methods;

[0169] One or more I / O interfaces 703 are connected between the processor and the memory and are configured to implement information exchange between the processor and the memory.

[0170] Among them, the processor 701 is a device with data processing capabilities, including but not limited to a central processing unit (CPU); the memory 702 is a device with data storage capabilities, including but not limited to random access memory (RAM, more specifically SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory (FLASH); the I / O interface (read-write interface) 703 is connected between the processor 701 and the memory 702, and can realize information interaction between the processor 701 and the memory 702, including but not limited to a data bus (Bus), etc.

[0171] In some embodiments, the processor 701 , the memory 702 , and the I / O interface 703 are connected to each other through a bus, and further connected to other components of the computing device.

[0172] This embodiment further provides a computer-readable medium on which a computer program is stored. When the program is executed by a processor, the level detection method provided by this embodiment is implemented. To avoid repeated description, the specific steps of the level detection method are not repeated here.

[0173] It will be appreciated by those skilled in the art that all or some of the steps, systems, and functional modules / units in the invented method described above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some physical components or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0174] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0175] Those skilled in the art will understand that although some embodiments described herein include certain features included in other embodiments but not other features, the combination of features from different embodiments is meant to be within the scope of the present embodiment and to form different embodiments.

[0176] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present disclosure, but the present disclosure is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and substance of the present disclosure, and these modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A level detection circuit, characterized in that: include: A first detection circuit and a second detection circuit that share the same voltage input terminal and voltage output terminal; The first detection circuit comprises: a first PMOS tube and a second PMOS tube connected in series, and a third PMOS tube whose conduction state is controlled according to the output voltage of the voltage output terminal; the third PMOS tube is connected to the first PMOS tube and the second PMOS tube, and the first PMOS tube and the third PMOS tube are connected to the power supply voltage terminal; The second detection circuit includes: a first NMOS tube and a second NMOS tube connected in series, and a third NMOS tube whose conduction state is controlled according to the output voltage of the voltage output terminal; the third NMOS tube is connected to the first NMOS tube and the second NMOS tube, and the second NMOS tube and the third NMOS tube are connected to the ground terminal; When the input voltage of the voltage input terminal drops below the first threshold, the first PMOS transistor and the second PMOS transistor are in a conducting state, and the output voltage of the second PMOS transistor is output to the voltage output terminal through an inverter, so that the third PMOS transistor is in a conducting state, and the first detection circuit forms positive feedback to drive the output voltage of the voltage output terminal to convert from a preset high level to a preset low level; When the input voltage of the voltage input terminal rises to be greater than the second threshold value, the first NMOS tube and the second NMOS tube are in the on state, and the output voltage of the first NMOS tube is output to the voltage output terminal through the inverter, so that the third NMOS tube is in the on state, and the second detection circuit forms positive feedback to drive the output voltage of the voltage output terminal to convert from a preset low level to a preset high level.

2. The level detection circuit according to claim 1, characterized in that: The first threshold is determined according to a gate voltage value when the second PMOS tube is switched to a conducting state; The gate of the first PMOS tube is connected to the voltage input terminal, the source of the first PMOS tube is connected to the power supply voltage terminal, and the drain of the first PMOS tube is connected to the source of the second PMOS tube; The gate of the second PMOS tube is connected to the voltage input terminal, the drain of the second PMOS tube is connected to the input terminal of the inverter and the drain of the first NMOS tube, and the source of the second PMOS tube is connected to the drain of the first PMOS tube; The gate of the third PMOS tube is connected to the voltage output end, the source of the third PMOS tube is connected to the power supply voltage end, and the drain of the third PMOS tube is connected to the drain of the first PMOS tube and the source of the second PMOS tube.

3. The level detection circuit according to claim 1, characterized in that: The second threshold is determined according to the gate voltage value when the first NMOS tube is switched to the on state; The gate of the first NMOS tube is connected to the voltage input terminal, the source of the first NMOS tube is connected to the drain of the second NMOS tube, and the drain of the first NMOS tube is connected to the input terminal of the inverter and the drain of the second PMOS tube; The gate of the second NMOS tube is connected to the voltage input terminal, the source of the second NMOS tube is connected to the ground terminal, and the drain of the second NMOS tube is connected to the source of the first NMOS tube; The gate of the third NMOS tube is connected to the voltage output end, the source of the third NMOS tube is connected to the ground end, and the drain of the third NMOS tube is connected to the source of the first NMOS tube and the drain of the second NMOS tube.

4. The level detection circuit according to claim 1, characterized in that: The input end of the inverter is connected to the drain of the second PMOS tube and the drain of the first NMOS tube, and the output end of the inverter is connected to the voltage output end.

5. The level detection circuit according to claim 4, characterized in that: The inverter includes a fourth PMOS tube and a fourth NMOS tube; The gate of the fourth PMOS tube is connected to the drain of the second PMOS tube and the drain of the first NMOS tube, the source of the fourth PMOS tube is connected to the power supply voltage terminal, and the drain of the fourth PMOS tube is connected to the drain of the fourth NMOS tube and the voltage output terminal; The gate of the fourth NMOS tube is connected to the drain of the second PMOS tube and the drain of the first NMOS tube, the source of the fourth NMOS tube is connected to the ground end, and the drain of the fourth NMOS tube is connected to the drain of the fourth PMOS tube and the voltage output end.

6. The level detection circuit according to claim 2, characterized in that: The size ratio of the first PMOS tube to the third PMOS tube is in a first ratio range, so that the gate voltage value of the second PMOS tube when it is switched to the on state is less than a first preset voltage value, and the first preset voltage value is determined according to the power supply voltage terminal and the ground terminal.

7. The level detection circuit according to claim 3, characterized in that: The size ratio of the second NMOS tube to the third NMOS tube is in a second ratio range, so that the gate voltage value of the first NMOS tube when it is switched to the on state is greater than a second preset voltage value, and the second preset voltage value is determined according to the power supply voltage terminal and the ground terminal.

8. A level detection method, characterized in that: The method comprises: In the process of converting the input voltage from a high level to a low level, when it is detected that the input voltage is less than a first threshold, the first detection circuit of the level detection circuit according to any one of claims 1 to 7 outputs an output voltage of a preset low level; During the process of converting the input voltage from a low level to a high level, when it is detected that the input voltage is greater than a second threshold, the second detection circuit of the level detection circuit outputs an output voltage of a preset high level.

9. An electronic device, characterized in that: include: one or more processors; A storage device having one or more programs stored thereon, when the one or more programs are executed by the one or more processors, the one or more processors implement the method according to claim 8; One or more I / O interfaces are connected between the processor and the memory and are configured to implement information interaction between the processor and the memory.

10. A computer readable medium having a computer program stored thereon, wherein the program implements the method according to claim 8 when executed by a processor.

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