Redundant interlocking circuit for vehicle-gauge-level chip

Abstract

The invention provides a redundancy interlocking circuit for a vehicle gauge level chip, which comprises a first low-side driving module, a second low-side driving module, a first interlocking circuit and a second interlocking circuit, when the first low-side driving module works, the second low-side driving module is locked in a closed state through the first interlocking circuit and the second interlocking circuit, and when the second low-side driving module works, the first low-side driving module is locked in the closed state through the first interlocking circuit and the second interlocking circuit. The first interlocking circuit and the second interlocking circuit can independently achieve an interlocking function between the first low-side driving module and the second low-side driving module, namely, the first interlocking circuit and the second interlocking circuit achieve redundant interlocking, and after one of the first interlocking circuit and the second interlocking circuit is damaged, the first low-side driving module and the second low-side driving module can be driven by the first interlocking circuit and the second interlocking circuit. And the interlocking function between the first low-side driving module and the second low-side driving module can still be realized through the other low-side driving module, so that the interlocking function is prevented from losing efficacy.

Description

Technical Field

[0001] The present invention relates to the technical field of interlocking circuits, and in particular to a redundant interlocking circuit for automotive-grade chips. Background Art

[0002] With the rapid development of new energy vehicles in my country, the functions of vehicles are becoming more and more complex, and the number and integration of chips required are also increasing. A chip has multiple channels and can drive multiple loads. Sometimes when one load is working, another load is required to be turned off and not work, that is, an interlocking function is required between certain loads. For example, when the car is in the forward gear, the system requires that the reverse gear controller must be turned off, otherwise the car drive logic will go wrong. For example, when you step on the brake, make sure to lock the accelerator, etc.

[0003] In the actual application of automotive systems, automotive-grade chips have very high functional safety requirements, and the interlocking logic of the driving circuit must be accurate. However, the existing automotive interlocking circuits are likely to be damaged by external interference. Once damaged, the automotive-grade chips will lose the corresponding interlocking function. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide an interlocking circuit capable of preventing the interlocking function from failing.

[0005] In order to solve the above technical problems, the present invention provides a redundant interlocking circuit for an automotive-grade chip, which is characterized by comprising a first low-side driver module, a second low-side driver module, a first interlocking circuit and a second interlocking circuit, wherein:

[0006] The first low-side driver module comprises a first drive circuit and a first switch power tube, the first switch power tube is connected to the main loop of the first low-side driver module, and the first drive circuit is connected to the control electrode of the first switch power tube; the second low-side driver module comprises a second drive circuit and a second switch power tube, the second switch power tube is connected to the main loop of the second low-side driver module, and the second drive circuit is connected to the control electrode of the second switch power tube;

[0007] The first interlock circuit includes a first logic AND gate, a second logic AND gate, a first inverter, a second inverter, a third inverter and a control signal input terminal; the control signal input terminal is connected to the first input terminal of the first logic AND gate, and is connected to the first input terminal of the second logic AND gate via the first inverter, the output terminal of the first logic AND gate is connected to the first drive circuit, the first drive circuit is connected to the second input terminal of the second logic AND gate via the second inverter, the output terminal of the second logic AND gate is connected to the second drive circuit, and the second drive circuit is connected to the second input terminal of the first logic AND gate via the third inverter;

[0008] The second interlocking circuit includes a third switch power tube, a fourth switch power tube, a first comparator and a second comparator. The contact between the first drive circuit and the first switch power tube is grounded via the third switch power tube, and the contact between the second drive circuit and the second switch power tube is grounded via the fourth switch power tube. The positive phase input terminal of the first comparator is connected to the contact between the first drive circuit and the first switch power tube, the negative phase input terminal is connected to a reference voltage, and the output terminal is connected to the control electrode of the fourth switch power tube. The positive phase input terminal of the second comparator is connected to the contact between the second drive circuit and the second switch power tube, the negative phase input terminal is connected to a reference voltage, and the output terminal is connected to the control electrode of the third switch power tube.

[0009] Furthermore, the output end of the first logic AND gate is specifically connected to the first driving circuit via a first buffer, and the output end of the second logic AND gate is specifically connected to the second driving circuit via a second buffer.

[0010] Furthermore, the first power tube is an N-type MOS tube, whose drain is connected to the load in the main circuit of the first low-side driving module, whose source is grounded, whose gate is the control electrode, and connected to the first driving circuit; the second power tube is an N-type MOS tube, whose drain is connected to the load in the main circuit of the second low-side driving module, whose source is grounded, whose gate is the control electrode, and connected to the second driving circuit.

[0011] Further, the third power tube is an N-type MOS tube, whose drain is connected to the contact between the first drive circuit and the first switching power tube, the source is grounded, and the gate is a control electrode connected to the output end of the second comparator; the fourth power tube is an N-type MOS tube, whose drain is connected to the contact between the second drive circuit and the second switching power tube, the source is grounded, and the gate is a control electrode connected to the output end of the first comparator.

[0012] Further, the third power tube is an NPN type transistor, whose collector is connected to the contact between the first drive circuit and the first switching power tube, the emitter is grounded, and the base serves as a control electrode and is connected to the output end of the second comparator; the fourth power tube is an NPN type transistor, whose collector is connected to the contact between the second drive circuit and the second switching power tube, the emitter is grounded, and the base serves as a control electrode and is connected to the output end of the first comparator.

[0013] Further, the negative phase input terminal of the first comparator is connected to the reference voltage specifically: the negative phase input terminal of the first comparator is connected to the reference voltage circuit, the reference voltage circuit includes a power supply and two resistors, the power supply is grounded in turn through the two resistors, a reference voltage obtained by dividing the power supply voltage by the resistors is generated between the two resistors, and the negative phase input terminal of the first comparator is connected to the connection point between the two resistors to access the reference voltage; the negative phase input terminal of the second comparator is connected to the reference voltage specifically: the negative phase input terminal of the second comparator is connected to the reference voltage circuit, the reference voltage circuit includes a power supply and two resistors, the power supply is grounded in turn through the two resistors, a reference voltage obtained by dividing the power supply voltage by the resistors is generated between the two resistors, and the negative phase input terminal of the second comparator is connected to the connection point between the two resistors to access the reference voltage.

[0014] Furthermore, the negative phase input terminal of the first comparator and the negative phase input terminal of the second comparator are connected to a reference voltage, specifically, a bandgap reference circuit is connected to the bandgap reference voltage.

[0015] The present invention has the following beneficial effects: in the initial state, the first drive circuit and the second drive circuit are turned off to generate a low-level signal, the low-level signal generated by the first drive circuit is converted into a high-level signal through the second inverter and input to the second input end of the second logic AND gate, and the low-level signal generated by the second drive circuit is converted into a high-level signal through the third inverter and input to the second input end of the first logic AND gate. When a high-level signal is input to the control signal input end, the high-level signal is directly input to the first input end of the first logic AND gate. Since the high-level signal has been input to the second input end of the first logic AND gate in the initial state, both input ends of the first logic AND gate are high-level, and the output end of the first logic AND gate outputs a high-level signal to the first drive circuit, so that the first drive circuit works to generate a high level to turn on the first switch power tube, so that the first low-side drive module works, at this time, the high-level signal generated by the first drive circuit is converted into a low-level signal by the second inverter and output to the second logic AND gate, so that the output end of the second logic AND gate continuously outputs a low-level signal to the second drive circuit, and the second drive circuit generates a low level to turn off the second switch power tube, and the second low-side drive module is locked in a closed state. When a low-level signal is input to the control signal input terminal, the low-level signal is converted into a high-level signal by the first inverter and then input to the first input terminal of the second logic AND gate. Since a high-level signal has been input to the second input terminal of the second logic AND gate in the initial state, both input terminals of the second logic AND gate are at a high level. Then the second logic AND gate outputs a high-level signal to the second drive circuit, so that the second drive circuit works to generate a high level to turn on the second switch power tube, so that the second low-side drive module works. At this time, the high-level signal generated by the second drive circuit is converted into a low-level signal by the third inverter and output to the first logic AND gate, so that the output terminal of the first logic AND gate continues to output a low-level signal to the first drive circuit. Then the first drive circuit generates a low level to turn off the first switch power tube, and locks the first low-side drive module in a closed state. In this way, the first interlocking circuit is used to lock the second low-side drive module in a closed state when the first low-side drive module works, and the first low-side drive module is locked in a closed state when the second low-side drive module works.

[0016] During the operation of the first low-side driver module, the first driver circuit generates a high level to turn on the first switch power tube, and the contact between the first driver circuit and the first switch power tube inputs a high level to the positive input terminal of the first comparator. The high level is greater than the reference voltage connected to the negative input terminal of the first comparator, and the first comparator outputs a high level to the control electrode of the fourth switch power tube to turn on the fourth switch power tube. After the fourth switch power tube is turned on, a strong pull-down path is created between the second driver circuit and the control electrode of the second switch power tube, so that the control electrode level of the second switch power tube is pulled down to ensure that the second switch power tube is turned off. In this way, the second interlocking circuit is used to lock the second low-side driver module in a closed state when the first low-side driver module is operating. During the operation of the second low-side driver module, the second driver circuit generates a high level to turn on the second switch power tube, and the contact between the second driver circuit and the second switch power tube inputs a high level to the positive input terminal of the second comparator. The high level is greater than the reference voltage connected to the negative input terminal of the second comparator, and the second comparator outputs a high level to the control electrode of the third switch power tube to turn on the third switch power tube. After the third switch power tube is turned on, a strong pull-down path is created between the first driver circuit and the control electrode of the first switch power tube, so that the control electrode level of the first switch power tube is pulled down to ensure that the first switch power tube is turned off. In this way, the first low-side driver module is locked in the off state when the second low-side driver module is operating through the second interlocking circuit.

[0017] In summary, the first interlock circuit and the second interlock circuit can independently realize the interlocking function between the first low-side driver module and the second low-side driver module, that is, the first interlock circuit and the second interlock circuit realize redundant interlocking. After one of the first interlock circuit and the second interlock circuit is destroyed, the interlocking function between the first low-side driver module and the second low-side driver module can still be realized through the other one, thereby preventing the interlocking function from failing. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is a circuit schematic diagram of a redundant interlocking circuit for an automotive-grade chip according to Embodiment 1.

[0019] Figure 2 This is a circuit schematic diagram of a redundant interlocking circuit for an automotive-grade chip according to Embodiment 2.

[0020] Figure 3 This is a circuit schematic diagram of a redundant interlocking circuit for an automotive-grade chip according to Example 3. DETAILED DESCRIPTION

[0021] The present invention is further described in detail below in conjunction with specific implementation methods.

[0022] Embodiment 1

[0023] This embodiment provides a redundant interlocking circuit for an automotive-grade chip, such as Figure 1 As shown, the redundant interlock circuit includes a first low-side driver module 1, a second low-side driver module 2, a first interlock circuit 3 and a second interlock circuit 4. The low-side driver module refers to a module in an electronic circuit that drives a load by grounding a switch, and is characterized in that the load is activated by closing the ground switch.

[0024] The first low-side driver module 1 includes a first drive circuit DC1 and a first switch power tube M1. The first switch power tube M1 is connected to the main circuit of the first low-side driver module 1. The first drive circuit DC1 is connected to the control electrode of the first switch power tube M1. Specifically, the first switch power tube M1 is an N-type MOS tube, whose drain is connected to the load in the main circuit of the first low-side driver module 1, the source is grounded, the gate is the control electrode, and is connected to the first drive circuit DC1. The second low-side driver module 2 includes a second drive circuit DC2 and a second switch power tube M2. The second switch power tube M2 is connected to the main circuit of the second low-side driver module 2. The second drive circuit DC2 is connected to the control electrode of the second switch power tube M2. Specifically, the second switch power tube M2 is an N-type MOS tube, whose drain is connected to the load in the main circuit of the second low-side driver module 2, the source is grounded, the gate is the control electrode, and is connected to the second drive circuit DC2.

[0025] The first interlock circuit 3 includes a first logic AND gate C1, a second logic AND gate C2, a first inverter D1, a second inverter D2, a third inverter D3, a first buffer B1, a second buffer B2 and a control signal input terminal IN. The logic AND gate is a basic logic gate circuit that performs an "AND" operation, which has multiple input terminals and an output terminal. When all the input terminals are at a high level (logic 1) at the same time, the output terminal is a high level (logic 1), otherwise the output terminal is a low level (logic 0). In this embodiment, the first logic AND gate C1 and the second logic AND gate C2 each have two input terminals and one output terminal. The inverter is also called a logic NOT gate, which has an input terminal and an output terminal. When its input terminal is at a high level (logic 1), the output terminal is a low level (logic 0), and when its input terminal is at a low level, the output terminal is a high level. In other words, the level states of the input terminal and the output terminal of the inverter are always inverted. A buffer is an electronic device used in electronic circuits to enhance signals and isolate loads. When the level signal is weak or a stronger level is required, the use of a buffer can enhance the signal level. At the same time, the buffer can avoid the mutual influence of resistance between input and output, so that the load circuit is not affected by fluctuations in the input signal level.

[0026] In the first interlock circuit 3, the control signal input terminal IN is connected to the first input terminal of the first logic AND gate C1, and is connected to the first input terminal of the second logic AND gate C2 via the first inverter D1, the output terminal of the first logic AND gate C1 is connected to the first drive circuit DC1 via the first buffer B1, the first drive circuit DC1 is connected to the second input terminal of the second logic AND gate C2 via the second inverter D2, the output terminal of the second logic AND gate C2 is connected to the second drive circuit DC2 via the second buffer B2, and the second drive circuit DC2 is connected to the second input terminal of the first logic AND gate C1 via the third inverter D3.

[0027] In the initial state, the first drive circuit DC1 and the second drive circuit DC2 are turned off to generate a low-level signal. The low-level signal generated by the first drive circuit DC1 is converted into a high-level signal through the second inverter D2 and input into the second input end of the second logic AND gate C2. The low-level signal is also output to the control electrode of the first switch power tube M1, so that the first switch power tube M1 is turned off, and the load of the first low-side drive module 1 cannot be grounded through the first switch power tube M1, and the first low-side drive module 1 is in the off state; the low-level signal generated by the second drive circuit DC2 is converted into a high-level signal through the third inverter D3 and input into the second input end of the first logic AND gate C1. The low-level signal is also output to the control electrode of the second switch power tube M2, so that the second switch power tube M2 is turned off, and the load of the second low-side drive module 2 cannot be grounded through the second switch power tube M2, and the second low-side drive module 2 is in the off state.

[0028] When a high-level signal is input to the control signal input terminal IN, the high-level signal is directly input to the first input terminal of the first logic AND gate C1. Since the high-level signal has been input to the second input terminal of the first logic AND gate C1 in the initial state, both input terminals of the first logic AND gate C1 are at a high level. Then the output terminal of the first logic AND gate C1 outputs a high-level signal to the first drive circuit DC1, so that the first drive circuit DC1 works to generate a high level to turn on the first switch power tube M1, so that the load of the first low-side drive module 1 is grounded through the first switch power tube M1, and the first low-side drive module 1 works. The high-level signal input to the control signal input terminal IN will also be converted into a low-level signal by the first inverter D1 and then input to the first input terminal of the second logic AND gate C2, so that the output terminal of the second logic AND gate C2 outputs a low-level signal to the second drive circuit DC2. The second drive circuit DC2 generates a low level to keep the second switch power tube M2 in the off state, so that the load of the second low-side drive module 2 cannot be grounded through the second switch power tube M2, and the second low-side drive module 2 is closed and does not work. When the first low-side driver module 1 is working, the high-level signal generated by the first driver circuit DC1 is converted into a low-level signal through the second inverter D2 and output to the second input end of the second logic AND gate C2, so that the output end of the second logic AND gate C2 continues to output a low-level signal to the second driver circuit DC2, ensuring that the second driver circuit DC2 generates a low level to turn off the second switch power tube M2, so that the load of the second low-side driver module 2 cannot be grounded through the second switch power tube M2, and the second low-side driver module 2 is locked in a closed state.

[0029] When a low-level signal is input to the control signal input terminal IN, the low-level signal is converted into a high-level signal by the first inverter D1 and then input to the first input terminal of the second logic AND gate C2. Since a high-level signal has been input to the second input terminal of the second logic AND gate C2 in the initial state, both input terminals of the second logic AND gate C2 are at a high level, and the second logic AND gate C2 outputs a high-level signal to the second drive circuit DC2, so that the second drive circuit DC2 works to generate a high level to turn on the second switch power tube M2, so that the second low-side drive module 2 works. The low-level signal input to the control signal input terminal IN is also directly input to the first input terminal of the first logic AND gate C1, so that the output terminal of the first logic AND gate C1 outputs a low-level signal to the first drive circuit DC1. The first drive circuit DC1 generates a low level to keep the first switch power tube M1 in the off state, so that the load of the first low-side drive module 1 cannot be grounded through the first switch power tube M1, and the first low-side drive module 1 is turned off and does not work. When the second low-side driver module 2 is working, the high-level signal generated by the second driver circuit DC2 is converted into a low-level signal through the third inverter D3 and output to the second input end of the first logic AND gate C1, so that the output end of the first logic AND gate C1 continues to output a low-level signal to the first driver circuit DC1, ensuring that the first driver circuit DC1 generates a low level to turn off the first switch power tube M1, so that the load of the first low-side driver module 1 cannot be grounded through the first switch power tube M1, and the first low-side driver module 1 is locked in a closed state.

[0030] In summary, when a high-level signal is input to the control signal input terminal IN, the first interlock circuit 3 is used to make the first low-side driver module 1 work and the second low-side driver module 2 be locked in the off state, and when a low-level signal is input to the control signal input terminal IN, the first interlock circuit 3 is used to make the second low-side driver module 2 work and the first low-side driver module 1 be locked in the off state.

[0031] The second interlock circuit 4 includes a third switch power tube M3, a fourth switch power tube M4, a first comparator COMP1 and a second comparator COMP2. The connection point between the first drive circuit DC1 and the first switch power tube M1 is grounded via the third switch power tube M3. Specifically, the third switch power tube M3 is an N-type MOS tube, whose drain is connected to the connection point between the first drive circuit DC1 and the first switch power tube M1, whose source is grounded, and whose gate is a control electrode. The connection point between the second drive circuit DC2 and the second switch power tube M2 is grounded via the fourth switch power tube M4. Specifically, the fourth switch power tube M4 is an N-type MOS tube, whose drain is connected to the connection point between the second drive circuit DC2 and the second switch power tube M2, whose source is grounded, and whose gate is a control electrode. The positive phase input terminal of the first comparator COMP1 is connected to the connection point between the first drive circuit DC1 and the first switch power tube M1, the negative phase input terminal is connected to the reference voltage, and the output terminal is connected to the control electrode of the fourth switch power tube M4. The positive phase input terminal of the second comparator COMP1 is connected to the connection point between the second drive circuit DC2 and the second switch power tube M2, the negative phase input terminal is connected to the reference voltage, and the output terminal is connected to the control electrode of the third switch power tube M3. Among them, the reference voltage is provided by using the scheme of resistor voltage division of the power supply voltage. Specifically, the negative phase input terminal of the first comparator COMP1 is connected to a reference voltage circuit, which includes a power supply and two resistors. The power supply is grounded in turn through the two resistors, and a reference voltage obtained by resistor voltage division of the power supply voltage is generated between the two resistors. The negative phase input terminal of the first comparator COMP1 is connected to the connection point between the two resistors to access the reference voltage. Similarly, the negative input terminal of the second comparator COMP2 is connected to another reference voltage circuit of the same structure, which includes a power supply and two resistors. The power supply is grounded via the two resistors in turn, and a reference voltage is generated between the two resistors after the power supply voltage is divided by the resistors. The negative input terminal of the second comparator COMP2 is connected to the junction between the two resistors to access the reference voltage.

[0032] During the operation of the first low-side driver module 1, the first driver circuit DC1 generates a high level to turn on the first switch power tube M1, and the contact between the first driver circuit DC1 and the first switch power tube M1 inputs a high level to the positive input terminal of the first comparator COMP1. The high level is greater than the reference voltage connected to the negative input terminal of the first comparator COMP1, and the first comparator COMP1 outputs a high level to the control electrode of the fourth switch power tube M4, so that the fourth switch power tube M4 is turned on. After the fourth switch power tube M4 is turned on, a strong pull-down path is created between the second driver circuit DC2 and the control electrode of the second switch power tube M2, so that the control electrode level of the second switch power tube M2 is pulled down, thereby ensuring that the control electrode level of the second switch power tube M2 will not be a high level, and ensuring that the second switch power tube M2 is turned off. In this way, the second interlock circuit 4 is used to lock the second low-side driver module 2 in a closed state when the first low-side driver module 1 is working. During the operation of the second low-side driver module 2, the second driver circuit DC2 generates a high level to turn on the second switch power tube M2, and the contact between the second driver circuit DC2 and the second switch power tube M2 inputs a high level to the positive input terminal of the second comparator COMP2. The high level is greater than the reference voltage connected to the negative input terminal of the second comparator COMP2, and the second comparator COMP2 outputs a high level to the control electrode of the third switch power tube M3, so that the third switch power tube M3 is turned on. After the third switch power tube M3 is turned on, a strong pull-down path is created between the first driver circuit DC1 and the control electrode of the first switch power tube M1, so that the control electrode level of the first switch power tube M1 is pulled down, thereby ensuring that the control electrode level of the first switch power tube M1 will not be a high level, and ensuring that the first switch power tube M1 is turned off. In this way, the first low-side driver module 1 is locked in the off state when the second low-side driver module 2 is working through the second interlock circuit 4.

[0033] In summary, the first interlock circuit 3 and the second interlock circuit 4 can each independently realize the interlocking function between the first low-side driver module 1 and the second low-side driver module 2, that is, the first interlock circuit 3 and the second interlock circuit 4 realize redundant interlocking. After one of the first interlock circuit 3 and the second interlock circuit 4 is destroyed, the interlocking function between the first low-side driver module 1 and the second low-side driver module 2 can still be realized through the other one, thereby preventing the interlocking function from failing.

[0034] Embodiment 2

[0035] This embodiment provides another redundant interlocking circuit for automotive-grade chips, such as Figure 2As shown, the redundant interlocking circuit is basically the same as the first embodiment, except that: the reference voltage connected to the negative phase input terminal of the first comparator COMP1 and the negative phase input terminal of the second comparator COMP2 is not provided by adopting the scheme of resistor voltage division power supply voltage, but is connected to the bandgap reference circuit to access the bandgap reference voltage Bandgap, which is more accurate and stable than the scheme of adopting resistor voltage division power supply voltage.

[0036] Embodiment 3

[0037] This embodiment provides another redundant interlocking circuit for automotive-grade chips, such as Figure 3 As shown, the redundant interlocking circuit is basically the same as the first embodiment, except that: the third switch power tube M3 and the fourth switch power tube M4 use NPN type triodes instead of N-type MOS tubes, wherein the collector of the third switch power tube M3 is connected to the connection point between the first drive circuit DC1 and the first switch power tube M1, the emitter is grounded, the base is used as a control electrode, and is connected to the output end of the second comparator COMP2; the collector of the fourth switch power tube M4 is connected to the connection point between the second drive circuit DC2 and the second switch power tube M2, the emitter is grounded, the base is used as a control electrode, and is connected to the output end of the first comparator COMP1. The third switch power tube M3 and the fourth switch power tube M4 use triodes as pull-down tubes to improve the response speed of the second interlocking circuit 4.

[0038] The above is only an implementation method of the invention, and does not limit the scope of patent protection. Those skilled in the art can make non-substantial changes or substitutions based on the invention, which still fall within the scope of patent protection.

Claims

1. A redundant interlocking circuit for automotive-grade chips, characterized in that: It includes a first low-side driver module, a second low-side driver module, a first interlock circuit and a second interlock circuit, wherein: The first low-side driver module comprises a first drive circuit and a first switch power tube, the first switch power tube is connected to the main loop of the first low-side driver module, and the first drive circuit is connected to the control electrode of the first switch power tube; the second low-side driver module comprises a second drive circuit and a second switch power tube, the second switch power tube is connected to the main loop of the second low-side driver module, and the second drive circuit is connected to the control electrode of the second switch power tube; The first interlock circuit includes a first logic AND gate, a second logic AND gate, a first inverter, a second inverter, a third inverter and a control signal input terminal; the control signal input terminal is connected to the first input terminal of the first logic AND gate, and is connected to the first input terminal of the second logic AND gate via the first inverter, the output terminal of the first logic AND gate is connected to the first drive circuit, the first drive circuit is connected to the second input terminal of the second logic AND gate via the second inverter, the output terminal of the second logic AND gate is connected to the second drive circuit, and the second drive circuit is connected to the second input terminal of the first logic AND gate via the third inverter; The second interlocking circuit includes a third switch power tube, a fourth switch power tube, a first comparator and a second comparator. The contact between the first drive circuit and the first switch power tube is grounded via the third switch power tube, and the contact between the second drive circuit and the second switch power tube is grounded via the fourth switch power tube. The positive phase input terminal of the first comparator is connected to the contact between the first drive circuit and the first switch power tube, the negative phase input terminal is connected to a reference voltage, and the output terminal is connected to the control electrode of the fourth switch power tube. The positive phase input terminal of the second comparator is connected to the contact between the second drive circuit and the second switch power tube, the negative phase input terminal is connected to a reference voltage, and the output terminal is connected to the control electrode of the third switch power tube.

2. The redundant interlocking circuit for automotive-grade chips according to claim 1 is characterized in that: The output end of the first logic AND gate is specifically connected to the first driving circuit via a first buffer, and the output end of the second logic AND gate is specifically connected to the second driving circuit via a second buffer.

3. The redundant interlocking circuit for automotive-grade chips according to claim 1 is characterized in that: The first power tube is an N-type MOS tube, the drain of which is connected to the load in the main loop of the first low-side driving module, the source is grounded, and the gate is a control electrode connected to the first driving circuit; The second power tube is an N-type MOS tube, a drain of which is connected to the load in the main loop of the second low-side driving module, a source is grounded, and a gate is a control electrode connected to the second driving circuit.

4. The redundant interlocking circuit for automotive-grade chips according to claim 1 is characterized in that: The third power tube is an N-type MOS tube, the drain of which is connected to the connection point between the first drive circuit and the first switch power tube, the source is grounded, and the gate is a control electrode connected to the output end of the second comparator; The fourth power tube is an N-type MOS tube, a drain of which is connected to the connection point between the second drive circuit and the second switch power tube, a source is grounded, and a gate is a control electrode connected to the output end of the first comparator.

5. The redundant interlocking circuit for automotive-grade chips according to claim 1 is characterized in that: The third power tube is an NPN type transistor, whose collector is connected to the contact between the first drive circuit and the first switching power tube, the emitter is grounded, and the base is used as a control electrode and connected to the output end of the second comparator; the fourth power tube is an NPN type transistor, whose collector is connected to the contact between the second drive circuit and the second switching power tube, the emitter is grounded, and the base is used as a control electrode and connected to the output end of the first comparator.

6. The redundant interlocking circuit for automotive-grade chips according to claim 1 is characterized in that: The negative phase input terminal of the first comparator is connected to the reference voltage. Specifically: the negative phase input terminal of the first comparator is connected to the reference voltage circuit, the reference voltage circuit includes a power supply and two resistors, the power supply is grounded through the two resistors in sequence, a reference voltage is generated between the two resistors after the power supply voltage is divided by the resistors, and the negative phase input terminal of the first comparator is connected to the junction between the two resistors to access the reference voltage; The negative input terminal of the second comparator is connected to the reference voltage. Specifically: the negative input terminal of the second comparator is connected to the reference voltage circuit, and the reference voltage circuit includes a power supply and two resistors. The power supply is grounded through the two resistors in sequence, and a reference voltage is generated between the two resistors after the power supply voltage is divided by the resistors. The negative input terminal of the second comparator is connected to the junction between the two resistors to access the reference voltage.

7. The redundant interlocking circuit for automotive-grade chips according to claim 1 is characterized in that: The negative phase input terminal of the first comparator and the negative phase input terminal of the second comparator are connected to a reference voltage, specifically, a bandgap reference circuit is connected to the bandgap reference voltage.

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