Successive approximation register type analog-to-digital converter, terminal equipment and signal processing method

Abstract

The present disclosure provides a successive approximation register type analog-to-digital converter, including a comparator, a serial data latch module and a digital-to-analog converter. The comparator compares an input signal with a reference signal according to the bit position. For each bit position, after the comparison of the bit position is completed, the comparison result of the bit position is sent to the serial data latch module; the serial data latch module generates a first reset signal after receiving the comparison result of the last bit position, and sends the first reset signal to the digital-to-analog converter; the digital-to-analog converter is reset according to the first reset signal. As long as the comparison result of the last bit position is obtained, the digital-to-analog converter can be reset immediately, which saves the timing of the synchronization data and the reset data latch logic, optimizes the time decomposition of the successive approximation register type analog-to-digital converter, and is conducive to improving the sampling rate. The present disclosure also provides a terminal device and a signal processing method.

Description

Technical Field

[0001] The present disclosure relates to the field of communication technology, and in particular to a successive approximation register analog-to-digital converter, a terminal device, and a signal processing method. Background Art

[0002] In high-speed ADC (analog-to-digital converter)-based serdes (parallel converter) applications, the speed requirements for ADC are getting higher and higher. In 112G serdes applications, the ADC needs to achieve a 64GHz sampling rate. The implementation method generally adopts a multi-channel time-interleaved architecture. The internal SUBADC (low-precision sub-analog-to-digital converter) is implemented through a high-speed asynchronous SARADC (successive approximation register analog-to-digital converter), requiring the SARADC to achieve a sampling rate of up to 1GHz and a resolution of 7bit.

[0003] The internal timing of high-speed asynchronous SAR ADC is very tight, so it is difficult to achieve a sampling rate of 1 GHz. The time left for conversion is very limited, less than 1 ns. In the case of 7-bit resolution, the time left for each bit conversion may be only about 100 ps, ​​so it is very critical to optimize its timing. Summary of the invention

[0004] The present disclosure provides a successive approximation register type analog-to-digital converter, a terminal device and a signal processing method.

[0005] In a first aspect, an embodiment of the present disclosure provides a successive approximation register type analog-to-digital converter, including a comparator, a serial data latch module, and a digital-to-analog converter;

[0006] The comparator is used to compare the input signal with the reference signal according to the bit position, and for each bit position, after the bit position comparison is completed, send the comparison result of the bit position to the serial data latch module;

[0007] The serial data latch module is used to generate a first reset signal after receiving the comparison result of the last bit, and send the first reset signal to the digital-to-analog converter;

[0008] The digital-to-analog converter is used to reset according to the first reset signal.

[0009] On the other hand, an embodiment of the present disclosure further provides a terminal device, comprising the successive approximation register analog-to-digital converter as described above.

[0010] In another aspect, the present disclosure also provides a signal processing method, which is applied to the successive approximation register analog-to-digital converter as described above, and the method includes:

[0011] Compare the input signal with the reference signal bit by bit;

[0012] After the last bit is compared, a first reset signal is generated;

[0013] The digital-to-analog converter is reset according to the first reset signal.

[0014] The successive approximation register type analog-to-digital converter provided by the disclosed embodiment includes a comparator, a serial data latch module and a digital-to-analog converter. The comparator compares the input signal with the reference signal according to the bit position. For each bit position, after the comparison of the bit position is completed, the comparison result of the bit position is sent to the serial data latch module; the serial data latch module generates a first reset signal after receiving the comparison result of the last bit position, and sends the first reset signal to the digital-to-analog converter; the digital-to-analog converter is reset according to the first reset signal. The disclosed embodiment controls the reset of the digital-to-analog converter by the comparison result of the last bit position of the input signal. As long as the comparison result of the last bit position is obtained, the digital-to-analog converter can be reset immediately, so that data synchronization and data latch reset can be put into the next cycle for execution, which saves the timing of synchronization data and reset data latch logic, optimizes the time decomposition of the successive approximation register type analog-to-digital converter, and is conducive to improving the sampling rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 Module schematic diagram of SARADC provided in the embodiment of the present disclosure Figure 1 ;

[0016] Figure 2 Module schematic diagram of SARADC provided in the embodiment of the present disclosure Figure 2 ;

[0017] Figure 3 A schematic diagram of the structure of a SARADC provided in an embodiment of the present disclosure;

[0018] Figure 4 A signal timing diagram of a SARADC provided in an embodiment of the present disclosure;

[0019] Figure 5 It is a structural diagram of SARADC in the related art;

[0020] Figure 6 It is a signal timing diagram of SARADC in the related art;

[0021] Figure 7 A schematic diagram of time comparison between the SAR ADC in the embodiment of the present disclosure and the SAR ADC in the related art;

[0022] Figure 8The signal processing flow diagram provided in the embodiment of the present disclosure is as follows: Figure 1 ;

[0023] Fig. 9 The signal processing flow diagram provided in the embodiment of the present disclosure is as follows: Figure 2 . DETAILED DESCRIPTION

[0024] Example embodiments will be described more fully below with reference to the accompanying drawings, but the example embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. On the contrary, the purpose of providing these embodiments is to make the present disclosure thorough and complete and to enable those skilled in the art to fully understand the scope of the present disclosure.

[0025] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0026] The terms used herein are only used to describe specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It will also be understood that when the terms "comprising" and / or "made of" are used in this specification, the presence of the features, wholes, steps, operations, elements and / or components is specified, but the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof is not excluded.

[0027] The embodiments described herein may be described with reference to plan views and / or cross-sectional views by means of idealized schematic diagrams of the present disclosure. Therefore, the example illustrations may be modified according to manufacturing techniques and / or tolerances. Therefore, the embodiments are not limited to the embodiments shown in the accompanying drawings, but include modifications of the configurations formed based on the manufacturing process. Therefore, the regions illustrated in the accompanying drawings have schematic properties, and the shapes of the regions shown in the figures illustrate the specific shapes of the regions of the elements, but are not intended to be limiting.

[0028] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted as having an idealized or overly formal meaning unless explicitly defined as such herein.

[0029] One cycle of the high-speed asynchronous SARADC clock signal includes two stages, namely the sampling and holding stage and the conversion stage. The sampling and holding stage mainly samples the input signal, and the conversion stage mainly converts the sampled input signal. When the resolution is 7bit, the conversion stage requires at least 7 data comparisons. After each data comparison, the comparison result is transmitted to the DAC through the data latch module. Each data conversion can be divided into three delay times: 1) the comparison delay of the comparator; 2) the data latch logic delay; 3) the response time of the DAC. After each data conversion, the clock needs to be used to latch the data. This process consumes timing, and then the data latch module needs to be reset to avoid affecting the next sampling stage. In the related art, DAC reset and data latch reset are both achieved by resetting the data latch logic, and the data latch reset also needs to occupy the time of the conversion stage.

[0030] The inventors of the disclosed embodiments discovered that, during the conversion phase, the DAC does not need to respond to the data comparison of the last bit, and can convert normally as long as the comparator compares the result, so that the DAC can be reset immediately. Therefore, the DAC reset can be controlled independently to optimize the signal timing. Based on the above discovery, the disclosed embodiments provide a successive approximation register analog-to-digital converter (SARADC).

[0031] The present disclosure provides a SAR ADC, such as Figure 1 As shown, the SARADC includes a comparator 1, a serial data latch module 2 and a digital-to-analog converter 3. The comparator 1 is used to compare the input signal with the reference signal according to the bit position. For each bit position, after the bit position comparison is completed, the comparison result of the bit position is sent to the serial data latch module 2; the serial data latch module 2 is used to generate a first reset signal (dac_rst) after receiving the comparison result of the last bit position, and send the first reset signal (dac_rst) to the digital-to-analog converter 3; the digital-to-analog converter is used to reset according to the first reset signal (dac_rst).

[0032] The serial data latch module 2 latches the comparison result of each received bit, and sends a voltage control signal to the digital-to-analog converter 3 according to the comparison result of each bit. The digital-to-analog converter 3 controls the voltage of the input signal according to the voltage control signal corresponding to each bit.

[0033] The digital-to-analog converter 3 includes but is not limited to a CDAC (capacitive digital-to-analog converter), and may also be other types of digital-to-analog converters, such as a resistive DAC (R2R-DAC) or a current-steering DAC (Current_Steering DACs).

[0034] The disclosed embodiment controls the DAC reset by comparing the last bit of the input signal. The DAC can be reset immediately as long as the comparison result of the last bit is obtained. In this way, data synchronization and data latch reset can be executed in the next cycle, which saves the timing of synchronizing data and resetting data latch logic, optimizes the time decomposition of SARADC, and is conducive to improving the sampling rate.

[0035] It should be noted that the SARADC may also include an asynchronous clock generation module. The asynchronous clock generation module is used to generate an asynchronous clock signal (clk_async) and send the asynchronous clock signal to the comparator 1. The comparator 1 is used to compare the input signal with the reference signal according to the asynchronous clock signal.

[0036] In some embodiments, Figure 2 As shown, the SARADC may further include a data synchronization module 4, and the serial data latch module 2 is further used to latch the comparison result of each bit and send the comparison result of each bit to the data synchronization module 4; the data synchronization module 4 is used to perform data synchronization processing on the comparison result of each bit.

[0037] Figure 3 A schematic diagram of the structure of the SARADC provided in an embodiment of the present disclosure is shown in FIG. Figure 4 A schematic diagram of the signal timing of the SARADC provided in the embodiment of the present disclosure, combined with Figure 3 and Figure 4 As shown in Figure 1, the data synchronization process (S&H time) includes two stages: S (setup) and H (hold). The data synchronization process occurs after the DAC is reset.

[0038] Before the data latch is reset, the latch output clock signal (dout_latch_clk) is input to the data synchronization module 4. The S phase is between the first reset signal (dac_rst) and the latch output clock signal (dout_latch_clk), and the H phase is from the latch output clock signal (dout_latch_clk) to the data latch reset.

[0039] In some embodiments, the data synchronization module 4 is used to perform data synchronization processing on the comparison result of each bit in the next sampling and holding phase.

[0040] In some embodiments, the serial data latch module 2 includes a plurality of serial data latch units, the number of which is the same as the number of the bits; the data synchronization module 4 includes a plurality of data synchronization units, each of which corresponds to each serial data latch unit. Each serial data latch unit is used to latch the comparison result of the corresponding bit, and send the comparison result of the corresponding bit to the corresponding data synchronization unit; each data synchronization unit is used to perform data synchronization processing on the comparison result of the corresponding bit.

[0041] like Figure 3 As shown, the serial data latch module 2 includes n serial data latch units (D_LATCH N, D_LATCH N-1, ..., D_LATCH 1, D_LATCH 0), and correspondingly, the data synchronization module 4 includes n data synchronization units DFF (D type flip-flops) respectively connected to each serial data latch unit. The n serial data latch units latch the comparison results of the corresponding bits and send them to the data synchronization units connected thereto for data synchronization. Exemplarily, D_LATCH N latches the comparison result D of the nth bit. <n>, and the comparison result D of the nth bit <n>It is sent to the corresponding DFF N, which then <n>Perform data synchronization.

[0042] like Figure 4 As shown, the asynchronous clock signal (clk_async) generated by the asynchronous clock generation module is a pulse signal, and each rising edge of the asynchronous clock signal triggers a serial data latch unit to output a corresponding bit comparison result to a corresponding synchronization unit.

[0043] In some embodiments, the serial data latch module 2 is further used to receive a second reset signal (d_latch_rst) and reset according to the second reset signal (d_latch_rst); the second reset signal (d_latch_rst) is generated in the next sampling and holding phase.

[0044] In some embodiments, the second reset signal may be generated by a data latch unit D_LATCH 0 that latches the last bit comparison result, or the second reset signal may be generated by a clock generator for generating a clock signal (clkin). Figure 4 As shown, the second reset signal (d_latch_rst) is generated in the sampling and holding phase of the next clock signal cycle. Therefore, the data latch reset can be delayed to the sampling and holding phase of the next clock signal cycle without affecting the data sampling of the next clock cycle, thereby saving the timing of resetting the data latch logic.

[0045] like Figure 3 As shown, in the embodiment of the present disclosure, the input signal is a differential signal, including a first input signal (VIP) and a second input signal (VIN), and the above two input signals are input to the comparator 1 through a sampling switch.

[0046] The digital-to-analog converter 3 includes a first digital-to-analog converter DACP and a second digital-to-analog converter DACN, and the serial data latch module 2 includes a first serial data latch module and a second serial data latch module, the first serial data latch module is a module connected to the first digital-to-analog converter DACP, and the second serial data latch module is a module connected to the second digital-to-analog converter DACN.

[0047] Comparator 1 is used to send the comparison result of each bit to the first serial data latch module and the second data latch module after the bit comparison is completed; the first serial data latch module is used to generate a first reset signal (dac_rst) after receiving the comparison result of the last bit, and send the first reset signal (dac_rst) to the first digital-to-analog converter DACP and the second digital-to-analog converter DACN; the first digital-to-analog converter DACP and the second digital-to-analog converter DACN are used to reset according to the first reset signal (dac_rst).

[0048] In the disclosed embodiment, the data synchronization module 4 is connected to the first digital-to-analog converter DACP. It should be noted that the data synchronization module 4 may also be connected to the second digital-to-analog converter DACN.

[0049] To clearly illustrate the solution of the embodiment of the present disclosure, the following Figure 3-6 , the structure and signal timing of the SAR ADC of the embodiment of the present disclosure are compared and explained with the structure and signal timing of the SAR ADC of the related art.

[0050] Figure 5 It is a structural diagram of SARADC in the related technology, such as Figure 5 As shown in the figure, the traditional differential signal SARADC includes DAC (i.e., DACP and DACN), comparator, asynchronous clock generation module, serial data latch module (D_LATCH N-D_LATCH0) and synchronization module (DFF N -DFF0). In traditional high-speed SAR ADCs, the timing of the conversion phase is very tight, which needs to include the conversion of all bit data and the reset of the corresponding serial data latch unit, and actually also needs to include the reset of the DAC. Figure 6 Schematic diagram of the signal timing of SARADC in the related art. Figure 6 As shown, since the reset of the serial data latch module needs to clear the data latched in each serial data latch unit (i.e., the comparison result of each bit), the second reset signal (d_latch_rst) used to reset the serial data latch module needs to be generated before the sampling and holding phase of the next clock cycle, otherwise it will affect the data sampling of the next clock cycle. Therefore, when the sampling speed of SARADC is very fast, the time left for serial data latch to establish and hold (S&H time) is very small, that is, the data synchronization time is short, and there is a problem of shortage of timing resources.

[0051] like Figure 3 As shown, the differential signal SARADC provided by the embodiment of the present disclosure, compared with the traditional differential signal SARADC, adds a DAC reset signal input terminal at the switching switch of the DAC, that is, a DAC reset signal input terminal is added in DACP and DACN respectively, for receiving the first reset signal (dac_rst).

[0052] like Figure 4 As shown in the figure, the timing of the first reset signal (dac_rst) is controlled by the asynchronous clock. When the comparator completes the data comparison of the last bit, the first reset signal (dac_rst) is immediately generated to reset DACP and DACN. Compared with the traditional architecture timing, the latch output clock signal (dout_latch_clk) and the second reset signal (d_latch_rst) can be generated in the sampling and holding phase of the next clock cycle. Figure 4 and Figure 6 It can be seen that the time (S&H time) reserved for serial data latch establishment and holding in the embodiment of the present disclosure is greater than the time reserved for serial data latch establishment and holding in the related art. Therefore, the timing of the current clock cycle conversion phase can be relaxed, the problem of shortage of timing resources in the conversion phase can be solved, and the working efficiency of SARADC can be improved.

[0053] Figure 7 FIG. 4 is a time comparison diagram of the SAR ADC in the embodiment of the present disclosure and the SAR ADC in the related art. Figure 7 As shown, in the related art, in the conversion stage, after completing the data comparison of n bits, data synchronization, D_LATCH reset and DAC reset are required, and timing resources are tight; however, by adopting the solution of the embodiment of the present disclosure, in the conversion stage, after completing the data comparison of n bits, only DAC reset can be performed, and data synchronization and D_LATCH reset can be performed in the sampling and holding stage of the next clock cycle, thereby solving the problem of tight timing resources in the conversion stage.

[0054] The embodiment of the present disclosure also provides a terminal device, comprising the successive approximation register type analog-to-digital converter as described above.

[0055] The terminal device provided by the embodiment of the present disclosure includes a SARADC, and the SARADC includes a comparator, a serial data latch module and a digital-to-analog converter. The comparator compares the input signal with the reference signal according to the bit position, and for each bit position, after the bit position comparison is completed, the comparison result of the bit position is sent to the serial data latch module; the serial data latch module generates a first reset signal after receiving the comparison result of the last bit position, and sends the first reset signal to the digital-to-analog converter; the digital-to-analog converter is reset according to the first reset signal. The embodiment of the present disclosure controls the reset of the digital-to-analog converter by the comparison result of the last bit position of the input signal. As long as the comparison result of the last bit position is obtained, the digital-to-analog converter can be reset immediately, so that data synchronization and data latch reset can be put into the next cycle for execution, which saves the timing of synchronization data and reset data latch logic, optimizes the time decomposition of the successive approximation register type analog-to-digital converter, and is conducive to improving the sampling rate.

[0056] The present disclosure also provides a signal processing method, which is applied to the successive approximation register analog-to-digital converter as described above. Figure 8 and Figure 1 As shown, the method comprises the following steps:

[0057] Step S11, comparing the input signal with the reference signal bit by bit.

[0058] In this step, the input signal and the reference signal are input into the comparator, and the comparator 1 compares the data bit by bit according to the input signal and the reference signal, and sends the comparison result of each bit to the serial data latch module 2.

[0059] Step S12: after the last bit is compared, a first reset signal is generated.

[0060] After the last bit is compared, the serial data latch module 2 generates a first reset signal (dac_rst) and sends the first reset signal (dac_rst) to the digital-to-analog converter 3 .

[0061] Step S13, resetting the digital-to-analog converter according to the first reset signal.

[0062] After receiving the first reset signal (dac_rst), the digital-to-analog converter 3 is reset.

[0063] The signal processing method provided by the embodiment of the present disclosure includes: comparing the input signal with the reference signal according to the bit position, generating a first reset signal after the comparison of the last bit position is completed, and resetting the digital-to-analog converter according to the first reset signal; the embodiment of the present disclosure controls the reset of the digital-to-analog converter by the comparison result of the last bit position of the input signal, and the digital-to-analog converter can be reset immediately as long as the comparison result of the last bit position is obtained, so that the data synchronization and data latch reset can be put into the next cycle for execution, which saves the timing of the synchronization data and reset data latch logic, optimizes the time decomposition of the successive approximation register type analog-to-digital converter, and is conducive to improving the sampling rate.

[0064] In some embodiments, after comparing the input signal with the reference signal according to the bit position (i.e., step S11), the signal processing method may further include the following steps:

[0065] Step S11 ′: for each bit, after the bit comparison is completed, the comparison result of each bit is latched, and data synchronization processing is performed on the comparison result of each bit.

[0066] In some embodiments, the performing data synchronization processing on the comparison result of each bit includes: performing data synchronization processing on the comparison result of each bit in the next sampling and holding phase.

[0067] After receiving the comparison result corresponding to the serial data latch unit, each serial data latch unit of the serial data latch module 2 latches the comparison result, and performs data synchronization processing on the comparison result of each bit in the sampling and holding phase of the next clock cycle, and puts the data synchronization originally performed in the current clock cycle into the next clock cycle, thereby solving the problem of tight timing resources in the conversion phase.

[0068] In some embodiments, Fig. 9 As shown, the signal processing method may further include the following steps:

[0069] Step S21, generating a second reset signal in the next sampling and holding phase.

[0070] Step S22, resetting the serial data latch module according to the second reset signal.

[0071] In the sampling phase of the next clock cycle, after receiving the second reset signal (d_latch_rst), the serial data latch module 2 is reset to clear the comparison results of each bit previously latched.

[0072] In some embodiments, when the input signal of the SARADC is a differential signal (including a first input signal VIP and a second input signal VIN), the step of comparing the input signal with a reference signal bit by bit (i.e., step S11) includes the following steps: comparing the first input signal VIP with the reference signal bit by bit, and comparing the second input signal VIN with the reference signal bit by bit.

[0073] The step of generating a first reset signal after the last bit position is compared (ie, step S12) comprises the following steps: generating a first reset signal after the last bit position of the first input signal VIP is compared.

[0074] The resetting of the digital-to-analog converter according to the first reset signal (ie step S13) comprises the following steps: resetting the first digital-to-analog converter and the second digital-to-analog converter respectively according to the first reset signal.

[0075] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for limiting purposes. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly stated, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the scope of the invention as set forth in the appended claims.< / n> < / n> < / n>

Claims

1. A successive approximation register analog-to-digital converter, characterized in that: It includes a comparator, a serial data latch module and a digital-to-analog converter; The comparator is used to compare the input signal with the reference signal according to the bit position, and for each bit position, after the bit position comparison is completed, send the comparison result of the bit position to the serial data latch module; The serial data latch module is used to generate a first reset signal after receiving the comparison result of the last bit, and send the first reset signal to the digital-to-analog converter; The digital-to-analog converter is used to reset according to the first reset signal.

2. The successive approximation register analog-to-digital converter according to claim 1, wherein: It also includes a data synchronization module, and the serial data latch module is further used to latch the comparison result of each bit position and send the comparison result of each bit position to the data synchronization module; The data synchronization module is used to perform data synchronization processing on the comparison results of each bit.

3. The successive approximation register analog-to-digital converter according to claim 2, wherein: The data synchronization module is used to perform data synchronization processing on the comparison result of each bit in the next sampling and holding phase.

4. The successive approximation register analog-to-digital converter according to claim 2, wherein: The serial data latch module includes a plurality of serial data latch units, the number of which is the same as the number of the bits; the data synchronization module includes a plurality of data synchronization units, each of which corresponds to each of the serial data latch units one by one; Each of the serial data latch units is used to latch the comparison result of the corresponding bit position, and send the comparison result of the corresponding bit position to the corresponding data synchronization unit; Each of the data synchronization units is used to perform data synchronization processing on the comparison result of the corresponding bit position.

5. The successive approximation register analog-to-digital converter according to claim 1, wherein: The serial data latch module is also used to receive a second reset signal and reset according to the second reset signal; the second reset signal is generated in the next sampling and holding phase.

6. The successive approximation register analog-to-digital converter according to any one of claims 1 to 5, characterized in that: The input signal is a differential signal, the digital-to-analog converter includes a first digital-to-analog converter and a second digital-to-analog converter, and the serial data latch module includes a first serial data latch module and a second serial data latch module; The comparator is used for sending the comparison result of each bit to the first serial data latch module and the second data latch module after the bit comparison is completed; The first serial data latch module is used to generate a first reset signal after receiving the comparison result of the last bit, and send the first reset signal to the first digital-to-analog converter and the second digital-to-analog converter; The first digital-to-analog converter and the second digital-to-analog converter are used to be reset according to the first reset signal.

7. A terminal device, characterized in that: It comprises a successive approximation register type analog-to-digital converter as described in any one of claims 1-6.

8. A signal processing method, characterized in that: Applied to the successive approximation register analog-to-digital converter according to any one of claims 1 to 6, the method comprising: Compare the input signal with the reference signal bit by bit; After the last bit is compared, a first reset signal is generated; The digital-to-analog converter is reset according to the first reset signal.

9. The method according to claim 8, characterized in that After comparing the input signal with the reference signal bit by bit, the method further includes: For each bit, after the bit comparison is completed, the comparison result of each bit is latched, and data synchronization processing is performed on the comparison result of each bit.

10. The method according to claim 9, characterized in that The data synchronization processing of the comparison results of each bit position includes: In the next sampling and holding phase, data synchronization processing is performed on the comparison results of each bit.

11. The method according to claim 8, characterized in that The method further comprises: generating a second reset signal in the next sample-and-hold phase; The serial data latch module is reset according to the second reset signal.

12. The method according to any one of claims 8 to 11, characterized in that: The method is applied to the successive approximation register analog-to-digital converter as claimed in claim 6; the input signal is a differential signal, including a first input signal and a second input signal; The step of comparing the input signal with the reference signal according to the bit position includes: Compare the first input signal with a reference signal bit by bit, and compare the second input signal with a reference signal bit by bit; The step of generating a first reset signal after the last bit is compared comprises: After the last bit of the first input signal is compared, generating the first reset signal; The resetting the digital-to-analog converter according to the first reset signal comprises: The first digital-to-analog converter and the second digital-to-analog converter are reset respectively according to the first reset signal.

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