Signal processing method and device, equipment, storage medium and program product

Abstract

Provided in the present application are a signal processing method, apparatus, device, storage medium and program product, the method comprising: opening a first state of a phase-locked loop (PLL) in a radio frequency transceiver chip, the radio frequency transceiver chip being a radio frequency transceiver chip in a time division duplex (TDD) transceiver system, and a second state of a phase-locked loop (PLL) in the radio frequency transceiver chip being a radio frequency transceiver chip in the TDD transceiver system; the radio frequency transceiver chip comprises a transmitting link and a receiving link, and the PLL is connected with a local oscillator of the transmitting link and is connected with a local oscillator of the receiving link; obtaining a first direct current offset of a signal of a receiving link; and under the condition that the first direct current offset is greater than or equal to a preset value, the state of the PLL is switched from the first state to a target state, and under the target state, the direct current offset of the signal of the receiving link is smaller than the preset value. According to the embodiment of the invention, multiple states of the PLL are configured for the radio frequency transceiver chip, so that the influence of direct current offset is reduced by switching the states of the PLL, and resource occupation can be reduced.

Description

Technical Field

[0001] The present application relates to the field of wireless technology, and in particular to a signal processing method, apparatus, device, storage medium and program product. Background Art

[0002] At present, the fifth generation mobile communication network (5G) base station usually adopts the zero intermediate frequency receiver architecture, which has low receiver hardware complexity, small size and reduced power consumption. However, the zero intermediate frequency receiver architecture will produce a large DC offset at the zero intermediate frequency, which is easy to cause interference to the baseband signal.

[0003] To address the DC offset problem of zero-IF receivers, calibration is usually performed in different gain modes, and then the calibration value is stored in a lookup table in memory, or the input of the low-noise amplifier is terminated with a virtual load and the DC offset is evaluated and stored in memory. In this way, in the working mode or in the burst time slot, the stored DC offset is subtracted from the received digital baseband signal, or fed to the analog baseband circuit through a digital-to-analog converter (DAC) for subtraction, which can reduce the impact of the DC offset.

[0004] However, the above method of subtracting signals requires a large amount of storage resources, resulting in high operating costs. Summary of the invention

[0005] The embodiments of the present application provide a signal processing method, apparatus, device, storage medium and program product to solve the problem of high equipment operating cost when processing the influence of DC offset.

[0006] To solve the above technical problems, this application is implemented as follows: In a first aspect, an embodiment of the present application provides a signal processing method, the method comprising: Turning on a first state of a phase-locked loop (PLL) in a radio frequency transceiver chip, wherein the radio frequency transceiver chip is a radio frequency transceiver chip in a time division duplex (TDD) transceiver system, the radio frequency transceiver chip includes a transmitting link and a receiving link, the PLL is connected to a local oscillator of the transmitting link and to a local oscillator of the receiving link, and the first state is one of at least two states of the PLL; Acquire a first DC offset of a signal of the receiving link; When the first DC offset is greater than or equal to a preset value, the state of the PLL is switched from the first state to a target state, wherein the target state is one of the at least two states except the first state, and in the target state, the DC offset of the signal of the receiving link is less than the preset value.

[0007] Optionally, when the first DC offset is greater than or equal to a preset value, switching the state of the PLL from the first state to a target state includes: In a case where the first DC offset is greater than or equal to a preset value, switching the state of the PLL from the first state to a second state of the at least two states in a receiving time slot, wherein the PLL generates local oscillator signals with the same frequency for the transmitting link and the receiving link in the first state, and the second state is a state of interrupting the transmission of the local oscillator signal of the transmitting link; Acquire a second DC offset of the signal of the receiving link; A target state of the PLL is determined according to the second DC offset.

[0008] Optionally, determining a target state of the PLL according to the second DC offset includes: When the second DC offset is greater than or equal to the preset value, switching the state of the PLL from the second state to a third state of the at least two states, wherein the PLL generates a first local oscillator signal for the transmitting link and a second local oscillator signal for the receiving link, and the first local oscillator signal and the second local oscillator signal have different frequencies; The DC signal of the receiving link is filtered by a baseband filter until the DC signal offset of the receiving link is less than the preset value.

[0009] Optionally, after switching the state of the PLL from the second state to a third state of the at least two states, the method further includes: Acquire an adjacent channel leakage ratio (ACLR) of the transmission link; When the ACLR is less than a preset threshold value, switching the state of the PLL from the third state to a fourth state of the at least two states in a transmission time slot, wherein in the fourth state, the PLL interrupts transmission of the local oscillator signal of the receiving link; The filtering process of the DC signal of the receiving link by the baseband filter until the DC signal offset of the receiving link is less than the preset value includes: When the ACLR is greater than or equal to the preset threshold value, the DC signal of the receiving link is filtered by a baseband filter until the DC signal offset of the receiving link is less than the preset value.

[0010] Optionally, determining a target state of the PLL according to the second DC offset includes: When the second DC offset is less than the preset value, the second state is determined as the target state of the PLL.

[0011] Optionally, before starting the first state of the PLL in the radio frequency transceiver chip, the method further includes: Acquiring a first temperature value in the radio frequency transceiver chip; After the first state of the PLL in the radio frequency transceiver chip is turned on, the method further includes: Acquiring a second temperature value in the radio frequency transceiver chip; When the first DC offset is less than the preset value and the difference between the second temperature value and the first temperature value is greater than a preset threshold, the temperature of the RF transceiver chip is updated from the first temperature value to the second temperature value, and the DC offset of the signal of the receiving link is detected based on the updated temperature value.

[0012] Optionally, the local oscillator of the transmitting link is connected to the reference signal transmitting device through the PLL, and the local oscillator of the receiving link is connected to the PLL through a first switch; The local oscillator of the transmission link is connected to the mixer of the transmission link through a second switch; The local oscillator of the receiving link is connected to the mixer of the receiving link through a third switch; In the first state, the first switch, the second switch and the third switch are all in a closed state; In the second state of the PLL, the first switch and the third switch are both in a closed state, and the second switch is in an open state.

[0013] Optionally, the PLL includes a first PLL and a second PLL; The first end of the first PLL and the first end of the second PLL are connected to the reference signal transmitting device, and the frequencies of the signals output by the first PLL and the second PLL are different; The second end of the first PLL is connected to the local oscillator of the transmitting link, the second end of the second PLL is connected to the local oscillator of the receiving link through a fourth switch, and the second end of the first PLL and the second end of the second PLL are connected through the first switch; In the first state, the first switch, the second switch and the third switch are all in a closed state, and the fourth switch is in an open state; In the second state of the PLL, the first switch and the third switch are both in a closed state, and the second switch and the fourth switch are in an open state; In a third state of the PLL, the first switch is in an open state, and the second switch, the third switch and the fourth switch are all in a closed state; In a fourth state of the PLL, the first switch and the third switch are both in an open state, and the second switch and the fourth switch are both in a closed state.

[0014] In a second aspect, an embodiment of the present application provides a signal processing device, the device comprising: An enabling module, used to enable a first state of a phase-locked loop (PLL) in a radio frequency transceiver chip, wherein the radio frequency transceiver chip is a radio frequency transceiver chip in a time division duplex (TDD) transceiver system, the radio frequency transceiver chip includes a transmitting link and a receiving link, the PLL is connected to a local oscillator of the transmitting link and to a local oscillator of the receiving link, and the first state is one of at least two states of the PLL; A first acquisition module, used to acquire a first DC offset of a signal of the receiving link; a switching module, configured to switch the state of the PLL from the first state to a target state when the first DC offset is greater than or equal to a preset value, wherein the target state is one of the at least two states except the first state, and in the target state, the DC offset of the signal of the receiving link is less than the preset value.

[0015] Optionally, when the first DC offset is greater than or equal to a preset value, the switching module includes: a switching submodule, configured to switch the state of the PLL from the first state to a second state of the at least two states in a receiving time slot when the first DC offset is greater than or equal to a preset value, wherein the PLL generates local oscillator signals with the same frequency for the transmitting link and the receiving link in the first state, and the second state is a state of interrupting the transmission of the local oscillator signal of the transmitting link; An acquisition submodule, used for acquiring a second DC offset of the signal of the receiving link; A determination submodule is used to determine a target state of the PLL according to the second DC offset.

[0016] Optionally, the determining submodule includes: a first switching unit, configured to switch the state of the PLL from the second state to a third state of the at least two states when the second DC offset is greater than or equal to the preset value, wherein the PLL generates a first local oscillator signal for the transmitting link and a second local oscillator signal for the receiving link, and the first local oscillator signal and the second local oscillator signal have different frequencies; The processing unit is used to filter the DC signal of the receiving link through a baseband filter until the DC signal offset of the receiving link is less than the preset value.

[0017] Optionally, the determining submodule further includes: An acquisition unit, configured to acquire an adjacent channel leakage ratio ACLR of the transmission link; A second switching unit, configured to switch the state of the PLL from the third state to a fourth state of the at least two states in a transmission time slot when the ACLR is less than a preset threshold value, wherein in the fourth state, the PLL interrupts transmission of the local oscillator signal of the receiving link; The processing unit is specifically used for: When the ACLR is greater than or equal to the preset threshold value, the DC signal of the receiving link is filtered by a baseband filter until the DC signal offset of the receiving link is less than the preset value.

[0018] Optionally, the determining submodule is specifically used for: When the second DC offset is less than the preset value, the second state is determined as the target state of the PLL.

[0019] Optionally, the device further comprises: A second acquisition module, used to acquire a first temperature value in the radio frequency transceiver chip; The device also includes: A third acquisition module, used to acquire a second temperature value in the radio frequency transceiver chip; An updating module is used to update the temperature of the RF transceiver chip from the first temperature value to the second temperature value when the first DC offset is less than the preset value and the difference between the second temperature value and the first temperature value is greater than a preset threshold, and detect the DC offset of the signal of the receiving link based on the updated temperature value.

[0020] Optionally, the local oscillator of the transmitting link is connected to the reference signal transmitting device through the PLL, and the local oscillator of the receiving link is connected to the PLL through a first switch; The local oscillator of the transmission link is connected to the mixer of the transmission link through a second switch; The local oscillator of the receiving link is connected to the mixer of the receiving link through a third switch; In the first state, the first switch, the second switch and the third switch are all in a closed state; In the second state of the PLL, the first switch and the third switch are both in a closed state, and the second switch is in an open state.

[0021] Optionally, the PLL includes a first PLL and a second PLL; The first end of the first PLL and the first end of the second PLL are connected to the reference signal transmitting device, and the frequencies of the signals output by the first PLL and the second PLL are different; The second end of the first PLL is connected to the local oscillator of the transmitting link, the second end of the second PLL is connected to the local oscillator of the receiving link through a fourth switch, and the second end of the first PLL and the second end of the second PLL are connected through the first switch; In the first state, the first switch, the second switch and the third switch are all in a closed state, and the fourth switch is in an open state; In the second state of the PLL, the first switch and the third switch are both in a closed state, and the second switch and the fourth switch are in an open state; In a third state of the PLL, the first switch is in an open state, and the second switch, the third switch and the fourth switch are all in a closed state; In a fourth state of the PLL, the first switch and the third switch are both in an open state, and the second switch and the fourth switch are both in a closed state.

[0022] In a third aspect, an embodiment of the present application provides an electronic device, comprising: a processor, a memory, and a program stored in the memory and executable on the processor, wherein the program, when executed by the processor, implements the steps of the signal processing method described in the first aspect.

[0023] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the signal processing method described in the first aspect are implemented.

[0024] In a fifth aspect, a computer program product is provided, comprising computer instructions, which, when executed by a processor, implement the steps of the signal processing method as described in the first aspect.

[0025] In the embodiment of the present application, a plurality of states of the PLL are configured for the RF transceiver chip, thereby reducing the influence of the DC offset by switching the state of the PLL, thereby reducing resource usage and lowering the operating cost of the equipment. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments of the present application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0027] Figure 1 This is a zero intermediate frequency receiver architecture diagram provided in an embodiment of the present application; Figure 2 It is one of the flowcharts of a signal processing method provided in an embodiment of the present application; Figure 3 It is a structural schematic diagram of a radio frequency transceiver chip provided in an embodiment of the present application; Figure 4 is a schematic diagram of a phase-locked loop provided in an embodiment of the present application; Figure 5 This is the second flowchart of a signal processing method provided in an embodiment of the present application; Figure 6 is a structural schematic diagram of a signal processing device provided in an embodiment of the present application; Figure 7 It is a structural diagram of a communication device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0028] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0029] In order to facilitate understanding of the content of this application, the related technology is explained.

[0030] like Figure 1 As shown, Figure 1 This is a zero intermediate frequency receiver architecture diagram used in 5G base stations. Its working principle is: the antenna receives the frequency F sig The RF signal is filtered by the RF filter and amplified by the low noise amplifier; lo , F lo =Fsig ) mixes the RF signal to the baseband; at the baseband, the baseband signal is amplified to the appropriate power and the out-of-band useless signal is filtered out through the baseband filter and baseband amplifier; after being converted into a digital baseband signal by the analog-to-digital converter (ADC), it is processed by the digital module and finally the digital signal is output.

[0031] Since the zero-IF receiver has low hardware complexity and small size, it also reduces power consumption. However, it generates a large DC offset at the zero IF, which interferes with the baseband signal and affects the performance. Generally speaking, the generation of DC offset can be divided into three aspects: the first is the self-mixing of the local oscillator signal, that is, due to the poor isolation between the RF and local oscillator ports of the mixer, the local oscillator leaks to the front stage and reflects to the mixer input, mixing with the local oscillator; the second is the transmission leakage self-mixing, that is, the transmission signal will leak to the RF port of the mixer through the receiving link, and due to the limited isolation between the RF and local oscillator ports of the mixer, the transmission signal will self-mix; the third is the self-mixing of the strong interference signal, that is, the strong interference outside the system is transmitted to the RF port of the mixer, and due to the limited isolation between the RF and local oscillator ports of the mixer, a DC offset is caused.

[0032] To address the DC offset problem, a high-pass filter can be added after the mixer to filter out the DC offset. However, its cutoff frequency is related to the capacitance value. If you want to filter out the DC offset, the capacitance value must be very large, and the larger the capacitance volume, this is not conducive to the high integration of the device. It will also slow down the switching speed between the transmit mode and the receive mode, and will also introduce excessive delay, resulting in a decrease in the sensitivity of the receive link. Most importantly, this method may filter out the entire received signal.

[0033] The embodiments of the present application provide a signal processing method, apparatus, device, storage medium and program product to solve the problem of high equipment operating cost when processing the influence of DC offset.

[0034] See also Figure 2 , Figure 2 is a flow chart of a signal processing method provided by an embodiment of the present application, such as Figure 2 As shown, the method comprises the following steps: Step 201, starting a first state of a phase-locked loop (PLL) in a radio frequency transceiver chip, wherein the radio frequency transceiver chip is a radio frequency transceiver chip in a time division duplexing (TDD) transceiver system, the radio frequency transceiver chip includes a transmitting link and a receiving link, the PLL is connected to a local oscillator of the transmitting link and to a local oscillator of the receiving link, and the first state is one of at least two states of the PLL; Step 202: Acquire a first DC offset of a signal of the receiving link; Step 203: When the first DC offset is greater than or equal to a preset value, switch the state of the PLL from the first state to a target state, wherein the target state is one of the at least two states except the first state, and in the target state, the DC offset of the signal of the receiving link is less than the preset value.

[0035] like Figure 3 As shown, the RF transceiver chip (TRX) includes a transmitting link (the upper part of the figure) and a receiving link (the lower part of the figure). By configuring a phase-locked loop (PLL) to be connected to the local oscillators of the transmitting link and the receiving link at the same time, and configuring different states of the PLL, the PLL can be switched between different states, thereby achieving the purpose of reducing or eliminating the DC offset.

[0036] Among them, PLL is a closed-loop feedback control system, and its schematic diagram can be found in Figure 4 As shown in Figure 1. PLL can lock the phase and frequency of the input signal and generate an output signal that is synchronized with the input signal.

[0037] The phase-locked loop is mainly composed of a phase detector, a low-pass filter, a voltage-controlled oscillator and a frequency divider. The working principle of the phase-locked loop is based on feedback control. When the frequency F of the input signal after frequency division is ref / M and the frequency F of the voltage-controlled oscillator output signal after the feedback loop divides it out When / N is different, the phase detector will detect the phase difference and generate an error signal. This error signal is processed by the filter and used to adjust the frequency of the voltage-controlled oscillator until F ref / M and F out / N frequency and phase are consistent, at this time PLL enters the locked state, and finally achieves a stable frequency of F out =F ref ×N / M output signal.

[0038] Based on the above principle, the PLL is connected to the reference signal transmitting device, and a signal of the corresponding frequency can be output through the PLL.

[0039] Meanwhile, in the TDD transceiver system, the register stores at least two states of the PLL configuration, for example, the following four states of the configuration switch, where the four switch states correspond one to one to the four states of the PLL.

[0040] Switch state 1: S1 connected, S2 connected, S3 connected, S4 disconnected; Switch state 2: S1 connected, S2 disconnected, S3 connected, S4 disconnected; Switch state 3: S1 is disconnected, S2 is connected, S3 is connected, and S4 is connected; Switch state 4: S1 is disconnected, S2 is connected, S3 is disconnected, and S4 is connected.

[0041] The PLL state is switched by adjusting the switch state.

[0042] In at least two states of the PLL, a single state or coordinated switching between multiple states can be used to reduce the DC offset of the signal of the receiving link.

[0043] The at least two states of the PLL may include at least two of the following states: The PLL generates a local oscillator signal with the same frequency for the transmit link and the receive link; The PLL generates local oscillator signals with different frequencies for the transmit link and the receive link; The PLL only generates the local oscillator signal for the receive link; The PLL only generates the local oscillator signal for the transmit chain.

[0044] When the PLL is in the first state, if the DC offset of the receiving link is greater than the preset value, the PLL can be switched to the second state. If the DC offset of the receiving link is less than the preset value in the second state, the second state is the target state. If the DC offset of the receiving link is still greater than the preset value in the second state, the PLL can be switched to the third state and / or the fourth state until the DC offset of the receiving link is less than the preset value, and the current state of the PLL is the target state.

[0045] The above-mentioned various states of PLL can be Figure 3 The present invention can be implemented by the switch combination shown in the figure. In addition, it can also be implemented in other ways, for example, by configuring different PLLs to be connected to the transmitting link and the receiving link respectively, and each PLL corresponds to one of the at least two states mentioned above, and the state switching of the PLL is realized by controlling the working state of each PLL.

[0046] Optionally, when the first DC offset is greater than or equal to a preset value, switching the state of the PLL from the first state to a target state includes: In a case where the first DC offset is greater than or equal to a preset value, switching the state of the PLL from the first state to a second state of the at least two states in a receiving time slot, wherein the PLL generates local oscillator signals with the same frequency for the transmitting link and the receiving link in the first state, and the second state is a state of interrupting the transmission of the local oscillator signal of the transmitting link; Acquire a second DC offset of the signal of the receiving link; A target state of the PLL is determined according to the second DC offset.

[0047] When the PLL is in the first state, if the DC offset of the signal of the receiving link is greater than the preset value, considering that in the TDD transceiver system, the transmission leakage self-mixing generated by the transmitting local oscillator has a greater impact on the chip performance, in the TDD transceiver system, the local oscillator signal of the transmitting link is turned off in the receiving time slot, that is, the state of the PLL is switched to the second state in the receiving time slot, so that the receiving link can reduce the interference caused by the leakage of the transmitting signal in the receiving time slot.

[0048] like Figure 3 As shown, in the first state of the PLL, the first switch (S1), the second switch (S2), and the third switch (S3) are in a closed state, and the fourth switch (S4) is in an open state, and PLL1 generates a local oscillator signal with the same power for the transmitting link and the receiving link; in the second state, S1 and S3 are in a connected state, and S2 and S4 are in a disconnected state, that is, the local oscillator signal of the transmitting link is interrupted during the receiving time slot, and PLL1 only generates a local oscillator signal for the receiving link.

[0049] In the above manner, the PLL state can be switched to reduce the transmission leakage generated by the transmission local oscillator in the receiving time slot, thereby reducing the DC offset of the receiving link.

[0050] Optionally, determining a target state of the PLL according to the second DC offset includes: When the second DC offset is greater than or equal to the preset value, switching the state of the PLL from the second state to a third state of the at least two states, wherein the PLL generates a first local oscillator signal for the transmitting link and a second local oscillator signal for the receiving link, and the first local oscillator signal and the second local oscillator signal have different frequencies; The DC signal of the receiving link is filtered by a baseband filter until the DC signal offset of the receiving link is less than the preset value.

[0051] When the PLL is in the second state, if the DC offset of the receiving link is still greater than or equal to the preset value, it means that there is still self-mixing of the received local oscillator signal or self-mixing of the strong interference signal. In this case, the mixer of the receiving link of the RF transceiver chip adopts the baseband frequency shifting function, and the PLL generates local oscillator signals with different frequencies for the transmitting link and the receiving link.

[0052] like Figure 3 As shown, in the third state, S1 is disconnected, S2 is connected, S3 is connected, S4 is connected, and PLL1 and PLL2 generate local oscillator signals with different frequencies, respectively, for the transmitting link and the receiving link.

[0053] In the third state, when the signal of the receiving link is mixed to the frequency difference between the first local oscillator signal and the second local oscillator signal, the DC is filtered out by the baseband filter until the DC signal offset of the receiving signal is less than the preset value.

[0054] By means of the above method, the DC offset caused by the self-mixing of the received local oscillator signal or the self-mixing of the strong interference signal can be reduced.

[0055] Optionally, after switching the state of the PLL from the second state to a third state of the at least two states, the method further includes: Obtaining an adjacent channel leakage ratio (ACLR) of the transmission link; When the ACLR is less than a preset threshold value, switching the state of the PLL from the third state to a fourth state of the at least two states in a transmission time slot, wherein in the fourth state, the PLL interrupts transmission of the local oscillator signal of the receiving link; The filtering process of the DC signal of the receiving link by the baseband filter until the DC signal offset of the receiving link is less than the preset value includes: When the ACLR is greater than or equal to the preset threshold value, the DC signal of the receiving link is filtered by a baseband filter until the DC signal offset of the receiving link is less than the preset value.

[0056] When the PLL is in the third state, the ACLR of the transmitting link is obtained. If the ACLR is less than the preset threshold value, it means that the spectrum of the transmitting link is expanded, causing the ACLR value to deteriorate. In this case, the local oscillator signal of the receiving link is interrupted during the transmitting time slot, and the DC signal of the receiving link is filtered through the baseband filter.

[0057] If the ACLR is greater than the preset threshold value, it means that the spectrum of the transmission link does not cause the ACLR value to deteriorate, and the DC signal of the receiving link is filtered out through the baseband filter.

[0058] Through the above method, the interference to the transmitted signal can be reduced and the signal quality can be improved.

[0059] Optionally, determining a target state of the PLL according to the second DC offset includes: When the second DC offset is less than the preset value, the second state is determined as the target state of the PLL.

[0060] When the PLL switches from the first state to the second state, if the DC offset of the receiving link is less than a preset value, the second state is determined as the target state of the PLL.

[0061] Optionally, before starting the first state of the PLL in the radio frequency transceiver chip, the method further includes: Acquiring a first temperature value in the radio frequency transceiver chip; After the first state of the PLL in the radio frequency transceiver chip is turned on, the method further includes: Acquiring a second temperature value in the radio frequency transceiver chip; When the first DC offset is less than the preset value and the difference between the second temperature value and the first temperature value is greater than a preset threshold, the temperature of the RF transceiver chip is updated from the first temperature value to the second temperature value, and the DC offset of the signal of the receiving link is detected based on the updated temperature value.

[0062] Since the performance of the RF transceiver chip may be affected by changes in system temperature, a first temperature value inside the chip is obtained before the first state of the PLL is turned on, and a second temperature value inside the chip is obtained after the first state is turned on. When the first DC offset is less than a preset value, if the temperature change inside the chip is large (greater than a preset threshold), the temperature value is updated, and the DC offset of the signal of the receiving link is re-detected based on the updated temperature value, and it is determined whether the DC offset is greater than the preset value based on the re-detected DC offset.

[0063] Similarly, before the PLL switches to the second state, a first temperature value inside the chip can be obtained, and after switching to the second state, a second temperature value inside the chip can be obtained. If the temperature changes greatly, the DC offset of the signal of the receiving link can be detected again based on the changed temperature.

[0064] Through the above method, the impact of temperature change on the detection result of the DC offset can be reduced, thereby improving the detection accuracy of the DC offset.

[0065] Optionally, the local oscillator of the transmitting link is connected to the reference signal transmitting device through the PLL, and the local oscillator of the receiving link is connected to the PLL through a first switch; The local oscillator of the transmission link is connected to the mixer of the transmission link through a second switch; The local oscillator of the receiving link is connected to the mixer of the receiving link through a third switch; In the first state, the first switch, the second switch and the third switch are all in a closed state; In the second state of the PLL, the first switch and the third switch are both in a closed state, and the second switch is in an open state.

[0066] like Figure 3 As shown, the PLL is connected to the reference signal transmitting device and the local oscillator of the transmitting link, and the PLL is connected to the local oscillator of the receiving link through the first switch S1.

[0067] The local oscillator of the transmission link is connected to the mixer of the transmission link through the second switch S2, and the local oscillator of the reception link is connected to the mixer of the reception link through the third switch S3.

[0068] Based on the above structure, when the PLL is in the first state, the first switch S1, the second switch S2 and the third switch S3 are closed, and the reference signal transmitting device transmits local oscillator signals with the same power for the transmitting link and the receiving link through PLL1.

[0069] When the PLL is in the second state, the first switch S1 and the third switch S3 are closed, the second switch S2 is open, and the PLL1 generates a local oscillator signal for a receiving link.

[0070] By closing and opening a plurality of switches to switch the PLL state, the DC offset of the receiving link can be reduced, and resource occupation and the operating cost of the equipment can be reduced.

[0071] Optionally, the PLL includes a first PLL and a second PLL; The first end of the first PLL and the first end of the second PLL are connected to the reference signal transmitting device, and the frequencies of the signals output by the first PLL and the second PLL are different; The second end of the first PLL is connected to the local oscillator of the transmitting link, the second end of the second PLL is connected to the local oscillator of the receiving link through a fourth switch, and the second end of the first PLL and the second end of the second PLL are connected through the first switch; In the first state, the first switch, the second switch and the third switch are all in a closed state, and the fourth switch is in an open state; In the second state of the PLL, the first switch and the third switch are both in a closed state, and the second switch and the fourth switch are in an open state; In a third state of the PLL, the first switch is in an open state, and the second switch, the third switch and the fourth switch are all in a closed state; In a fourth state of the PLL, the first switch and the third switch are both in an open state, and the second switch and the fourth switch are both in a closed state.

[0072] like Figure 3 As shown, the first PLL and the second PLL are respectively connected to the reference signal transmitting device, and the first PLL and the second PLL process the signal transmitted by the reference signal transmitting device to obtain a first local oscillation signal and a second local oscillation signal with different frequencies.

[0073] In the first state, the first switch S1, the second switch S2 and the third switch S3 are all closed, the fourth switch S4 is open, and the PLL1 generates a local oscillator signal for a transmitting link and a local oscillator signal for a receiving link with the same frequency; In the second state, the first switch S1 and the third switch S3 are both closed, the second switch S2 and the fourth switch S4 are open, and the PLL1 generates a local oscillator signal used only for the receiving link; In the third state, the first switch S1 is opened, the second switch S2, the third switch S3 and the fourth switch S4 are closed, PLL1 and PLL2 are both in the on state, and PLL1 and PLL2 generate local oscillator signals of different frequencies for the transmitting link and the receiving link respectively; In the fourth state, the first switch S1 and the third switch S3 are opened, the second switch S2 and the fourth switch S4 are closed, and the PLL1 generates a local oscillator signal used only for the transmission link.

[0074] By closing and opening a plurality of switches to switch the PLL state, the DC offset of the receiving link can be reduced, and resource occupation and the operating cost of the equipment can be reduced.

[0075] The embodiments of the present application can reduce or eliminate the DC offset introduced in the zero intermediate frequency architecture by switching the state of the PLL, which helps to improve the performance of the system.

[0076] To facilitate understanding of this embodiment, the specific implementation methods of this application are described below with reference to the accompanying drawings.

[0077] like Figure 5 As shown, the signal processing method includes the following steps: Step 1: In the TDD transceiver system, four states of PLL configuration are stored in the RF chip register: switch state 1: S1 connected, S2 connected, S3 connected, S4 disconnected, the address bit is 1011 (1-4 bits); switch state 2: S1 connected, S2 disconnected, S3 connected, S4 disconnected, the address bit is 1001 (5-8 bits); switch state 3: S1 disconnected, S2 connected, S3 connected, S4 connected, the address bit is 0111 (9-12 bits); switch state 4: S1 disconnected, S2 connected, S3 disconnected, S4 connected, the address bit is 0110 (13-16 bits).

[0078] Step 2: Set the clock reference signal frequency to F ref , the RF signal frequency is set to F sig , the temperature sensor of the RF transceiver chip records the temperature at this time as T, and the microcontroller unit (MCU) reads the address bit of switch state 1 in the memory. The switch state at this time is switch state 1. Start PLL1 to generate a frequency of F lo The local oscillator signals are used for the transmitting link and the receiving link respectively. In the zero intermediate frequency architecture, F sig =F lo .

[0079] Step 3: Based on the baseband digital signal processing result, the chip internally determines whether a DC offset occurs in the receiving link (ie, the DC offset is greater than a preset value).

[0080] If no DC offset occurs, it is necessary to consider that the performance of the RF transceiver chip may be affected by changes in system temperature. That is, the chip determines whether the temperature changes based on the temperature displayed by the temperature sensor at this time. If the temperature remains unchanged, the entire process ends. If the temperature changes, T is updated to the temperature of the chip at this time, and re-determines whether DC offset occurs in the receiving link, and the process is repeated; If DC offset occurs, considering that in the TDD transceiver system, the transmit leakage self-mixing generated by the transmit local oscillator has a greater impact on the chip performance, so the local oscillator of the transmit link is first turned off in the receive time slot, and the MCU of the RF transceiver chip reads the address bit of switch state 2 in the memory. The switch state at this time is switch state 2.

[0081] Step 4: Based on the baseband digital signal processing, the chip determines whether the DC offset is eliminated (i.e., the DC offset is less than the preset value).

[0082] If the DC offset is eliminated, the corresponding transmission leakage self-mixing is eliminated, and the chip determines whether the temperature has changed based on the temperature displayed by the temperature sensor at this time. If the temperature remains unchanged, the entire process ends; if the temperature changes, T is updated to the temperature of the chip at this time, and it is re-determined whether there is a DC offset in the receiving link, and the process is repeated; If the DC offset is not eliminated, it means that there is still self-mixing of the received local oscillator signal or strong interference signal. In this case, the mixer of the receiving link of the RF transceiver chip uses the baseband frequency shifting function, and PLL1 still generates a frequency of F. lo The transmitting local oscillator is then started to generate a frequency of F lo1 The receiving local oscillator, F sig -F lo1 =F if , the MCU of the RF transceiver chip reads the address bit of switch state 3 in the memory, and the switch state at this time is switch state 3.

[0083] Step 5: Based on the signal output by the mixer of the transmitting link, the chip determines whether the spectrum of the transmitting link is extended, causing the adjacent channel leakage ratio (ACLR) to deteriorate. If the ACLR value is not lower than the threshold value Th, step 6 is executed; if the ACLR value is lower than the threshold value, the local oscillator of the receiving link is turned off in the transmitting time slot, and the MCU of the RF transceiver chip reads the address bit of switch state 4 in the memory. At this time, the switch state is switch state 4.

[0084] Step 6: When the received signal is mixed to F if , the DC is filtered out by the baseband filter. At this time, the self-mixing of the local oscillator signal and the strong interference signal is eliminated. The next step is to enter the temperature judgment unit. According to the temperature displayed by the temperature sensor at this time, the chip determines whether the temperature has changed. If the temperature remains unchanged, the whole process ends; if the temperature changes, T is updated to the temperature of the chip at this time, and it is re-judged whether there is a DC offset in the receiving link, and the process is cyclic.

[0085] The above process of the present application is described below through two specific embodiments.

[0086] Embodiment 1: Only the transmission mixing frequency self-leakage based on Figure 5 Corresponding to the above process, the signal processing method of this embodiment includes: Same as steps 1 and 2 above; Step 3: According to the digital signal processing of the baseband, the chip determines that a DC offset occurs in the receiving link, and turns off the local oscillator of the transmitting link in the receiving time slot. The MCU of the RF transceiver chip reads the address bit of switch state 2 in the memory. At this time, the switch state is switch state 2; Step 4: Based on the baseband digital signal processing, the chip determines that the DC offset has been eliminated. Then, based on the temperature displayed by the temperature sensor at this time, the chip determines whether the temperature has changed. If the temperature remains unchanged, the entire process ends; if the temperature changes, T is updated to the temperature of the chip at this time, and jumps back to the first judgment unit to loop the process.

[0087] Embodiment 2: Simultaneous existence of transmission mixing self-leakage, local oscillator signal self-mixing and strong interference signal self-mixing based on Figure 5 Corresponding to the above process, the signal processing method of this embodiment includes: Same as steps 1 and 2 above; Step 3: According to the digital signal processing of the baseband, the chip determines that a DC offset occurs in the receiving link, and turns off the local oscillator of the transmitting link in the receiving time slot. The MCU of the RF transceiver chip reads the address bit of switch state 2 in the memory. At this time, the switch state is switch state 2; Step 4: According to the baseband digital signal processing, the chip determines that the DC offset has not been eliminated. The mixer of the RF transceiver chip receiving link uses the baseband frequency shifting function, and PLL1 still generates a frequency of F lo The transmitting local oscillator is then started to generate a frequency of F lo1 The receiving local oscillator, F sig -F lo1 =F if , the MCU of the RF transceiver chip reads the address bit of switch state 3 in the memory, and the switch state at this time is switch state 3; Step 5: Based on the signal output by the mixer of the transmitting link, the chip determines whether the spectrum of the transmitting link is extended, causing the ACLR value to deteriorate. If the ACLR value is not lower than the threshold value Th, step 6 is executed; if it is lower than the threshold value Th, the local oscillator of the receiving link is turned off in the transmitting time slot, and the MCU of the RF transceiver chip reads the address bit of switch state 4 in the memory. At this time, the switch state is switch state 4; Step 6: When the received signal is mixed to F if , the DC is filtered out through the baseband filter. At this time, the self-mixing of the local oscillator signal and the strong interference signal is eliminated, and the next step is to enter the temperature judgment unit. According to the temperature displayed by the temperature sensor at this time, the chip determines whether the temperature has changed. If the temperature remains unchanged, the whole process ends; if the temperature changes, T is updated to the temperature of the chip at this time, and jumps back to the first judgment unit to loop the process.

[0088] The RF transceiver chip is responsible for high-speed conversion between digital and analog signals of 5G base stations and is a key component in 5G network equipment. In the embodiment of the present application, by configuring multiple states of PLL for the RF transceiver chip, the influence of local oscillator offset is reduced or eliminated by switching the state of PLL. The above method occupies fewer resources and is more conducive to the integration of the whole machine.

[0089] See also Figure 6 , Figure 6 is a structural diagram of a signal processing device provided in an embodiment of the present application, such as Figure 6 As shown, the signal processing device 600 includes: The start module 601 is used to start the first state of the phase-locked loop PLL in the radio frequency transceiver chip, wherein the radio frequency transceiver chip is a radio frequency transceiver chip in a time division duplex TDD transceiver system, the radio frequency transceiver chip includes a transmitting link and a receiving link, the PLL is connected to the local oscillator of the transmitting link and to the local oscillator of the receiving link, and the first state is one of at least two states of the PLL; A first acquisition module 602, configured to acquire a first DC offset of a signal of the receiving link; The switching module 603 is used to switch the state of the PLL from the first state to a target state when the first DC offset is greater than or equal to a preset value, wherein the target state is one of the at least two states except the first state, and in the target state, the DC offset of the signal of the receiving link is less than the preset value.

[0090] Optionally, when the first DC offset is greater than or equal to a preset value, the switching module includes: a switching submodule, configured to switch the state of the PLL from the first state to a second state of the at least two states in a receiving time slot when the first DC offset is greater than or equal to a preset value, wherein the PLL generates local oscillator signals with the same frequency for the transmitting link and the receiving link in the first state, and the second state is a state of interrupting the transmission of the local oscillator signal of the transmitting link; An acquisition submodule, used for acquiring a second DC offset of the signal of the receiving link; A determination submodule is used to determine a target state of the PLL according to the second DC offset.

[0091] Optionally, the determining submodule includes: a first switching unit, configured to switch the state of the PLL from the second state to a third state of the at least two states when the second DC offset is greater than or equal to the preset value, wherein the PLL generates a first local oscillator signal for the transmitting link and a second local oscillator signal for the receiving link, and the first local oscillator signal and the second local oscillator signal have different frequencies; The processing unit is used to filter the DC signal of the receiving link through a baseband filter until the DC signal offset of the receiving link is less than the preset value.

[0092] Optionally, the determining submodule further includes: An acquisition unit, configured to acquire an adjacent channel leakage ratio ACLR of the transmission link; A second switching unit, configured to switch the state of the PLL from the third state to a fourth state of the at least two states in a transmission time slot when the ACLR is less than a preset threshold value, wherein in the fourth state, the PLL interrupts transmission of the local oscillator signal of the receiving link; The processing unit is specifically used for: When the ACLR is greater than or equal to the preset threshold value, the DC signal of the receiving link is filtered by a baseband filter until the DC signal offset of the receiving link is less than the preset value.

[0093] Optionally, the determining submodule is specifically used for: When the second DC offset is less than the preset value, the second state is determined as the target state of the PLL.

[0094] Optionally, the device further comprises: A second acquisition module, used to acquire a first temperature value in the radio frequency transceiver chip; The device also includes: A third acquisition module, used to acquire a second temperature value in the radio frequency transceiver chip; An updating module is used to update the temperature of the RF transceiver chip from the first temperature value to the second temperature value when the first DC offset is less than the preset value and the difference between the second temperature value and the first temperature value is greater than a preset threshold, and detect the DC offset of the signal of the receiving link based on the updated temperature value.

[0095] Optionally, the local oscillator of the transmitting link is connected to the reference signal transmitting device through the PLL, and the local oscillator of the receiving link is connected to the PLL through a first switch; The local oscillator of the transmission link is connected to the mixer of the transmission link through a second switch; The local oscillator of the receiving link is connected to the mixer of the receiving link through a third switch; In the first state, the first switch, the second switch and the third switch are all in a closed state; In the second state of the PLL, the first switch and the third switch are both in a closed state, and the second switch is in an open state.

[0096] Optionally, the PLL includes a first PLL and a second PLL; The first end of the first PLL and the first end of the second PLL are connected to the reference signal transmitting device, and the frequencies of the signals output by the first PLL and the second PLL are different; The second end of the first PLL is connected to the local oscillator of the transmitting link, the second end of the second PLL is connected to the local oscillator of the receiving link through a fourth switch, and the second end of the first PLL and the second end of the second PLL are connected through the first switch; In the first state, the first switch, the second switch and the third switch are all in a closed state, and the fourth switch is in an open state; In the second state of the PLL, the first switch and the third switch are both in a closed state, and the second switch and the fourth switch are in an open state; In a third state of the PLL, the first switch is in an open state, and the second switch, the third switch and the fourth switch are all in a closed state; In a fourth state of the PLL, the first switch and the third switch are both in an open state, and the second switch and the fourth switch are both in a closed state.

[0097] The signal processing device can realize Figure 2 The various processes implemented in the method embodiment can achieve the same technical effect, and to avoid repetition, they will not be described again here.

[0098] It should be noted that the electronic device provided in the embodiment of the present application is a device capable of executing the above-mentioned signal processing method, and all implementations in the above-mentioned signal processing method embodiment are applicable to the electronic device and can achieve the same or similar beneficial effects. To avoid repeated description, this embodiment will not be described in detail.

[0099] The present application also provides a communication device. Since the principle of solving the problem by the communication device is similar to the signal processing method in the present application, the implementation of the communication device can refer to the implementation of the method, and the repeated parts will not be repeated. Figure 7As shown, the communication device of the embodiment of the present application includes: a processor 700, which is used to read the program in the memory 720 and execute the following process: Turning on a first state of a phase-locked loop (PLL) in a radio frequency transceiver chip, wherein the radio frequency transceiver chip is a radio frequency transceiver chip in a time division duplex (TDD) transceiver system, the radio frequency transceiver chip includes a transmitting link and a receiving link, the PLL is connected to a local oscillator of the transmitting link and to a local oscillator of the receiving link, and the first state is one of at least two states of the PLL; Acquire a first DC offset of a signal of the receiving link; When the first DC offset is greater than or equal to a preset value, the state of the PLL is switched from the first state to a target state, wherein the target state is one of the at least two states except the first state, and in the target state, the DC offset of the signal of the receiving link is less than the preset value.

[0100] Among them, Figure 7 In the embodiment, the bus architecture may include any number of interconnected buses and bridges, specifically linking together various circuits of one or more processors represented by processor 700 and memory represented by memory 720. The bus architecture may also link together various other circuits such as peripherals, voltage regulators, and power management circuits, which are well known in the art and are therefore not further described herein. The bus interface provides an interface. The transceiver 710 may be a plurality of components, namely, a transmitter and a transceiver, providing a unit for communicating with various other devices on a transmission medium. The processor 700 is responsible for managing the bus architecture and general processing, and the memory 720 may store data used by the processor 700 when performing operations.

[0101] Optionally, the processor 700 is further configured to read a program in the memory 720 to execute the step of switching the state of the PLL from the first state to a target state when the first DC offset is greater than or equal to a preset value, including: In a case where the first DC offset is greater than or equal to a preset value, switching the state of the PLL from the first state to a second state of the at least two states in a receiving time slot, wherein the PLL generates local oscillator signals with the same frequency for the transmitting link and the receiving link in the first state, and the second state is a state of interrupting the transmission of the local oscillator signal of the transmitting link; Acquire a second DC offset of the signal of the receiving link; A target state of the PLL is determined according to the second DC offset.

[0102] Optionally, the processor 700 is further configured to read a program in the memory 720 to execute the step of determining the target state of the PLL according to the second DC offset, including: When the second DC offset is greater than or equal to the preset value, switching the state of the PLL from the second state to a third state of the at least two states, wherein the PLL generates a first local oscillator signal for the transmitting link and a second local oscillator signal for the receiving link, and the first local oscillator signal and the second local oscillator signal have different frequencies; The DC signal of the receiving link is filtered by a baseband filter until the DC signal offset of the receiving link is less than the preset value.

[0103] Optionally, the processor 700 is further configured to read a program in the memory 720 and execute the following steps: Acquire an adjacent channel leakage ratio (ACLR) of the transmission link; When the ACLR is less than a preset threshold value, switching the state of the PLL from the third state to a fourth state of the at least two states in a transmission time slot, wherein in the fourth state, the PLL interrupts transmission of the local oscillator signal of the receiving link; The filtering process of the DC signal of the receiving link by the baseband filter until the DC signal offset of the receiving link is less than the preset value includes: When the ACLR is greater than or equal to the preset threshold value, the DC signal of the receiving link is filtered by a baseband filter until the DC signal offset of the receiving link is less than the preset value.

[0104] Optionally, the processor 700 is further configured to read a program in the memory 720 to execute the step of determining the target state of the PLL according to the second DC offset, including: When the second DC offset is less than the preset value, the second state is determined as the target state of the PLL.

[0105] Optionally, the processor 700 is further configured to read a program in the memory 720 and execute the following steps: Acquire a first temperature value in the radio frequency transceiver chip; Acquiring a second temperature value in the radio frequency transceiver chip; When the first DC offset is less than the preset value and the difference between the second temperature value and the first temperature value is greater than a preset threshold, the temperature of the RF transceiver chip is updated from the first temperature value to the second temperature value, and the DC offset of the signal of the receiving link is detected based on the updated temperature value.

[0106] Optionally, the local oscillator of the transmitting link is connected to the reference signal transmitting device through the PLL, and the local oscillator of the receiving link is connected to the PLL through a first switch; The local oscillator of the transmission link is connected to the mixer of the transmission link through a second switch; The local oscillator of the receiving link is connected to the mixer of the receiving link through a third switch; In the first state, the first switch, the second switch and the third switch are all in a closed state; In the second state of the PLL, the first switch and the third switch are both in a closed state, and the second switch is in an open state.

[0107] Optionally, the PLL includes a first PLL and a second PLL; The first end of the first PLL and the first end of the second PLL are connected to the reference signal transmitting device, and the frequencies of the signals output by the first PLL and the second PLL are different; The second end of the first PLL is connected to the local oscillator of the transmitting link, the second end of the second PLL is connected to the local oscillator of the receiving link through a fourth switch, and the second end of the first PLL and the second end of the second PLL are connected through the first switch; In the first state, the first switch, the second switch and the third switch are all in a closed state, and the fourth switch is in an open state; In the second state of the PLL, the first switch and the third switch are both in a closed state, and the second switch and the fourth switch are in an open state; In a third state of the PLL, the first switch is in an open state, and the second switch, the third switch and the fourth switch are all in a closed state; In a fourth state of the PLL, the first switch and the third switch are both in an open state, and the second switch and the fourth switch are both in a closed state.

[0108] The communication device provided in the embodiment of the present application can execute the above method embodiment, and its implementation principle and technical effect are similar, so this embodiment will not be repeated here.

[0109] The embodiment of the present application also provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, each process of the above-mentioned signal processing method embodiment is implemented, and the same technical effect can be achieved. To avoid repetition, it is not repeated here. The computer-readable storage medium is, for example, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0110] The present application also provides a computer program product, including computer instructions, which, when executed by a processor, implement the above Figure 2 The various processes of the method embodiment shown can achieve the same technical effect, and will not be described again here to avoid repetition.

[0111] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0112] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, a magnetic disk, or an optical disk), and includes a number of instructions for a terminal (which can be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) to execute the methods described in each embodiment of the present application.

[0113] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims

1. A signal processing method, characterized in that: include: Turning on a first state of a phase-locked loop (PLL) in a radio frequency transceiver chip, wherein the radio frequency transceiver chip is a radio frequency transceiver chip in a time division duplex (TDD) transceiver system, the radio frequency transceiver chip includes a transmitting link and a receiving link, the PLL is connected to a local oscillator of the transmitting link and to a local oscillator of the receiving link, and the first state is one of at least two states of the PLL; Acquire a first DC offset of a signal of the receiving link; When the first DC offset is greater than or equal to a preset value, the state of the PLL is switched from the first state to a target state, wherein the target state is one of the at least two states except the first state, and in the target state, the DC offset of the signal of the receiving link is less than the preset value.

2. The method according to claim 1, characterized in that The step of switching the state of the PLL from the first state to a target state when the first DC offset is greater than or equal to a preset value includes: In a case where the first DC offset is greater than or equal to a preset value, switching the state of the PLL from the first state to a second state of the at least two states in a receiving time slot, wherein the PLL generates local oscillator signals with the same frequency for the transmitting link and the receiving link in the first state, and the second state is a state of interrupting the transmission of the local oscillator signal of the transmitting link; Acquire a second DC offset of the signal of the receiving link; A target state of the PLL is determined according to the second DC offset.

3. The method according to claim 2, characterized in that The step of determining a target state of the PLL according to the second DC offset comprises: When the second DC offset is greater than or equal to the preset value, switching the state of the PLL from the second state to a third state of the at least two states, wherein the PLL generates a first local oscillator signal for the transmitting link and a second local oscillator signal for the receiving link, and the first local oscillator signal and the second local oscillator signal have different frequencies; The DC signal of the receiving link is filtered by a baseband filter until the DC signal offset of the receiving link is less than the preset value.

4. The method according to claim 3, characterized in that After switching the state of the PLL from the second state to a third state of the at least two states, the method further includes: Acquire an adjacent channel leakage ratio (ACLR) of the transmission link; When the ACLR is less than a preset threshold value, switching the state of the PLL from the third state to a fourth state of the at least two states in a transmission time slot, wherein in the fourth state, the PLL interrupts transmission of the local oscillator signal of the receiving link; The filtering process of the DC signal of the receiving link by the baseband filter until the DC signal offset of the receiving link is less than the preset value includes: When the ACLR is greater than or equal to the preset threshold value, the DC signal of the receiving link is filtered by a baseband filter until the DC signal offset of the receiving link is less than the preset value.

5. The method according to claim 2, characterized in that: The step of determining a target state of the PLL according to the second DC offset comprises: When the second DC offset is less than the preset value, the second state is determined as the target state of the PLL.

6. The method according to any one of claims 1 to 5, characterized in that Before starting the first state of the PLL in the radio frequency transceiver chip, the method further includes: Acquire a first temperature value in the radio frequency transceiver chip; After the first state of the PLL in the radio frequency transceiver chip is turned on, the method further includes: Acquiring a second temperature value in the radio frequency transceiver chip; When the first DC offset is less than the preset value and the difference between the second temperature value and the first temperature value is greater than a preset threshold, the temperature of the RF transceiver chip is updated from the first temperature value to the second temperature value, and the DC offset of the signal of the receiving link is detected based on the updated temperature value.

7. The method according to any one of claims 1 to 5, characterized in that The local oscillator of the transmitting link is connected to the reference signal transmitting device through the PLL, and the local oscillator of the receiving link is connected to the PLL through the first switch; The local oscillator of the transmission link is connected to the mixer of the transmission link through a second switch; The local oscillator of the receiving link is connected to the mixer of the receiving link through a third switch; In the first state, the first switch, the second switch and the third switch are all in a closed state; In the second state of the PLL, the first switch and the third switch are both in a closed state, and the second switch is in an open state.

8. The method according to claim 7, characterized in that The PLL includes a first PLL and a second PLL; The first end of the first PLL and the first end of the second PLL are connected to the reference signal transmitting device, and the frequencies of the signals output by the first PLL and the second PLL are different; The second end of the first PLL is connected to the local oscillator of the transmitting link, the second end of the second PLL is connected to the local oscillator of the receiving link through a fourth switch, and the second end of the first PLL and the second end of the second PLL are connected through the first switch; In the first state, the first switch, the second switch and the third switch are all in a closed state, and the fourth switch is in an open state; In the second state of the PLL, the first switch and the third switch are both in a closed state, and the second switch and the fourth switch are in an open state; In a third state of the PLL, the first switch is in an open state, and the second switch, the third switch and the fourth switch are all in a closed state; In a fourth state of the PLL, the first switch and the third switch are both in an open state, and the second switch and the fourth switch are both in a closed state.

9. A signal processing device, characterized in that: include: An enabling module, used to enable a first state of a phase-locked loop (PLL) in a radio frequency transceiver chip, wherein the radio frequency transceiver chip is a radio frequency transceiver chip in a time division duplex (TDD) transceiver system, the radio frequency transceiver chip includes a transmitting link and a receiving link, the PLL is connected to a local oscillator of the transmitting link and to a local oscillator of the receiving link, and the first state is one of at least two states of the PLL; A first acquisition module, used to acquire a first DC offset of a signal of the receiving link; a switching module, configured to switch the state of the PLL from the first state to a target state when the first DC offset is greater than or equal to a preset value, wherein the target state is one of the at least two states except the first state, and in the target state, the DC offset of the signal of the receiving link is less than the preset value.

10. An electronic device, characterized in that: include: A processor, a memory, and a program stored in the memory and executable on the processor, wherein when the program is executed by the processor, the steps of the signal processing method according to any one of claims 1 to 8 are implemented.

11. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the signal processing method according to any one of claims 1 to 8 are implemented.

12. A computer program product, characterized in that The method comprises computer instructions, which, when executed by a processor, implement the steps of the signal processing method according to any one of claims 1 to 8.

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