A gateway core circuit supporting expansion

Abstract

The present invention discloses a gateway core circuit supporting expansion, belonging to the technical field of gateways for Internet of Things devices. A gateway core circuit supporting expansion includes a power management circuit, a DC isolation circuit, a minimum system circuit, a Flash circuit, a USB circuit, a USB-to-serial port circuit, and an expansion interface; the present invention converts 5V voltage into 3.3V, 1.5V, and 0.9V voltages respectively by setting a power management circuit, and realizes the data processing function of the gateway by setting the DC isolation circuit, the minimum system circuit, the Flash circuit, the USB circuit, and the USB-to-serial port circuit to cooperate with each other, and realizes the gateway with different peripheral communication interface circuits by setting the minimum system circuit and the expansion interface to cooperate with each other, so as to adapt to data collection and server data exchange in different scenes, thereby achieving real-time management of on-site equipment.

Description

Technical Field

[0001] The present invention relates to the technical field of Internet of Things device gateways, and in particular to a gateway core circuit supporting expansion. Background Art

[0002] A gateway, also known as an internetwork connector or protocol converter, is a complex device that implements network interconnection above the network layer. It is only used for interconnecting two networks with different high-level protocols. Gateways can be used for both wide area network interconnection and local area network interconnection. The main function of a gateway is to convert and translate between two systems with different communication protocols, data formats or languages, or even completely different architectures. Unlike a bridge that simply conveys information, a gateway will repackage the received information to meet the needs of the destination system.

[0003] The traditional Internet of Things device gateway has a single network connection method, and the communication connection method with the industrial field controller is relatively simple, and the device gateway has great limitations when used. Summary of the invention

[0004] The purpose of the present invention is to solve the problems in the prior art and to propose a gateway core circuit that supports expansion.

[0005] In order to achieve the above object, the present invention adopts the following technical solutions:

[0006] It includes a power management circuit, a DC isolation circuit, a minimum system circuit, a Flash circuit, a USB circuit, a USB-to-serial port circuit, and an expansion interface; the power management circuit is electrically connected to the DC isolation circuit, the minimum system circuit, the Flash circuit, the USB circuit, the USB-to-serial port circuit, and the expansion interface respectively, and the minimum system circuit is electrically connected to the Flash circuit, the USB circuit, the USB-to-serial port circuit, and the expansion interface; the expansion interface includes: a connector H1 and a connector H2, and the connectors H1 and H2 are electrically connected to the minimum system circuit and the power management circuit.

[0007] Preferably, the power management circuit includes: resistor R4, resistor R5, resistor R6, resistor R7, resistor R8, resistor R9, resistor R10, resistor R11, resistor R12, capacitor C5, capacitor C6, capacitor C7, capacitor C8, capacitor C9, capacitor C10, capacitor C11, capacitor C12, capacitor C13, capacitor C14, capacitor C15, capacitor C16, capacitor C17, capacitor C18, capacitor C19, inductor L1, inductor L2, inductor L3, chip U1, chip U2; pin 16 of the chip U1 is respectively connected to one end of the capacitor C5 and the DC isolation The circuit is electrically connected; Pin 7, Pin 10, and Pin 19 of the chip U1 are electrically connected to one end of capacitor C9, one end of capacitor C10, one end of capacitor C11, and a DC isolation circuit, respectively; Pin 9 of the chip U1 is electrically connected to one end of resistor R6; Pin 8 of the chip U1 is electrically connected to one end of resistor R8; Pin 18 of the chip U1 is electrically connected to one end of resistor R9; Pin 11 of the chip U1 is electrically connected to one end of inductor L1; Pin 14 of the chip U1 is electrically connected to the other end of capacitor C6, the other end of resistor R4, and one end of resistor R5, respectively; Pin 6 of chip U1 is electrically connected to one end of inductor L2; Pin 3 of chip U1 is electrically connected to the other end of capacitor C12, the other end of resistor R7, and one end of resistor R10 respectively; Pin 20 of chip U1 is electrically connected to one end of inductor L3; Pin 2 of chip U1 is electrically connected to the other end of capacitor C15, the other end of resistor R11, and one end of resistor R12 respectively; Pin 3 of chip U2 is electrically connected to one end of capacitor C18 and one end of capacitor C18 respectively; Pin 2 of chip U2 is electrically connected to the minimum system circuit and one end of capacitor C19 respectively; The other end of the inductor L1 is electrically connected to one end of the capacitor C6, one end of the resistor R4, one end of the capacitor C7, and one end of the capacitor C8; the other end of the inductor L2 is electrically connected to one end of the capacitor C12, one end of the resistor R7, one end of the capacitor C13, and one end of the capacitor C14; the other end of the inductor L3 is electrically connected to one end of the capacitor C15, one end of the resistor R11, one end of the capacitor C16, and one end of the capacitor C17; the other end of the resistor R8 and the other end of the resistor R9 are electrically connected to one end of the capacitor C8; the other end of the resistor R6 is electrically connected to the DC isolation circuit;The other end of the capacitor C5, the other end of the capacitor C9, the other end of the capacitor C10, the other end of the capacitor C11, the pin 12 of the chip U1, the pin 13 of the chip U1, the pin 5 of the chip U1, the pin 4 of the chip U1, the pin 1 of the chip U1, the pin 15 of the chip U1, the pin 17 of the chip U1, the pin 21 of the chip U1, the other end of the resistor R5, the other end of the capacitor C7, the other end of the capacitor C8, the other end of the resistor R10, the other end of the capacitor C13, the other end of the capacitor C14, the other end of the resistor R12, the other end of the capacitor C16, the other end of the capacitor C17, the other end of the capacitor C18, the other end of the capacitor C19, and the pin 1 of the chip U2 are grounded. ;

[0008] Preferably, the DC isolation circuit includes: a resistor R1, a resistor R21, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C47, a capacitor C48, a capacitor C49, and a capacitor C50; one end of the resistor R1 is electrically connected to one end of the capacitor C1, one end of the capacitor C2, and a USB circuit; the other end of the resistor R1 is electrically connected to one end of the capacitor C3, one end of the capacitor C4, and a power management circuit; one end of the resistor R21 is electrically connected to one end of the capacitor C47, one end of the capacitor C48, and a USB circuit; the other end of the resistor R21 is electrically connected to one end of the capacitor C49, one end of the capacitor C50, and a power management circuit; the other end of the capacitor C1, the other end of the capacitor C2, the other end of the capacitor C3, the other end of the capacitor C4, the other end of the capacitor C47, the other end of the capacitor C48, the other end of the capacitor C49, and the other end of the capacitor C50 are grounded.

[0009] Preferably, the minimum system circuit includes: a power supply filter circuit, a reset circuit, a crystal oscillator circuit, and a burning button circuit.

[0010] Preferably, the Flash circuit includes: a chip U4, a resistor R25, a resistor R26, a resistor R27, a resistor R28, a resistor R29, a resistor R30, a resistor R31, and a capacitor C52; a pin 1 of the chip U4 is electrically connected to the minimum system circuit and one end of the resistor R25; a pin 2 of the chip U4 is electrically connected to the minimum system circuit; a pin 3 of the chip U4 is electrically connected to the minimum system circuit and one end of the resistor R26; a pin 4 and a pin 9 of the chip U4 are grounded; a pin 5 of the chip U4 is electrically connected to the minimum system circuit and the electrical One end of the resistor R29 and one end of the resistor R30 are electrically connected; the pin 6 of the chip U4 is electrically connected to the minimum system circuit; the pin 7 of the chip U4 is electrically connected to the minimum system circuit and one end of the resistor R27; the pin 8 of the chip U4 is electrically connected to the power management circuit and one end of the capacitor C52; the other end of the resistor R25, the other end of the resistor R26, the other end of the resistor R27, the other end of the resistor R28, and the other end of the resistor R29 are electrically connected to the power management circuit; the other end of the resistor R30 and the other end of the resistor R31 are grounded.

[0011] Preferably, the USB circuit includes: a connector USB1, a resistor R2, and a resistor R3; pin 4 of the connector USB1 is electrically connected to one end of the resistor R2; pin 10 of the connector USB1 is electrically connected to one end of the resistor R3; pin 5, pin 6, pin 7, and pin 8 of the connector USB1 are electrically connected to the minimum system circuit; pin 2 and pin 11 of the connector USB1 are connected to a DC isolation circuit; pin 1, pin 12, pin 13, pin 14 of the connector USB1, the other end of the resistor R2, and the other end of the resistor R3 are grounded.

[0012] Preferably, the USB to serial port circuit includes: a connector USB2, a resistor R20, a resistor R22, a chip U3, and a capacitor C51; pin 4 of the connector USB2 is electrically connected to one end of the resistor R20; pin 10 of the connector USB2 is electrically connected to one end of the resistor R22; pin 5, pin 6, pin 7, and pin 8 of the connector USB2 are electrically connected to pin 1 and pin 2 of the chip U3; pin 2 and pin 11 of the connector USB2 are connected to a DC isolation circuit; pin 1, pin 12, pin 13, pin 14 of the connector USB2, the other end of the resistor R20, and the other end of the resistor R22 are grounded; pin 3 of the chip U3 is grounded; pin 7 of the chip U3 is electrically connected to one end of the capacitor C51 and a power management circuit; pin 8 and pin 9 of the chip U3 are electrically connected to a minimum system circuit; pin 10 of the chip U3 is electrically connected to a power management circuit; the other end of the capacitor C51 is grounded.

[0013] Furthermore, the power supply filter circuit includes: chip U5, resistor R14, resistor R15, resistor R18, resistor R32, capacitor C20, Schottky diode D6, capacitor C21, capacitor C22, capacitor C23, capacitor C24, capacitor C25, capacitor C26, capacitor C27, capacitor C28, capacitor C29, capacitor C30, capacitor C31, capacitor C32, capacitor C33, capacitor C34, capacitor C35, capacitor C36, capacitor C37, capacitor C38, capacitor C39, capacitor C40, capacitor C41; the chip U5 pin 1 to pin 8, pin 10 to pin 18, pin 31 to pin 33, pin 35 to pin 45, pin 52 to pin 64, pin 67 to pin 78, pin 82, pin 84 to pin 86, pin 118 to pin 127 are electrically connected to the expansion interface; pin 9 of the chip U5 is electrically connected to one end of the resistor R14; pin 19 of the chip U5 is electrically connected to one end of the resistor R15; pin 47 of the chip U5 is electrically connected to one end of the resistor R18; pin 29 of the chip U5 is electrically connected to the negative electrode of the Schottky diode D6; pin 34, pin 66, pin 77, pin 83, and pin 28 of the chip U5 are electrically connected to one end of the capacitor C24, one end of the capacitor C25, one end of the capacitor C26, one end of the capacitor C27, one end of the capacitor C28, and the power management circuit; the chip Pin 46, pin 51, pin 81, pin 17, and pin 16 of U5 are electrically connected to one end of capacitor C30, one end of capacitor C31, one end of capacitor C32, one end of capacitor C33, one end of capacitor C34, and a power management circuit; Pin 91 of the chip U5 is electrically connected to one end of resistor R32; Pin 48 and pin 49 of the chip U5 are electrically connected to one end of capacitor C21, one end of capacitor C22, and a power management circuit; Pin 28, pin 20, pin 26, pin 50, pin 65, and pin 107 of the chip U5 are electrically connected to one end of capacitor C23, one end of capacitor C35, one end of capacitor C36, one end of capacitor C37, one end of capacitor C38, and a capacitor One end of C39 is electrically connected; Pin 30 of the chip U5 is electrically connected to one end of capacitor C29; Pin 89 of the chip U5 is electrically connected to the power management circuit and one end of capacitor C40; Pin 97 of the chip U5 is electrically connected to the power management circuit and one end of capacitor C41; Pins 22 to 25 of the chip U5 are electrically connected to the crystal oscillator circuit; Pin 27 of the chip U5 is electrically connected to the reset circuit; Pin 17 of the chip U5 is electrically connected to the Flash circuit and the burning button circuit; The other end of the capacitor C40 and the other end of the capacitor C41 are electrically connected to one end of the resistor R32; The anode of the Schottky diode D6 is electrically connected to one end of the capacitor C20 and the power management circuit;The other end of the capacitor C20, the other end of the capacitor C24, the other end of the capacitor C25, the other end of the capacitor C26, the other end of the capacitor C27, the other end of the capacitor C28, the other end of the capacitor C30, the other end of the capacitor C31, the other end of the capacitor C32, the other end of the capacitor C33, the other end of the capacitor C34, the other end of the resistor R32, the pin 129 of the chip U5, the other end of the capacitor C21, the other end of the capacitor C22, the other end of the capacitor C23, the other end of the capacitor C35, the other end of the capacitor C36, the other end of the capacitor C37, the other end of the capacitor C38, the other end of the capacitor C39, and the other end of the capacitor C29 are grounded. ;

[0014] Furthermore, the reset circuit includes: a resistor R16, a capacitor C44, and a switch KEY1; a pin 4 of the switch KEY1 is electrically connected to one end of the resistor R16, one end of the capacitor C44, and a power supply filter circuit; the other end of the resistor R16 is electrically connected to a power supply management circuit; the other end of the capacitor C44 and a pin 1 of the switch KEY1 are grounded.

[0015] Further, the crystal oscillator circuit includes: a crystal oscillator X1, a crystal oscillator X2, a resistor R19, a capacitor C42, a capacitor C43, a capacitor C45, and a capacitor C46; pin 3 of the crystal oscillator X1 is electrically connected to a power supply filter circuit and one end of the capacitor C42; pin 1 of the crystal oscillator X1 is electrically connected to a power supply filter circuit and one end of the capacitor C43; one end of the crystal oscillator X2 is electrically connected to a power supply filter circuit, one end of the capacitor C45, and one end of the resistor R19; the other end of the crystal oscillator X2 is electrically connected to a power supply filter circuit, one end of the capacitor C46, ​​and the other end of the resistor R19; pin 2, pin 4, the other end of the capacitor C42, the other end of the capacitor C43, the other end of the capacitor C45, and the other end of the capacitor C46 of the crystal oscillator X1 are grounded.

[0016] Furthermore, the burning key circuit includes: a resistor R17 and a switch KEY2; a pin 1 of the switch KEY2 is electrically connected to one end of the resistor R17; the other end of the resistor R17 is electrically connected to a power supply filter circuit; and a pin 4 of the switch KEY2 is grounded.

[0017] Compared with the prior art, the present invention provides a gateway core circuit that supports expansion, which has the following beneficial effects:

[0018] 1. The core circuit of the gateway that supports expansion converts 5V voltage into 3.3V, 1.5V, and 0.9V voltages respectively by setting a power management circuit, and sets a DC isolation circuit, a minimum system circuit, a Flash circuit, a USB circuit, and a USB-to-serial port circuit to cooperate with each other to realize the data processing function of the gateway.

[0019] 2. The core circuit of the gateway that supports expansion can realize the matching of the gateway with different peripheral communication interface circuits by setting the mutual cooperation of the minimum system circuit and the expansion interface, adapt to data collection and server data exchange in different scenarios, and thus achieve real-time management of on-site equipment.

[0020] The parts not involved in the core circuit of the gateway that supports expansion are the same as the existing technology or can be implemented by existing technology. The present invention integrates multi-functional modules such as power management, DC isolation, minimum system, Flash storage, USB and USB to serial port, and designs expansion interfaces, which significantly enhances the expandability and connection diversity of the gateway. It is suitable for a wider range of Internet of Things and industrial field controller communication scenarios, and improves the flexibility and compatibility of equipment use. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 is a system block diagram of the present invention;

[0022] Figure 2 is a circuit schematic diagram of the power management circuit of the present invention;

[0023] Figure 3 A circuit schematic diagram of a DC isolation circuit of the present invention;

[0024] Figure 4 is a circuit schematic diagram of the minimum system circuit of the present invention;

[0025] Figure 5 It is a circuit principle diagram of the Flash circuit of the present invention;

[0026] Figure 6 is a circuit schematic diagram of the USB circuit of the present invention;

[0027] Figure 7 The schematic diagram of the USB to serial port circuit of the present invention;

[0028] Figure 8 It is a circuit principle diagram of the expansion interface circuit of the present invention. DETAILED DESCRIPTION

[0029] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments.

[0030] In the description of the present invention, it is necessary to understand that the terms "upper", "lower", "front", "back", "left", "right", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0031] Reference Figure 1 and Figure 8 , including a power management circuit, a DC isolation circuit, a minimum system circuit, a Flash circuit, a USB circuit, a USB-to-serial port circuit, and an expansion interface; the power management circuit is electrically connected to the DC isolation circuit, the minimum system circuit, the Flash circuit, the USB circuit, the USB-to-serial port circuit, and the expansion interface respectively, and the minimum system circuit is electrically connected to the Flash circuit, the USB circuit, the USB-to-serial port circuit, and the expansion interface; the expansion interface includes: connector H1 and connector H2, and connector H1 and connector H2 are electrically connected to the minimum system circuit and the power management circuit.

[0032] In the present invention, by designing a circuit including an expansion interface, the user can easily connect additional functional modules or hardware to the gateway without making major modifications to the core circuit. This design enables the gateway to adapt to the needs of different application scenarios and improves its flexibility and versatility.

[0033] The combination of power management circuit and DC isolation circuit helps to protect the core circuit from external power fluctuation or interference, thereby improving the reliability and stability of the entire system. The DC isolation circuit can also prevent potential problems such as current backflow or short circuit, further enhancing the safety of the circuit.

[0034] By integrating USB circuit and USB to serial port circuit, the core circuit of the gateway can support multiple communication modes, such as USB data transmission, serial port communication, etc., providing users with more communication options, so that the gateway can communicate with other devices flexibly and efficiently;

[0035] Through standardized connectors H1 and H2, the gateway core circuit can be easily integrated and deployed with other systems or devices. This standardized design reduces the complexity and cost of system integration, allowing the gateway to adapt to different application scenarios more quickly.

[0036] In one embodiment, since the core circuit of the gateway that supports expansion adopts a modular design concept, when a functional module fails or needs to be upgraded, the user can simply replace or upgrade the corresponding module without redesigning or reconstructing the entire system, thereby reducing maintenance costs while improving the maintainability and upgradeability of the system.

[0037] Reference Figure 2The power management circuit includes: resistor R4 (resistance value is 68kΩ), resistor R5 (resistance value is 15kΩ), resistor R6 (resistance value is 100kΩ), resistor R7 (resistance value is 150kΩ), resistor R8 (resistance value is 100kΩ), resistor R9 (resistance value is 100kΩ), resistor R10 (resistance value is 100kΩ), resistor R11 (resistance value is 4.99kΩ), resistor R12 (resistance value is 10kΩ), capacitor C5 (capacitance value is 1uF), capacitor C6 (capacitance value is 220pF), capacitor C7 (capacitance value is 10uF), capacitor C8 (capacitance value is 100nF), capacitor C9 (capacitance value is 100nF), capacitor C10 (capacitance value is 100kΩ), capacitor C11 (capacitance value is 4.99kΩ), capacitor C12 (capacitance value is 10kΩ), capacitor C13 (capacitance value is 100nF), capacitor C14 (capacitance value is 100nF), capacitor C15 (capacitance value is 100kΩ), capacitor C16 (capacitance value is 220pF), capacitor C17 (capacitance value is 100uF), capacitor C18 (capacitance value is 100nF), capacitor C19 (capacitance value is 100nF), capacitor C20 (capacitance value is 100kΩ), capacitor C21 (capacitance value is 100kΩ), capacitor C22 (capacitance value is 100kΩ), capacitor C23 (capacitance value is 100kΩ), capacitor C24 (capacitance value is 100kΩ), capacitor C25 (capacit Capacitor C9 (capacitance value is 10uF), capacitor C10 (capacitance value is 10uF), capacitor C11 (capacitance value is 10uF), capacitor C12 (capacitance value is 220pF), capacitor C13 (capacitance value is 10uF), capacitor C14 (capacitance value is 100nF), capacitor C15 (capacitance value is 220pF), capacitor C16 (capacitance value is 10uF), capacitor C17 (capacitance value is 100nF), capacitor C18 (capacitance value is 1uF), capacitor C19 (capacitance value is 1uF), inductor (inductance value is 1.5uH), inductor L2 (inductance value is 1.5uH), inductor L3 (inductance value is 1.5uH), chip U1 (model EA3036CQBR), chip U2 (XC6206P182MR); Pin 16 of chip U1 is electrically connected to one end of capacitor C5 and the DC isolation circuit respectively; Pin 7, pin 10, and pin 19 of chip U1 are electrically connected to one end of capacitor C9, one end of capacitor C10, one end of capacitor C11, and the DC isolation circuit respectively; Pin 9 of chip U1 is electrically connected to one end of resistor R6; Pin 8 of chip U1 is electrically connected to one end of resistor R8; Pin 18 of chip U1 is electrically connected to one end of resistor R9; Pin 11 of chip U1 is electrically connected to one end of inductor L1; Pin 14 of chip U1 is electrically connected to the other end of capacitor C6, the other end of resistor R4, and one end of resistor R5 respectively; Pin 6 of chip U1 is electrically connected to one end of inductor L2; Pin 3 of chip U1 is electrically connected to the other end of capacitor C12, the other end of resistor R7, and one end of resistor R10 respectively; Pin 20 of chip U1 is electrically connected to one end of inductor L3; Pin 2 of chip U1 is electrically connected to the other end of capacitor C15, the other end of resistor R11, and one end of resistor R12 respectively; Pin 3 of chip U2 is electrically connected to one end of capacitor C18 and one end of capacitor C19 respectively; Pin 2 of chip U2 is electrically connected to the minimum system circuit, capacitor C 19; the other end of the inductor L1 is electrically connected to one end of the capacitor C6, one end of the resistor R4, one end of the capacitor C7, and one end of the capacitor C8; the other end of the inductor L2 is electrically connected to one end of the capacitor C12, one end of the resistor R7, one end of the capacitor C13, and one end of the capacitor C14; the other end of the inductor L3 is electrically connected to one end of the capacitor C15, one end of the resistor R11, one end of the capacitor C16, and one end of the capacitor C17; the other end of the resistor R8 and the other end of the resistor R9 are electrically connected to one end of the capacitor C8; the other end of the resistor R6 is electrically connected to the DC isolation circuit; the other end of the capacitor C5 and the other end of the capacitor C9 are electrically connected to the DC isolation circuit; end, the other end of capacitor C10, the other end of capacitor C11, pin 12 of chip U1, pin 13 of chip U1, pin 5 of chip U1, pin 4 of chip U1, pin 1 of chip U1, pin 15 of chip U1, pin 17 of chip U1, pin 21 of chip U1, the other end of resistor R5, the other end of capacitor C7, the other end of capacitor C8, the other end of resistor R10, the other end of capacitor C13, the other end of capacitor C14, the other end of resistor R12, the other end of capacitor C16, the other end of capacitor C17, the other end of capacitor C18, the other end of capacitor C19, and pin 1 of chip U2 are grounded. .

[0038] In the present invention, chip U1 and chip U2 have functions such as voltage regulation, overvoltage protection, and current limitation, which further enhance the reliability and stability of the power supply. Specifically, chip U1 and chip U2 use linear regulation or switch regulation technology to achieve efficient voltage conversion. Chip U1 and chip U2 integrate voltage regulators, which can automatically adjust the output voltage according to the input voltage and load conditions to ensure the stability of the output voltage. When the input voltage exceeds the set value, chip U1 and chip U2 can quickly cut off the power supply or reduce the output voltage to prevent circuit damage, thereby protecting subsequent circuits and loads. In the case of excessive load or short circuit, chip U1 and chip U2 can limit the output current to prevent the circuit from overheating or damage. Through precise current detection and control, these chips can ensure that the power supply can operate safely under various load conditions. Chip U1 and chip U2 also have auxiliary functions such as overheat protection, undervoltage protection, and soft start, which further improve the reliability and stability of the power supply, thereby helping to prevent the power supply from being damaged under abnormal conditions and extending the service life of the power supply.

[0039] In the power management circuit, the connection method between the components is very important. The accurate connection method can ensure the correct distribution and transmission of current and voltage in the circuit. In this embodiment, the resistors, capacitors, inductors and chips of the power management circuit together form an efficient and stable power management circuit through accurate connection methods. Through reasonable layout and wiring, electromagnetic interference and noise can be reduced, and the anti-interference ability and stability of the circuit can be improved.

[0040] Specifically, when the external power supply is connected, the power management circuit starts working, and the circuits inside chip U1 and chip U2 start to adjust the voltage and current to ensure the stability of the output voltage and current; the components in the power management circuit (such as resistors, capacitors, inductors, etc.) continuously monitor the changes in the power supply voltage and current to ensure the stable operation of the circuit; when the power supply voltage is too high or too low, or the current is too large, the protection components in the power management circuit (such as resistors, capacitors, etc.) will play a role to limit the current or voltage to prevent circuit damage; the processed power supply is output to other circuit modules through expansion interfaces, etc., to provide stable power support for the entire gateway core circuit.

[0041] Reference Figure 3The DC isolation circuit includes: resistor R1 (resistance value is 0Ω), resistor R21 (resistance value is 0Ω), capacitor C1 (capacitance value is 10uF), capacitor C2 (capacitance value is 100nF), capacitor C3 (capacitance value is 10uF), capacitor C4 (capacitance value is 100nF), capacitor C47 (capacitance value is 10uF), capacitor C48 (capacitance value is 100nF), capacitor C49 (capacitance value is 10uF), capacitor C50 (capacitance value is 100nF); one end of the resistor R1 is respectively connected to one end of the capacitor C1, one end of the capacitor C2, and the USB circuit The resistors R21 are electrically connected to one end of the capacitor C47, one end of the capacitor C48, and the USB circuit; the other end of the resistor R21 is electrically connected to one end of the capacitor C49, one end of the capacitor C50, and the power management circuit; the other end of the capacitor C1, the other end of the capacitor C2, the other end of the capacitor C3, the other end of the capacitor C4, the other end of the capacitor C47, the other end of the capacitor C48, the other end of the capacitor C49, and the other end of the capacitor C50 are grounded.

[0042] In the present invention, the DC isolation circuit realizes electrical isolation between the input power supply and the subsequent circuit through a combination of components such as resistors R1, resistor R21 and capacitors C1, capacitor C2, capacitor C3, capacitor C4, capacitor C47, capacitor C48, capacitor C49, and capacitor C50, thereby preventing the current shock caused by power fluctuation or abnormality from damaging the core circuit, thereby enhancing the security of the entire gateway core circuit;

[0043] Electrical isolation also helps reduce the impact of noise and interference in the power supply line on the core circuit. Especially in complex electromagnetic environments, this isolation measure can significantly improve the circuit's anti-interference ability and ensure the stable operation of the gateway's core circuit.

[0044] The design of the DC isolation circuit in this embodiment enables the gateway core circuit to adapt to different power input environments. By adjusting the component parameters in the isolation circuit, compatibility with power supplies of different voltage levels and current characteristics can be achieved, thereby broadening the application scope of the gateway core circuit; at the same time, in abnormal situations such as unstable power quality or surge voltage, the DC isolation circuit can effectively protect subsequent circuits from damage;

[0045] Furthermore, the DC isolation circuit can reduce the impact of high-frequency noise and ripple in the power supply line on signal quality. By isolating the power supply noise, it can ensure that the signal transmission in the gateway core circuit is clearer and more accurate, thereby improving the performance of the entire system. Reasonable DC isolation circuit design helps to reduce the power consumption of the circuit. By reducing unnecessary energy loss, it can extend the life of the gateway core circuit and improve energy utilization efficiency.

[0046] Furthermore, as an independent module of the gateway core circuit, the DC isolation circuit is convenient for subsequent maintenance and upgrades. When the power supply needs to be replaced or upgraded, only the DC isolation circuit needs to be adjusted accordingly, without the need to make large-scale changes to the entire core circuit. By isolating the DC isolation circuit from the core circuit, power supply-related problems can be more easily located and resolved, thereby improving the maintainability of the system and reducing maintenance costs.

[0047] When power is input to the core circuit of the gateway, it first passes through the DC isolation circuit. The combination of resistors and capacitors in the DC isolation circuit acts as an isolation circuit, isolating the DC component in the power supply from the signal. The isolated signal continues to be transmitted to subsequent circuit modules, such as USB circuits. When the power supply fluctuates or fails, the DC isolation circuit can protect subsequent sensitive components from damage. Due to the existence of the DC isolation circuit, the entire gateway system can operate more stably, reducing system failures caused by external interference.

[0048] Reference Figure 4The minimum system circuit includes: power supply filter circuit, reset circuit, crystal oscillator circuit, and burning button circuit; the power supply filter circuit includes: chip U5 (model T113-S3), resistor R14 (resistance value is 33Ω), resistor R15 (resistance value is 33Ω), resistor R18 (resistance value is 240Ω), resistor R32 (resistance value is 0Ω), capacitor C20 (capacitance value is 2.2uF), Schottky diode D6, capacitor C21 (capacitance value is 100nF), capacitor C22 (capacitance value is 100nF), capacitor C23 (capacitance value is 2.2uF), capacitor C24 (capacitance value is 100nF), capacitor C25 (capacitance value is 100nF), capacitor C26 (capacitance value is 0 Capacitor C27 (capacitance value is 100nF), capacitor C28 (capacitance value is 100nF), capacitor C29 (capacitance value is 2.2uF), capacitor C30 (capacitance value is 100nF), capacitor C31 (capacitance value is 100nF), capacitor C32 (capacitance value is 100nF), capacitor C33 (capacitance value is 100nF), capacitor C34 (capacitance value is 100nF), capacitor C35 (capacitance value is 100nF), capacitor C36 (capacitance value is 100nF), capacitor C37 (capacitance value is 100nF), capacitor C38 (capacitance value is 100nF), capacitor C39 (capacitance value is 100nF), capacitor C40 (capacitance value is 2.2uF), capacitor C41 (capacitance value is 100nF); chip U5 pin 1 to pin 8, pin 10 to pin 18, pin 31 to pin 33, pin 35 to pin 45, pin 52 to pin 64, pin 67 to pin 78, pin 82, pin 84 to pin 86, pin 118 to pin 127 are electrically connected to the expansion interface; chip U5 pin 9 is electrically connected to one end of resistor R14; chip U5 pin 19 is electrically connected to one end of resistor R15; chip U5 pin 47 The pin 29 of the chip U5 is electrically connected to the negative electrode of the Schottky diode D6; the pin 34, pin 66, pin 77, pin 83, and pin 28 of the chip U5 are electrically connected to one end of the capacitor C24, one end of the capacitor C25, one end of the capacitor C26, one end of the capacitor C27, one end of the capacitor C28, and the power management circuit; the pin 46, pin 51, pin 81, pin 17, and pin 16 of the chip U5 are electrically connected to one end of the capacitor C30, one end of the capacitor C31, and the power management circuit. One end of capacitor C32, one end of capacitor C33, one end of capacitor C34, and the power management circuit are electrically connected; pin 91 of chip U5 is electrically connected to one end of resistor R32; pin 48 and pin 49 of chip U5 are electrically connected to one end of capacitor C21, one end of capacitor C22, and the power management circuit; pin 28, pin 20, pin 26, pin 50, pin 65, and pin 107 of chip U5 are electrically connected to one end of capacitor C23, one end of capacitor C35, one end of capacitor C36, and one end of capacitor C37. The chip U5 is electrically connected to one end, one end of capacitor C38, and one end of capacitor C39; the chip U5 pin 30 is electrically connected to one end of capacitor C29; the chip U5 pin 89 is electrically connected to the power management circuit and one end of capacitor C40; the chip U5 pin 97 is electrically connected to the power management circuit and one end of capacitor C41; the chip U5 pins 22 to 25 are electrically connected to the crystal oscillator circuit; the chip U5 pin 27 is electrically connected to the reset circuit; the chip U5 pin 17 is electrically connected to the Flash circuit and the burning button circuit. The other end of capacitor C40 and the other end of capacitor C41 are electrically connected to one end of resistor R32; the anode of Schottky diode D6 is electrically connected to one end of capacitor C20 and the power management circuit; the other end of capacitor C20, the other end of capacitor C24, the other end of capacitor C25, the other end of capacitor C26, the other end of capacitor C27, the other end of capacitor C28, the other end of capacitor C30, the other end of capacitor C31, the other end of capacitor C32, the other end of capacitor C33, the other end of capacitor C34, the other end of resistor R32, pin 129 of chip U5, the other end of capacitor C21, the other end of capacitor C22, the other end of capacitor C23, the other end of capacitor C35, the other end of capacitor C36, the other end of capacitor C37, the other end of capacitor C38, the other end of capacitor C39, and the other end of capacitor C29 are grounded; wherein the reset circuit includes: resistor R16 (resistance value is 4.7kΩ), capacitor C44 (capacitance value is 100nF), switch KEY1. Pin 4 of switch KEY1 is electrically connected to one end of resistor R16, one end of capacitor C44, and power filter circuit; the other end of resistor R16 is electrically connected to power management circuit; the other end of capacitor C44 and pin 1 of switch KEY1 are grounded; wherein the crystal oscillator circuit includes: crystal oscillator X1 (frequency is 24MHz), crystal oscillator X2 (frequency is 32.768kHz), resistor R19 (resistance value is 1MΩ), capacitor C42 (capacitance value is 18pF), capacitor C43 (capacitance value is 18pF), capacitor C45 (capacitance value is 18pF), capacitor C46 (capacitance value is 18pF). Pin 3 of crystal oscillator X1 is electrically connected to the power filter circuit and one end of capacitor C42; Pin 1 of crystal oscillator X1 is electrically connected to the power filter circuit and one end of capacitor C43; One end of crystal oscillator X2 is electrically connected to the power filter circuit, one end of capacitor C45, and one end of resistor R19; The other end of crystal oscillator X2 is electrically connected to the power filter circuit, one end of capacitor C46, ​​and the other end of resistor R19. Pin 2 and pin 4 of crystal oscillator X1, the other end of capacitor C42, the other end of capacitor C43, the other end of capacitor C45, and the other end of capacitor C46 are grounded; wherein the burning key circuit includes: resistor R17 (resistance value is 0Ω) and switch KEY2. Pin 1 of switch KEY2 is electrically connected to one end of resistor R17; The other end of resistor R17 is electrically connected to the power filter circuit; Pin 4 of switch KEY2 is grounded. .

[0049] In the present invention, multiple capacitors (such as C20, C21, C22, etc.) are connected to the pins of the chip U5 in the power management circuit to form a filter network. Resistors (such as R14, R15, etc.) are used to adjust the current and form a filter circuit together with the capacitors. Through the design of the filter circuit, differential mode and common mode interference signals can be eliminated, and the electromagnetic compatibility and stability of the circuit can be improved;

[0050] The power filter circuit can eliminate high-order harmonics and other high-frequency interference in the current, thereby providing a stable DC voltage for the circuit to use. This helps prevent the circuit from malfunctioning due to power fluctuations;

[0051] The reset circuit is used to reset the circuit to the initial state when necessary to ensure the stable operation of the circuit. The reset circuit can reset the circuit to a known stable state when powered on or when an abnormality occurs in the circuit, which helps prevent the circuit from malfunctioning due to an unknown state. In this embodiment, the resistor R16 is connected in series with the capacitor C44 to form a delay circuit. The switch KEY1 is used to manually trigger the reset operation. When the switch KEY1 is pressed, the capacitor C44 starts to charge and discharges through the resistor R16. This discharge process triggers the reset signal. The reset signal is transmitted to the pin 27 of the chip U5 through the power filter circuit, thereby triggering the reset operation of the circuit.

[0052] The crystal oscillator circuit provides a stable clock signal for the core circuit of the gateway to ensure that the circuit can operate according to the predetermined timing. In this embodiment, the crystal oscillators X1 and X2 are used as oscillators, and together with capacitors C42, C43, C45, C46 and resistor R19, an oscillation circuit is formed. Capacitors C42, C43, C45 and C46 are used to adjust the oscillation frequency and stability. Resistor R19 is used to provide the current required for the crystal oscillator to work. The oscillation signal is transmitted to pins 22 to 25 of the chip U5 through the power filter circuit as the clock signal of the circuit;

[0053] Furthermore, it allows developers to burn programs or update firmware by pressing a button when needed, which is convenient for system debugging and maintenance, thus improving the flexibility and scalability of the system;

[0054] Furthermore, as an independent module, the design of the minimum system circuit makes it easy to integrate with other circuit modules (such as power management circuit, DC isolation circuit, etc.). This modular design not only simplifies the design and production process of the system, but also facilitates future expansion and upgrading.

[0055] Furthermore, by optimizing circuit design and selecting appropriate components, the minimum system circuit not only ensures performance, but also takes into account cost and power consumption control. This is especially important for application scenarios such as IoT device gateways that have strict requirements on cost and power consumption.

[0056] Reference Figure 5The Flash circuit includes: chip U4 (model W25N01GVZEIG), resistor R25 (resistance value is 10kΩ), resistor R26 (resistance value is 10kΩ), resistor R27 (resistance value is 10kΩ), resistor R28 (resistance value is 10kΩ), resistor R29 (resistance value is 10kΩ), resistor R30 (resistance value is 10kΩ), resistor R31 (resistance value is 10kΩ), capacitor C52 (capacitance value is 100nF); pin 1 of chip U4 is connected to the minimum system circuit, resistor R2 5; Pin 2 of chip U4 is electrically connected to the minimum system circuit; Pin 3 of chip U4 is electrically connected to the minimum system circuit and one end of resistor R26; Pin 4 and Pin 9 of chip U4 are grounded; Pin 5 of chip U4 is electrically connected to the minimum system circuit, one end of resistor R29, and one end of resistor R30; Pin 6 of chip U4 is electrically connected to the minimum system circuit; Pin 7 of chip U4 is electrically connected to the minimum system circuit and one end of resistor R27; Pin 8 of chip U4 is electrically connected to the power management circuit and one end of capacitor C52. The other end of resistor R25, the other end of resistor R26, the other end of resistor R27, the other end of resistor R28, and the other end of resistor R29 are electrically connected to the power management circuit; the other end of resistor R30 and the other end of resistor R31 are grounded.

[0057] In this embodiment, the Flash circuit is used as a non-volatile memory, which can keep the stored data unchanged after power failure. It can not only be used to store key data such as operating system, application program, configuration parameters, etc., but also can quickly load these programs and data when the device is started, ensuring that the gateway can quickly enter the working state;

[0058] Through chip U4 and its peripheral circuits, the Flash circuit provides sufficient storage capacity to meet the needs of gateway devices running multiple protocols and processing large amounts of data in complex network environments;

[0059] The Flash circuit has a fast data read and write speed and a high data retention capability. During frequent data read and write operations, the Flash circuit can maintain efficient and stable performance, reducing system crashes or restarts caused by data loss or damage.

[0060] The programmability of the Flash circuit enables the gateway device to support firmware upgrades and configuration updates. When it is necessary to fix software vulnerabilities, add new functions, or adjust configuration parameters, this can be achieved by updating the storage content in the Flash circuit. This not only improves the flexibility and scalability of the gateway device, but also reduces maintenance costs. Users do not need to replace the entire hardware device, but can obtain the latest functions and performance improvements through a simple firmware upgrade.

[0061] Reference Figure 6The USB circuit includes: a connector USB1 (the connector type is Type-C), a resistor R2 (the resistance value is 5.1kΩ), and a resistor R3 (the resistance value is 5.1kΩ); pin 4 of the connector USB1 is electrically connected to one end of the resistor R2; pin 10 of the connector USB1 is electrically connected to one end of the resistor R3; pin 5, pin 6, pin 7, and pin 8 of the connector USB1 are electrically connected to the minimum system circuit; pin 2 and pin 11 of the connector USB1 are connected to the DC isolation circuit; pin 1, pin 12, pin 13, pin 14 of the connector USB1, the other end of the resistor R2, and the other end of the resistor R3 are grounded.

[0062] In this embodiment, by introducing the USB circuit, the gateway core circuit can communicate with devices supporting the USB interface, which greatly expands the communication range and compatibility of the gateway. As a widely used interface standard, USB supports a variety of peripherals and data transmission protocols, so that the gateway can flexibly exchange data with a variety of external devices; since the USB interface has become a widely accepted standard, the use of the USB circuit can enhance the compatibility of the gateway core circuit, so that the gateway can interoperate with more devices and systems without the need for additional adapters or conversion devices;

[0063] Furthermore, resistors R2 and R3 play a role in current limiting and protection in the circuit. During USB communication, these resistors can prevent circuit damage caused by excessive current, thereby improving the stability and reliability of data transmission. Especially when connecting or disconnecting USB devices, these resistors can reduce the impact of instantaneous current and protect the circuit from damage;

[0064] Furthermore, the USB circuit has a simple structure and a relatively small number of components, which is conducive to reducing production costs and improving production efficiency; at the same time, simple circuit design also means a lower failure rate and easier maintenance and repair.

[0065] Reference Figure 7The USB to serial port circuit includes: a connector USB2 (the connector type is Type-C), a resistor R20 (the resistance value is 5.1kΩ), a resistor R22 (the resistance value is 5.1kΩ), a chip U3 (the model is CH340E), and a capacitor C51 (the capacitance value is 100nF); Pin 4 of the connector USB2 is electrically connected to one end of the resistor R20; Pin 10 of the connector USB2 is electrically connected to one end of the resistor R22; Pin 5, Pin 6, Pin 7, and Pin 8 of the connector USB2 are electrically connected to the Pin 1 and pin 2 are electrically connected; Pin 2 and pin 11 of connector USB2 are connected to the DC isolation circuit; Pin 1, pin 12, pin 13, pin 14 of connector USB2, the other end of resistor R20, and the other end of resistor R22 are grounded; Pin 3 of chip U3 is grounded; Pin 7 of chip U3 is electrically connected to one end of capacitor C51 and the power management circuit; Pin 8 and pin 9 of chip U3 are electrically connected to the minimum system circuit; Pin 10 of chip U3 is electrically connected to the power management circuit; the other end of capacitor C51 is grounded.

[0066] In this embodiment, by introducing a USB-to-serial port circuit (including connector USB2, related resistors, chip U3, capacitor C51 and other components), the gateway core circuit can provide an additional serial port communication interface, which greatly enhances the communication flexibility between the gateway and different devices, so that the gateway can not only transmit data through the USB interface, but also connect and communicate with more types of devices through the converted serial port interface;

[0067] Serial communication is a widely used communication method adopted by many industrial, scientific research and experimental equipment. Through the USB to serial port circuit, the gateway can easily access these devices, thereby expanding its application scenarios; for example, in the field of Industrial Internet of Things (IIoT), the gateway can realize data interaction with sensors, actuators and other devices through the serial port interface, realizing a wider range of equipment interconnection and intelligent control;

[0068] The DC isolation circuit in the USB-to-serial port circuit can effectively isolate the electrical interference between the USB interface and the serial port interface, improving the stability and reliability of data transmission, which is especially important for gateways operating in complex electromagnetic environments;

[0069] Through the USB to serial port circuit, the gateway can be easily connected to a computer or other device that supports the USB interface, without the need for complex configuration and settings, to achieve fast data transmission and convenient device connection.

[0070] Reference Figure 1-Figure 8The power supply filter circuit includes: chip U5, resistor R14, resistor R15, resistor R18, resistor R32, capacitor C20, Schottky diode D6, capacitor C21, capacitor C22, capacitor C23, capacitor C24, capacitor C25, capacitor C26, capacitor C27, capacitor C28, capacitor C29, capacitor C30, capacitor C31, capacitor C32, capacitor C33, capacitor C34, capacitor C35, capacitor C36, capacitor C37, capacitor C38, capacitor C39, capacitor C40, capacitor C41; chip U5 pin 1 to pin 8, pin 10 to pin 18, pin 31 to pin 33, pin 35 to pin 45, pin 52 To pin 64, pin 67 to pin 78, pin 82, pin 84 to pin 86, pin 118 to pin 127 are electrically connected to the expansion interface; Pin 9 of chip U5 is electrically connected to one end of resistor R14; Pin 19 of chip U5 is electrically connected to one end of resistor R15; Pin 47 of chip U5 is electrically connected to one end of resistor R18; Pin 29 of chip U5 is electrically connected to the negative electrode of Schottky diode D6; Pin 34, pin 66, pin 77, pin 83, and pin 28 of chip U5 are electrically connected to one end of capacitor C24, one end of capacitor C25, one end of capacitor C26, one end of capacitor C27, one end of capacitor C28, and the power management circuit; Pin 46, pin 51, pin 81, pin 17, and pin 16 of chip U5 are electrically connected to one end of capacitor C30, one end of capacitor C31, one end of capacitor C32, one end of capacitor C33, one end of capacitor C34, and a power management circuit; pin 91 of chip U5 is electrically connected to one end of resistor R32; pin 48 and pin 49 of chip U5 are electrically connected to one end of capacitor C21, one end of capacitor C22, and a power management circuit; pin 28, pin 20, pin 26, pin 50, pin 65, and pin 107 of chip U5 are electrically connected to one end of capacitor C23, one end of capacitor C35, one end of capacitor C36, one end of capacitor C37, and one end of capacitor C38. One end of the chip U5 is electrically connected to one end of the capacitor C39; the pin 30 of the chip U5 is electrically connected to one end of the capacitor C29; the pin 89 of the chip U5 is electrically connected to the power management circuit and one end of the capacitor C40; the pin 97 of the chip U5 is electrically connected to the power management circuit and one end of the capacitor C41; the pins 22 to 25 of the chip U5 are electrically connected to the crystal oscillator circuit; the pin 27 of the chip U5 is electrically connected to the reset circuit; the pin 17 of the chip U5 is electrically connected to the Flash circuit and the burning button circuit; the other end of the capacitor C40 and the other end of the capacitor C41 are electrically connected to one end of the resistor R32; the anode of the Schottky diode D6 is electrically connected to one end of the capacitor C20 and the power management circuit;The other end of capacitor C20, the other end of capacitor C24, the other end of capacitor C25, the other end of capacitor C26, the other end of capacitor C27, the other end of capacitor C28, the other end of capacitor C30, the other end of capacitor C31, the other end of capacitor C32, the other end of capacitor C33, the other end of capacitor C34, the other end of resistor R32, pin 129 of chip U5, the other end of capacitor C21, the other end of capacitor C22, the other end of capacitor C23, the other end of capacitor C35, the other end of capacitor C36, the other end of capacitor C37, the other end of capacitor C38, the other end of capacitor C39, and the other end of capacitor C29 are grounded. ;

[0071] In the present invention, through the parallel and series combination of multiple capacitors, the power filter circuit can effectively filter out high-frequency noise and ripple in the power supply, and provide a stable and clean power supply for the core processor (such as chip U5) in the minimum system circuit, thereby ensuring the stable operation of the gateway device; the capacitors and resistors and other components in the power filter circuit can form a certain impedance network to attenuate and isolate external interference signals, thereby improving the anti-interference ability of the gateway device, so that it can maintain normal operation in a complex industrial field environment; the power filter circuit can also protect the core processor from abnormal conditions such as power fluctuations and overvoltage to a certain extent, extend its service life, and improve the reliability of the entire gateway device;

[0072] The operation mode of the power supply filter circuit is as follows:

[0073] Component selection and layout: According to the power requirements and filtering requirements of the core processor (chip U5), select appropriate components such as capacitors, resistors, and Schottky diodes, and reasonably layout these components on the circuit board to ensure that the connection paths between them are as short as possible to reduce signal loss and interference;

[0074] Power input and filtering: The power supply voltage provided by the power management circuit is input into the power supply filtering circuit through an appropriate path. Multiple capacitors (such as C20, C24, C25, etc.) are connected in parallel at the power input end to filter out high-frequency noise in the power supply.

[0075] Voltage stabilization and decoupling: Schottky diode D6 and capacitor C20 work together to form a voltage stabilization circuit to fine-tune the power supply voltage to ensure that it is stable within the range required by the core processor. Other capacitors (such as C23, C35, etc.) are used as decoupling capacitors and are connected in parallel to different power pins of the core processor to further reduce the impact of power supply fluctuations on the processor;

[0076] Grounding and protection: The other end of all capacitors and the other end of resistor R32 are grounded to form a complete grounding loop to ensure filtering effect. Resistor R32 cooperates with capacitor C40 and capacitor C41 to form an overvoltage protection circuit. When the power supply voltage is too high, it discharges through resistor R32 to protect the core processor from damage.

[0077] Operation monitoring and adjustment: During the operation of the gateway device, the effect of the power supply filter circuit can be evaluated by monitoring parameters such as the power pin voltage and current of the core processor. According to the actual situation, the capacitance of the capacitor, the resistance value of the resistor and other parameters can be adjusted to optimize the filtering effect and improve the stability and reliability of the gateway device.

[0078] Reference Figure 1-Figure 8 The reset circuit includes: a resistor R16, a capacitor C44, and a switch KEY1; a pin 4 of the switch KEY1 is electrically connected to one end of the resistor R16, one end of the capacitor C44, and a power filter circuit; the other end of the resistor R16 is electrically connected to the power management circuit; the other end of the capacitor C44 and the pin 1 of the switch KEY1 are grounded.

[0079] In this embodiment, when the system is operating normally, the switch KEY1 is in the off state, and the capacitor C44 is slowly charged to the power supply voltage through the resistor R16. At this time, the reset signal (usually connected to the reset pin in the minimum system circuit) is kept at a high level, and the system is operating normally;

[0080] When the system needs to be reset, the switch KEY1 is pressed, and the capacitor C44 is rapidly discharged to the ground potential through the switch KEY1. Due to the rapid discharge of the capacitor C44, the reset signal is pulled down to a low level, triggering the reset operation of the system; after the system is reset, the switch KEY1 is released, and the capacitor C44 is slowly charged to the power supply voltage through the resistor R16 again, and the reset signal returns to a high level, and the system resumes normal operation;

[0081] The length of the reset time depends on the capacity of capacitor C44 and the resistance of resistor R16. A larger capacitor and a smaller resistor will result in a longer reset time, while a smaller capacitor and a larger resistor will result in a shorter reset time. In actual design, it is necessary to select appropriate capacitor and resistor values ​​according to the specific needs of the system.

[0082] In some designs, the reset circuit may also include other components (such as a voltage monitor) to implement an automatic reset function. When the power supply voltage drops below a certain threshold, the voltage monitor triggers a reset operation without manually pressing the switch KEY1.

[0083] Reference Figure 1-Figure 8The crystal oscillator circuit includes: crystal oscillator X1, crystal oscillator X2, resistor R19, capacitor C42, capacitor C43, capacitor C45, and capacitor C46; pin 3 of the crystal oscillator X1 is electrically connected to the power supply filter circuit and one end of the capacitor C42; pin 1 of the crystal oscillator X1 is electrically connected to the power supply filter circuit and one end of the capacitor C43; one end of the crystal oscillator X2 is electrically connected to the power supply filter circuit, one end of the capacitor C45, and one end of the resistor R19; the other end of the crystal oscillator X2 is electrically connected to the power supply filter circuit, one end of the capacitor C46, ​​and the other end of the resistor R19; pin 2, pin 4 of the crystal oscillator X1, the other end of the capacitor C42, the other end of the capacitor C43, the other end of the capacitor C45, and the other end of the capacitor C46 are grounded.

[0084] In the present invention, suitable crystal oscillators (such as crystal oscillator X1 and crystal oscillator X2) are selected. These crystal oscillators usually have specific frequency and stability requirements. Suitable capacitors (such as capacitors C42, C43, C45, C46) and resistors (such as resistor R19) are selected to form the oscillation circuit of the crystal oscillator. According to the requirements of circuit layout and signal transmission, the positions of these components are reasonably arranged to reduce interference and improve signal quality.

[0085] Connect pin 3 of crystal oscillator X1 to the power filter circuit and one end of capacitor C42, connect pin 1 to the power filter circuit and one end of capacitor C43, connect one end of crystal oscillator X2 to the power filter circuit, one end of capacitor C45 and one end of resistor R19, and the other end to the power filter circuit, one end of capacitor C46 and the other end of resistor R19, and ensure that pin 2 and pin 4 of the crystal oscillator and the other ends of all capacitors are grounded to form a complete oscillation circuit;

[0086] When the power filter circuit provides a stable power supply, the crystal oscillator circuit starts to oscillate and generates a stable clock signal. This clock signal is transmitted to other parts of the gateway's minimum system circuit (such as the CPU) through the power filter circuit to control data processing and communication protocol conversion. During the entire operation process, the crystal oscillator circuit maintains a stable oscillation frequency to ensure that the gateway can continuously and accurately perform its functions.

[0087] Furthermore, in the actual design process, the crystal oscillator circuit may need to be debugged and optimized to ensure that its performance meets the requirements of the gateway, including adjusting the values ​​of capacitors and resistors, optimizing circuit layout, improving signal transmission paths, etc.

[0088] Reference Figure 8 , in the expansion interface, connector H1 (connector type is 2×20p pin header), connector H2 (connector type is 2×20p pin header).

[0089] In this embodiment, in the design of the core circuit of the gateway, an interface for the burning key circuit is reserved, including a resistor R17 and a switch KEY2. One end of the resistor R17 is electrically connected to the power filter circuit, and the other end is electrically connected to the pin 1 of the switch KEY2. The pin 4 of the switch KEY2 is grounded to form a simple circuit loop.

[0090] Burning process: When it is necessary to burn a program or data, the technician will press the switch KEY2. After pressing the switch, the circuit is closed, and the resistor R17 transmits the electrical signal of the power filter circuit to the circuit related to burning (this part of the circuit may be located in other parts of the minimum system circuit, such as a pin of the chip U5); after receiving the electrical signal, the circuit related to burning will trigger the burning operation and write the new program or data into the memory of the gateway core circuit (such as the Flash circuit); after the burning is completed, the technician releases the switch KEY2, the circuit is disconnected, and the burning process ends;

[0091] Operation monitoring: After the burning is completed, the gateway core circuit will restart and load the new program or data; the technician can verify whether the burning is successful by observing the running status of the gateway core circuit or by connecting the debugging tool.

[0092] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical scheme and inventive concept of the present invention within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

Claims

1. A gateway core circuit supporting expansion, characterized in that: Including power management circuit, DC isolation circuit, minimum system circuit, Flash circuit, USB circuit, USB to serial port circuit, and expansion interface; The power management circuit is electrically connected to the DC isolation circuit, the minimum system circuit, the Flash circuit, the USB circuit, the USB-to-serial port circuit, and the expansion interface respectively; the minimum system circuit is electrically connected to the Flash circuit, the USB circuit, the USB-to-serial port circuit, and the expansion interface; The expansion interface includes: a connector H1 and a connector H2, and the connector H1 and the connector H2 are electrically connected to the minimum system circuit and the power management circuit.

2. A gateway core circuit supporting expansion according to claim 1, characterized in that: The power management circuit includes: resistor R4, resistor R5, resistor R6, resistor R7, resistor R8, resistor R9, resistor R10, resistor R11, resistor R12, capacitor C5, capacitor C6, capacitor C7, capacitor C8, capacitor C9, capacitor C10, capacitor C11, capacitor C12, capacitor C13, capacitor C14, capacitor C15, capacitor C16, capacitor C17, capacitor C18, capacitor C19, inductor L1, inductor L2, inductor L3, chip U1, chip U2; Pin 16 of the chip U1 is electrically connected to one end of the capacitor C5 and the DC isolation circuit respectively; Pin 7, Pin 10, and Pin 19 of the chip U1 are electrically connected to one end of the capacitor C9, one end of the capacitor C10, one end of the capacitor C11, and the DC isolation circuit respectively; Pin 9 of the chip U1 is electrically connected to one end of the resistor R6; Pin 8 of the chip U1 is electrically connected to one end of the resistor R8; Pin 18 of the chip U1 is electrically connected to one end of the resistor R9; Pin 11 of the chip U1 is electrically connected to one end of the inductor L1 The pin 14 of the chip U1 is electrically connected to the other end of the capacitor C6, the other end of the resistor R4, and one end of the resistor R5 respectively; the pin 6 of the chip U1 is electrically connected to one end of the inductor L2; the pin 3 of the chip U1 is electrically connected to the other end of the capacitor C12, the other end of the resistor R7, and one end of the resistor R10 respectively; the pin 20 of the chip U1 is electrically connected to one end of the inductor L3; the pin 2 of the chip U1 is electrically connected to the other end of the capacitor C15, the other end of the resistor R11, and one end of the resistor R12 respectively; Pin 3 of the chip U2 is electrically connected to one end of the capacitor C18 and one end of the capacitor C18 respectively; Pin 2 of the chip U2 is electrically connected to the minimum system circuit and one end of the capacitor C19 respectively; The other end of the inductor L1 is electrically connected to one end of the capacitor C6, one end of the resistor R4, one end of the capacitor C7, and one end of the capacitor C8; the other end of the inductor L2 is electrically connected to one end of the capacitor C12, one end of the resistor R7, one end of the capacitor C13, and one end of the capacitor C14; the other end of the inductor L3 is electrically connected to one end of the capacitor C15, one end of the resistor R11, one end of the capacitor C16, and one end of the capacitor C17; The other end of the resistor R8 and the other end of the resistor R9 are electrically connected to one end of the capacitor C8; the other end of the resistor R6 is electrically connected to the DC isolation circuit; The other end of the capacitor C5, the other end of the capacitor C9, the other end of the capacitor C10, the other end of the capacitor C11, pin 12 of chip U1, pin 13 of chip U1, pin 5 of chip U1, pin 4 of chip U1, pin 1 of chip U1, pin 15 of chip U1, pin 17 of chip U1, pin 21 of chip U1, the other end of the resistor R5, the other end of the capacitor C7, the other end of the capacitor C8, the other end of the resistor R10, the other end of the capacitor C13, the other end of the capacitor C14, the other end of the resistor R12, the other end of the capacitor C16, the other end of the capacitor C17, the other end of the capacitor C18, the other end of the capacitor C19, and pin 1 of the chip U2 are grounded.

3. The gateway core circuit supporting expansion according to claim 1, characterized in that: The DC isolation circuit includes: a resistor R1, a resistor R21, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C47, a capacitor C48, a capacitor C49, and a capacitor C50; One end of the resistor R1 is electrically connected to one end of the capacitor C1, one end of the capacitor C2, and the USB circuit respectively; the other end of the resistor R1 is electrically connected to one end of the capacitor C3, one end of the capacitor C4, and the power management circuit respectively; one end of the resistor R21 is electrically connected to one end of the capacitor C47, one end of the capacitor C48, and the USB circuit respectively; the other end of the resistor R21 is electrically connected to one end of the capacitor C49, one end of the capacitor C50, and the power management circuit respectively; the other end of the capacitor C1, the other end of the capacitor C2, the other end of the capacitor C3, the other end of the capacitor C4, the other end of the capacitor C47, the other end of the capacitor C48, the other end of the capacitor C49, and the other end of the capacitor C50 are grounded.

4. The gateway core circuit supporting expansion according to claim 1, characterized in that: The minimum system circuit includes: a power supply filter circuit, a reset circuit, a crystal oscillator circuit, and a burning button circuit; The burning key circuit includes: a resistor R17 and a switch KEY2; The pin 1 of the switch KEY2 is electrically connected to one end of the resistor R17; the other end of the resistor R17 is electrically connected to the power supply filter circuit; and the pin 4 of the switch KEY2 is grounded.

5. The gateway core circuit supporting expansion according to claim 1, characterized in that: The Flash circuit includes: a chip U4, a resistor R25, a resistor R26, a resistor R27, a resistor R28, a resistor R29, a resistor R30, a resistor R31, and a capacitor C52; Pin 1 of the chip U4 is electrically connected to the minimum system circuit and one end of the resistor R25; Pin 2 of the chip U4 is electrically connected to the minimum system circuit; Pin 3 of the chip U4 is electrically connected to the minimum system circuit and one end of the resistor R26; Pin 4 and Pin 9 of the chip U4 are grounded; Pin 5 of the chip U4 is electrically connected to the minimum system circuit, one end of the resistor R29, and one end of the resistor R30; Pin 6 of the chip U4 is electrically connected to the minimum system circuit; Pin 7 of the chip U4 is electrically connected to the minimum system circuit and one end of the resistor R27; Pin 8 of the chip U4 is electrically connected to the power management circuit and one end of the capacitor C52; The other end of the resistor R25, the other end of the resistor R26, the other end of the resistor R27, the other end of the resistor R28, and the other end of the resistor R29 are electrically connected to the power management circuit; the other end of the resistor R30 and the other end of the resistor R31 are grounded.

6. The gateway core circuit supporting expansion according to claim 1, characterized in that: The USB circuit comprises: a connector USB1, a resistor R2, and a resistor R3; Pin 4 of the connector USB1 is electrically connected to one end of the resistor R2; Pin 10 of the connector USB1 is electrically connected to one end of the resistor R3; Pin 5, Pin 6, Pin 7, and Pin 8 of the connector USB1 are electrically connected to the minimum system circuit; Pin 2 and Pin 11 of the connector USB1 are connected to the DC isolation circuit; Pin 1, Pin 12, Pin 13, Pin 14 of the connector USB1, the other end of the resistor R2, and the other end of the resistor R3 are grounded.

7. The gateway core circuit supporting expansion according to claim 1, characterized in that: The USB to serial port circuit includes: a connector USB2, a resistor R20, a resistor R22, a chip U3, and a capacitor C51; Pin 4 of the connector USB2 is electrically connected to one end of the resistor R20; Pin 10 of the connector USB2 is electrically connected to one end of the resistor R22; Pin 5, Pin 6, Pin 7, and Pin 8 of the connector USB2 are electrically connected to Pin 1 and Pin 2 of the chip U3; Pin 2 and Pin 11 of the connector USB2 are connected to the DC isolation circuit; Pin 1, Pin 12, Pin 13, Pin 14 of the connector USB2, the other end of the resistor R20, and the other end of the resistor R22 are grounded; Pin 3 of the chip U3 is grounded; Pin 7 of the chip U3 is electrically connected to one end of the capacitor C51 and the power management circuit; Pin 8 and Pin 9 of the chip U3 are electrically connected to the minimum system circuit; Pin 10 of the chip U3 is electrically connected to the power management circuit; the other end of the capacitor C51 is grounded.

8. The minimum system circuit according to claim 4, characterized in that: The power supply filter circuit includes: chip U5, resistor R14, resistor R15, resistor R18, resistor R32, capacitor C20, Schottky diode D6, capacitor C21, capacitor C22, capacitor C23, capacitor C24, capacitor C25, capacitor C26, capacitor C27, capacitor C28, capacitor C29, capacitor C30, capacitor C31, capacitor C32, capacitor C33, capacitor C34, capacitor C35, capacitor C36, capacitor C37, capacitor C38, capacitor C39, capacitor C40, capacitor C41; Pin 1 to pin 8, pin 10 to pin 18, pin 31 to pin 33, pin 35 to pin 45, pin 52 to pin 64, pin 67 to pin 78, pin 82, pin 84 to pin 86, and pin 118 to pin 127 of the chip U5 are electrically connected to the expansion interface; Pin 9 of the chip U5 is electrically connected to one end of the resistor R14; Pin 19 of the chip U5 is electrically connected to one end of the resistor R15; Pin 47 of the chip U5 is electrically connected to one end of the resistor R18; Pin 29 of U5 is electrically connected to the negative electrode of Schottky diode D6; Pin 34, Pin 66, Pin 77, Pin 83, Pin 28 of the chip U5 are electrically connected to one end of capacitor C24, one end of capacitor C25, one end of capacitor C26, one end of capacitor C27, one end of capacitor C28, and the power management circuit; Pin 46, Pin 51, Pin 81, Pin 17, Pin 16 of the chip U5 are electrically connected to one end of capacitor C30, one end of capacitor C31, one end of capacitor C32, and one end of capacitor C33. one end of the chip U5, one end of the capacitor C34, and the power management circuit are electrically connected; the pin 91 of the chip U5 is electrically connected to one end of the resistor R32; the pin 48 and pin 49 of the chip U5 are electrically connected to one end of the capacitor C21, one end of the capacitor C22, and the power management circuit; the pin 28, pin 20, pin 26, pin 50, pin 65, and pin 107 of the chip U5 are electrically connected to one end of the capacitor C23, one end of the capacitor C35, one end of the capacitor C36, one end of the capacitor C37, and one end of the capacitor C38 , one end of capacitor C39; pin 30 of the chip U5 is electrically connected to one end of capacitor C29; pin 89 of the chip U5 is electrically connected to the power management circuit and one end of capacitor C40; pin 97 of the chip U5 is electrically connected to the power management circuit and one end of capacitor C41; pins 22 to 25 of the chip U5 are electrically connected to the crystal oscillator circuit; pin 27 of the chip U5 is electrically connected to the reset circuit; pin 17 of the chip U5 is electrically connected to the Flash circuit and the burning button circuit; The other end of the capacitor C40 and the other end of the capacitor C41 are electrically connected to one end of the resistor R32; the anode of the Schottky diode D6 is electrically connected to one end of the capacitor C20 and the power management circuit; The other end of capacitor C20, the other end of capacitor C24, the other end of capacitor C25, the other end of capacitor C26, the other end of capacitor C27, the other end of capacitor C28, the other end of capacitor C30, the other end of capacitor C31, the other end of capacitor C32, the other end of capacitor C33, the other end of capacitor C34, the other end of resistor R32, pin 129 of chip U5, the other end of capacitor C21, the other end of capacitor C22, the other end of capacitor C23, the other end of capacitor C35, the other end of capacitor C36, the other end of capacitor C37, the other end of capacitor C38, the other end of capacitor C39, and the other end of capacitor C29 are grounded.

9. The minimum system circuit according to claim 4, characterized in that: The reset circuit includes: a resistor R16, a capacitor C44, and a switch KEY1; Pin 4 of the switch KEY1 is electrically connected to one end of the resistor R16, one end of the capacitor C44, and a power filter circuit; the other end of the resistor R16 is electrically connected to a power management circuit; the other end of the capacitor C44 and pin 1 of the switch KEY1 are grounded.

10. The minimum system circuit according to claim 4, characterized in that: The crystal oscillator circuit includes: a crystal oscillator X1, a crystal oscillator X2, a resistor R19, a capacitor C42, a capacitor C43, a capacitor C45, and a capacitor C46; Pin 3 of the crystal oscillator X1 is electrically connected to a power filter circuit and one end of a capacitor C42; Pin 1 of the crystal oscillator X1 is electrically connected to a power filter circuit and one end of a capacitor C43; One end of the crystal oscillator X2 is electrically connected to a power filter circuit, one end of a capacitor C45, and one end of a resistor R19; The other end of the crystal oscillator X2 is electrically connected to a power filter circuit, one end of a capacitor C46, ​​and the other end of a resistor R19; Pin 2, pin 4 of the crystal oscillator X1, the other end of the capacitor C42, the other end of the capacitor C43, the other end of the capacitor C45, and the other end of the capacitor C46 are grounded.

Images