Chip performance testing method and device, storage medium and electronic device

Abstract

The present application discloses a chip performance testing method and device, a storage medium and an electronic device, the method comprising: responding to a target test request, locating a target data segment included in an initial data stream received by a switching chip, wherein the target test request is used to test the decoding performance of a physical coding sublayer of the switching chip for a data stream of a target data segment having a misaligned field; converting field modification information for each target data segment according to configuration information of the switching chip, wherein the configuration information is used to indicate a field modification method for the target data segment in the data stream received by the switching chip; performing field modification on the corresponding target data segment in the initial data stream according to the modification method indicated by the field modification information to obtain a target data stream; and sending the target data stream to the physical coding sublayer. The above technical solution is adopted to solve the problem of low test efficiency of the performance of chip decoding abnormal data streams in the related art.

Description

Technical Field

[0001] The present application relates to the field of Ethernet communication technology, and in particular to a chip performance testing method and device, a storage medium and an electronic device. Background Art

[0002] As an important part of the chip's physical layer, the chip's physical coding sublayer is responsible for encoding the data stream into a format suitable for physical layer processing and transmission. During the data transmission process, abnormal data errors may occur. By testing the decoding performance of the chip's physical coding sublayer for data streams with abnormal fields, the chip's performance in the face of different types of interference can be evaluated, thereby meeting the reliability requirements of network communications. In the related art, the data stream that the chip's physical coding sublayer is about to receive is randomly inserted or inserted at a fixed period to generate an abnormal data stream, and then the abnormal data stream is sent to the physical coding sublayer to test the chip's performance. However, this insertion method is pseudo-random and cannot ensure that it can cover the specific fields that need to be inserted, resulting in low test efficiency for the chip's decoding of abnormal data streams. No effective solution has been proposed for the problem of low test efficiency for the chip's decoding of abnormal data streams in the related art. Summary of the invention

[0003] The embodiments of the present application provide a chip performance testing method and device, a storage medium, and an electronic device to at least solve the problem of low efficiency in testing the decoding performance of a chip for abnormal data streams in the related art.

[0004] According to one embodiment of the present application, a method for testing chip performance is provided, including:

[0005] In response to a target test request, a target data segment included in an initial data stream received by the switching chip is located, wherein the target test request is used to test a decoding performance of a physical coding sublayer of the switching chip on a data stream of a target data segment having a misaligned field;

[0006] Converting field modification information for each of the target data segments according to the configuration information of the switching chip, wherein the configuration information is used to indicate a field modification method for the target data segment in the data stream received by the switching chip;

[0007] Performing field modification on the target data segment corresponding to the initial data stream according to the modification mode indicated by the field modification information to obtain a target data stream;

[0008] The target data stream is sent to the physical coding sublayer.

[0009] Optionally, converting the field modification information for each of the target data segments according to the configuration information of the switching chip includes:

[0010] Classifying channel data corresponding to a plurality of physical coding sublayer channels included in the initial data stream to obtain a sub-data stream belonging to each of the physical coding sublayer channels;

[0011] Filtering target configuration information corresponding to the physical coding sublayer channel from the configuration information;

[0012] The field modification information is converted for the target data segment in the sub-data stream according to the target configuration information.

[0013] Optionally, converting the field modification information for the target data segment in the sub-data stream according to the target configuration information includes:

[0014] Dividing the plurality of target data segments included in the sub-data stream into a plurality of data segment sequences according to a period parameter, wherein the period parameter is used to indicate the number of the target data segments that need to be modified in a single field modification round, each of the data segment sequences includes a plurality of the target data segments that are sequentially arranged in chronological order in the sub-data stream, and there is no identical target data segment between any two of the data segment sequences;

[0015] Filtering candidate data segments of the field to be modified from each of the data segment sequences according to the filtering parameters;

[0016] Target modification information of a field in the candidate data segment is determined according to modification parameters, wherein the field modification information includes the target modification information of the candidate data segment, wherein the target configuration information includes the period parameter, the screening parameter and the modification parameter.

[0017] Optionally, the filtering out candidate data segments of the field to be modified from each of the data segment sequences according to the filtering parameters includes:

[0018] Detect the target screening type indicated by the Screening Type field;

[0019] A target number of candidate data segments are screened out from the data segment sequence according to a screening method indicated by the target screening type, wherein the screening parameters include the screening type field and the target number.

[0020] Optionally, the filtering out a target number of candidate data segments from the data segment sequence according to the filtering method indicated by the target filtering type includes:

[0021] In the case where the target screening type is a random screening type, randomly screening the target number of data segments from the data segment sequence to determine as the candidate data segments;

[0022] In the case where the target screening type is a sequential screening type, the target number of data segments in the data segment sequence that are arranged at the front end of the sequence are determined as the candidate data segments.

[0023] Optionally, locating a target data segment included in an initial data stream received by the switching chip includes:

[0024] The fields included in the initial data stream are screened in sequence to obtain a first data segment in the initial data stream, wherein the first data segment is the target data segment that appears for the first time in the initial data stream;

[0025] A second data segment is located from the data located after the first data segment in the initial data stream according to the arrangement of the target data segment, wherein the second data segment is the target data segment located after the first data segment in the initial data stream.

[0026] Optionally, locating the second data segment from the data located after the first data segment in the initial data stream according to the arrangement of the target data segment includes:

[0027] Acquire a character spacing corresponding to a data segment type to which the target data segment belongs, wherein the character spacing is used to indicate a spacing between adjacent target data segments in a data stream;

[0028] Filter out target characters from the data located after the first data segment in the initial data stream according to the character spacing;

[0029] In a case where the target character is a character corresponding to a data segment of the data segment type, the target character is determined to be the second data segment.

[0030] According to another embodiment of the present application, a chip performance testing device is provided, including:

[0031] A positioning module, configured to respond to a target test request and locate a target data segment included in an initial data stream received by the switching chip, wherein the target test request is used to test a decoding performance of a physical coding sublayer of the switching chip on a data stream of a target data segment having a misaligned field;

[0032] A conversion module, used for converting field modification information for each of the target data segments according to the configuration information of the switching chip, wherein the configuration information is used for indicating a field modification mode for the target data segment in the data stream received by the switching chip;

[0033] A modification module, configured to perform field modification on the target data segment corresponding to the initial data stream according to the modification method indicated by the field modification information, so as to obtain a target data stream;

[0034] A sending module is used to send the target data stream to the physical coding sublayer.

[0035] According to another aspect of the embodiments of the present application, a computer-readable storage medium is provided, in which a computer program is stored, wherein the computer program is configured to execute the above-mentioned chip performance testing method when running.

[0036] According to another aspect of an embodiment of the present application, an electronic device is provided, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the chip performance testing method through the computer program.

[0037] In the embodiment of the present application, by locating the target data segment from the initial data stream received by the switching chip, and converting the field modification information for each target data segment according to the configuration information for indicating the field modification method of the target data segment in the data stream received by the switching chip, the field modification of the corresponding target data segment in the initial data stream can be performed according to the modification method indicated by the field modification information to obtain the target data stream, and finally the target data stream is sent to the physical coding sublayer to test the decoding performance of the physical coding sublayer of the switching chip for the data stream of the target data segment with misaligned fields. The above technical solution solves the problem of low test efficiency of the performance of chip decoding abnormal data streams in the related art, and achieves the technical effect of improving the test efficiency of the performance of chip decoding abnormal data streams. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0039] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0040] Figure 1 It is a hardware environment diagram of a chip performance testing method according to an embodiment of the present application;

[0041] Figure 2 is a flow chart of a chip performance testing method according to an embodiment of the present application;

[0042] Figure 3 It is a relationship diagram between a PCS and an OSI reference model at a rate of 40G or higher according to an embodiment of the present application;

[0043] Figure 4 is a relationship diagram between a new PCS and an OSI reference model according to an embodiment of the present application;

[0044] Figure 5 is a SH identification and locking flow chart according to an embodiment of the present application;

[0045] Figure 6 is a flowchart of AM identification and locking according to an embodiment of the present application;

[0046] Figure 7 is a diagram of a SH misinsertion function interface according to an embodiment of the present application;

[0047] Figure 8 This is a simplified diagram of a data flow configuration SH plugged into a wrong interface according to an embodiment of the present application;

[0048] Fig. 9 is a flow chart of SH identification misinsertion according to an embodiment of the present application;

[0049] Fig.10 is a diagram of an AM misinsertion function interface according to an embodiment of the present application;

[0050] Fig.11 This is a simplified diagram of a data flow configuration after an AM is inserted into a wrong interface according to an embodiment of the present application;

[0051] Fig.12 is a flow chart of AM identification error insertion according to an embodiment of the present application;

[0052] Fig.13 It is a structural block diagram of a chip performance testing device according to an embodiment of the present application. DETAILED DESCRIPTION

[0053] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0054] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0055] The method embodiments provided in the embodiments of the present application can be executed in a computer terminal, a device terminal or a similar computing device. Taking running on a computer terminal as an example, Figure 1 FIG. 1 is a schematic diagram of a hardware environment for a chip performance testing method according to an embodiment of the present application. Figure 1 As shown, the computer terminal may include one or more ( Figure 1 Only one is shown in the figure) processor 102 (processor 102 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing data. In an exemplary embodiment, the computer terminal may also include a transmission device 106 and an input / output device 108 for communication functions. It can be understood by those skilled in the art that Figure 1 The structure shown is only for illustration and does not limit the structure of the above-mentioned computer terminal. Figure 1 More or fewer components as shown, or with Figure 1 Equivalent functions or comparisons shown Figure 1 A different configuration with more features is shown.

[0056] The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the method for sending message push in the embodiment of the present invention. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, to implement the above method. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include a memory remotely arranged relative to the processor 102, and these remote memories may be connected to the computer terminal via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0057] The transmission device 106 is used to receive or send data via a network. The specific example of the above network may include a wireless network provided by a communication provider of a computer terminal. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, referred to as NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 can be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0058] In this embodiment, a chip performance testing method is provided, which is applied to the above-mentioned computer terminal. Figure 2 : is a flow chart of a chip performance testing method according to an embodiment of the present application, the process includes the following steps:

[0059] Step S202, responding to a target test request, locating a target data segment included in an initial data stream received by the switching chip, wherein the target test request is used to test decoding performance of a physical coding sublayer of the switching chip on a data stream of a target data segment having a misaligned field;

[0060] Step S204, converting field modification information for each of the target data segments according to the configuration information of the switching chip, wherein the configuration information is used to indicate a field modification method for the target data segment in the data stream received by the switching chip;

[0061] Step S206, modifying the field of the target data segment corresponding to the initial data stream according to the modification method indicated by the field modification information to obtain a target data stream;

[0062] Step S208: sending the target data stream to the physical coding sublayer.

[0063] Through the above steps, by locating the target data segment from the initial data stream received by the switching chip, and according to the configuration information for indicating the field modification method of the target data segment in the data stream received by the switching chip, the field modification information for each target data segment is converted, and then the field modification of the corresponding target data segment in the initial data stream can be performed according to the modification method indicated by the field modification information to obtain the target data stream, and finally the target data stream is sent to the physical coding sublayer to test the decoding performance of the physical coding sublayer of the switching chip for the data stream of the target data segment with misaligned fields. The above technical solution solves the problem of low test efficiency of the chip decoding abnormal data stream performance in the related art, and achieves the technical effect of improving the test efficiency of the chip decoding abnormal data stream performance.

[0064] In the technical solution provided in the above step S202, the initial data stream is the data stream before being sent to the physical coding sublayer of the switching chip.

[0065] Optionally, in an embodiment of the present application, the target data segment is a data segment containing specific fields in the initial data stream received by the switching chip. Such specific fields play an important role in the correct decoding and synchronization of the data stream. For example, the target data segment may be a data segment containing SH (Sync Header) or AM (Alignment Marker), and this solution does not limit this.

[0066] Optionally, in the embodiment of the present application, the target data segment included in the initial data stream received by the switching chip is located, and different methods of positioning can be performed according to the type of specific fields included in the target data segment. For example, when the target data segment is a data segment including SH, the positioning of SH can be to lock the data block including SH, which can be achieved by the following steps:

[0067] S0: Initialize SH identification and locking process, rx_block_lock = 0 (indicates that block locking is not currently implemented), reset counter, sh_cnt = 0 (valid SH counter is set to 0), sh_invalid_cnt = 0 (invalid SH counter is set to 0); jump to S1;

[0068] S1: Search for the first valid SH in the current physical coding sublayer channel data stream, and after finding it, count the counter sh_cnt++; jump to S3;

[0069] S2: According to the last valid SH, take the next 2 bits as the next SH with an interval of 66 bits, and judge whether it is a valid SH. If it is a valid SH, then sh_cnt++. Jump to S3; if it is an invalid SH, then sh_invalid_cnt=1, and jump to S5;

[0070] S3: When sh_cnt<64, jump to S2 (indicates that the number of SHs required for stable locking has not yet been reached, and the process returns to S2 to continue verifying subsequent SHs); when sh_cnt=64, jump to S4 (indicates that 64 valid SHs have been continuously identified, meeting the conditions for block locking);

[0071] S4: The current physical coding sublayer channel achieves block lock, rx_block_lock = 1, sets sh_cnt = 63, and jumps to S2 (to prepare for the next round of verification, because after sh_cnt reaches 64, the next round of verification starts counting from 63 to ensure continuity check);

[0072] S5: The current SH is an invalid SH, the synchronization header (SH) is unlocked, rx_block_lock=0 (indicating that block lock is not currently implemented), and jumps to S0.

[0073] When the target data segment is a data segment containing AM, the positioning of AM can be achieved by the following steps:

[0074] S0: Initialize the AM identification and locking process, am_lock = 0 (indicates that AM is not currently locked), jump to S1;

[0075] S1: Search for the first AM in the current physical coding sublayer channel data stream. If the AM is valid, record the current AM field to first_am and jump to S2; if the AM is invalid, jump to S0;

[0076] S2: Search for the next AM field according to the protocol interval (different rates have different fixed intervals), compare the found AM field with first_am, if they are the same, jump to S3, if they are different, jump to S4;

[0077] S3: The current physical coding sublayer channel achieves AM lock, am_lock = 1, jump to S2;

[0078] S4: The current physical coding sublayer channel AM is locked, am_lock=0, jump to S0.

[0079] In the technical solution provided in the above step S204, the configuration information is information used to indicate the field modification method of the target data segment in the data stream received by the switching chip. The configuration information may be, but is not limited to, a mapping table that records specific fields with corresponding relationships and field modification methods. The target data segment contains one of the specific fields recorded in the mapping table, and then the field modification method corresponding to each target data segment can be converted according to the mapping table that records the specific fields with corresponding relationships and field modification methods.

[0080] Optionally, in an embodiment of the present application, the field modification method may include but is not limited to the modification period, number of modifications, modification type, etc. of the field, and this solution does not limit this.

[0081] In the technical solution provided in the above step S206, the field modification is performed on the corresponding target data segment in the initial data stream according to the modification method indicated by the field modification information. The number of target data segments that need to be modified in a single field modification round can be first determined, and then the candidate data segments of the fields to be modified are screened out from the target data segments, and then the fields in the candidate data segments are modified according to the modification information.

[0082] In the technical solution provided in the above step S208, the target data stream obtained after the field is modified is sent to the physical coding sublayer to test the decoding performance of the physical coding sublayer of the switching chip for the data stream with the misaligned field.

[0083] As an optional implementation manner, converting the field modification information for each of the target data segments according to the configuration information of the switching chip includes:

[0084] Classifying channel data corresponding to a plurality of physical coding sublayer channels included in the initial data stream to obtain a sub-data stream belonging to each of the physical coding sublayer channels;

[0085] Filtering target configuration information corresponding to the physical coding sublayer channel from the configuration information;

[0086] The field modification information is converted for the target data segment in the sub-data stream according to the target configuration information.

[0087] Optionally, in an embodiment of the present application, the physical coding sublayer channel is a PCS lane (Physical Coding Sublayer lane), which is used to transmit data streams.

[0088] Optionally, in an embodiment of the present application, when the initial data stream is received and enters the test environment of the PCS sublayer, it is necessary to classify the channel data corresponding to multiple physical coding sublayer channels (PCS lanes) in the data stream. The classification can be performed according to the specific fields contained in different channel data. For example, the channel data containing the SH field and the channel data containing the AM field are classified, so that the sub-data streams of the physical coding sublayer channels corresponding to different specific fields can be obtained, and then each sub-data stream is numbered and sorted according to the numbering information carried by the specific field in each sub-data stream. For example (taking AM as an example of the specific field), a 100Gbps data stream may be decomposed into 20 5Gbps sub-data streams, and each sub-data stream is assigned to an independent PCS channel for processing. When the initial data stream enters the test environment of the PCS sublayer, the AM in each sub-data stream is first identified, and the channel number information carried by it is read, so that the PCS channel number to which each sub-data stream belongs can be determined based on the channel number information in the AM, and then the sub-data streams are sorted according to the number, and then the sub-data streams can be error-processed in order according to the sorting result.

[0089] Optionally, in an embodiment of the present application, since the configuration information records the configuration information corresponding to different types of fields, the specific fields contained in the sub-data stream in the physical coding sub-layer channel can be matched with the field types recorded in the configuration information, and the target configuration information corresponding to the physical coding sub-layer channel can be screened out from the configuration information. For example, the sub-data stream in the current physical coding sub-layer channel contains an AM field, and the target configuration information corresponding to the AM field can be screened out from the configuration information, such as the size of the error insertion cycle, the number of error insertions in a single cycle, the inversion method, etc., and the current sub-data stream is subjected to error processing according to the corresponding target configuration information.

[0090] As an optional implementation manner, converting the field modification information for the target data segment in the sub-data stream according to the target configuration information includes:

[0091] Dividing the plurality of target data segments included in the sub-data stream into a plurality of data segment sequences according to a period parameter, wherein the period parameter is used to indicate the number of the target data segments that need to be modified in a single field modification round, each of the data segment sequences includes a plurality of the target data segments that are sequentially arranged in chronological order in the sub-data stream, and there is no identical target data segment between any two of the data segment sequences;

[0092] Filtering candidate data segments of the field to be modified from each of the data segment sequences according to the filtering parameters;

[0093] Target modification information of a field in the candidate data segment is determined according to modification parameters, wherein the field modification information includes the target modification information of the candidate data segment, wherein the target configuration information includes the period parameter, the screening parameter and the modification parameter.

[0094] Optionally, in an embodiment of the present application, when modifying the fields of the sub-data stream of each PCS lane, firstly, the target data segments (e.g., data blocks containing SH or AM) in the sub-data stream are divided into multiple data segment sequences according to the cycle parameters in the configuration information. The cycle parameters specify the number of target data segments that need to be modified in a single field modification round, that is, in each cycle, a specific number of target data segments will be operated in chronological order. For example, if the cycle parameter is 10, then in each cycle, 10 consecutive target data segments with SH or AM will be modified.

[0095] Optionally, in an embodiment of the present application, a screening parameter is used to further screen candidate data segments of the fields to be modified from each data segment sequence, and the screening parameter is used to indicate how many target data segments will be selected for modification in each cycle. For example, if the screening parameter is 3, then in each data segment sequence, there are three target data segments that will be marked as candidate data segments to be modified, and the other data segments remain unchanged.

[0096] Optionally, in an embodiment of the present application, a modification parameter is used to determine which fields in the candidate data segment will be modified and how to modify them. For example, the modification parameter may specify an inversion operation on a specific bit of SH or AM. For example, for SH, assuming that the identified SH is 0b10, if the modification parameter is configured as 1, SH will be set to 0b00; if the modification parameter is configured as 2, SH will be set to 0b11; if the modification parameter is configured as 3, SH will be set to 0b01. For AM, the size of an AM is 66 bits. For example, when the modification parameter of PCS lane 0 is configured as 0x0011, it means that bit 0 and bit 4 of AM of PCS lane 0 are inverted.

[0097] As an optional implementation manner, the step of selecting candidate data segments of the field to be modified from each of the data segment sequences according to the screening parameters includes:

[0098] Detect the target screening type indicated by the Screening Type field;

[0099] A target number of candidate data segments are screened out from the data segment sequence according to a screening method indicated by the target screening type, wherein the screening parameters include the screening type field and the target number.

[0100] Optionally, in an embodiment of the present application, the screening type field is used to indicate a method for selecting candidate data segments for the field to be modified from a data segment sequence. The screening type may include but is not limited to interval screening, random screening, sequential screening, etc., and this solution does not limit this.

[0101] For example, when the filter type is interval filter, it is specified that starting from the start position of the data segment sequence, a data segment is selected at every specific position as a candidate data segment. For example, if it is configured as "every 3", then every 3rd, 6th, 9th... data segment in the data segment sequence will be selected as a candidate data segment.

[0102] As an optional implementation manner, the screening out a target number of candidate data segments from the data segment sequence according to the screening method indicated by the target screening type includes:

[0103] In the case where the target screening type is a random screening type, randomly screening the target number of data segments from the data segment sequence to determine as the candidate data segments;

[0104] In the case where the target screening type is a sequential screening type, the target number of data segments in the data segment sequence that are arranged at the front end of the sequence are determined as the candidate data segments.

[0105] Optionally, in an embodiment of the present application, when the target screening type is configured as a random screening type, a target number of data segments are randomly selected from the data segment sequence to be determined as candidate data segments. This screening method can simulate the randomness and uncertainty of data errors during data transmission, and is suitable for testing the chip's processing capabilities when faced with unexpected, randomly occurring data anomalies.

[0106] Optionally, in the embodiment of the present application, when the target screening type is configured as a sequential screening type, a target number of data segments at the front of the sequence in the data segment sequence will always be selected as candidate data segments in each cycle. This screening method can simulate the scenario of continuous abnormal data during data transmission, and can evaluate the processing capability and stability of the chip when facing continuous abnormal data streams.

[0107] As an optional implementation manner, locating the target data segment included in the initial data stream received by the switching chip includes:

[0108] The fields included in the initial data stream are screened in sequence to obtain a first data segment in the initial data stream, wherein the first data segment is the target data segment that appears for the first time in the initial data stream;

[0109] According to the arrangement of the target data segments, a second data segment is located from the data located after the first data segment in the initial data stream, wherein the second data segment is the target data segment located after the first data segment in the initial data stream.

[0110] Optionally, in the embodiment of the present application, the target data segment is located from the initial data stream by first starting from the starting position of the initial data stream and detecting the fields in the data stream one by one until the first field that meets the definition of the target data segment is identified. For example, if the target data segment is a data segment containing SH, the initial data stream is scanned to find a 2-bit synchronization header (0b01 or 0b10), and the first data segment containing SH found is used as the first data segment.

[0111] Optionally, in an embodiment of the present application, the arrangement of the target data segments follows specific rules defined by the protocol. For example, for SH, according to the protocol, the interval between SH and SH is fixed, usually 66 bits, that is, each SH will be followed by 64 bits of payload data, and the next SH.

[0112] As an optional implementation manner, locating the second data segment from the data located after the first data segment in the initial data stream according to the arrangement of the target data segment includes:

[0113] Acquire a character spacing corresponding to a data segment type to which the target data segment belongs, wherein the character spacing is used to indicate a spacing between adjacent target data segments in a data stream;

[0114] Filter out target characters from the data located after the first data segment in the initial data stream according to the character spacing;

[0115] In a case where the target character is a character corresponding to a data segment of the data segment type, the target character is determined to be the second data segment.

[0116] Optionally, in the embodiment of the present application, character spacing refers to a fixed interval between adjacent target data segments in a data stream. Depending on the different rates of the Ethernet protocol, the character spacing of different types of fields may be different. For example, for SH, in the data stream of the PCS sublayer, its character spacing is 66 bits, that is, each SH is followed by 66 bits until the next SH appears; for AM, its character spacing depends on the specific protocol rate.

[0117] Optionally, in an embodiment of the present application, taking SH as an example, according to the Ethernet protocol, the SH interval is 66 bits. Therefore, after finding the first SH, 66 bits will be skipped backward in the data stream, and then the next 2-bit field will be checked whether it is SH. If the found 2-bit field is 0b01 or 0b10, it is confirmed that the second SH is found, and the data segment where the valid SH found after the first data segment is located is determined as the second data segment; if it does not match, continue to search according to the protocol interval until the next valid SH field is found.

[0118] In order to better understand the above process, the above process is described below in conjunction with an optional embodiment, but it is not intended to limit the technical solution of the embodiment of the present application.

[0119] The present application also provides an abnormal Sync header / Alignment marker insertion test tool and test method integrated in the PCS sublayer. The basic idea of ​​this solution is to add a set of block locking and AM locking modules at the rx direction entrance of the PCS sublayer, and on this basis, add a set of inversion logic to perform custom inversion operations on the locked SH / AM, and then construct illegal abnormal SH / AM to test the rx end's ability and robustness to handle exceptions. In the chip testing phase, it can effectively verify whether the Ethernet switching chip PCS block locking and AM synchronization functions meet the protocol requirements.

[0120] Specific:

[0121] 1. SH / AM is inserted into the wrong tool position:

[0122] Figure 3 is a relationship diagram between a PCS and an OSI reference model at a rate of 40G or higher according to an embodiment of the present application, Figure 4 is a new relationship diagram between PCS and OSI reference model according to an embodiment of the present application, Figure 3 Based on the reference model shown, Figure 4 As shown, before the PCS receives the data stream sent by the FEC / PMA, a set of SH / AM error insertion tools is added. The error insertion tools will identify and process the data stream and then send it to the PCS.

[0123] 2. Identification and locking function of SH / AM wrong insertion tool:

[0124] To accurately detect SH and AM misinsertion, you first need to identify and lock SH and AM. Different speeds correspond to different numbers of PCS lanes. For example, 40G has 4 PCS lanes and 100G has 20 PCS lanes. Each PCS lane has an independent SH identification and locking process.

[0125] Figure 5 is a SH identification and locking flow chart according to an embodiment of the present application, such as Figure 5 As shown, the SH identification and locking process is as follows:

[0126] S0: Initialize SH identification lock process after SH / AM misinsertion tool is enabled, rx_block_lock = 0, reset counter, sh_cnt = 0, sh_invalid_cnt = 0; jump to S1;

[0127] S1: Search for the first valid SH in the current pcs lane data stream, and after finding it, count the counter sh_cnt++; jump to S3;

[0128] S2: According to the last valid SH, take the next 2 bits as the next SH with an interval of 66 bits, and judge whether it is a valid SH. If it is a valid SH, then sh_cnt++. Jump to S3; if it is an invalid SH, then sh_invalid_cnt=1, and jump to S5;

[0129] S3: When sh_cnt<64, jump to S2; when sh_cnt=64, jump to S4;

[0130] S4: The current pcs lane implements block lock, rx_block_lock=1, set sh_cnt=63, jump to S2;

[0131] S5: The current SH is an invalid SH, the synchronization header (SH) is unlocked, rx_block_lock=0, and jumps to S0.

[0132] Similarly, each pcs lane has an independent set of AM identification and locking processes, and the AM identification and locking process starts after the pcs lane completes the SH identification and locking.

[0133] Figure 6 is a flowchart of AM identification and locking according to an embodiment of the present application, such as Figure 6 As shown, the AM identification and locking process is as follows:

[0134] S0: Initialize AM identification and locking process after SH identification and locking, am_lock = 0, jump to S1;

[0135] S1: Search for the first AM in the current pcs lane data stream. If AM is valid, record the current AM field to first_am and jump to S2; if AM is invalid, jump to S0;

[0136] S2: Search for the next AM field according to the protocol interval (different rates have different fixed intervals), compare the found AM field with first_am, if they are the same, jump to S3, if they are different, jump to S4;

[0137] S3: The current pcs lane achieves AM lock, am_lock = 1, jump to S2;

[0138] S4: The current pcs lane AM is unlocked, am_lock=0, jump to S0.

[0139] 3. The wrong insertion (misplacement) function of the SH / AM wrong insertion tool:

[0140] The following are the SH's misinsertion functions:

[0141] The data flow of PCS lane is in blocks, each block is 66 bits, the first 2 bits are syncheader (SH), the last 64 bits are payload, SH is 0b01 for data block and 0b10 for control block. Through insertion error, SH changes to illegal values ​​0b00 and 0b11, or SH does not match the payload.

[0142] Figure 7 is a diagram of a SH plug-in error function interface according to an embodiment of the present application, such as Figure 7 As shown, from 40G to 400G, the number of PCS lanes ranges from 1 to 20. One or more PCS lanes can be configured to enable the SH error insertion function through PcsShErrInsertLane0~19. PcsShErrInsertBitsLane0~19 can configure which bit of SH is inverted. Assuming that the identified SH is 0b10, if the interface is configured with 1, SH will be set to 0b00; if the interface is configured with 2, SH will be set to 0b11; if the interface is configured with 3, SH will be set to 0b01. PcsShErrInsertCyclesLane0~19 is used to configure the error insertion cycle size, in units of 66bits block. PcsShErrInsertCntLane0~19 is used to configure the number of error insertions in a cycle. Assuming that it is configured with 3, the first three SHs in each cycle will be inserted incorrectly. The above interfaces are all provided per pcs lane. Figure 8 This is a simplified diagram of a data flow configuration SH plugged into a wrong interface according to an embodiment of the present application.

[0143] Fig. 9 is a flow chart of SH identification error insertion according to an embodiment of the present application, such as Fig. 9As shown, the data stream of PMA / FEC is sent to the SH identification and insertion error module on the corresponding PCS lane. The SH identification is locked first, and the block information is synchronized to the insertion error module after locking. The insertion error module inserts the SH error according to the configured insertion error cycle, insertion error number, etc., and sends the data to the AM identification and insertion error module (optional).

[0144] The following is the AM's mis-insertion function:

[0145] After the data stream on the PCS lane completes AM identification and locking, the AM error insertion function interface is configured to perform the error insertion.

[0146] Fig.10 is a diagram of an AM plug-in error function interface according to an embodiment of the present application, such as Fig.10 As shown, one or more PCS lanes can be configured to enable the AM error insertion function through PcsAmErrInsertLane0~19. PcsAmErrInsertBitsLane0~19 can configure which AM bits are inverted. The size of an AM is 66 bits. For example, when PcsAmErrInsertBitsLane0 is configured as 0x0011, it means that bit0 and bit 4 of the AM of PCS lane 0 are inverted. PcsAmErrInsertCyclesLane0~19 are used to configure the error insertion cycle size. For example, if PcsAmErrInsertCyclesLane0 is configured as 10, it means that PCS lane 0 inserts errors with 10 AMs as a cycle. PcsAmErrInsertCntLane0~19 are used to configure the number of error insertions in a cycle. For example, if PcsAmErrInsertCntLane0 is configured as 3, the first 3 AMs in each AM cycle of PCS lane 0 will be inserted incorrectly. The above interfaces are all provided per pcs lane. Fig.11 This is a simplified diagram of a data flow configuration in which an AM is inserted into a wrong interface according to an embodiment of the present application.

[0147] Fig.12 is a flow chart of an AM identifying misinsertion according to an embodiment of the present application, such as Fig.12 The data stream of PMA / FEC shown is sent to the AM error identification module on the corresponding PCS lane (if the SH error identification function is enabled, the data stream should be processed by SH error identification before being sent to the AM error identification module). AM identification is locked first, and after locking, the AM block information is synchronized to the error insertion module. The error insertion module inserts the AM block according to the configured error insertion cycle, number of error insertions, error insertion position, etc., and sends the data to the next module.

[0148] This solution provides a Sync header / Alignment marker insertion tool integrated in the PCS sublayer, which can accurately and effectively implement the periodic Sync header / Alignment marker insertion function, greatly facilitating SH / AM-related tests, as well as the PCS module's ability to handle exceptions and robustness. Through this application solution, through the SH / AM insertion tool integrated in the PCS sublayer, the sync header and alignment marker in the data stream are identified and the sync header and alignment marker are inserted (misplaced) according to the custom configuration. During the chip testing phase, it can be effectively verified whether the Ethernet switch chip PCS block locking and AM synchronization functions meet the protocol requirements.

[0149] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software and a necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the latter is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a digital logic circuit and a corresponding RTL (register transfer language), and the computer software product is stored in a storage medium (such as ROM / RAM, a disk, or an optical disk), including a number of instructions for a terminal device (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods of each embodiment of the present application.

[0150] Fig.13 is a structural block diagram of a chip performance testing device according to an embodiment of the present application; Fig.13 As shown, including:

[0151] A positioning module 1302 is used to respond to a target test request and locate a target data segment included in an initial data stream received by the switching chip, wherein the target test request is used to test the decoding performance of the physical coding sublayer of the switching chip on a data stream of a target data segment having a misaligned field;

[0152] The conversion module 1304 is used to convert the field modification information of each target data segment according to the configuration information of the switching chip, wherein the configuration information is used to indicate the field modification mode of the target data segment in the data stream received by the switching chip;

[0153] A modification module 1306, configured to perform field modification on the target data segment corresponding to the initial data stream according to the modification method indicated by the field modification information, so as to obtain a target data stream;

[0154] The sending module 1308 is configured to send the target data stream to the physical coding sublayer.

[0155] Through the above embodiment, by locating the target data segment from the initial data stream received by the switching chip, and converting the field modification information for each target data segment according to the configuration information for indicating the field modification method of the target data segment in the data stream received by the switching chip, the field modification of each target data segment can be performed according to the modification method indicated by the field modification information to obtain the target data stream, and finally the target data stream is sent to the physical coding sublayer to test the decoding performance of the physical coding sublayer of the switching chip for the data stream of the target data segment with misaligned fields. The above technical solution solves the problem of low test efficiency of the chip decoding abnormal data stream performance in the related art, and achieves the technical effect of improving the test efficiency of the chip decoding abnormal data stream performance.

[0156] Optionally, the conversion module includes:

[0157] a classification unit, configured to classify channel data corresponding to a plurality of physical coding sublayer channels included in the initial data stream, to obtain a sub-data stream belonging to each of the physical coding sublayer channels;

[0158] A first screening unit, configured to screen out target configuration information corresponding to the physical coding sublayer channel from the configuration information;

[0159] A conversion unit is used to convert the field modification information for the target data segment in the sub-data stream according to the target configuration information.

[0160] Optionally, the conversion unit is further used for:

[0161] Dividing the plurality of target data segments included in the sub-data stream into a plurality of data segment sequences according to a period parameter, wherein the period parameter is used to indicate the number of the target data segments that need to be modified in a single field modification round, each of the data segment sequences includes a plurality of the target data segments that are sequentially arranged in chronological order in the sub-data stream, and there is no identical target data segment between any two of the data segment sequences;

[0162] Filtering candidate data segments of the field to be modified from each of the data segment sequences according to the filtering parameters;

[0163] Target modification information of a field in the candidate data segment is determined according to modification parameters, wherein the field modification information includes the target modification information of the candidate data segment, wherein the target configuration information includes the period parameter, the screening parameter and the modification parameter.

[0164] Optionally, the conversion unit is further used for:

[0165] Detect the target screening type indicated by the Screening Type field;

[0166] A target number of candidate data segments are screened out from the data segment sequence according to a screening method indicated by the target screening type, wherein the screening parameters include the screening type field and the target number.

[0167] Optionally, the conversion unit is further used for:

[0168] In the case where the target screening type is a random screening type, randomly screening the target number of data segments from the data segment sequence to determine as the candidate data segments;

[0169] In the case where the target screening type is a sequential screening type, the target number of data segments in the data segment sequence that are arranged at the front end of the sequence are determined as the candidate data segments.

[0170] Optionally, the positioning module includes:

[0171] A second screening unit is used to screen the fields included in the initial data stream in sequence to obtain a first data segment in the initial data stream, wherein the first data segment is the target data segment that appears for the first time in the initial data stream;

[0172] A positioning unit is used to locate a second data segment from the data located after the first data segment in the initial data stream according to the arrangement of the target data segment, wherein the second data segment is the target data segment located after the first data segment in the initial data stream.

[0173] Optionally, the positioning unit is further used for:

[0174] Acquire a character spacing corresponding to a data segment type to which the target data segment belongs, wherein the character spacing is used to indicate a spacing between adjacent target data segments in a data stream;

[0175] Filter out target characters from the data located after the first data segment in the initial data stream according to the character spacing;

[0176] In a case where the target character is a character corresponding to a data segment of the data segment type, the target character is determined to be the second data segment.

[0177] An embodiment of the present application further provides a storage medium, which includes a stored program, wherein when the program is run, any of the above-mentioned chip performance testing methods is executed.

[0178] Optionally, in this embodiment, the storage medium may be configured to store program codes for executing the following steps:

[0179] S1, responding to a target test request, locating a target data segment included in an initial data stream received by a switching chip, wherein the target test request is used to test a decoding performance of a physical coding sublayer of the switching chip on a data stream of a target data segment having a misaligned field;

[0180] S2, converting field modification information for each of the target data segments according to the configuration information of the switching chip, wherein the configuration information is used to indicate a field modification method for the target data segment in the data stream received by the switching chip;

[0181] S3, modifying the field of the target data segment corresponding to the initial data stream according to the modification method indicated by the field modification information to obtain a target data stream;

[0182] S4, sending the target data stream to the physical coding sublayer.

[0183] An embodiment of the present application further provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any of the above-mentioned chip performance testing method embodiments.

[0184] Optionally, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0185] Optionally, in this embodiment, the processor may be configured to perform the following steps through a computer program:

[0186] S1, responding to a target test request, locating a target data segment included in an initial data stream received by a switching chip, wherein the target test request is used to test a decoding performance of a physical coding sublayer of the switching chip on a data stream of a target data segment having a misaligned field;

[0187] S2, converting field modification information for each of the target data segments according to the configuration information of the switching chip, wherein the configuration information is used to indicate a field modification method for the target data segment in the data stream received by the switching chip;

[0188] S3, modifying the field of the target data segment corresponding to the initial data stream according to the modification method indicated by the field modification information to obtain a target data stream;

[0189] S4, sending the target data stream to the physical coding sublayer.

[0190] Optionally, in this embodiment, the above-mentioned storage medium may include but is not limited to: a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and other media that can store program codes.

[0191] Optionally, the specific examples in this embodiment may refer to the examples described in the above embodiments and optional implementation modes, and this embodiment will not be described in detail here.

[0192] Obviously, those skilled in the art should understand that the above modules or steps of the present application can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, and optionally, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order from that herein, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present application is not limited to any specific combination of hardware and software.

[0193] The above is only a preferred implementation of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A chip performance testing method, characterized in that: include: In response to a target test request, a target data segment included in an initial data stream received by the switching chip is located, wherein the target test request is used to test a decoding performance of a physical coding sublayer of the switching chip on a data stream of a target data segment having a misaligned field; Converting field modification information for each of the target data segments according to the configuration information of the switching chip, wherein the configuration information is used to indicate a field modification method for the target data segment in the data stream received by the switching chip; Performing field modification on the target data segment corresponding to the initial data stream according to the modification mode indicated by the field modification information to obtain a target data stream; The target data stream is sent to the physical coding sublayer.

2. The method according to claim 1, characterized in that The converting the field modification information of each target data segment according to the configuration information of the switching chip includes: Classifying channel data corresponding to a plurality of physical coding sublayer channels included in the initial data stream to obtain a sub-data stream belonging to each of the physical coding sublayer channels; Filtering target configuration information corresponding to the physical coding sublayer channel from the configuration information; The field modification information is converted for the target data segment in the sub-data stream according to the target configuration information.

3. The method according to claim 2, characterized in that The converting the field modification information for the target data segment in the sub-data stream according to the target configuration information comprises: Dividing the plurality of target data segments included in the sub-data stream into a plurality of data segment sequences according to a period parameter, wherein the period parameter is used to indicate the number of the target data segments that need to be modified in a single field modification round, each of the data segment sequences includes a plurality of the target data segments that are sequentially arranged in chronological order in the sub-data stream, and there is no identical target data segment between any two of the data segment sequences; According to the screening parameters, candidate data segments of the fields to be modified are screened out from each of the data segment sequences; according to the modification parameters, target modification information of the fields in the candidate data segments is determined, wherein the field modification information includes the target modification information of the candidate data segments, wherein the target configuration information includes the periodic parameters, the screening parameters and the modification parameters.

4. The method according to claim 3, characterized in that The step of selecting candidate data segments of the field to be modified from each of the data segment sequences according to the screening parameters includes: Detect the target screening type indicated by the Screening Type field; A target number of candidate data segments are screened out from the data segment sequence according to a screening method indicated by the target screening type, wherein the screening parameters include the screening type field and the target number.

5. The method according to claim 4, characterized in that The step of selecting a target number of candidate data segments from the data segment sequence according to the screening method indicated by the target screening type includes: In the case where the target screening type is a random screening type, randomly screening the target number of data segments from the data segment sequence to determine as the candidate data segments; In the case where the target screening type is a sequential screening type, the target number of data segments in the data segment sequence that are arranged at the front end of the sequence are determined as the candidate data segments.

6. The method according to claim 1, characterized in that The step of locating a target data segment included in an initial data stream received by the switching chip includes: The fields included in the initial data stream are screened in sequence to obtain a first data segment in the initial data stream, wherein the first data segment is the target data segment that appears for the first time in the initial data stream; According to the arrangement of the target data segments, a second data segment is located from the data located after the first data segment in the initial data stream, wherein the second data segment is the target data segment located after the first data segment in the initial data stream.

7. The method according to claim 6, characterized in that The step of locating the second data segment from the data located after the first data segment in the initial data stream according to the arrangement of the target data segment comprises: Acquire a character spacing corresponding to a data segment type to which the target data segment belongs, wherein the character spacing is used to indicate a spacing between adjacent target data segments in a data stream; Filter out target characters from the data located after the first data segment in the initial data stream according to the character spacing; In a case where the target character is a character corresponding to a data segment of the data segment type, the target character is determined to be the second data segment.

8. A chip performance testing device, characterized in that: include: A positioning module, used to respond to a target test request and locate a target data segment included in an initial data stream received by the switching chip, wherein the target test request is used to test the decoding performance of the physical coding sublayer of the switching chip on a data stream of a target data segment having a misaligned field; A conversion module, used for converting field modification information for each of the target data segments according to the configuration information of the switching chip, wherein the configuration information is used for indicating a field modification mode for the target data segment in the data stream received by the switching chip; A modification module, configured to perform field modification on the target data segment corresponding to the initial data stream according to the modification method indicated by the field modification information, so as to obtain a target data stream; A sending module is used to send the target data stream to the physical coding sublayer.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium includes a stored program, wherein the program executes the method according to any one of claims 1 to 7 when executed.

10. An electronic device comprising a memory and a processor, characterized in that: A computer program is stored in the memory, and the processor is configured to execute the method according to any one of claims 1 to 7 through the computer program.

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