Decoding circuit, display driver chip and electronic equipment

Abstract

The present application discloses a decoding circuit, a display driver chip and an electronic device, and relates to the field of electronic technology. The decoding circuit is connected to a signal line, and the decoding circuit is used to: obtain a signal input by the signal line, and the signal corresponds to a signal line state; when the signal line state changes from a first state to a second state, according to the flipping situation and rotation direction of the first state to the second state, and whether the polarity of the first state is the same as the polarity of the second state, a reference signal corresponding to the change of the signal line state is output, and the reference signal is used to obtain the transmitted data. The decoding circuit in the present application is used to output a reference signal corresponding to the change of the signal line state to achieve decoding.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a decoding circuit, a display driver chip and an electronic device. Background Art

[0002] In the mobile industry processor interface (MIPI) standard, the data transmission process may include: the transmitting end maps the data to be transmitted into symbols, performs encoding operations based on the symbols to obtain the signal to be transmitted, and transmits the signal to the receiving end. After receiving the signal, the receiving end performs a decoding operation based on the signal to obtain a reference signal corresponding to the symbol, and demaps the symbol to obtain the data. The encoding operation can be implemented based on the encoding circuit, and the decoding operation can be implemented based on the decoding circuit. Summary of the invention

[0003] The present application provides a decoding circuit, a display driver chip and an electronic device, which are used to output a reference signal corresponding to a symbol based on a received signal. The technical solution is as follows:

[0004] In a first aspect, a decoding circuit is provided, which is connected to a signal line, and is used for: obtaining a signal input from the signal line, the signal corresponding to a signal line state; when the signal line state changes from a first state to a second state, according to the flipping situation and rotation direction from the first state to the second state, and whether the polarity of the first state is the same as the polarity of the second state, outputting a reference signal corresponding to the change in the signal line state, and the reference signal is used to obtain the transmitted data.

[0005] In some embodiments, the decoding circuit includes a first sub-circuit, a second sub-circuit and a third sub-circuit, and the first sub-circuit, the second sub-circuit and the third sub-circuit are respectively connected to the signal line; the first sub-circuit is used to determine the rotation direction of the first state changing to the second state, and output the rotation indication signal included in the reference signal according to the rotation direction; the second sub-circuit is used to determine the polarity of the first state and the second state, and output the polarity indication signal included in the reference signal according to whether the polarity of the first state is the same as the polarity of the second state; the third sub-circuit is used to determine the flipping situation of the first state changing to the second state, and output the flip indication signal included in the reference signal according to the flipping situation.

[0006] In some embodiments, the signals corresponding to the first state include a first signal, a second signal, and a third signal, and the signals corresponding to the second state include a fourth signal, a fifth signal, and a sixth signal; the first signal is obtained by comparing a signal transmitted by the first line and a signal transmitted by the second line received at a first time point, the second signal is obtained by comparing a signal transmitted by the second line and a signal transmitted by the third line received at a first time point, and the third signal is obtained by comparing a signal transmitted by the third line and a signal transmitted by the first line received at a first time point; the fourth signal is obtained by comparing a signal transmitted by the first line and a signal transmitted by the second line received at a second time point, the fifth signal is obtained by comparing a signal transmitted by the second line and a signal transmitted by the third line received at a second time point, and the sixth signal is obtained by comparing a signal transmitted by the third line and a signal transmitted by the first line received at a second time point, and the first time point is earlier than the second time point.

[0007] In some embodiments, the first subcircuit is used to determine a first difference between the first signal and the fifth signal, a second difference between the second signal and the sixth signal, and a third difference between the third signal and the fourth signal; a rotation indication signal is output according to the first difference, the second difference and the third difference, and the first difference, the second difference and the third difference are used together to indicate the rotation direction.

[0008] Exemplarily, the first subcircuit includes a first XOR gate, a second XOR gate, a third XOR gate, a first XOR gate, a second XOR gate, a third XOR gate, a first NAND gate, a second NAND gate and a third NAND gate; the input end of the first XOR gate and the input end of the first XOR gate are both used to receive the first signal and the fifth signal, the input end of the second XOR gate and the input end of the second XOR gate are both used to receive the second signal and the sixth signal, and the input end of the third XOR gate and the input end of the third XOR gate are both used to receive the third signal and the fourth signal; the output end of the first XOR gate, the output end of the second XOR gate and the output end of the third XOR gate are all connected to the input end of the first NAND gate, the output end of the first XOR gate, the output end of the second XOR gate and the output end of the third XOR gate are all connected to the input end of the second NAND gate; the output end of the first NAND gate and the output end of the second NAND gate are both connected to the input end of the third NAND gate, and the output end of the third NAND gate is used to output a rotation indication signal.

[0009] In some embodiments, the second subcircuit is used to determine the polarity of the first state based on the first signal, the second signal and the third signal; determine the polarity of the second state based on the fourth signal, the fifth signal and the sixth signal; and output a polarity indication signal based on whether the polarity of the first state is the same as the polarity of the second state.

[0010] Exemplarily, the second subcircuit includes a fourth XOR gate, a fifth XOR gate, a sixth XOR gate, a seventh XOR gate and a fourth XOR gate; in the first signal, the second signal and the third signal, the input end of the fourth XOR gate is used to receive any two signals, the input end of the fifth XOR gate is used to receive the remaining signal, and the input end of the fifth XOR gate is also connected to the output end of the fourth XOR gate; in the fourth signal, the fifth signal and the sixth signal, the input end of the sixth XOR gate is used to receive any two signals, the input end of the seventh XOR gate is used to receive the remaining signal, and the input end of the seventh XOR gate is also connected to the output end of the sixth XOR gate; the input end of the fourth XOR gate is respectively connected to the output end of the fifth XOR gate and the output end of the seventh XOR gate, and the output end of the fourth XOR gate is used to output a polarity indication signal.

[0011] In some embodiments, the third sub-circuit is used to determine a fourth difference between the first signal and the fourth signal, a fifth difference between the second signal and the fifth signal, and a sixth difference between the third signal and the sixth signal; and output a flip indication signal according to the fourth difference, the fifth difference and the sixth difference.

[0012] Exemplarily, the third sub-circuit includes a fifth XOR gate, a sixth XOR gate, a seventh XOR gate, a fourth NAND gate and a NOT gate; the input end of the fifth XOR gate is used to receive the first signal and the fourth signal, the input end of the sixth XOR gate is used to receive the second signal and the fifth signal, and the input end of the seventh XOR gate is used to receive the third signal and the sixth signal; the input end of the fourth NAND gate is respectively connected to the output ends of the fifth XOR gate, the sixth XOR gate and the seventh XOR gate, the input end of the NOT gate is connected to the output end of the fourth NAND gate, and the NOT gate is used to output a flip indication signal.

[0013] In a second aspect, a display driver chip is provided, and the display driver chip includes any decoding circuit in the first aspect.

[0014] In a third aspect, an electronic device is provided, and the electronic device includes the display driver chip in the second aspect.

[0015] The technical solution provided by this application brings at least the following beneficial effects:

[0016] The decoding circuit in the present application is used to output a reference signal corresponding to the change in the state of the signal line when the state of the signal line corresponding to the signal changes from the first state to the second state according to the flipping situation and rotation direction of the first state to the second state, and whether the polarity of the first state is the same as the polarity of the second state. Based on this method of obtaining the structure of the decoding circuit, the structure of the decoding circuit can be obtained based on fewer gate-level components, thereby obtaining a decoding circuit with a smaller size, a simpler structure, lower power consumption and a faster speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a schematic diagram of a C-PHY transmission link model provided in an embodiment of the present application;

[0018] Figure 2 is a structural schematic diagram of a data clock recovery device provided in an embodiment of the present application;

[0019] Figure 3 is a schematic diagram of a change in a signal line state provided by an embodiment of the present application;

[0020] Figure 4 is a schematic diagram of a rotation indication signal provided in an embodiment of the present application;

[0021] Figure 5 is a structural schematic diagram of a first sub-circuit provided in an embodiment of the present application;

[0022] Figure 6 is a schematic diagram of a polarity indication signal provided in an embodiment of the present application;

[0023] Figure 7 is a structural schematic diagram of a second sub-circuit provided in an embodiment of the present application;

[0024] Figure 8 is a schematic diagram of a flip indication signal provided in an embodiment of the present application;

[0025] Fig. 9 is a structural schematic diagram of a third sub-circuit provided in an embodiment of the present application;

[0026] Fig.10 is a schematic diagram of the structure of a display driver chip provided in an embodiment of the present application;

[0027] Fig.11 It is a structural schematic diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0028] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0029] In the mobile industry, the MIPI standard defines the communication interface between processors and various devices. The MIPI standard is promoted by the MIPI Alliance to promote the advancement and innovation of mobile device technology. Among the various physical layers defined by MIPI, the C physical layer (C-PHY) has a higher bandwidth for data transmission and stronger signal anti-interference ability and stability.

[0030] Signals are transmitted between the transmitter (TX) and receiver (RX) of C-PHY through three signal lines. The transmitter maps the data to be transmitted and generates symbols to be transmitted, and the value of the symbol corresponds to the change in the signal line state (wire state). Then, the transmitter performs an encoding operation based on the value of the symbol to be transmitted to obtain the signal to be transmitted. For example, the transmitter uses the value of the current symbol to encode the signal line state of the previous cycle to obtain the current signal line state, and obtains the current signal to be transmitted based on the signal line state. The transmitter controls the voltage change of the three signal lines to achieve the change of the signal line state to transmit the signal to the receiver.

[0031] After receiving the signal, the receiving end compares the signal to obtain a single-ended signal, performs a decoding operation based on the single-ended signal, and obtains a reference signal corresponding to the symbol. Among them, since the single-ended signal obtained by comparison is also determined when the signal received by the receiving end is determined, the signal received by the receiving end and the single-ended signal obtained by comparison can both be considered to correspond to the state of the signal line. In the case where the state of the signal line changes, a decoding operation is performed based on the change in the state of the signal line to obtain a reference signal corresponding to the symbol. Then, the receiving end demaps based on the symbol to obtain the transmitted data and complete the MIPI communication. The decoding operation is an indispensable part of MIPI communication, which ensures the integrity and accuracy of the data during the transmission process. Only the data obtained by correct decoding can be used by the receiving end for subsequent processing.

[0032] C-PHY can be used in various mobile devices. For example, C-PHY is used for communication between processors and other components in various mobile devices, such as display screens, cameras, memory, etc. The encoding and decoding mechanisms in C-PHY can ensure efficient and reliable communication between processors and other components in mobile devices.

[0033] Figure 1 Schematic diagram of a C-PHY transmission link model provided by an embodiment of the present application. Figure 1 As shown, the transmitting end includes a mapper, a serializer, an encoder, a driver 1, a driver 2, and a driver 3. The connection relationship between the mapper, the serializer, the encoder, the driver 1, the driver 2, and the driver 3 is as follows: Figure 1 shown.

[0034] The mapper is used to map a 16-bit data unit according to the received clock signal, generate 7 3-bit symbols, and input the 7 symbols into the serializer. The serializer is a parallel-to-serial converter, which is used to serialize the 7 received symbols and transmit one symbol at a time to the encoder. The encoder encodes the symbol into a signal transmitted through the signal line according to the value of the received symbol, and the state change of the signal line corresponds to the value of the symbol. The signal obtained based on the symbol includes signals transmitted at driver 1, driver 2 and driver 3 respectively. The signal is transmitted to the receiving end through the channel.

[0035] The receiving end includes a data and clock recovery, a decoder, a deserializer, and a demapper. The connection relationship between the data and clock recovery, the decoder, the deserializer, and the demapper is as follows: Figure 1 shown.

[0036] The data clock recovery device is used to receive signals transmitted by signal line A, signal line B and signal line C, and output six single-ended signals to the decoder based on the received signals. Among them, the six single-ended signals include three single-ended signals obtained based on the currently received signal, and three single-ended signals obtained based on the signal received in the previous time period. In the embodiment of the present application, the state of the signal line changes once after each time period. For example, after a time period, the state of the signal line changes from the +x state to the -x state. The embodiment of the present application does not limit the length of the time period.

[0037] like Figure 1 As shown, Prv_AB represents a single-ended signal obtained by comparing the signal of signal line A received in the previous time period with the signal of signal line B; Prv_BC represents a single-ended signal obtained by comparing the signal of signal line B received in the previous time period with the signal of signal line C; Prv_CA represents a single-ended signal obtained by comparing the signal of signal line C received in the previous time period with the signal of signal line A.

[0038] Prs_AB represents a single-ended signal obtained by comparing the currently received signal of signal line A with the signal of signal line B; Prs_BC represents a single-ended signal obtained by comparing the currently received signal of signal line B with the signal of signal line C; Prs_CA represents a single-ended signal obtained by comparing the currently received signal of signal line C with the signal of signal line A.

[0039] In the embodiment of the present application, Prv_AB, Prv_BC, Prv_CA, Prs_AB, Prs_BC and Prs_CA are all digital signals for illustration. Taking Prv_AB as an example, when the amplitude of the signal of signal line A received in the previous time period is greater than the amplitude of the signal of signal line B, Prv_AB obtained by comparison is 1; when the amplitude of the signal of signal line A received in the previous time period is less than the amplitude of the signal of signal line B, Prv_AB obtained by comparison is 0. The principles of Prv_BC, Prv_CA, Prs_AB, Prs_BC and Prs_CA are the same, and will not be repeated here.

[0040] Figure 2 Schematic diagram of the structure of a data clock recovery device provided by an embodiment of the present application. Figure 2 As shown in FIG. 1 , the data clock recovery device includes an equalizer (EQ), a comparator (comparator), a clock recovery device and a D flip-flop (data flip-flop, DFF). The number and connection relationship of the EQ, comparator, clock recovery device and DFF can be as follows: Figure 2 shown.

[0041] EQ is used to reduce interference on the received signal. The comparator is used to compare the amplitudes of the two input signals and output a single-ended signal based on the comparison result of the amplitudes. The clock recovery device is used to recover the clock signal based on the single-ended signal output by the comparator and output the clock signal to the DFF. The clock recovery device can be a clock and data recovery (CDR). The DFF is used to store the received single-ended signal based on the clock signal and output the single-ended signal to the decoding circuit. For example, the DFF stores the received single-ended signal at the rising edge or falling edge of the clock signal. The interval between two adjacent rising edges of the clock signal is equal to a time period. Similarly, the interval between two adjacent falling edges of the clock signal is also equal to a time period.

[0042] exist Figure 2 In the data clock recoverer shown, the signal lines connected by multiple EQs include signal line A, signal line B and signal line C. The single-ended signal output by the comparator based on the signal transmitted by signal line A and signal line B is represented as Data_AB, the single-ended signal output by the comparator based on the signal transmitted by signal line B and signal line C is represented as Data_BC, and the single-ended signal output by the comparator based on the signal transmitted by signal line C and signal line A is represented as Data_CA.

[0043] DFF 1 to DFF 3 respectively store the signal Prv_AB obtained based on Data_AB of the previous time period, the signal Prv_BC obtained based on Data_BC of the previous time period, and the signal Prv_CA obtained based on Data_CA of the previous time period. DFF 4 to DFF 6 respectively store the signal Prs_AB obtained based on the current Data_AB, the signal Prs_BC obtained based on the current Data_BC, and the signal Prs_CA obtained based on the current Data_CA.

[0044] For example, Prs_AB refers to the current Data_AB stored, Prs_BC refers to the current Data_BC stored, and Prs_CA refers to the current Data_CA stored. Prv_AB refers to the Data_AB stored in the previous time period, Prv_BC refers to the Data_BC stored in the previous time period, and Prv_CA refers to the Data_CA stored in the previous time period.

[0045] The storage situation is described by taking two adjacent rising edges of the clock signal as an example. The two adjacent rising edges are called rising edge 1 and rising edge 2. At rising edge 1, DFF 4 stores the current Data_AB, called Prs_AB, DFF 5 stores the current Data_BC, called Prs_BC, and DFF 6 stores the current Data_CA, called Prs_CA. At rising edge 2, the Prs_AB stored by DFF 4 is transferred to DFF 1 for storage. Since the Prs_AB stored by DFF 1 is the Prs_AB of the previous time period, this Prs_AB is renamed Prv_AB. Similarly, at rising edge 2, the Prs_BC stored by DFF 5 is transferred to DFF 2 for storage. Since the Prs_BC stored by DFF 2 is the Prs_BC of the previous time period, this Prs_BC is renamed Prv_BC. At rising edge 2, the Prs_CA stored in DFF 6 is transmitted to DFF 3 for storage. Since the Prs_CA stored in DFF 3 is the Prs_CA of the previous time period, this Prs_CA is renamed as Prv_CA.

[0046] Furthermore, at rising edge 2, DFF 4 stores the current Data_AB, called Prs_AB, DFF 5 stores the current Data_BC, called Prs_BC, and DFF 6 stores the current Data_CA, called Prs_CA. The principle of DFF storing the received single-ended signal at the falling edge of the clock signal is the same and will not be repeated here.

[0047] The decoder performs a decoding operation based on the six single-ended signals obtained to obtain a reference signal corresponding to the symbol. The reference signal includes a flip indication signal, a rotation indication signal, and a polarity indication signal. In an embodiment of the present application, the flip indication signal is represented by F, the rotation indication signal is represented by R, and the polarity indication signal is represented by P. The deserializer is a serial-to-parallel converter, and each reference signal received from the decoder corresponds to a symbol. After receiving the reference signal 7 times, the deserializer converts the serially received reference signal into 7 parallel symbols and transmits the 7 parallel symbols to the demapper. The demapper demaps the 7 received symbols to obtain a 16-bit data unit.

[0048] Figure 1 The encoder shown may be an encoding circuit, and the decoder may be a decoding circuit. The structure of the decoding circuit may be determined according to the reverse logic of the encoding. Before decoding, the clock signal embedded in the data needs to be recovered, and the signal line state corresponding to the single-ended signal of two adjacent time periods is sampled based on the recovered clock signal. Then, the structure of the decoding circuit may be designed by comparing the level conversion content.

[0049] In the related art, after determining the logical expression corresponding to the reverse logic of the code, the Karnaugh map is used to design the simplest AND / OR formula (Sum of Products, SOP) of this logical expression, thereby simplifying the circuit corresponding to the reverse logic of the code. However, the method of designing the simplest AND / OR formula by the Karnaugh map may become complicated and error-prone when dealing with problems with multiple input variables. When the number of input variables increases, the size of the Karnaugh map will increase rapidly, making it more difficult to manually simplify the logical expression. In addition, even if the most simplified logical expression is obtained, the circuit generated based on this logical expression may still contain a large number of gate-level components, resulting in a complex decoding circuit and high power consumption. Typically, the number of gate-level components included in the decoding circuit is more than 30.

[0050] The embodiment of the present application provides a decoding circuit, the decoding circuit is connected to the signal line, and the decoding circuit is used to: obtain a signal input by the signal line, the signal corresponds to the state of the signal line; when the state of the signal line changes from a first state to a second state, according to the flipping situation and rotation direction of the first state to the second state, and whether the polarity of the first state is the same as the polarity of the second state, output a reference signal corresponding to the change of the state of the signal line, and the reference signal is used to obtain the transmitted data. The decoding circuit provided by the embodiment of the present application can be applied to the receiving end, and the decoding circuit can also be called a decoder.

[0051] In the embodiment of the present application, the output reference signal is a reference signal corresponding to the symbol. The signal line connected to the decoding circuit is a signal line that transmits a single-ended signal. For example, the decoding circuit is Figure 1In the decoder, the signal line connected to the decoding circuit refers to the signal line connecting the decoder and the data clock recovery device. The first state refers to the signal line state corresponding to the single-ended signal of the previous time period, for example, the first state refers to the signal line state corresponding to Prv_AB, Prv_BC and Prv_CA. The second state refers to the signal line state corresponding to the current single-ended signal, for example, the second state refers to the signal line state corresponding to Prs_AB, Prs_BC and Prs_CA.

[0052] Exemplarily, the signal line state, the amplitude of the signal transmitted by the signal line, the amplitude difference of different signals, and the single-ended signal output by the comparator are shown in Table 1. For ease of explanation, in Table 1, the signal line state is referred to as state, the signal transmitted by signal line A is referred to as A, the signal transmitted by signal line B is referred to as B, and the signal transmitted by signal line C is referred to as C. In Table 1, the amplitude of the signal is expressed as a multiple of the power supply voltage, and V represents the power supply voltage. Referring to Table 1, Data_AB, Data_BC, and Data_CA are all digital signals for explanation, "1" represents a high level, and "0" represents a low level.

[0053] Table 1

[0054]

[0055]

[0056] For example, Figure 3 This is a schematic diagram of a change in a signal line state provided in an embodiment of the present application. Figure 3 Six signal line states and reference signals corresponding to changes in signal line states are shown. In the embodiment of the present application, the numbers corresponding to the signal line states are arranged in the order of Data_AB, Data_BC, and Data_CA, and the signals included in the reference signal are arranged in the order of a flip indication signal, a rotation indication signal, and a polarity indication signal. In the embodiment of the present application, taking the flip indication signal, the rotation indication signal, and the polarity indication signal as digital signals as an example, "1" represents a high level and "0" represents a low level.

[0057] based on Figure 3 The schematic diagram of the change of the signal line state is shown in FIG. 2 , and the corresponding relationship between the change of the signal line state and the reference signal is shown in Table 2.

[0058] Table 2

[0059]

[0060] In Table 2, n / a indicates that the corresponding state change does not occur. For example, when the previous signal line state is +x, the signal line state will not change to +x. 1xx indicates that the flip indication signal is 1, and the rotation indication signal and polarity indication signal are not considered, which can be any situation. 1xx occurs when the two signal line states are completely different. In the embodiment of the present application, +x is completely different from -x, +y is completely different from -y, and +z is completely different from -z.

[0061] In a possible implementation, the decoding circuit is applied to C-PHY. In this case, the number of signal lines connected to the decoding circuit may be six, and the signals transmitted by the six signal lines are obtained by processing the signals transmitted by the three signal lines connecting the transmitting end and the receiving end of C-PHY.

[0062] Exemplarily, the decoding circuit includes a first sub-circuit, a second sub-circuit and a third sub-circuit, and the first sub-circuit, the second sub-circuit and the third sub-circuit are respectively connected to the signal line; the first sub-circuit is used to determine the rotation direction of the change from the first state to the second state, and output the rotation indication signal included in the reference signal according to the rotation direction; the second sub-circuit is used to determine the polarity of the first state and the second state, and output the polarity indication signal included in the reference signal according to whether the polarity of the first state is the same as the polarity of the second state; the third sub-circuit is used to determine the flipping situation of the change from the first state to the second state, and output the flip indication signal included in the reference signal according to the flipping situation.

[0063] For example, when the rotation direction from the first state to the second state is clockwise, the rotation indication signal output by the first subcircuit is the first case; when the rotation direction from the first state to the second state is counterclockwise, the rotation indication signal output by the first subcircuit is the second case. The first case can be 1, and the second case can be 0. The rotation direction can refer to Figure 3 Rotation directions between +x, -x, +y, -y, +z and -z are shown.

[0064] For another example, when the polarity of the first state is the same as the polarity of the second state, the polarity indication signal output by the second subcircuit is the third case; when the polarity of the first state is different from the polarity of the second state, the polarity indication signal output by the second subcircuit is the fourth case. The third case can be 0, and the fourth case can be 1.

[0065] For another example, when the first state is changed to the second state by completely flipping the first state, that is, when the first state is completely different from the second state, the flip indication signal output by the third subcircuit is the fifth case; when the first state is changed to the second state by incompletely flipping the first state, that is, when the first state is not completely different from the second state, the flip indication signal output by the third subcircuit is the sixth case. The fifth case can be 1, and the sixth case can be 0.

[0066] In some embodiments, the first subcircuit, the second subcircuit and the third subcircuit are all composed of gate-level elements. Since gate-level elements consume less power than other types of circuit elements, when the first subcircuit, the second subcircuit and the third subcircuit are all composed of gate-level elements, the decoding circuit has a lower complexity and a higher speed.

[0067] In some embodiments, the signals corresponding to the first state include a first signal, a second signal, and a third signal, and the signals corresponding to the second state include a fourth signal, a fifth signal, and a sixth signal. The first signal is obtained by comparing the signal transmitted by the first line and the signal transmitted by the second line received at the first time point, the second signal is obtained by comparing the signal transmitted by the second line and the signal transmitted by the third line received at the first time point, and the third signal is obtained by comparing the signal transmitted by the third line and the signal transmitted by the first line received at the first time point; the fourth signal is obtained by comparing the signal transmitted by the first line and the signal transmitted by the second line received at the second time point, the fifth signal is obtained by comparing the signal transmitted by the second line and the signal transmitted by the third line received at the second time point, and the sixth signal is obtained by comparing the signal transmitted by the third line and the signal transmitted by the first line received at the second time point, and the first time point is earlier than the second time point.

[0068] In the embodiment of the present application, the first line can be Figure 2 The signal line A shown, the second line can be Figure 2 The signal line B shown, the third line can be Figure 2 The first time point may be a time point of the previous time period, and the second time point may be a time point of the current time period. Figure 2 In the data clock recovery device shown, the first signal may be Prv_AB, the second signal may be Prv_BC, the third signal may be Prv_CA, the fourth signal may be Prs_AB, the fifth signal may be Prs_BC, and the sixth signal may be Prs_CA.

[0069] In some embodiments, the first subcircuit is used to determine a first difference between the first signal and the fifth signal, a second difference between the second signal and the sixth signal, and a third difference between the third signal and the fourth signal; a rotation indication signal is output according to the first difference, the second difference and the third difference, and the first difference, the second difference and the third difference are used together to indicate the rotation direction.

[0070] For example, when the first difference situation indicates that the first signal is the same as the fifth signal, the second difference situation indicates that the second signal is the same as the sixth signal, and the third difference situation indicates that the third signal is the same as the fourth signal, the first difference situation, the second difference situation, and the third difference situation are used together to indicate that the rotation direction is clockwise rotation, and the rotation indication signal output by the first subcircuit is the first situation; when the first difference situation indicates that the first signal is different from the fifth signal, the second difference situation indicates that the second signal is different from the sixth signal, and the third difference situation indicates that the third signal is different from the fourth signal, the first difference situation, the second difference situation, and the third difference situation are also used together to indicate that the rotation direction is clockwise rotation, and the rotation indication signal output by the first subcircuit is the first situation; otherwise, the first difference situation, the second difference situation, and the third difference situation are used together to indicate that the rotation direction is counterclockwise rotation, and the rotation indication signal output by the first subcircuit is the second situation. The first situation can be 1, and the second situation can be 0.

[0071] Figure 4 is a schematic diagram of a rotation indication signal provided by an embodiment of the present application. Figure 4 As shown, when the rotation direction from the first state to the second state is clockwise, the rotation indication signal is 1; when the rotation direction from the first state to the second state is counterclockwise, the rotation indication signal is 0.

[0072] Figure 5 is a schematic diagram of the structure of a first sub-circuit provided in an embodiment of the present application. Figure 5As shown, the first subcircuit includes a first XOR gate, a second XOR gate, a third XOR gate, a first XOR gate, a second XOR gate, a third XOR gate, a first NAND gate, a second NAND gate and a third NAND gate. The input end of the first XOR gate and the input end of the first XOR gate are both used to receive the first signal and the fifth signal, the input end of the second XOR gate and the input end of the second XOR gate are both used to receive the second signal and the sixth signal, and the input end of the third XOR gate and the input end of the third XOR gate are both used to receive the third signal and the fourth signal. The output end of the first XOR gate, the output end of the second XOR gate and the output end of the third XOR gate are all connected to the input end of the first NAND gate. The output end of the first XOR gate, the output end of the second XOR gate and the output end of the third XOR gate are all connected to the input end of the second NAND gate. The output end of the first NAND gate and the output end of the second NAND gate are both connected to the input end of the third NAND gate, and the output end of the third NAND gate is used to output a rotation indication signal.

[0073] exist Figure 5 In the first subcircuit shown, the first subcircuit includes 9 gate-level elements, so the number of gate-level elements included in the first subcircuit is small, the first subcircuit has a small size, a simple structure, low power consumption, and a high speed.

[0074] In some embodiments, the second subcircuit is used to determine the polarity of the first state according to the first signal, the second signal and the third signal; determine the polarity of the second state according to the fourth signal, the fifth signal and the sixth signal; and output a polarity indication signal according to whether the polarity of the first state is the same as the polarity of the second state. For example, when the polarity of the first state is the same as the polarity of the second state, the polarity indication signal output by the second subcircuit is the third case; when the polarity of the first state is different from the polarity of the second state, the polarity indication signal output by the second subcircuit is the fourth case. The third case can be 0, and the fourth case can be 1.

[0075] Figure 6 is a schematic diagram of a polarity indication signal provided in an embodiment of the present application. Figure 6 As shown, when the polarity of the first state and the polarity of the second state are both negative, or the polarity of the first state and the polarity of the second state are both positive, the polarity indication signal is 0; otherwise, the polarity indication signal is 1.

[0076] Exemplarily, the second subcircuit includes a fourth same-or gate, a fifth same-or gate, a sixth same-or gate, a seventh same-or gate and a fourth x-or gate. In the first signal, the second signal and the third signal, the input end of the fourth same-or gate is used to receive any two of the three signals, the input end of the fifth same-or gate is used to receive the remaining one signal, and the input end of the fifth same-or gate is also connected to the output end of the fourth same-or gate. In the fourth signal, the fifth signal and the sixth signal, the input end of the sixth same-or gate is used to receive any two of the three signals, the input end of the seventh same-or gate is used to receive the remaining one signal, and the input end of the seventh same-or gate is also connected to the output end of the sixth same-or gate. The input end of the fourth x-or gate is respectively connected to the output end of the fifth same-or gate and the output end of the seventh same-or gate, and the output end of the fourth x-or gate is used to output a polarity indication signal.

[0077] Figure 7 It is a structural schematic diagram of a second sub-circuit provided in an embodiment of the present application. Figure 7 For example, the first signal and the second signal are input into the fourth XOR gate, the third signal is input into the fifth XOR gate, the fourth signal and the fifth signal are input into the sixth XOR gate, and the sixth signal is input into the seventh XOR gate.

[0078] exist Figure 7 In the second sub-circuit shown, the second sub-circuit includes 5 gate-level elements, so the number of gate-level elements included in the second sub-circuit is small, the second sub-circuit has a small size, a simple structure, low power consumption, and a high speed.

[0079] In some embodiments, the third subcircuit is used to determine a fourth difference between the first signal and the fourth signal, a fifth difference between the second signal and the fifth signal, and a sixth difference between the third signal and the sixth signal; and output a flip indication signal according to the fourth difference, the fifth difference, and the sixth difference. For example, when the fourth difference signal indicates that the first signal is different from the fourth signal, the fifth difference signal indicates that the second signal is different from the fifth signal, and the sixth difference signal indicates that the third signal is different from the sixth signal, the first state is completely different from the second state, and the flip indication signal output by the third subcircuit is the fifth state; otherwise, the first state is not completely different from the second state, and the flip indication signal output by the third subcircuit is the sixth state.

[0080] The fifth case may be 1, and the sixth case may be 0.

[0081] Figure 8 Schematic diagram of a flip indication signal provided by an embodiment of the present application. Figure 8 As shown, when the first state and the second state are completely different, the flip indication signal is 1, otherwise it is 0.

[0082] Fig. 9is a schematic diagram of the structure of a third sub-circuit provided in an embodiment of the present application. Fig. 9 As shown, the third sub-circuit includes a fifth XOR gate, a sixth XOR gate, a seventh XOR gate, a fourth NAND gate and a NOT gate. The input end of the fifth XOR gate is used to receive the first signal and the fourth signal, the input end of the sixth XOR gate is used to receive the second signal and the fifth signal, the input end of the seventh XOR gate is used to receive the third signal and the sixth signal, the input end of the fourth NAND gate is connected to the output ends of the fifth XOR gate, the sixth XOR gate and the seventh XOR gate respectively, the input end of the NOT gate is connected to the output end of the fourth NAND gate, and the NOT gate is used to output a flip indication signal.

[0083] exist Fig. 9 In the third sub-circuit shown, the third sub-circuit includes 5 gate-level elements, so the number of gate-level elements included in the third sub-circuit is small, the third sub-circuit has a small size, a simple structure, low power consumption, and a high speed.

[0084] The decoding circuit provided in the embodiment of the present application is used to output a reference signal corresponding to the change in the state of the signal line according to the flipping situation and rotation direction of the first state to the second state, and whether the polarity of the first state is the same as the polarity of the second state, when the state of the signal line corresponding to the signal changes from the first state to the second state. Based on this method of obtaining the structure of the decoding circuit, the structure of the decoding circuit can be obtained based on fewer gate-level components, thereby obtaining a decoding circuit with a smaller size, a simpler structure, lower power consumption and a faster speed.

[0085] In an exemplary embodiment, a display driver chip is further provided, and the chip includes any one of the above-mentioned decoding circuits. Fig.10 is a schematic diagram of the structure of a display driver chip provided in an embodiment of the present application, such as Fig.10 As shown, the display driver chip includes a decoding circuit. The display driver chip may also include other circuits, such as Fig.10 The display driver chip also includes a data clock recovery device, a deserializer and a demapper. The connection relationship between the data clock recovery device, the decoding circuit, the deserializer and the demapper is as follows: Fig.10 The display driver chip may also include Figure 1 The circuit included in the transmitting end shown is not limited in the embodiment of the present application.

[0086] In an exemplary embodiment, an electronic device is also provided, and the electronic device may include the above-mentioned display driver chip. The electronic device may have relatively large differences due to different configurations or performances. For example, the electronic device may also include one or more processors, and the processor may be a central processing unit (CPU). The electronic device may also have components such as a memory, a wired or wireless network interface, a keyboard, and an input and output interface for storage and input and output. The electronic device may also include other components for realizing the functions of the device, which will not be repeated here.

[0087] Fig.11 Schematic diagram of the structure of an electronic device provided in an embodiment of the present application. Fig.11 As shown, the electronic device includes a display driver chip and a display, and the display driver chip is used to drive the display to display an image. For example, the transmitted data is image data, and after the display driver chip obtains the image data, it drives the display to display an image corresponding to the image data.

[0088] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, stored data, displayed data, etc.) and signals involved in this application are all authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant laws, regulations and standards of relevant countries and regions.

[0089] It should be understood that the "plurality" mentioned in this article refers to two or more. "And / or" describes the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the associated objects are in an "or" relationship.

[0090] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein.

[0091] The embodiments described in the above exemplary embodiments do not represent all embodiments consistent with the present application. Instead, they are only examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0092] The above are merely exemplary embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. A decoding circuit, characterized in that: The decoding circuit is connected to the signal line, and the decoding circuit is used for: Acquire a signal inputted by the signal line, wherein the signal corresponds to a state of the signal line; When the state of the signal line changes from a first state to a second state, a reference signal corresponding to the change in the state of the signal line is output based on the flipping situation and rotation direction of the first state to the second state, and whether the polarity of the first state is the same as the polarity of the second state, and the reference signal is used to obtain the transmitted data.

2. The decoding circuit according to claim 1, characterized in that: The decoding circuit comprises a first sub-circuit, a second sub-circuit and a third sub-circuit, wherein the first sub-circuit, the second sub-circuit and the third sub-circuit are respectively connected to the signal line; The first subcircuit is used to determine a rotation direction when the first state changes to the second state, and output a rotation indication signal included in the reference signal according to the rotation direction; The second sub-circuit is used to determine the polarities of the first state and the second state, and output a polarity indication signal included in the reference signal according to whether the polarity of the first state is the same as the polarity of the second state; The third sub-circuit is used to determine a flipping situation in which the first state changes to the second state, and output a flipping indication signal included in the reference signal according to the flipping situation.

3. The decoding circuit according to claim 2, characterized in that: The signals corresponding to the first state include a first signal, a second signal and a third signal, and the signals corresponding to the second state include a fourth signal, a fifth signal and a sixth signal; The first signal is obtained by comparing a signal transmitted by a first line and a signal transmitted by a second line received at a first time point, the second signal is obtained by comparing a signal transmitted by the second line and a signal transmitted by a third line received at the first time point, and the third signal is obtained by comparing a signal transmitted by the third line and a signal transmitted by the first line received at the first time point; The fourth signal is obtained by comparing the signal transmitted by the first line and the signal transmitted by the second line received at the second time point, the fifth signal is obtained by comparing the signal transmitted by the second line and the signal transmitted by the third line received at the second time point, and the sixth signal is obtained by comparing the signal transmitted by the third line and the signal transmitted by the first line received at the second time point, and the first time point is earlier than the second time point.

4. The decoding circuit according to claim 3, characterized in that: The first sub-circuit is used to determine a first difference between the first signal and the fifth signal, a second difference between the second signal and the sixth signal, and a third difference between the third signal and the fourth signal; and output the rotation indication signal according to the first difference, the second difference and the third difference, the first difference, the second difference and the third difference are jointly used to indicate the rotation direction.

5. The decoding circuit according to claim 4, characterized in that: The first sub-circuit includes a first XOR gate, a second XOR gate, a third XOR gate, a first XOR gate, a second XOR gate, a third XOR gate, a first NAND gate, a second NAND gate and a third NAND gate; The input end of the first XOR gate and the input end of the first XOR gate are both used to receive the first signal and the fifth signal, the input end of the second XOR gate and the input end of the second XOR gate are both used to receive the second signal and the sixth signal, and the input end of the third XOR gate and the input end of the third XOR gate are both used to receive the third signal and the fourth signal; The output end of the first XOR gate, the output end of the second XOR gate and the output end of the third XOR gate are all connected to the input end of the first NAND gate, the output end of the first XOR gate, the output end of the second XOR gate and the output end of the third XOR gate are all connected to the input end of the second NAND gate; the output end of the first NAND gate and the output end of the second NAND gate are both connected to the input end of the third NAND gate, and the output end of the third NAND gate is used to output the rotation indication signal.

6. The decoding circuit according to any one of claims 3 to 5, characterized in that: The second sub-circuit is used to determine the polarity of the first state according to the first signal, the second signal and the third signal; determine the polarity of the second state according to the fourth signal, the fifth signal and the sixth signal; and output the polarity indication signal according to whether the polarity of the first state is the same as the polarity of the second state.

7. The decoding circuit according to claim 6, characterized in that: The second sub-circuit includes a fourth XOR gate, a fifth XOR gate, a sixth XOR gate, a seventh XOR gate and a fourth XOR gate; Among the first signal, the second signal and the third signal, the input end of the fourth XOR gate is used to receive any two signals, the input end of the fifth XOR gate is used to receive the remaining one signal, and the input end of the fifth XOR gate is also connected to the output end of the fourth XOR gate; Among the fourth signal, the fifth signal and the sixth signal, the input end of the sixth XOR gate is used to receive any two signals, the input end of the seventh XOR gate is used to receive the remaining one signal, and the input end of the seventh XOR gate is also connected to the output end of the sixth XOR gate; The input end of the fourth XOR gate is connected to the output end of the fifth XOR gate and the output end of the seventh XOR gate respectively, and the output end of the fourth XOR gate is used to output the polarity indication signal.

8. The decoding circuit according to any one of claims 3 to 7, characterized in that: The third sub-circuit is used to determine a fourth difference between the first signal and the fourth signal, a fifth difference between the second signal and the fifth signal, and a sixth difference between the third signal and the sixth signal; and output the flip indication signal according to the fourth difference, the fifth difference and the sixth difference.

9. The decoding circuit according to claim 8, characterized in that: The third sub-circuit includes a fifth XOR gate, a sixth XOR gate, a seventh XOR gate, a fourth NAND gate and a NOT gate; The input end of the fifth XOR gate is used to receive the first signal and the fourth signal, the input end of the sixth XOR gate is used to receive the second signal and the fifth signal, and the input end of the seventh XOR gate is used to receive the third signal and the sixth signal; The input end of the fourth NAND gate is connected to the output ends of the fifth XOR gate, the sixth XOR gate and the seventh XOR gate respectively, the input end of the NOT gate is connected to the output end of the fourth NAND gate, and the NOT gate is used to output the flip indication signal.

10. A display driver chip, characterized in that: The chip comprises the decoding circuit as claimed in any one of claims 1 to 9.

11. An electronic device, characterized in that: The electronic device comprises the chip as claimed in claim 10.

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