Vertical transistor for static random access memory and manufacturing method thereof

Abstract

The invention discloses a vertical transistor for a static random access memory and a manufacturing method thereof, and relates to the technical field of integrated circuits. The vertical transistor for the static random access memory comprises a first transistor formed on a substrate; the channel material of the first transistor is indium gallium zinc oxide; an isolation layer formed on the first transistor; a second transistor formed on the isolation layer; the second transistor is an organic electrochemical transistor; at least one source-drain electrode of the second transistor is electrically connected with at least one source-drain electrode of the first transistor. The manufacturing method of the vertical transistor for the static random access memory comprises the following steps: providing a substrate; forming a first transistor on the substrate; the channel material of the first transistor is indium gallium zinc oxide. An isolation layer is formed on the first transistor. Forming a second transistor on the isolation layer; the second transistor is an organic electrochemical transistor. According to the technical scheme provided by the invention, the integration level of the organic electrochemical transistor can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a vertical transistor for static random access memory and a manufacturing method thereof. Background Art

[0002] Organic electrochemical transistors (OECTs) and their circuits benefit from their ultra-low driving voltage (<1V), low power consumption (<1μW), high transconductance (>10ms) and biocompatibility, and can be widely used in the next generation of smart sensors, bioelectronics, wearable electronics and artificial neural electronics. However, OECTs in the existing technology still have a series of problems, such as their low integration density, which greatly limits their further development and integrated applications.

[0003] In addition, electronic applications are still mainly based on silicon-based manufacturing at this stage, but the demand for higher performance, new applications and flexible integration has led to the research of new materials, including the research of oxide channel materials. Indium potassium zinc oxide (a-IGZO) has good field effect mobility (>10cm 2 / V·s), high current switching ratio, low off-state leakage current, low manufacturing process temperature (<450℃) and other properties, so the application prospects of transistors with indium potassium zinc oxide channels are good. Combining organic electrochemical transistors with indium potassium zinc oxide channel transistors can form a bistable circuit composed of two inverters, thereby realizing static random access memory function. Since the information in the static memory (binary code, 0 or 1) is memorized by a bistable circuit with memory function, the memorized information will not be lost when the power is not cut off. Summary of the invention

[0004] The object of the present invention is to provide a vertical transistor for static random access memory, so as to improve the integration level of organic electrochemical transistors.

[0005] In order to achieve the above-mentioned purpose, in a first aspect, the present invention provides a vertical transistor for a static random access memory, the vertical transistor for a static random access memory comprising: a substrate, a first transistor, an isolation layer, and a second transistor. The first transistor is formed on the substrate; the channel material of the first transistor is indium gallium zinc oxide; the isolation layer is formed on the first transistor; the second transistor is formed on the isolation layer; the second transistor is an organic electrochemical transistor; at least one source-drain electrode of the second transistor is electrically connected to at least one source-drain electrode of the first transistor.

[0006] In the case of adopting the above technical solution, the first transistor is formed on the substrate, the isolation layer is formed on the first transistor, and the second transistor is formed on the isolation layer, forming a vertical transistor for static random access memory that vertically integrates the indium gallium zinc oxide transistor and the organic electrochemical transistor. Compared with the organic electrochemical transistor formed only on a plane in the prior art, the integration is greatly improved. In addition, due to the integration with the indium gallium zinc oxide transistor, the good performance of the indium gallium zinc oxide transistor can effectively improve the performance of the vertical transistor for static random access memory provided by the present invention. In addition, since organic electrochemical transistors are usually made at a lower temperature, and the indium gallium zinc oxide transistor has a high thermal budget requirement in the process of manufacturing transistors, the first transistor and the second transistor are stacked in the above manner, which can ensure that the first transistor does not suffer structural damage when manufacturing the vertical transistor for static random access memory, and ensure the performance of the first transistor. In addition, at least one source-drain electrode of the second transistor is electrically connected to at least one source-drain electrode of the first transistor, and the first transistor and the second transistor included in the vertical transistor for static random access memory provided by the present invention can realize effective logical functions, which expands the application range of the vertical transistor for static random access memory provided by the present invention.

[0007] As a possible implementation scheme, the first transistor includes: a first electrode block, a second electrode block, a first active area, a gate dielectric layer, and a first gate electrode block; the first electrode block and the second electrode block are formed on the substrate at intervals along the thickness direction of the substrate; the first active area is formed on the first electrode block, the second electrode block, and a partial area of ​​the substrate; the partial area of ​​the substrate is the area of ​​the substrate between the first electrode block and the second electrode block; the gate dielectric layer is formed on the first electrode block, the second electrode block, the first active area, and the substrate; the material of the gate dielectric layer is a material with a high dielectric constant; the first gate electrode block is formed on the gate dielectric layer; the orthographic projection of the first gate electrode block on the substrate overlaps with the orthographic projection of the first active area on the substrate; and the isolation layer is formed on the gate dielectric layer and the first gate electrode block.

[0008] When the above technical solution is adopted, the first transistor is an indium gallium zinc oxide thin film transistor (IGZO TFT), and the gate dielectric layer is a material with a high dielectric constant, so that the gate capacitance of the first transistor is changed, the turn-on and turn-off speeds of the first transistor are accelerated, and the power consumption of the first transistor is reduced; and the control ability of the first gate electrode block over the active layer is enhanced, the threshold voltage of the first transistor is reduced, and the short channel effect of the first transistor is weakened.

[0009] As a possible implementation, the length direction of the channel of the second transistor includes: parallel to the thickness direction of the substrate, and perpendicular to the thickness direction of the substrate.

[0010] When the above scheme is adopted, the length direction of the channel of the second transistor can be the traditional parallel to the thickness direction of the substrate to form a simpler planar organic electrochemical transistor, thereby reducing the process difficulty of manufacturing vertical transistors for static random access memory; the length direction of the channel of the second transistor can also be perpendicular to the thickness direction of the substrate, so that the second transistor obtains a channel between vertically stacked dense source and drain gold electrodes, thereby making the second transistor have better reliability.

[0011] As a possible implementation scheme, the second transistor includes: a third electrode block, a fourth electrode block, a second gate electrode block, a second active area and an electrolyte layer; along the thickness direction of the substrate, the third electrode block, the fourth electrode block and the second gate electrode block are spaced apart on the isolation layer; the second active area is formed on the third electrode block, the fourth electrode block and a partial area of ​​the isolation layer; the partial area of ​​the isolation layer is the area of ​​the isolation layer between the third electrode block and the fourth electrode block; the electrolyte layer is formed on the isolation layer, the second active area, the third electrode block, the fourth electrode block and the second gate electrode block.

[0012] As a possible implementation scheme, the third electrode block includes: a first electrode sub-block and a second electrode sub-block; the second gate electrode block includes: a first gate electrode sub-block and a second gate electrode sub-block; along the thickness direction of the substrate, the first gate electrode sub-block, the first electrode sub-block, the fourth electrode block, the second electrode sub-block and the second gate electrode sub-block are sequentially formed on the isolation layer; the second active region includes: a first active sub-region and a second active sub-region; the first active sub-region and the second active sub-region are formed on the isolation layer at intervals; the first active sub-region is formed on the first electrode sub-block and on the fourth electrode block; and the second active sub-region is at least formed on the fourth electrode block and between the second electrode sub-block.

[0013] In the case of adopting the above scheme, the first electrode sub-block and the fourth electrode block form a pair of source-drain electrodes, the first active sub-region serves as their channel, and the first gate electrode sub-block performs gate control regulation on the first active sub-region; the second electrode sub-block and the fourth electrode block form another pair of source-drain electrodes, the second active sub-region serves as their channel, and the second gate electrode sub-block performs gate control regulation on the second active sub-region. In this case, the second transistor forms a structure of two sub-transistors, with two channels and two pairs of source-drain electrodes, which can significantly reduce the channel resistance and the resistance between the source-drain electrode and the channel, which is beneficial to improve the saturation leakage current of the second transistor and improve the switching speed of the second transistor; in addition, since the first active sub-region and the second active sub-region contact the electrolyte layer at the same time, the contact area with the electrolyte layer is expanded, the speed of the electrochemical reaction of the second transistor is improved, the gate control capability of the second transistor is improved, and thus the switching speed of the second transistor is improved.

[0014] As a possible implementation, the first active sub-region and the second active sub-region have opposite conductivity types.

[0015] In the case of adopting the above solution, a complementary transistor structure is formed in the second transistor, so that the second transistor can realize additional circuit logic, and expand the application scope of the manufacturing method of the vertical transistor for static random access memory provided by the present invention. In addition, the first active sub-region and the second active sub-region have opposite conductivity types, so that the second transistor has both N-type and P-type channels, which solves the problem of performance degradation of N-type organic electrochemical transistors and improves the performance of the vertical transistor for static random access memory provided by the present invention.

[0016] In a second aspect, the present invention further provides a method for manufacturing a vertical transistor for a static random access memory, the method for manufacturing a vertical transistor for a static random access memory comprising: first, providing a substrate. Next, forming a first transistor on the substrate; the channel material of the first transistor is indium gallium zinc oxide. Next, forming an isolation layer on the first transistor. Next, forming a second transistor on the isolation layer; the second transistor is an organic electrochemical transistor; at least one source-drain electrode of the second transistor is electrically connected to at least one source-drain electrode of the first transistor.

[0017] Compared with the prior art, the beneficial effects of the method for manufacturing a vertical transistor for a static random access memory provided by the present application are the same as the beneficial effects of the vertical transistor for a static random access memory provided by the above technical solution, and will not be repeated here.

[0018] As a possible implementation scheme, forming a first transistor on a substrate includes: first, forming a first electrode block and a second electrode block on the substrate at intervals along a direction parallel to the substrate. Next, forming a first active area on the first electrode block, the second electrode block and a partial area of ​​the substrate; the partial area of ​​the substrate is the area of ​​the substrate between the first electrode block and the second electrode block. Next, forming a gate dielectric layer on the first electrode block, the second electrode block, the first active area and the substrate; the material of the gate dielectric layer is a material with a high dielectric constant. Next, forming a first gate electrode block on the gate dielectric layer; the orthographic projection of the first gate electrode block on the substrate overlaps with the orthographic projection of the first active area on the substrate. Forming an isolation layer on the first transistor includes forming an isolation layer on the gate dielectric layer and the first gate electrode block. Forming a second transistor on the isolation layer includes: first, forming a third electrode block, a fourth electrode block and a second gate electrode block on the isolation layer at intervals along a direction parallel to the substrate. Next, forming a second active area on the third electrode block, the fourth electrode block and a partial area of ​​the isolation layer; the partial area of ​​the isolation layer is the area of ​​the isolation layer between the third electrode block and the fourth electrode block. Next, an electrolyte layer is formed on the isolation layer, the second active region, the third electrode block, the fourth electrode block, and the second gate electrode block.

[0019] As a possible implementation, forming a first electrode block and a second electrode block on the substrate along the thickness direction of the substrate at intervals includes: growing a first electrode layer on the substrate; patterning the first electrode layer to form the first electrode block and the second electrode block. Forming a first active area on the first electrode block, the second electrode block and a partial area of ​​the substrate includes: forming a first active layer on the first electrode block, the second electrode block and a partial area of ​​the substrate by magnetron sputtering; patterning the first active layer to form the first active area. Forming a gate dielectric layer on the first electrode block, the second electrode block, the first active area and the substrate includes: forming a gate dielectric layer on the first electrode block, the second electrode block, the first active area and the substrate by atomic layer deposition. Forming a first gate electrode block on the gate dielectric layer includes: growing a first gate electrode layer on the gate dielectric layer; patterning the first gate electrode layer to form a first gate electrode block.

[0020] As a possible implementation scheme, after forming an isolation layer on the gate dielectric layer and the first gate electrode block, it also includes: forming a through hole penetrating the isolation layer on the isolation layer; the through hole electrically connects at least one source-drain electrode of the second transistor and at least one source-drain electrode of the first transistor. Forming a third electrode block, a fourth electrode block and a second gate electrode block on the isolation layer in a direction parallel to the substrate includes: forming a second electrode layer on the isolation layer; patterning the second electrode layer to form a third electrode block, a fourth electrode block and a second gate electrode block; immersing the second gate electrode block in a modification solution to modify the second gate electrode block. Forming a second active area on the third electrode block, the fourth electrode block and a partial area of ​​the isolation layer includes: forming a second active layer on the third electrode block, the fourth electrode block and the isolation layer; patterning the second active layer to form a second active area. Forming an electrolyte layer on the isolation layer, the second active area, the third electrode block and the fourth electrode block includes: dripping an electrolyte solution on the isolation layer, and the electrolyte solution at least immerses the isolation layer, the second active area, the third electrode block, the fourth electrode block and a portion of the second gate electrode block. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0022] Figure 1 A schematic diagram of a vertical transistor for a static random access memory provided by an embodiment of the present invention;

[0023] Figure 2 A schematic diagram of a vertical transistor for a static random access memory provided by an embodiment of the present invention;

[0024] Figure 3A schematic diagram of a vertical transistor with a through hole for a static random access memory provided by an embodiment of the present invention;

[0025] Figure 4 A layout of a vertical transistor for a static random access memory provided by an embodiment of the present invention;

[0026] Figure 5 A flow chart of a method for manufacturing a vertical transistor for a static random access memory provided by an embodiment of the present invention.

[0027] Reference numerals:

[0028] 100-substrate, 200-first transistor,

[0029] 210 - first electrode group, 211 - first electrode block,

[0030] 212 - second electrode block, 220 - first active region,

[0031] 230 - gate dielectric layer, 240 - first gate electrode block,

[0032] 300-isolation layer, 310-through hole,

[0033] 400 - a second transistor, 410 - a third electrode block,

[0034] 411 - first electrode sub-block, 412 - second electrode sub-block,

[0035] 420 - fourth electrode block, 430 - second active region,

[0036] 431 - first active sub-region, 432 - second active sub-region,

[0037] 440 - second gate electrode block, 441 - first gate electrode sub-block,

[0038] 442 - second gate electrode sub-block, 450 - electrolyte layer,

[0039] 460 - second electrode group. DETAILED DESCRIPTION

[0040] In order to make the technical problems, technical solutions and beneficial effects to be solved by the embodiments of the present invention more clearly understood, the embodiments of the present invention are further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the embodiments of the present invention and are not used to limit the embodiments of the present invention.

[0041] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0042] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present invention, "multiple" means two or more, unless otherwise clearly and specifically defined. "Several" means one or more, unless otherwise clearly and specifically defined.

[0043] In the description of the embodiments of the present invention, it should be understood that the directions or positional relationships indicated by the terms "up", "down", "front", "back", "left", "right", etc. are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as a limitation on the embodiments of the present invention.

[0044] In the description of the embodiments of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the embodiments of the present invention can be understood according to specific circumstances.

[0045] Organic electrochemical transistors (OECTs) and their circuits benefit from their ultra-low driving voltage (<1V), low power consumption (<1μW), high transconductance (>10ms) and biocompatibility, and can be widely used in the next generation of smart sensors, bioelectronics, wearable electronics and artificial neural electronics. However, the current OECTs based on conventional planar structures still have a series of problems, including poor device stability, slow electrochemical reaction and switching speed, low integration density and extremely poor N-type device performance, which greatly limits their further development and integrated applications.

[0046] In addition, electronic applications are still mainly based on silicon-based manufacturing at this stage, but the demand for higher performance, new applications and flexible integration has led to the research of new materials, including the research of oxide channel materials. Indium potassium zinc oxide (a-IGZO) has good field effect mobility (>10cm2 / V·s), high current switching ratio, low off-state leakage current, low manufacturing process temperature (<450℃) and other properties, so the application prospects of transistors with indium potassium zinc oxide channels are good.

[0047] The purpose of the embodiment of the present invention is to provide a vertical transistor for static random access memory, so as to improve the integration of organic electrochemical transistors.

[0048] In order to achieve the above objectives, first of all, please refer to Figure 1 and Figure 4 According to an embodiment of the present invention, a vertical transistor for a static random access memory includes: a substrate 100, a first transistor 200, an isolation layer 300, and a second transistor 400. The first transistor 200 is formed on the substrate 100; the channel material of the first transistor 200 is indium gallium zinc oxide; the isolation layer 300 is formed on the first transistor 200; the second transistor 400 is formed on the isolation layer 300; the second transistor 400 is an organic electrochemical transistor; at least one source-drain electrode of the second transistor 400 is electrically connected to at least one source-drain electrode of the first transistor 200.

[0049] When using the above technical solution, please refer to Figure 1 and Figure 4, a first transistor 200 is formed on a substrate 100, an isolation layer 300 is formed on the first transistor 200, and a second transistor 400 is formed on the isolation layer 300, forming a vertical transistor for a static random access memory that vertically integrates an indium gallium zinc oxide transistor and an organic electrochemical transistor. Compared with the organic electrochemical transistor formed only on a plane in the prior art, the integration level is greatly improved. In addition, due to the integration with the indium gallium zinc oxide transistor, the good performance of the indium gallium zinc oxide transistor can effectively improve the performance of the vertical transistor for a static random access memory provided in an embodiment of the present invention. In addition, since organic electrochemical transistors are usually made at a lower temperature, and indium gallium zinc oxide transistors have high thermal budget requirements in the transistor manufacturing process, the first transistor 200 and the second transistor 400 are stacked in the above manner, which can ensure that the first transistor 200 does not suffer structural damage when manufacturing a vertical transistor for a static random access memory, thereby ensuring the performance of the first transistor 200. In addition, at least one source-drain electrode of the second transistor 400 is electrically connected to at least one source-drain electrode of the first transistor 200. The vertical transistor for static random access memory provided in the embodiment of the present invention includes the first transistor 200 and the second transistor 400, which can realize effective logical functions, thereby expanding the application scope of the vertical transistor for static random access memory provided in the embodiment of the present invention.

[0050] Regarding the substrate 100 included in the vertical transistor for static random access memory provided in the embodiment of the present invention, its material can be an insulating material with high strength including silicon oxide, glass, etc. to reduce the leakage of the first transistor 200 to the substrate 100, thereby improving the performance of the vertical transistor for static random access memory provided in the embodiment of the present invention, and organic insulating materials such as PI can also be used to achieve better shock resistance or realize flexible transistors; its material can also be a semiconductor substrate 100 including silicon and silicon on insulator to improve the compatibility of the vertical transistor for static random access memory provided in the embodiment of the present invention with existing manufacturing processes.

[0051] The thickness of the substrate 100 is not specifically limited in the embodiment of the present invention and can be determined according to actual needs. Optionally, the thickness of the substrate 100 is greater than or equal to 0.1 mm and less than or equal to 5 mm. Specifically, the thickness of the substrate 100 can be 0.1 mm, 1 mm, 2 mm, 3 mm, 4 mm or 5 mm.

[0052] As a possible implementation, please refer to Figure 1 and Figure 4The first transistor 200 includes: a first electrode block 211, a second electrode block 212, a first active region 220, a gate dielectric layer 230, and a first gate electrode block 240; the first electrode block 211 and the second electrode block 212 are formed on the substrate 100 at intervals along the thickness direction of the substrate 100; the first active region 220 is formed on the first electrode block 211, the second electrode block 212, and a partial region of the substrate 100; the partial region of the substrate 100 is the substrate 100 between the first electrode block 211 and the second electrode block 212. The gate dielectric layer 230 is formed on the first electrode block 211, the second electrode block 212, the first active area 220 and the substrate 100; the material of the gate dielectric layer 230 is a material with a high dielectric constant; the first gate electrode block 240 is formed on the gate dielectric layer 230; the orthographic projection of the first gate electrode block 240 on the substrate 100 overlaps with the orthographic projection of the first active area 220 on the substrate 100; the isolation layer 300 is formed on the gate dielectric layer 230 and the first gate electrode block 240. The first electrode group 210 includes a first electrode block 211 and a second electrode block 212.

[0053] When using the above technical solution, please refer to Figure 1 and Figure 4 The first transistor 200 is an indium gallium zinc oxide thin film transistor (IGZO TFT), and the gate dielectric layer 230 is a material with a high dielectric constant, which changes the gate capacitance of the first transistor 200, speeds up the turn-on and turn-off speeds of the first transistor 200, and reduces the power consumption of the first transistor 200; and strengthens the control ability of the first gate electrode block 240 over the active layer, reduces the threshold voltage of the first transistor 200, and weakens the short channel effect of the first transistor 200.

[0054] For details, please refer to Figure 1 and Figure 4 , regarding the first electrode block 211 and the second electrode block 212 formed on the substrate 100 in a direction parallel to the substrate 100 and spaced apart from each other, they serve as the source electrode or the drain electrode of the first transistor 200 .

[0055] Regarding the specific structure of the first electrode block 211 and the second electrode block 212, they may be a single-layer structure or a multi-layer structure to achieve other functions, which is not specifically limited in the embodiment of the present invention.

[0056] The embodiment of the present invention does not specifically limit the materials of the first electrode block 211 and the second electrode block 212, as long as they can meet the performance requirements of the vertical transistor for static random access memory provided by the embodiment of the present invention. Exemplarily, the materials of the first electrode block 211 and the second electrode block 212 include one or a combination of gold, titanium, and silver.

[0057] It should be noted that the material of the first electrode block 211 and the material of the second electrode block 212 can be the same material, so that the first electrode block 211 and the second electrode block 212 can be manufactured at the same time when manufacturing the vertical transistor for static random access memory provided in an embodiment of the present invention; the material of the first electrode block 211 and the material of the second electrode block 212 can also be different materials to achieve better performance.

[0058] The embodiment of the present invention does not specifically limit the thickness of the first electrode block 211 and the second electrode block 212, as long as they can meet the performance requirements of the vertical transistor for static random access memory provided by the embodiment of the present invention. Exemplarily, the thickness of the first electrode block 211 and the second electrode block 212 is greater than or equal to 30nm and less than or equal to 80nm. Specifically, the thickness of the first electrode block 211 and the second electrode block 212 can be 30nm, 40nm, 50nm, 60nm, 70nm or 80nm.

[0059] It should be noted that the thickness of the first electrode block 211 and the thickness of the second electrode block 212 can be the same, so that the first electrode block 211 and the second electrode block 212 can be manufactured simultaneously when manufacturing the vertical transistor for static random access memory provided in an embodiment of the present invention; the thickness of the first electrode block 211 and the thickness of the second electrode block 212 can also be different to achieve more design possibilities.

[0060] In some embodiments, when the first electrode block 211 is a two-layer structure, the first electrode block 211 includes a first diffusion barrier layer and a first connection layer, the first diffusion barrier layer is formed on the substrate 100, and the first connection layer is formed on the first diffusion barrier layer. The first diffusion barrier layer is titanium, and the material of the first connection layer is gold. The thickness of the first diffusion barrier layer is greater than or equal to 8nm and less than or equal to 15nm; the thickness of the first connection layer is greater than or equal to 30nm and less than or equal to 80nm. When the second electrode block 212 is a two-layer structure, the second electrode block 212 includes a second diffusion barrier layer and a second connection layer, the second diffusion barrier layer is formed on the substrate 100, and the second connection layer is formed on the second diffusion barrier layer. The second diffusion barrier layer is titanium, and the material of the second connection layer is gold. The thickness of the second diffusion barrier layer is greater than or equal to 8nm and less than or equal to 15nm; the thickness of the second connection layer is greater than or equal to 30nm and less than or equal to 80nm.

[0061] As for the length of the first active region 220 , the embodiment of the present invention does not impose any specific limitation thereon, as long as the performance of the first transistor 200 is not affected.

[0062] Exemplarily, the length of the first active sub-region 431 is greater than or equal to 10 nm and less than or equal to 500 μm. Specifically, the length of the first active sub-region 431 may be 10 nm, 1 μm, 100 μm, 200 μm, 300 μm or 500 μm.

[0063] Regarding the thickness of the first active region 220, it needs to meet various performance requirements for the first transistor 200 including the on-off current ratio and the effective mobility. Exemplarily, the thickness of the first active region 220 is greater than or equal to 5nm and less than or equal to 7nm. Specifically, the thickness of the first active region 220 can be 5nm, 6nm, 7nm, 8nm, 9nm or 10nm.

[0064] When the above technical solution is adopted, it can be avoided that the first active area 220 is too thin, resulting in the inability to form a uniform and continuous film layer when manufacturing the vertical transistor for static random access memory provided by the embodiment of the present invention, thereby ensuring the performance of the first transistor 200, thereby ensuring the performance of the vertical transistor for static random access memory provided by the embodiment of the present invention; it can also be avoided that the first active area 220 is too thick, resulting in the weakening of the induced charge of the gate electrode field effect, and the problem that the thicker the first active area 220 is, the more defects and oxygen vacancies there are in the film, thereby resulting in a smaller mobility of the first active area 220, thereby ensuring the performance of the first transistor 200, thereby ensuring the performance of the vertical transistor for static random access memory provided by the embodiment of the present invention.

[0065] The gate dielectric layer 230 is formed on the first electrode block 211, the second electrode block 212, the first active region 220 and the substrate 100. The gate dielectric layer 230 is made of a material with a high dielectric constant, such as silicon oxide, silicon nitride, hafnium dioxide, zirconium dioxide and aluminum oxide.

[0066] When the above technical solution is adopted, and the gate dielectric layer 230 is a material with a high dielectric constant, the gate capacitance of the first transistor 200 is changed, the turn-on and turn-off speeds of the first transistor 200 are accelerated, and the power consumption of the first transistor 200 is reduced; and the control ability of the first gate electrode block 240 over the active layer is enhanced, the threshold voltage of the first transistor 200 is reduced, and the short channel effect of the first transistor 200 is weakened.

[0067] Preferably, the material of the gate dielectric layer 230 is aluminum oxide.

[0068] Regarding the thickness of the gate dielectric layer 230, it needs to meet the performance requirements of the gate capacitance of the first transistor 200. Exemplarily, the thickness of the gate dielectric layer 230 is greater than or equal to 10nm and less than or equal to 70nm. Specifically, the thickness of the gate dielectric layer 230 can be 10nm, 20nm, 30nm, 40nm, 50nm, 60nm or 70nm.

[0069] When the above technical solution is adopted, the thickness of the gate dielectric layer 230 is within this range, which can avoid serious leakage of the gate electrode to the first active area 220 due to too small thickness, thereby ensuring the performance of the first transistor 200; it can also avoid excessive gate capacitance due to too large thickness, thereby affecting the performance of the first transistor 200, thereby ensuring the performance of the vertical transistor for static random access memory provided by the embodiment of the present invention.

[0070] Regarding the first gate electrode block 240, its material includes one or a combination of titanium nitride, gold, titanium, molybdenum, and silver. The thickness of the gate electrode of the first gate electrode block 240 is greater than or equal to 30nm and less than or equal to 300nm.

[0071] The isolation layer 300 is formed on the gate dielectric layer 230 and the first gate electrode block 240 to isolate the first transistor 200 from the second transistor 400 to avoid short circuit. The isolation layer 300 is made of aluminum oxide to achieve better isolation effect.

[0072] The embodiment of the present invention does not limit the thickness of the isolation layer 300, as long as it can effectively isolate the first transistor 200 from the second transistor 400. Exemplarily, the thickness of the isolation layer 300 is less than 30 nm.

[0073] As a possible implementation, please refer to Figure 1 and Figure 4 , the second transistor 400 includes: a third electrode block 410, a fourth electrode block 420, a second gate electrode block 440, a second active region 430 and an electrolyte layer 450; along the thickness direction of the substrate 100, the third electrode block 410, the fourth electrode block 420 and the second gate electrode block 440 are formed on the isolation layer 300 at intervals; the second active region 430 is formed on the third electrode block 410, the fourth electrode block 420 and a partial region of the isolation layer 300; the partial region of the isolation layer 300 is the region of the isolation layer 300 between the third electrode block 410 and the fourth electrode block 420; the electrolyte layer 450 is formed on the isolation layer 300, the second active region 430, the third electrode block 410 and the fourth electrode block 420; and the electrolyte layer 450 is at least partially formed on the second gate electrode block 440. The second electrode group 460 includes the third electrode block 410, the fourth electrode block 420 and the second gate electrode block 440.

[0074] Specifically, the third electrode block 410 and the fourth electrode block 420 formed on the substrate 100 in a direction parallel to the substrate 100 and spaced apart from each other serve as the source electrode or the drain electrode of the third transistor.

[0075] Regarding the specific structure of the third electrode block 410 and the fourth electrode block 420, they may be a single-layer structure or a multi-layer structure to achieve other functions, which is not specifically limited in the embodiment of the present invention.

[0076] The embodiment of the present invention does not specifically limit the materials of the third electrode block 410 and the fourth electrode block 420, as long as they can meet the performance requirements of the vertical transistor for static random access memory provided by the embodiment of the present invention. Exemplarily, the materials of the third electrode block 410 and the fourth electrode block 420 include one or a combination of gold, titanium, and silver.

[0077] It should be noted that the material of the third electrode block 410 and the material of the fourth electrode block 420 can be the same material, so that the third electrode block 410 and the fourth electrode block 420 can be manufactured simultaneously when manufacturing the vertical transistor for static random access memory provided in an embodiment of the present invention; the material of the third electrode block 410 and the material of the fourth electrode block 420 can also be different materials to achieve better performance.

[0078] The embodiment of the present invention does not specifically limit the thickness of the third electrode block 410 and the fourth electrode block 420, as long as it can meet the performance requirements of the vertical transistor for static random access memory provided by the embodiment of the present invention. Exemplarily, the thickness of the third electrode block 410 and the fourth electrode block 420 is greater than or equal to 30nm and less than or equal to 80nm. Specifically, the thickness of the third electrode block 410 and the fourth electrode block 420 can be 30nm, 40nm, 50nm, 60nm, 70nm or 80nm.

[0079] It should be noted that the thickness of the third electrode block 410 and the thickness of the fourth electrode block 420 can be the same, so that the third electrode block 410 and the fourth electrode block 420 can be manufactured simultaneously when manufacturing the vertical transistor for static random access memory provided in an embodiment of the present invention; the thickness of the third electrode block 410 and the thickness of the fourth electrode block 420 can also be different to achieve more design possibilities.

[0080] In some embodiments, when the third electrode block 410 is a two-layer structure, the third electrode block 410 includes a third diffusion barrier layer and a third connection layer, the third diffusion barrier layer is formed on the substrate 100, and the third connection layer is formed on the third diffusion barrier layer. The third diffusion barrier layer is titanium, and the material of the third connection layer is gold. The thickness of the third diffusion barrier layer is greater than or equal to 8nm and less than or equal to 15nm; the thickness of the third connection layer is greater than or equal to 30nm and less than or equal to 80nm. When the fourth electrode block 420 is a two-layer structure, the fourth electrode block 420 includes a fourth diffusion barrier layer and a fourth connection layer, the fourth diffusion barrier layer is formed on the substrate 100, and the fourth connection layer is formed on the fourth diffusion barrier layer. The fourth diffusion barrier layer is titanium, and the material of the fourth connection layer is gold. The thickness of the fourth diffusion barrier layer is greater than or equal to 8nm and less than or equal to 15nm; the thickness of the fourth connection layer is greater than or equal to 30nm and less than or equal to 80nm.

[0081] Regarding the material of the second active region 430 , possible organic materials such as P(g2t-TT) and P-3O may be selected to realize the function of the second transistor 400 .

[0082] Regarding the material of the electrolyte layer 450 , potassium chloride solution or sodium chloride solution may be selected to achieve the function of the second transistor 400 .

[0083] The embodiment of the present invention does not specifically limit the thickness of the electrolyte layer 450 , as long as the third electrode block 410 , the fourth electrode block 420 , the second gate electrode block 440 and the second active area 430 are immersed and the function of the second transistor 400 can be realized.

[0084] Regarding the position of the second gate electrode block 440 , the electrolyte layer 450 may be only partially formed on the second gate electrode block 440 , so that the second gate electrode block 440 protrudes out of the electrolyte layer 450 ; the electrolyte layer 450 may also be formed on the second gate electrode block 440 , that is, the second gate electrode block 440 is immersed in the electrolyte layer 450 .

[0085] Regarding the structure of the second gate electrode block 440, it includes a first gate electrode sublayer and a second gate electrode sublayer, the first gate electrode sublayer is formed on the isolation layer 300, and the second gate electrode sublayer is formed on the first gate electrode sublayer. The material of the first gate electrode sublayer is titanium, and the material of the second gate electrode sublayer is silver chloride. The thickness of the first gate electrode sublayer is greater than or equal to 8nm and less than or equal to 15nm; the thickness of the second gate electrode sublayer is greater than or equal to 30nm and less than or equal to 80nm.

[0086] In one embodiment, please refer to Figure 2The second transistor 400 includes a structure of two sub-transistors, with two channels and two pairs of sources and drains. Specifically, the above-mentioned third electrode block 410 includes: a first electrode sub-block 411 and a second electrode sub-block 412; the second gate electrode block 440 includes: a first gate electrode sub-block 441 and a second gate electrode sub-block 442; along the thickness direction of the substrate 100, the first gate electrode sub-block 441, the first electrode sub-block 411, the fourth electrode block 420, the second electrode sub-block 412 and the second gate electrode sub-block 442 are sequentially formed on the isolation layer 300; the above-mentioned second active area 430 includes: the second active area 430 includes: a first active sub-area 431 and a second active sub-area 432; the first active sub-area 431 and the second active sub-area 432 are formed at intervals on the isolation layer 300; the first active sub-area 431 is formed on the first electrode sub-block 411 and on the fourth electrode block 420; and the second active sub-area 432 is at least formed on the fourth electrode block 420 and between the second electrode sub-block 412.

[0087] In this case, the second transistor 400 forms a structure of two sub-transistors with two channels and two pairs of source and drain, which can significantly reduce the channel resistance and the resistance between the source and drain electrodes and the channel, which is beneficial to increasing the saturation leakage current of the second transistor 400 and improving the switching speed of the second transistor 400; in addition, since the first active sub-region 431 and the second active sub-region 432 contact the electrolyte layer 450 at the same time, the contact area with the electrolyte layer 450 is expanded, the speed of the electrochemical reaction of the second transistor 400 is increased, and the gate control capability of the second transistor 400 is increased, thereby improving the switching speed of the second transistor 400.

[0088] Regarding the conductivity types of the first active sub-region 431 and the second active sub-region 432 , they may be of the same conductivity type or of opposite conductivity types.

[0089] Preferably, the first active sub-region 431 and the second active sub-region 432 have opposite conductivity types.

[0090] In the case of adopting the above solution, a complementary transistor structure is formed in the second transistor 400, so that the second transistor 400 can realize additional circuit logic, and expand the application scope of the manufacturing method of the vertical transistor for static random access memory provided by the embodiment of the present invention. In addition, the conductivity types of the first active sub-region 431 and the second active sub-region 432 are opposite, so that the second transistor 400 has both N-type and P-type channels, which solves the problem of performance degradation of N-type organic electrochemical transistors and improves the performance of the vertical transistor for static random access memory provided by the embodiment of the present invention.

[0091] Regarding the length direction of the channel of the second transistor, it can be parallel to the thickness direction of the substrate or perpendicular to the thickness direction of the substrate. In this case, the length direction of the channel of the second transistor can be either the traditional direction parallel to the thickness direction of the substrate, forming a relatively simple planar organic electrochemical transistor, thereby reducing the process difficulty of manufacturing a vertical transistor for static random access memory; the length direction of the channel of the second transistor can also be perpendicular to the thickness direction of the substrate, so that the second transistor obtains a channel between vertically stacked dense source and drain gold electrodes, thereby making the second transistor have better reliability.

[0092] In some embodiments, the isolation layer further includes at least one through hole penetrating the isolation layer, and at least one source-drain electrode of the second transistor and at least one source-drain electrode of the first transistor are electrically connected through the through hole. The through hole can also lead other electrodes of the first transistor out from under the isolation layer to facilitate connection and testing of the first transistor. For example, please refer to Figure 3 The through hole 310 connects the fourth electrode block 420 and the first electrode block 211 .

[0093] In a second aspect, the present invention also provides a method for manufacturing a vertical transistor for a static random access memory, please refer to Figure 1 and Figure 4 The manufacturing method of the vertical transistor for static random access memory includes: first, providing a substrate 100. Next, forming a first transistor 200 on the substrate 100; the channel material of the first transistor 200 is indium gallium zinc oxide. Next, forming an isolation layer 300 on the first transistor 200. Next, forming a second transistor 400 on the isolation layer 300; the second transistor 400 is an organic electrochemical transistor; at least one source-drain electrode of the second transistor 400 is electrically connected to at least one source-drain electrode of the first transistor 200.

[0094] Compared with the prior art, the beneficial effects of the method for manufacturing a vertical transistor for a static random access memory provided by the present application are the same as the beneficial effects of the vertical transistor for a static random access memory provided by the above technical solution, and will not be repeated here.

[0095] As a possible implementation, please refer to Figure 1, forming a first transistor 200 on a substrate 100 includes: first, forming a first electrode block 211 and a second electrode block 212 on the substrate 100 at intervals along a direction parallel to the substrate 100. Next, forming a first active area 220 on the first electrode block 211, the second electrode block 212 and a partial area of ​​the substrate 100; the partial area of ​​the substrate 100 is the area of ​​the substrate 100 between the first electrode block 211 and the second electrode block 212. Next, forming a gate dielectric layer 230 on the first electrode block 211, the second electrode block 212, the first active area 220 and the substrate 100; the material of the gate dielectric layer 230 is a material with a high dielectric constant. Next, forming a first gate electrode block 240 on the gate dielectric layer 230; the orthographic projection of the first gate electrode block 240 on the substrate 100 overlaps with the orthographic projection of the first active area 220 on the substrate 100. Forming an isolation layer 300 on the first transistor 200 includes forming an isolation layer 300 on the gate dielectric layer 230 and the first gate electrode block 240. Forming the second transistor 400 on the isolation layer 300 includes: first, forming a third electrode block 410, a fourth electrode block 420, and a second gate electrode block 440 on the isolation layer 300 in a direction parallel to the substrate 100. Next, forming a second active region 430 on the third electrode block 410, the fourth electrode block 420, and a partial region of the isolation layer 300; the partial region of the isolation layer 300 is the region of the isolation layer 300 between the third electrode block 410 and the fourth electrode block 420. Next, forming an electrolyte layer 450 on the isolation layer 300, the second active region 430, the third electrode block 410, and the fourth electrode block 420; the electrolyte layer 450 is at least partially formed on the second gate electrode block 440.

[0096] As a possible implementation, please refer to Figure 1 , forming a first electrode block 211 and a second electrode block 212 on the substrate 100 along the thickness direction of the substrate 100 at intervals includes: growing a first electrode layer on the substrate 100; patterning the first electrode layer to form the first electrode block 211 and the second electrode block 212. Forming a first active area 220 on the first electrode block 211, the second electrode block 212 and a partial area of ​​the substrate 100 includes: forming a first active layer on the first electrode block 211, the second electrode block 212 and a partial area of ​​the substrate 100 by magnetron sputtering; patterning the first active layer to form the first active area 220. Forming a gate dielectric layer 230 on the first electrode block 211, the second electrode block 212, the first active area 220 and the substrate 100 includes: forming a gate dielectric layer 230 on the first electrode block 211, the second electrode block 212, the first active area 220 and the substrate 100 by atomic layer deposition. Forming the first gate electrode block 240 on the gate dielectric layer 230 includes: growing a first gate electrode layer on the gate dielectric layer 230 ; and patterning the first gate electrode layer to form the first gate electrode block 240 .

[0097] As a possible implementation, please refer to Figure 1 and Figure 3 , forming an isolation layer 300 on the first transistor 200 includes forming the isolation layer 300 on the gate dielectric layer 230 and the first gate electrode block 240, and further includes: forming a through hole 310 penetrating the isolation layer 300 on the isolation layer 300; the through hole 310 electrically connects at least one source-drain electrode of the second transistor 400 and at least one source-drain electrode of the first transistor 200; along a direction parallel to the substrate 100, forming a third electrode block 410, a fourth electrode block 420 and a second gate electrode block 440 at intervals on the isolation layer 300, including: forming a second electrode layer on the isolation layer 300; patterning the second electrode layer to form a third electrode block 410, a fourth electrode block 420 and a second gate electrode block 440; immersing the second gate electrode block 440 in a modification solution to modify the second gate electrode block 440. Forming the second active area 430 on the third electrode block 410, the fourth electrode block 420 and a portion of the isolation layer 300 includes: forming a second active layer on the third electrode block 410, the fourth electrode block 420 and the isolation layer 300; and patterning the second active layer to form the second active area 430. Forming the electrolyte layer 450 on the isolation layer 300, the second active area 430, the third electrode block 410 and the fourth electrode block 420 includes: dripping an electrolyte solution on the isolation layer 300, and the electrolyte solution at least immerses the isolation layer 300, the second active area 430, the third electrode block 410, the fourth electrode block 420 and a portion of the second gate electrode block 440.

[0098] Specifically, please refer to Figure 1 and Figure 5 First, a substrate 100 is provided. Regarding the material, thickness and beneficial effects of the substrate 100, please refer to the relevant description of the first aspect, which will not be repeated here.

[0099] Next, please refer to Figure 1 and Figure 5 , a first electrode layer is grown on the substrate 100; the first electrode layer is patterned to form a first electrode block 211 and a second electrode block 212. Specifically, an IGZO source-drain electrode is grown on an insulating substrate and patterned using conventional photolithography. In this case, a first electrode layer is grown on the substrate 100 using a process such as electron beam evaporation; the first electrode layer is then patterned using a patterning process such as photolithography and lift-off to form a first electrode block 211 and a second electrode block 212. For the material, thickness and structure of the first electrode block 211 and the second electrode block 212, please refer to the relevant description of the first aspect, which will not be repeated here.

[0100] Next, please refer to Figure 1 and Figure 5, a first active layer is formed on the first electrode block 211, the second electrode block 212 and a partial area of ​​the substrate 100; the first active layer is patterned to form a first active area 220. Specifically, the IGZO active layer is magnetron sputtered, and then the IGZO active layer is photolithographically and wet-etched for patterning. In this case, the first active layer is patterned by photolithography and wet etching processes to form the first active area 220, and the etching agent selected for wet etching is a dilute nitric acid solution. Regarding the material, thickness and structure of the first active area 220, please refer to the relevant description of the first aspect, which will not be repeated here.

[0101] Next, please refer to Figure 1 and Figure 5 A gate dielectric layer 230 is formed on the first electrode block 211, the second electrode block 212, the first active region 220 and the substrate 100 by atomic layer deposition. Specifically, the gate dielectric layer AlO is deposited on the IGZO active layer by atomic layer deposition. X The growth temperature of the atomic layer deposition is greater than or equal to 100° C. and less than or equal to 300° C. Regarding the material, thickness and structure of the gate dielectric layer 230 , please refer to the relevant description of the first aspect, which will not be repeated here.

[0102] Next, please refer to Figure 1 and Figure 5 , growing a first gate electrode layer on the gate dielectric layer; patterning the first gate electrode layer to form a first gate electrode block. X An IGZO gate electrode is grown on the gate dielectric layer 230 and patterned by conventional photolithography. In this case, a magnetron sputtering process is used to grow a first gate electrode layer on the gate dielectric layer 230 ; then the first gate electrode layer is patterned by photolithography and lift-off processes to form a first gate electrode block 240 .

[0103] Next, please refer to Figure 1 and Figure 5 , an isolation layer 300 is grown on the gate dielectric layer 230 and the first gate electrode block 240 .

[0104] Optionally, refer to Figure 3 and Figure 5 , an isolation layer is grown on the IGZO gate electrode, and photolithography and wet etching are performed to form a through hole. Specifically, after the isolation layer 300 is grown on the gate dielectric layer 230 and the first gate electrode block 240, a through hole 310 penetrating the isolation layer 300 is formed by photolithography and wet etching processes, and at least one source-drain electrode of the second transistor 400 and at least one source-drain electrode of the first transistor 200 are electrically connected through the through hole 310. The through hole 310 can also lead other electrodes of the first transistor 200 out from under the isolation layer 300 to facilitate connection and testing of the first transistor 200.

[0105] Next, please refer to Figure 1 and Figure 5 , forming a second electrode layer on the isolation layer; patterning the second electrode layer to form a third electrode block, a fourth electrode block and a second gate electrode block. Specifically, the OECT source, drain and gate electrode are grown on the isolation layer, and patterned by conventional photolithography. In this case, an electron beam evaporation process is used to grow the second electrode layer on the isolation layer 300, and the second electrode layer is patterned by photolithography and stripping processes to form a third electrode block 410, a fourth electrode block 420 and a second gate electrode block 440. The second gate electrode block 440 includes a first gate electrode sublayer and a second gate electrode sublayer. The first gate electrode sublayer is formed on the isolation layer 300, and the second gate electrode sublayer is formed on the first gate electrode sublayer. The material of the first gate electrode sublayer is titanium, and the material of the second gate electrode sublayer is silver. The thickness of the first gate electrode sublayer is greater than or equal to 8nm and less than or equal to 15nm; the thickness of the second gate electrode sublayer is greater than or equal to 30nm and less than or equal to 80nm.

[0106] Next, please refer to Figure 1 and Figure 5 , immerse the second gate electrode block 440 into the modification solution to modify the second gate electrode block 440. Specifically, the OECT gate electrode is modified by immersing the metal modification layer solution. In this case, the second gate electrode block 440 is immersed in a ferric chloride (FeCl3) solution to change the material of the second gate electrode sublayer from silver to silver chloride. The concentration of the ferric chloride (FeCl3) solution is greater than or equal to 0.5mM and less than or equal to 3mM, and the immersion treatment time is greater than or equal to 1h and less than or equal to 2h.

[0107] Next, please refer to Figure 1 and Figure 5 , forming a second active layer on the third electrode block 410 , the fourth electrode block 420 and the isolation layer 300 ; and patterning the second active layer to form a second active region 430 .

[0108] In some embodiments, please refer to Figure 2 and Figure 5The second transistor 400 includes a structure of two sub-transistors, with two channels and two pairs of source and drain, and the third electrode block 410 includes: a first electrode sub-block 411 and a second electrode sub-block 412; the second gate electrode block 440 includes: a first gate electrode sub-block 441 and a second gate electrode sub-block 442; along the thickness direction of the substrate 100, the first gate electrode sub-block 441, the first electrode sub-block 411, the fourth electrode block 420, the second electrode sub-block 412 and the second gate electrode sub-block 442 are sequentially formed on the isolation layer 300; the second active area 430 includes: a first active sub-area 431 and a second active sub-area 432; the first active sub-area 431 and the second active sub-area 432 are formed on the isolation layer 300 at intervals; the first active sub-area 431 is formed on the first electrode sub-block 411 and on the fourth electrode block 420; and the second active sub-area 432 is at least formed on the fourth electrode block 420 and between the second electrode sub-block 412. The material of the first active sub-region 431 is P(g2t-TT), and the material of the second active sub-region 432 is P-3O.

[0109] Alternatively, organic P-type and N-type semiconductors are grown and patterned by photolithography. In this case, please refer to Figure 2 and Figure 5 , firstly, the patterned area of ​​the first active sub-region 431 is determined on the first electrode sub-block 411, the fourth electrode block 420 and the isolation layer 300 therebetween by using photolithography and stripping processes, and then the P(g2t-TT) material is spin-coated, and the spin-coating speed used in the spin-coating process is greater than or equal to 1200rpm and less than or equal to 4000rpm, and the spin-coating time is greater than or equal to 50s and less than or equal to 70s. Then, the P-3O material is spin-coated on the second electrode sub-block 412, the fourth electrode block 420 and the isolation layer 300 therebetween, and the spin-coating speed used in the spin-coating process is greater than or equal to 1200rpm and less than or equal to 4000rpm, and the spin-coating time is greater than or equal to 50s and less than or equal to 70s. Then, patterning is performed by photolithography and oxygen plasma etching processes to form the second active sub-region 432, wherein the etching time of the oxygen plasma etching process is greater than or equal to 5min and less than or equal to 10min.

[0110] Next, please refer to Figure 1 and Figure 5 , drip an electrolyte solution on the isolation layer 300, and the electrolyte solution at least immerses the isolation layer 300, the second active area 430, the third electrode block 410, the fourth electrode block 420 and a portion of the second gate electrode block 440. Specifically, drip a liquid electrolyte and finally perform a test.

[0111] Regarding the specific parameters of the structure manufactured by the manufacturing method of the vertical transistor for static random access memory provided by the second aspect, please refer to the relevant description of the first aspect, and no further details will be given here.

[0112] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in a suitable manner in any one or more embodiments or examples.

[0113] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art may understand and implement other variations of the disclosed embodiments by viewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "one" or "an" does not exclude multiple situations. A single processor or other unit may implement several functions listed in the claims. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0114] Although the present invention has been described in conjunction with specific features and embodiments thereof, it is apparent that various modifications and combinations may be made thereto without departing from the spirit and scope of the present invention. Accordingly, this specification and the accompanying drawings are merely exemplary illustrations of the present invention as defined by the appended claims and are deemed to cover any and all modifications, variations, combinations or equivalents within the scope of the present invention. Obviously, those skilled in the art may make various modifications and variations to the present invention without departing from the spirit and scope of the present invention. Thus, the present invention is intended to include such modifications and variations if they fall within the scope of the claims of the present invention and their equivalents.

Claims

1. A vertical transistor for static random access memory, characterized in that: include: substrate; a first transistor formed on the substrate; The channel material of the first transistor is indium gallium zinc oxide; an isolation layer formed on the first transistor; and a second transistor formed on the isolation layer; the second transistor is an organic electrochemical transistor; at least one source-drain electrode of the second transistor is electrically connected to at least one source-drain electrode of the first transistor.

2. The vertical transistor for static random access memory according to claim 1, characterized in that: The first transistor includes: a first electrode block, a second electrode block, a first active region, a gate dielectric layer, and a first gate electrode block; The first electrode block and the second electrode block are formed on the substrate at intervals along the thickness direction of the substrate; The first active region is formed on the first electrode block, the second electrode block and a partial region of the substrate; the partial region of the substrate is a region of the substrate between the first electrode block and the second electrode block; The gate dielectric layer is formed on the first electrode block, the second electrode block, the first active region and the substrate; the material of the gate dielectric layer is a material with a high dielectric constant; The first gate electrode block is formed on the gate dielectric layer; an orthographic projection of the first gate electrode block on the substrate overlaps with an orthographic projection of the first active region on the substrate; The isolation layer is formed on the gate dielectric layer and on the first gate electrode block.

3. The vertical transistor for static random access memory according to claim 1, characterized in that: The length direction of the channel of the second transistor includes: parallel to the thickness direction of the substrate and perpendicular to the thickness direction of the substrate.

4. The vertical transistor for static random access memory according to claim 1, characterized in that: The second transistor includes: a third electrode block, a fourth electrode block, a second gate electrode block, a second active region and an electrolyte layer; Along the thickness direction of the substrate, the third electrode block, the fourth electrode block and the second gate electrode block are formed on the isolation layer at intervals; The second active region is formed on the third electrode block, the fourth electrode block and a partial region of the isolation layer; the partial region of the isolation layer is a region of the isolation layer between the third electrode block and the fourth electrode block; The electrolyte layer is formed on the isolation layer, on the second active region, on the third electrode block, on the fourth electrode block, and on the second gate electrode block.

5. The vertical transistor for static random access memory according to claim 4, characterized in that: The third electrode block includes: a first electrode sub-block and a second electrode sub-block; the second gate electrode block includes: a first gate electrode sub-block and a second gate electrode sub-block; along the thickness direction of the substrate, the first gate electrode sub-block, the first electrode sub-block, the fourth electrode block, the second electrode sub-block and the second gate electrode sub-block are sequentially formed on the isolation layer; The second active region includes: a first active sub-region and a second active sub-region; the first active sub-region and the second active sub-region are formed on the isolation layer with a gap; the first active sub-region is formed on the first electrode sub-block and the fourth electrode block; and the second active sub-region is at least formed on the fourth electrode block and between the second electrode sub-blocks.

6. The vertical transistor for static random access memory according to claim 5, characterized in that: The first active sub-region and the second active sub-region have opposite conductivity types.

7. A method for manufacturing a vertical transistor for a static random access memory, characterized in that: include: providing a substrate; forming a first transistor on the substrate; The channel material of the first transistor is indium gallium zinc oxide; forming an isolation layer on the first transistor; A second transistor is formed on the isolation layer; the second transistor is an organic electrochemical transistor; at least one source-drain electrode of the second transistor is electrically connected to at least one source-drain electrode of the first transistor.

8. The method for manufacturing a vertical transistor for a static random access memory according to claim 7, characterized in that: The forming a first transistor on the substrate comprises: Forming a first electrode block and a second electrode block on the substrate in a direction parallel to the substrate; forming a first active region on the first electrode block, the second electrode block and a partial region of the substrate; the partial region of the substrate is a region of the substrate between the first electrode block and the second electrode block; forming a gate dielectric layer on the first electrode block, the second electrode block, the first active region and the substrate; the material of the gate dielectric layer is a material with a high dielectric constant; forming a first gate electrode block on the gate dielectric layer; an orthographic projection of the first gate electrode block on the substrate overlaps with an orthographic projection of the first active region on the substrate; The forming of the isolation layer on the first transistor comprises: forming the isolation layer on the gate dielectric layer and the first gate electrode block; The forming of the second transistor on the isolation layer comprises: forming a third electrode block, a fourth electrode block and a second gate electrode block on the isolation layer in a direction parallel to the substrate; forming a second active region on the third electrode block, the fourth electrode block and a partial region of the isolation layer; the partial region of the isolation layer is a region of the isolation layer between the third electrode block and the fourth electrode block; An electrolyte layer is formed on the isolation layer, the second active region, the third electrode block, the fourth electrode block, and the second gate electrode block.

9. The method for manufacturing a vertical transistor for a static random access memory according to claim 8, characterized in that: The step of forming a first electrode block and a second electrode block on the substrate in a thickness direction of the substrate at intervals comprises: Growing a first electrode layer on the substrate; patterning the first electrode layer to form the first electrode block and the second electrode block; The forming of a first active area on the first electrode block, the second electrode block and a partial area of ​​the substrate comprises: forming a first active layer on the first electrode block, the second electrode block and a partial area of ​​the substrate by magnetron sputtering; patterning the first active layer to form the first active area; The forming of a gate dielectric layer on the first electrode block, the second electrode block, the first active region and the substrate comprises: forming the gate dielectric layer on the first electrode block, the second electrode block, the first active region and the substrate by atomic layer deposition; The forming of the first gate electrode block on the gate dielectric layer comprises: growing a first gate electrode layer on the gate dielectric layer; and patterning the first gate electrode layer to form the first gate electrode block.

10. The method for manufacturing a vertical transistor for a static random access memory according to claim 8, characterized in that: After forming the isolation layer on the gate dielectric layer and the first gate electrode block, the method further includes: forming a through hole penetrating the isolation layer on the isolation layer; the through hole electrically connects at least one source-drain electrode of the second transistor and at least one source-drain electrode of the first transistor; The step of forming a third electrode block, a fourth electrode block and a second gate electrode block on the isolation layer in a direction parallel to the substrate comprises: forming a second electrode layer on the isolation layer; patterning the second electrode layer to form the third electrode block, the fourth electrode block and the second gate electrode block; immersing the second gate electrode block in a modification solution to modify the second gate electrode block; The forming of the second active area on the third electrode block, the fourth electrode block and a partial area of ​​the isolation layer comprises: forming a second active layer on the third electrode block, the fourth electrode block and the isolation layer; patterning the second active layer to form the second active region; The forming of an electrolyte layer on the isolation layer, the second active area, the third electrode block, and the fourth electrode block includes: dripping an electrolyte solution on the isolation layer, wherein the electrolyte solution at least immerses the isolation layer, the second active area, the third electrode block, the fourth electrode block, and a portion of the second gate electrode block.

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