Semiconductor device and method for manufacturing the same

Abstract

The present technology provides a semiconductor device including a highly integrated memory cell and a method for manufacturing the same. A method for manufacturing a semiconductor device may include: forming a vertical stack including a plurality of recessed target layers spaced apart from each other in a first direction above a lower structure; forming a preliminary horizontal layer by recessing the recessed target layer in a second direction perpendicular to the first direction; forming a dielectric target layer on the preliminary horizontal layer; forming a conductive target layer on the dielectric target layer; forming an interlayer dielectric layer by trimming the dielectric target layer in a third direction intersecting the second direction; forming a horizontal layer by trimming the preliminary horizontal layer in the third direction; and forming a trimmed target layer by trimming the conductive target layer in the third direction.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2023-0131596, filed on October 4, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure relate to a semiconductor device, and more particularly, to a semiconductor device including a three-dimensional memory cell and a method for manufacturing the same. Background Art

[0004] To meet consumer demand for higher capacity, higher performance, and more compact electronic devices, memory devices using the recently proposed 3-dimensional (3D) technology are being developed, in which multiple memory cells are stacked in multiple layers. 3D semiconductor technology is state-of-the-art and requires further improvement to achieve structural stability, increased capacity, and performance characteristics. Summary of the invention

[0005] Various embodiments of the present disclosure relate to an improved 3D semiconductor device (hereinafter referred to as a semiconductor device) having highly integrated memory cells and a method for manufacturing the same.

[0006] In an embodiment of the present disclosure, a method for manufacturing a semiconductor device may include: forming a vertical stack of a plurality of recessed target layers spaced apart from each other in a first direction above a lower structure; forming a preliminary horizontal layer by recessing the recessed target layer in a second direction perpendicular to the first direction; forming a dielectric target layer on the preliminary horizontal layer; forming a conductive target layer on the dielectric target layer; forming an interlayer dielectric layer by trimming the dielectric target layer in a third direction intersecting the second direction; forming a horizontal layer by trimming the preliminary horizontal layer in the third direction; and forming a trimmed target layer by trimming the conductive target layer in the third direction.

[0007] In an embodiment of the present disclosure, a semiconductor device may include: a lower structure; a memory cell array disposed at a level higher than the lower structure and including a plurality of memory cells; and a support member disposed between the lower structure and the memory cell array and supporting the memory cell array.

[0008] In an embodiment of the present disclosure, a method for manufacturing a semiconductor device may include: forming a stack including a single crystal silicon layer above a lower structure; forming a plurality of sacrificial vertical openings in the stack; forming a single crystal silicon layer pattern by recessing the single crystal silicon layer exposed by the sacrificial vertical openings; forming a gate dielectric layer on the single crystal silicon layer pattern; forming a conductive layer on the gate dielectric layer; forming a plurality of cell isolation openings in the stack; trimming the gate dielectric layer exposed by the cell isolation openings; forming a horizontal layer by trimming the single crystal silicon layer pattern exposed by the cell isolation openings; trimming the conductive layer exposed by the cell isolation openings, and forming a cell isolation layer filling the cell isolation openings.

[0009] Other features, aspects, and advantages of the present invention will become apparent from the following detailed description, the accompanying drawings, and the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1A is a schematic perspective view of a storage unit according to an embodiment of the present disclosure.

[0011] Figure 1B yes Figure 1A A schematic cross-sectional view of a memory cell is shown.

[0012] Figure 1C yes Figure 1A A plan view of the switching element shown.

[0013] Figure 1D is a schematic cross-sectional view of a memory cell according to another embodiment of the present disclosure.

[0014] Figure 2 is a schematic plan view of a semiconductor device according to an embodiment of the present disclosure.

[0015] Figure 3A yes Figure 2 A schematic three-dimensional diagram of a first memory cell array MCA1 is shown.

[0016] Figure 3B is along Figure 2 A cross-sectional view taken along line AA' in FIG.

[0017] Figure 3C is along Figure 2 A cross-sectional view taken along line BB' in FIG.

[0018] Figure 3D is along Figure 2 A cross-sectional view taken along line CC'.

[0019] FIG. 4A to FIG. 4C , Figure 5A and Figure 5B Figure 6 7A to 7C , FIG. 8A to FIG. 8C , Fig.9A and Fig. 9B , Fig. 10A and Fig. 10B , Fig.11A and Fig. 11B , Fig. 12A and Fig. 12B , Fig.13A and Fig. 13B , Fig.14 , FIG. 15A to FIG. 15D , Fig.16A and Fig. 16B , Fig.17A and Fig. 17B , Fig.18A and Fig.18B , Fig.19A and Fig.19B , Fig. 20A and Fig. 20B , Fig.21A and Fig. 21B , Fig.22A and Fig. 22B , Fig.23A and Fig. 23B as well as Fig.24A and Fig. 24B is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0020] FIG. 25A to FIG. 25C is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to another embodiment of the present disclosure.

[0021] Figure 26 to Figure 28 is a perspective view showing a memory cell array according to other embodiments of the present disclosure. DETAILED DESCRIPTION

[0022] The embodiments described in this specification may be described with reference to cross-sectional views, plan views, and block diagrams that are ideal schematic views of the present disclosure. Therefore, the form of the diagram may change due to manufacturing technology and / or tolerances. Therefore, the embodiments of the present disclosure are limited to the specific forms shown, but may also include changes in form resulting from manufacturing processes. Therefore, the areas shown in the drawings have approximate properties, and the forms of the areas shown in the drawings are provided to illustrate the specific forms of the various areas of the device, and are not intended to limit the categories of the present disclosure.

[0023] The following embodiments relate to three-dimensional (3D) memory cells and semiconductors having vertically stacked 3D memory cells that increase memory cell density and reduce parasitic capacitance.

[0024] Figure 1A is a simplified schematic perspective view of a storage unit according to an embodiment of the present disclosure. Figure 1B yes Figure 1A A simplified schematic cross-sectional view of a memory cell is shown. Figure 1C yes Figure 1A A plan view of the switching element shown.

[0025] Reference Figures 1A to 1C , the memory cell MC may include a first conductive line BL, a switching element TR, and a data storage element CAP, and the switching element TR is disposed between the first conductive line BL and the data storage element CAP.

[0026] The first wire BL may be vertically oriented in the first direction D1. The first wire BL may include a bit line. The first wire BL may also be referred to as a vertical wire, a vertically oriented bit line, a vertically extending bit line, or a columnar bit line. The first wire BL may include a conductive material. The first wire BL may include a silicon-based material, a metal-based material, or any combination thereof. For example, the first wire BL may include polysilicon, a metal, a metal nitride, a metal silicide, or any combination thereof. In an embodiment, the first wire BL may include polysilicon, titanium nitride, tungsten, or any combination thereof. In an embodiment, the first wire BL may include a stack of titanium nitride and tungsten (TiN / W).

[0027] The switching element TR has a function of controlling the voltage supply (or current) to the data storage element CAP during the data write operation and / or data read operation of the data storage element CAP. The switching element TR may include a horizontal layer HL, an interlayer dielectric layer GD, and a second wire DWL extending in the second direction D2. The second wire DWL may include a horizontal wire or a horizontal word line. The horizontal layer HL may include an active layer. The switching element TR may include a transistor. In this case, the second wire DWL may function as a gate electrode. The switching element TR may also be referred to as an access element or a selection element. The second wire DWL may also be referred to as a horizontal gate electrode or a horizontal word line.

[0028] The horizontal layer HL may extend in a second direction D2 intersecting the first direction D1. The second wire DWL may extend in a third direction D3 intersecting the first direction D1 and the second direction D2. The first direction D1 may be a vertical direction. The second direction D2 and the third direction D3 may be a first horizontal direction and a second horizontal direction, respectively. The horizontal layer HL may extend in a first horizontal direction (i.e., the second direction D2). The second wire DWL may extend in a second horizontal direction (i.e., the third direction D3).

[0029] The horizontal layer HL may include a semiconductor material, including, for example, polysilicon, single crystal silicon, germanium, or silicon-germanium. In an embodiment, the horizontal layer HL may include an oxide semiconductor material. For example, the oxide semiconductor material may include indium gallium zinc oxide (IGZO). In an embodiment, the horizontal layer HL may include a conductive metal oxide.

[0030] The upper (top) surface and the lower (bottom) surface of the horizontal layer HL may each be flat. That is, the upper surface and the lower surface of the horizontal layer HL may be parallel to each other in the second direction D2.

[0031] The horizontal layer HL may include a channel CH, a first doping region SR between the channel CH and the first conductive line BL, and a second doping region DR between the channel CH and the data storage element CAP. If the horizontal layer HL is an oxide semiconductor material, the channel CH may be made of the oxide semiconductor material, and the first doping region SR and the second doping region DR may be omitted. The horizontal layer HL may also be referred to as an active layer or a thin body.

[0032] Impurities having the same conductivity type may be doped into the first doping region SR and the second doping region DR. N-type conductivity type impurities may be doped into the first doping region SR and the second doping region DR, and P-type conductivity type impurities may be doped into the first doping region SR and the second doping region DR. The first doping region SR and the second doping region DR may include at least one impurity selected from arsenic (As), phosphorus (P), boron (B), indium (In), and any combination thereof. The first doping region SR may be connected to the first conductive line BL. The second doping region DR may be connected to the data storage element CAP.

[0033] The first doping region SR and the second doping region DR may also be referred to as a first source / drain region and a second source / drain region, respectively.

[0034] The horizontal layer HL may be horizontally oriented in the second direction D2 from the first conductive line BL.

[0035] The second wire DWL may have a double structure. For example, the second wire DWL may include an upper horizontal wire G1 and a lower horizontal wire G2 facing each other with the horizontal layer HL disposed therebetween. The interlayer dielectric layer GD may be formed on the upper surface and the lower surface of the horizontal layer HL. The upper horizontal wire G1 may be disposed on the upper side of the horizontal layer HL. The lower horizontal wire G2 may be disposed on the lower side of the horizontal layer HL. The second wire DWL may include a pair of upper horizontal wires G1 and lower horizontal wires G2. In the second wire DWL, the same driving voltage may be applied to the upper horizontal wire G1 and the lower horizontal wire G2. For example, the upper horizontal wire G1 and the lower horizontal wire G2 may form a pair and may be coupled to one memory cell MC. In another embodiment, different driving voltages may be applied to the upper horizontal wire G1 and the lower horizontal wire G2. In this case, one of the upper horizontal wire G1 and the lower horizontal wire G2 may function as a back gate or a shielding gate.

[0036] The second wire DWL may include a metal-based material, a semiconductor material, or any combination thereof. The second wire DWL may include titanium nitride, tungsten, polysilicon, or any combination thereof. For example, the second wire DWL may include a TiN / W stack in which titanium nitride and tungsten are sequentially stacked. The second wire DWL may include an N-type work function material or a P-type work function material. The N-type work function material may have a low work function of 4.5 eV or less. The P-type work function material may have a high work function greater than 4.5 eV. The second wire DWL may include a stack of a low work function material and a high work function material.

[0037] In each of the upper horizontal line G1 and the lower horizontal line G2, the width in the second direction D2, for example, the width of the overlapping portion overlapping with the horizontal layer HL may be greater than the width of the portion not overlapping with the horizontal layer HL. Due to the difference between such widths, the sidewall of the second wire DWL extending in the third direction D3 may have a notch-shaped sidewall.

[0038] Return to reference Figure 1C , the second conductive line DWL may include a channel overlap portion WLP and a channel non-overlap portion NOL. The channel overlap portion WLP refers to a portion overlapping with the channel CH of the horizontal layer HL. The channel non-overlap portion NOL refers to a portion that does not overlap with the horizontal layer HL. The channel overlap portion WLP may have a cross shape. In an embodiment (not shown), the channel overlap portion may have a diamond shape. In another embodiment, the sides of the channel overlap portion WLP may each have a curved shape or a circular shape.

[0039] The channel CH and the channel overlap portion WLP of the second wire DWL may overlap. The channel CH may have a cross shape as shown, or may have a diamond shape in another embodiment (not shown). The size of the channel overlap portion WLP of the second wire DWL may be larger than the size of the channel CH. The channel overlap portion WLP of the second wire DWL may completely overlap with the channel CH.

[0040] From a top view, the horizontal layer HL may have a cross shape as shown, or may have a diamond shape in another embodiment (not shown). In another embodiment, the sides of the horizontal layer HL may each have a curved shape or a rounded shape.

[0041] The interlayer dielectric layer GD may be disposed between the horizontal layer HL and the second wire DWL. The interlayer dielectric layer GD may also be referred to as a gate dielectric layer. The interlayer dielectric layer GD may also be referred to as a horizontal layer side dielectric layer. The interlayer dielectric layer GD may include silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicate, high-k material, ferroelectric material, antiferroelectric material, or any combination thereof. The interlayer dielectric layer GD may include SiO2, Si3N4, HfO2, Al2O3, ZrO2, AlON, HfON, HfSiO, HfSiON, HfZrO, or any combination thereof. The interlayer dielectric layer GD may be formed by thermal oxidation of a semiconductor material.

[0042] The data storage element CAP may include a storage element such as a capacitor. The data storage element CAP may be horizontally arranged from the switching element TR in the second direction D2. The data storage element CAP may include a first electrode SN extending horizontally from the horizontal layer HL in the second direction D2. The data storage element CAP may also include a second electrode PN above the first electrode SN and a dielectric layer DE between the first electrode SN and the second electrode PN. The first electrode SN, the dielectric layer DE, and the second electrode PN may be arranged horizontally in the second direction D2. The first electrode SN may include an inner space and a plurality of outer surfaces. The inner space of the first electrode SN may include a plurality of inner surfaces. The outer surface of the first electrode SN may include a vertical outer surface and a plurality of horizontal outer surfaces. The vertical outer surface of the first electrode SN may extend vertically in the first direction D1. The horizontal outer surface of the first electrode SN may extend horizontally in the second direction D2 or the third direction D3. The inner space of the first electrode SN may be a 3D space. The dielectric layer DE may conformally cover the inner and outer surfaces of the first electrode SN. The second electrode PN may be arranged in the inner space of the first electrode SN on the dielectric layer DE. Some outer surfaces of the first electrode SN may be electrically connected to the second doping region DR of the horizontal layer HL.

[0043] The data storage element CAP may have a 3D structure. The first electrode SN may have a 3D structure, but the first electrode SN of the 3D structure may have a horizontal 3D structure oriented in the second direction D2. As an example of a 3D structure, the first electrode SN may have a cylindrical shape. The cylindrical shape of the first electrode SN may include a cylindrical inner surface and a cylindrical outer surface. Some of the cylindrical outer surfaces of the first electrode SN may be electrically connected to the second doping region DR of the horizontal layer HL. The dielectric layer DE and the second electrode PN may be disposed on the cylindrical inner surface of the first electrode SN.

[0044] In another embodiment, the first electrode SN may have a pillar shape or a cylindrical barrel shape. The cylindrical barrel shape may refer to a structure in which a pillar shape and a barrel shape are combined.

[0045] The first electrode SN and the second electrode PN may include a metal, a noble metal, a metal nitride, a conductive metal oxide, a conductive noble metal oxide, a metal carbide, a metal silicide, or any combination thereof. For example, the first electrode SN and the second electrode PN may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), titanium nitride / tungsten (TiN / W) stack, tungsten nitride / tungsten (WN / W) stack, or any combination thereof. The second electrode PN may include a combination of a metal-based material and a silicon-based material. For example, the second electrode PN may be a titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stack. In the titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stack, silicon germanium may be a gap filling material filling the inside of the first electrode SN. Titanium nitride (TiN) may be used as the second electrode PN of the data storage element CAP. Tungsten nitride may be a low resistance material.

[0046] The dielectric layer DE may also be referred to as a capacitor dielectric layer or a storage layer. The dielectric layer DE may include silicon oxide, silicon nitride, a high-k material, or any combination thereof. The high-k material may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanium oxide (SrTiO3). In another embodiment, the dielectric layer DE may be composed of a composite layer including two or more layers of high-k materials.

[0047] The dielectric layer DE may be formed of a zirconium (Zr)-based oxide. The dielectric layer DE may have a stacked structure including zirconium oxide (ZrO2). The dielectric layer DE may include a ZrO2 / Al2O3 (ZA) stack or a ZrO2 / Al2O3 / ZrO2 (ZAZ) stack. The ZA stack may have a structure in which aluminum oxide (Al2O3) is stacked on zirconium oxide (ZrO2). The ZAZ stack may have a structure in which zirconium oxide (ZrO2), aluminum oxide (Al2O3) and zirconium oxide (ZrO2) are stacked in sequence. The ZA stack and the ZAZ stack may also be referred to as ZrO2-based layers. In another embodiment, the dielectric layer DE may be formed of an Hf-based oxide. The dielectric layer DE may have a stacked structure including hafnium oxide (HfO2). The dielectric layer DE may include a HfO2 / Al2O3 (HA) stack or a HfO2 / Al2O3 / HfO2 (HAH) stack. The HA stack may have a structure in which aluminum oxide (Al2O3) is stacked on hafnium oxide (HfO2). The HAH stack may have a structure in which hafnium oxide (HfO2), aluminum oxide (Al2O3) and hafnium oxide (HfO2) are stacked in sequence. The HA stack and the HAH stack may also be referred to as HfO2-based layers. In the ZA stack, the ZAZ stack, the HA stack and the HAH stack, aluminum oxide (Al2O3) may have a larger band gap energy than each of zirconium oxide (ZrO2) and hafnium oxide (HfO2). Aluminum oxide (Al2O3) may have a lower dielectric constant than each of zirconium oxide (ZrO2) and hafnium oxide (HfO2). Therefore, the dielectric layer DE may include a stack of a high-k material and a high-band gap material having a larger band gap energy than the high-k material. In addition to aluminum oxide (Al2O3), the dielectric layer DE may also include silicon oxide (SiO2) as another high band gap material. The dielectric layer DE may include a high bandgap material so that the leakage current of the dielectric layer DE can be suppressed. The high bandgap material may be thinner than the high-k material. In another embodiment, the dielectric layer DE may have a stacking structure in which high-k materials and high bandgap materials are alternately stacked. For example, the dielectric layer DE may include a ZrO2 / Al2O3 / ZrO2 / Al2O3 (ZAZA) stack, a ZrO2 / Al2O3 / ZrO2 / Al2O3 / ZrO2 (ZAZAZ) stack, a HfO2 / Al2O3 / HfO2 / Al2O3 (HAHA) stack, or a HfO2 / Al2O3 / HfO2 / Al2O3 / HfO2 (HAHAH) stack. In such a stacking structure, aluminum oxide (Al2O3) may be thinner than each of zirconium oxide (ZrO2) and hafnium oxide (HfO2).

[0048] In another embodiment, the dielectric layer DE may include a high-k material and a high bandgap material, but may have a stacked structure in which a plurality of high-k materials and a plurality of high bandgap materials are stacked, or a mixed structure in which the high-k material and the high bandgap material are mixed with each other.

[0049] In another embodiment, the dielectric layer DE may include a ferroelectric material, an antiferroelectric material, or any combination thereof. For example, the dielectric layer DE may include HfZrO.

[0050] In another embodiment, the dielectric layer DE may include a combination of a high-k material and a ferroelectric material, a combination of a high-k material and an antiferroelectric material, or a combination of a high-k material, a ferroelectric material, and an antiferroelectric material.

[0051] In another embodiment, an interface control layer for improving leakage current may also be formed between the first electrode SN and the dielectric layer DE. The interface control layer may include titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), niobium nitride (NbN), or any combination thereof. The interface control layer may also be formed between the second electrode PN and the dielectric layer DE.

[0052] The data storage element CAP may be a 3D capacitor. The data storage element CAP may include a metal-insulator-metal (MIM) capacitor. The data storage element CAP may be replaced with other data storage materials. For example, the data storage material may be a thyristor, a phase change material, a magnetic tunnel junction (MTJ), or a variable resistance material.

[0053] For example, the memory cell MC may include a thyristor. The first wire BL may be a cathode wire. The data storage element CAP may be replaced with an anode wire. The horizontal layer HL may include four semiconductor layers stacked horizontally in the second direction D2. The thyristor may include a first diode and a second diode connected in series. When a forward bias having the same voltage is applied to the thyristor, the thyristor may have a high conductance state in which a high current flows or a low conductance state in which a low current or no current flows. The memory cell MC may have a state "1" and a state "0" respectively by using the high conductance state and the low conductance state of the thyristor.

[0054] Return to reference Figure 1A and Figure 1B , the memory cell MC may further include a first contact node BLC and a second contact node SNC. The first contact node BLC may surround the outer wall of the first conductive line BL. The second contact node SNC may be disposed between the horizontal layer HL and the first electrode SN. The first contact node BLC may include a metal-based material or a semiconductor material. The second contact node SNC may include a metal-based material or a semiconductor material. For example, the first contact node BLC and the second contact node SNC may each include titanium, titanium nitride, tungsten, or any combination thereof. In addition, the first contact node BLC and the second contact node SNC may each include doped polysilicon. The first doping region SR and the second doping region DR may include impurities diffused from the first contact node BLC and the second contact node SNC, respectively.

[0055] Figure 1D is a simplified schematic cross-sectional view of a memory cell according to another embodiment of the present disclosure. Figure 1D The memory cell MC1 shown may be similar to Figures 1A to 1C Hereinafter, detailed description of repeated components may be omitted.

[0056] The memory cell MC1 may include a first conductive line BL, a switching element TR, and a data storage element CAP. The switching element TR may include a horizontal layer HL, an interlayer dielectric layer GD, and a second conductive line DWL. The horizontal layer HL may include a first doped region SR, a second doped region DR, and a channel CH. The data storage element CAP may include a first electrode SN, a second electrode PN, and a dielectric layer DE.

[0057] The memory cell MC1 may further include a first contact node BLC between the first conductive line BL and the horizontal layer HL, and a second contact node SNC between the horizontal layer HL and the data storage element CAP. The first contact node BLC and the second contact node SNC may each include doped polysilicon. The first doping region SR and the second doping region DR may include impurities diffused from the first contact node BLC and the second contact node SNC, respectively.

[0058] The second wire DWL may include an upper horizontal line G1 and a lower horizontal line G2. The upper horizontal line G1 and the lower horizontal line G2 may each include a first work function electrode G11, a second work function electrode G12, and a third work function electrode G13. The second work function electrode G12, the first work function electrode G11, and the third work function electrode G13 may be horizontally arranged in the second direction D2. The first work function electrode G11, the second work function electrode G12, and the third work function electrode G13 may be in direct contact with each other. The second work function electrode G12 may be adjacent to the first wire BL. The third work function electrode G13 may be adjacent to the data storage element CAP. The first work function electrode G11 may be arranged between the second work function electrode G12 and the third work function electrode G13. The horizontal layer HL may have a thickness smaller than that of the first work function electrode G11, the second work function electrode G12, and the third work function electrode G13.

[0059] The first work function electrode G11, the second work function electrode G12, and the third work function electrode G13 may be formed of materials with different work functions. The first work function electrode G11 may have a work function higher than each of the second work function electrode G12 and the third work function electrode G13. The first work function electrode G11 may include a high work function material. The first work function electrode G11 may have a work function higher than the mid-bandgap work function of silicon. The second work function electrode G12 and the third work function electrode G13 may each include a low work function material. The second work function electrode G12 and the third work function electrode G13 may each have a work function lower than the mid-bandgap work function of silicon. Incidentally, the high work function material may have a work function higher than 4.5 eV. The low work function material may have a work function lower than 4.5 eV. The first work function electrode G11 may include a metal-based material. The second work function electrode G12 and the third work function electrode G13 may each include a semiconductor material.

[0060] The second work function electrode G12 and the third work function electrode G13 may each include N-type dopant-doped polysilicon. The first work function electrode G11 may include a metal, a metal nitride, or any combination thereof. The first work function electrode G11 may include tungsten, titanium nitride, or any combination thereof. A barrier material may also be formed between the second work function electrode G12 and the third work function electrode G13 and the first work function electrode G11.

[0061] In an embodiment, the upper horizontal line G1 and the lower horizontal line G2 of the second wire DWL may be horizontally arranged in the second direction D2 in the order of the second work function electrode G12-the first work function electrode G11-the third work function electrode G13. The first work function electrode G11 may include metal. The second work function electrode G12 and the third work function electrode G13 may each include polysilicon.

[0062] The upper horizontal line G1 and the lower horizontal line G2 of the second wire DWL may each have a polysilicon-metal-polysilicon (PMP) structure horizontally arranged in the second direction D2. In the PMP structure, the first work function electrode G11 may include a metal-based material, and the second work function electrode G12 and the third work function electrode G13 may each include N-type dopant-doped polysilicon. The N-type dopant may include phosphorus or arsenic.

[0063] The first barrier layer G12L may be disposed between the first work function electrode G11 and the second work function electrode G12. The second barrier layer G13L may be disposed between the first work function electrode G11 and the third work function electrode G13. The first barrier layer G12L and the second barrier layer G13L may each include titanium nitride, tantalum nitride, tungsten nitride, or molybdenum nitride. The second barrier layer G13L may cover the upper surface, the lower surface, and one side surface of the first work function electrode G11.

[0064] The first work function electrode G11 may have a larger volume than each of the second work function electrode G12 and the third work function electrode G13. Therefore, the second wire DWL may have a low resistance. The first work function electrode G11 of the upper horizontal line G1 and the lower horizontal line G2 may overlap vertically in the first direction D1, with the horizontal layer HL placed therebetween. The second work function electrode G12 and the third work function electrode G13 of the upper horizontal line G1 and the lower horizontal line G2 may overlap vertically in the first direction D1, with the horizontal layer HL placed therebetween. The overlapping area of ​​the first work function electrode G11 and the horizontal layer HL may be greater than the overlapping area between each of the second work function electrode G12 and the third work function electrode G13 and the horizontal layer HL. The first work function electrode G11 may extend in the third direction D3. The second work function electrode G12 and the third work function electrode G13 may each have an independent structure overlapping the horizontal layer HL. For example, the first work function electrode G11 may include a channel overlapping portion WLP and a channel non-overlapping portion NOL. The second work function electrode G12 and the third work function electrode G13 may each be a portion of the channel overlap portion WLP. The second work function electrode G12 and the third work function electrode G13 and the first work function electrode G11 may directly contact each other.

[0065] As described above, the upper horizontal line G1 and the lower horizontal line G2 may each have a three-work function electrode structure including a first work function electrode G11, a second work function electrode G12, and a third work function electrode G13. The second wire DWL may include a first work function electrode G11 pair, a second work function electrode G12 pair, and a third work function electrode G13 pair, each extending in a third direction D3 intersecting the horizontal layer HL, and the horizontal layer HL is disposed between each of the first work function electrode G11 pair, the second work function electrode G12 pair, and the third work function electrode G13 pair. The first work function electrode G11, the second work function electrode G12, and the third work function electrode G13 may overlap vertically with the channel CH.

[0066] The second conductive line DWL may include, for example, Figure 1CThe channel overlap portion WLP and the channel non-overlap portion NOL shown. The channel overlap portion WLP may have a cross shape. In an embodiment (not shown), the channel overlap portion WLP may have a rhombus shape. The channel overlap portion WLP may completely overlap with the channel CH. Through the channel overlap portion WLP and the channel non-overlap portion NOL, the second wire DWL extending in the third direction D3 may have a notch-shaped sidewall. From a top view, the notch-shaped sidewall may be provided by a protruding portion of the channel overlap portion WLP and a recessed portion of the channel non-overlap portion NOL. The channel overlap portion WLP may include a first work function electrode G11, a second work function electrode G12, and a third work function electrode G13. The first work function electrode G11, the second work function electrode G12, and the third work function electrode G13 may overlap vertically with the channel CH.

[0067] In the second direction D2, the first work function electrode G11 having a high work function may be disposed at the central portion of the second wire DWL, and the second work function electrode G12 and the third work function electrode G13 having a low work function may be disposed on both sides of the second wire DWL. Therefore, leakage current, such as gate induced drain leakage (GIDL), may be significantly reduced.

[0068] Since the first work function electrode G11 having a high work function is disposed at the central portion of the second wire DWL, the threshold voltage of the switching element TR can be significantly increased. Since the second work function electrode G12 of the second wire DWL has a low work function, a low electric field can be formed between the first wire BL and the second wire DWL. Since the third work function electrode G13 of the second wire DWL has a low work function, a low electric field can be formed between the data storage element CAP and the second wire DWL.

[0069] As described above, the memory cell MC1 may include a second wire DWL having a three-work function electrode structure. Each of the upper horizontal line G1 and the lower horizontal line G2 of the second wire DWL may include a first work function electrode G11, a second work function electrode G12, and a third work function electrode G13. The first work function electrode G11 may overlap the channel CH. The second work function electrode G12 may be adjacent to the first wire BL and the first doping region SR. The third work function electrode G13 may be adjacent to the data storage element CAP and the second doping region DR. Therefore, a low electric field is formed between the second wire DWL and the first wire BL due to the low work function of the second work function electrode G12, so that leakage current can be significantly reduced. Therefore, a low electric field is formed between the second wire DWL and the data storage element CAP due to the low work function of the third work function electrode G13, so that leakage current can be significantly reduced. Therefore, due to the high work function of the first work function electrode G11, the threshold voltage of the switching element TR can be significantly increased. Furthermore, since the height of the memory cell MC1 can be significantly reduced due to the high work function of the first work function electrode G11, it has been found to be advantageous in terms of integration.

[0070] Figure 2 is a simplified schematic plan view of a semiconductor device according to an embodiment of the present disclosure. Figure 3A yes Figure 2 A simplified schematic perspective view of a first memory cell array MCA1 is shown. Figure 3B is along Figure 2 A cross-sectional view taken along line AA' in FIG. Figure 3C is along Figure 2 A cross-sectional view taken along line BB' in FIG. Figure 3D is along Figure 2 A cross-sectional view taken along line CC'.

[0071] Reference Figure 2 , Figure 3A , Figure 3B , Figure 3C and Figure 3D The semiconductor device 100 includes a memory cell array MCA, and the memory cell array MCA includes a plurality of memory cells MC. For each memory cell MC, it is possible to refer to Figures 1A to 1C Each memory cell MC may include a first conductive line BL, a switching element TR, and a data storage element CAP.

[0072] The memory cell array MCA may include a three-dimensional (3D) array of memory cells MC, the three-dimensional array of memory cells MC including a column array of memory cells MC and a row array of memory cells MC. In the column array of memory cells MC, a plurality of memory cells MC may be stacked in a first direction D1. In the row array of memory cells MC, a plurality of memory cells MC may be horizontally arranged in a second direction D2 and a third direction D3. The memory cell array MCA may include sub-memory cell arrays MCA1 adjacent to each other in the second direction D2. The sub-memory cell array MCA1 may have a mirror structure in which two memory cells MC share a first conductive line BL. In another embodiment, the semiconductor device 100 may further include a sub-memory cell array having a mirror structure in which two memory cells MC share a second electrode PN of a data storage element CAP. The memory cell array MCA may include a plurality of sub-memory cell arrays MCA1 in which memory cells MC are vertically stacked in the first direction D1. The memory cell array MCA may include a plurality of sub-memory cell arrays MCA1 horizontally arranged in the third direction D3.

[0073] In another embodiment, a plurality of sub memory cell arrays MCA1 may be arranged in the memory cell array MCA in the second direction D2. For example, the data storage elements CAP, the switching elements TR, the first conductive lines BL and the switching elements TR may be sequentially arranged in an alternating manner in the second direction D2.

[0074] The inter-cell dielectric layer IL may be disposed between each pair of memory cells MC stacked in the first direction D1. The inter-cell dielectric layer IL may include, for example, silicon oxide. The inter-cell dielectric layer IL may also be referred to as a horizontal inter-cell dielectric layer. The hard mask HM may be disposed on the highest level inter-cell dielectric layer IL (see Figure 3C ).

[0075] The cell isolation layers ISOA and ISOB may be disposed between the memory cells MC adjacent to each other in the third direction D3. The cell isolation layers ISOA and ISOB may also be referred to as vertical inter-cell dielectric layers. The cell isolation layers ISOA and ISOB may each include, for example, silicon oxide, silicon oxycarbide (SiCO), silicon nitride, or any combination thereof. The cell isolation layers ISOA and ISOB may include a first cell isolation layer ISOA and a second cell isolation layer ISOB. The first cell isolation layer ISOA and the second cell isolation layer ISOB may extend vertically in the first direction D1. The first cell isolation layer ISOA and the second cell isolation layer ISOB may each have a column structure extending vertically in the first direction D1. The first cell isolation layer ISOA and the second cell isolation layer ISOB may be alternately repeated and disposed in the second direction D2. The first cell isolation layer ISOA may be disposed between the data storage elements CAP in the third direction D3. The second cell isolation layer ISOB may be disposed between the first conductive lines BL in the third direction D3. The second conductive line DWL may be disposed between the first cell isolation layer ISOA and the second cell isolation layer ISOB in the second direction D2. The first cell isolation layer ISOA and the second cell isolation layer ISOB may each include a stack of a cell isolation liner layer ISOL and a cell isolation gap-filling layer ISOG. The cell isolation liner layer ISOL may each include silicon oxide. The cell isolation gap-filling layer ISOG may each include silicon oxycarbide.

[0076] The memory cell array MCA may be disposed over the lower structure LS.

[0077] The memory cell array MCA may include a plurality of second conductive lines DWL vertically stacked in a first direction D1. The memory cell array MCA may also include a plurality of horizontal layers HL vertically stacked in the first direction D1. The memory cell array MCA may also include a plurality of data storage elements CAP vertically stacked in the first direction D1. The memory cell array MCA may also include a plurality of first conductive lines BL spaced apart from each other in a third direction D3.

[0078] The second conductive line DWL may include, for example, Figure 1C The channel overlap portion WLP and the channel non-overlap portion NOL shown. The channel overlap portion WLP may have a cross shape. In an embodiment (not shown), the channel overlap portion WLP may have a rhombus shape. The channel overlap portion WLP may completely overlap with the channel CH. The second conductor DWL extending in the third direction D3 may include a plurality of channel overlap portions WLP. Since the channel overlap portion WLP and the channel non-overlap portion NOL are alternately repeated in the third direction D3, the second conductor DWL may have a notch-shaped sidewall.

[0079] The protection layer structure may be disposed between the lowest second wire DWL among a plurality of second wires DWL and the lower structure LS. The protection layer structure may include a stack of a first protection layer BF1 and a second protection layer BF2. The first protection layer BF1 may be thinner than the second protection layer BF2. The first protection layer BF1 may cover the entire surface of the lower structure LS. The first protection layer BF1 and the second protection layer BF2 may be disposed between the first wire BL and the lower structure LS. The first protection layer BF1 and the second protection layer BF2 may be disposed between the data storage element CAP and the lower structure LS. The first wire BL and the data storage element CAP may be electrically separated from the lower structure LS by the first protection layer BF1 and the second protection layer BF2. The first protection layer BF1 and the second protection layer BF2 may be represented as a bottom dielectric layer or a bottom passivation layer. The first protection layer BF1 and the second protection layer BF2 may each include a dielectric material, such as silicon oxide.

[0080] The lower structure LS may include a plurality of support members LP. The support member LP is a part of the lower structure LS and may be a structure for supporting the memory cell array MCA. The support member LP and the lower structure LS may include the same material. The support member LP may include a thin protrusion LPA. A protection layer spacer HLS' may be formed on a side of each thin protrusion LPS. Figure 3B , the horizontal orientation length of the horizontal layer HL in the second direction D2 may be smaller than the horizontal orientation length of the support member LP. Figure 3C As shown, the horizontal orientation length of the horizontal layer HL in the third direction D3 may be smaller than the horizontal orientation length of the support member LP.

[0081] The first wire BL may extend vertically from the upper portion of the lower structure LS in the first direction D1. The horizontal layer HL may extend in the second direction D2 intersecting the first direction D1. The second wire DWL may extend in the third direction D3 intersecting the first direction D1 and the second direction D2.

[0082] From a top view, the horizontal layer HL may have a cross shape as shown, or may have a diamond shape in another embodiment (not shown). In another embodiment, the side of the horizontal layer HL may have a bent shape or a rounded (also called curved) shape. Figure 1B As shown, the horizontal layer HL may include a channel CH, a first doping region SR between the channel CH and the first conductive line BL, and a second doping region DR between the channel CH and the data storage element CAP. Return to reference Figure 3C , the horizontal level spacers HLS may be formed on the side of the horizontal layer HL. The horizontal level spacers HLS may each include a dielectric material such as silicon oxide. The protection level spacers HLS′ and the horizontal level spacers HLS may include the same material.

[0083] The first cover layer BC may be disposed between the second wire DWL and the first wire BL. The second cover layer CC may be disposed between the second wire DWL and the first electrode SN of the data storage element CAP. The first cover layer BC may be disposed between the upper horizontal line G1 and the first wire BL. In addition, the first cover layer BC may be disposed between the lower horizontal line G2 and the first wire BL. The second cover layer CC may be disposed between the upper horizontal line G1 and the first electrode SN of the data storage element CAP. In addition, the second cover layer CC may be disposed between the lower horizontal line G2 and the first electrode SN of the data storage element CAP. One memory cell MC may include a pair of first cover layers BC and a pair of second cover layers CC.

[0084] The first cover layer BC and the second cover layer CC may each include a dielectric material including, for example, silicon oxide, silicon nitride, silicon oxycarbide, an air gap, or any combination thereof. In an embodiment, the first cover layer BC may include silicon oxide, and the second cover layer CC may include a stack of silicon oxide and silicon nitride. In another embodiment, the first cover layer BC may include a stack of silicon oxide and silicon nitride.

[0085] The memory cell MC may further include a first contact node BLC and a second contact node SNC. The first contact node BLC may surround the outer wall of the first conductive line BL. The second contact node SNC may be disposed between the horizontal layer HL and the first electrode SN. The first contact node BLC may include a metal-based material or a semiconductor material. The second contact node SNC may include a metal-based material or a semiconductor material. For example, the first contact node BLC and the second contact node SNC may each include titanium, titanium nitride, tungsten, or any combination thereof. In addition, the first contact node BLC and the second contact node SNC may each include doped polysilicon. The first doping region SR and the second doping region DR may include impurities diffused from the first contact node BLC and the second contact node SNC, respectively.

[0086] The horizontal layers HL of the switching elements TR horizontally arranged in the third direction D3 may share one second wire DWL. The horizontal layers HL of the switching elements TR horizontally arranged in the third direction D3 may be connected to first wires BL different from each other. The switching elements TR stacked in the first direction D1 may share one first wire BL. The switching elements TR horizontally arranged in the third direction D3 may share one second wire DWL.

[0087] The first cell isolation layer ISOA may be disposed between the first electrodes SN of the data storage elements CAP in the third direction D3 for isolating the first electrodes SN from each other. The second electrodes PN of the data storage elements CAP may be connected to the common plate PL.

[0088] The lower structure LS may include a semiconductor substrate, a metal line structure, a dielectric structure, a conductive structure, a bonding pad structure, other types of memory or a peripheral circuit unit.

[0089] For example, the lower structure LS may include a structure in which a peripheral circuit unit, a metal line structure, and a bonding pad structure are sequentially stacked. The memory cell array MCA and the peripheral circuit unit of the lower structure LS may be combined by wafer bonding.

[0090] The peripheral circuit unit of the lower structure LS may be arranged at a level lower than the memory cell array MCA, which may also be referred to as a peripheral upper unit (COP) structure. The peripheral circuit unit may include at least one control circuit for driving the memory cell array MCA. At least one control circuit of the peripheral circuit unit may include an N-channel transistor, a P-channel transistor, a CMOS circuit, or any combination thereof. At least one control circuit of the peripheral circuit unit may include an address decoder circuit, a read circuit, and a write circuit. At least one control circuit of the peripheral circuit unit may include a planar channel transistor, a recessed channel transistor, a buried gate transistor, and a fin channel transistor (FinFET).

[0091] For example, the peripheral circuit unit may include a sub word line driver and a sense amplifier. The first conductive line BL may be connected to the sense amplifier. The second conductive line DWL may be connected to the sub word line driver.

[0092] In another embodiment, the peripheral circuit unit may be arranged at a level higher than the memory cell array MCA, which may also be referred to as a peripheral on cell (POC) structure. In this case, the lower structure LS may include a first semiconductor substrate. The peripheral circuit unit may include a second semiconductor substrate.

[0093] In another embodiment, the memory cell array MCA may include DRAM, embedded DRAM, NAND, FeRAM, STTRAM, PCRAM, or ReRAM.

[0094] In another embodiment, a single memory cell MC may be used Figure 1D The storage cell MCl is replaced.

[0095] FIG. 4A to FIG. 4C , Figure 5A and Figure 5B Figure 6 7A to 7C , FIG. 8A to FIG. 8C , Fig.9A and Fig. 9B , Fig. 10A and Fig. 10B , Fig.11A and Fig. 11B , Fig. 12A and Fig. 12B , Fig.13A and Fig. 13B , Fig.14 , FIG. 15A to FIG. 15D , Fig.16A and Fig. 16B , Fig.17A and Fig. 17B , Fig.18A and Fig.18B , Fig.19A and Fig.19B , Fig. 20A and Fig. 20B , Fig.21A and Fig. 21B , Fig.22A and Fig. 22B , Fig.23A and Fig. 23B as well as Fig.24A and Fig. 24B is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0096] Figure 4A 15A and 15B are plan views of the hierarchy of the fourth layer 14 showing a method of forming the stacked body SB and the sacrificial isolation openings 15A and 15B. Figure 4B is along Figure 4A A cross-sectional view taken along line AA' in FIG. Figure 4C is along Figure 4A A cross-sectional view taken along line BB' in FIG.

[0097] like FIG. 4A to FIG. 4C As shown, the stack SB can be formed on the lower structure 11. The lower structure 11 can be a material suitable for semiconductor processing, including at least one of a conductive material, a dielectric material and a semiconductor material. A variety of materials can be formed on the lower structure 11. The lower structure 11 may include a semiconductor substrate. For example, the lower structure 11 may be made of a material containing silicon. The lower structure 11 may include silicon, single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium, single crystal silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, or any combination thereof or multilayers thereof. The lower structure 11 may also include another semiconductor material, such as germanium. The lower structure 11 may also include a compound semiconductor substrate, such as a III / V semiconductor substrate, such as GaAs. The lower structure 11 may also include a silicon-on-insulator (SOI) substrate.

[0098] A plurality of sub-stacks may be alternately stacked on the stack SB. The first layer 12A, the second layer 13, the third layer 12B, and the fourth layer 14 may be stacked in sequence on each sub-stack. The first layer 12A and the third layer 12B may include the same material, and may include silicon germanium or single crystal silicon germanium. The second layer 13 and the fourth layer 14 may include the same material, and may include single crystal silicon. The first layer 12A, the second layer 13, the third layer 12B, and the fourth layer 14 may be formed by epitaxial growth. The first layer 12A at the lowest level of the stack SB may act as a seed layer during the epitaxial growth process. The first layer 12A may be thinner than the second layer 13. The fourth layer 14 may be thicker than the second layer 13.

[0099] In the present embodiment, the stack SB may include a plurality of fourth layers 14, a first stack SB1, a second stack SB2, and a third stack SB3. The first stack SB1, the fourth layer 14, the second stack SB2, the fourth layer 14, and the third stack SB3 may be stacked in the stack SB, for example, in the order described. The first stack SB1, the second stack SB2, and the third stack SB3 may each include a three-layer stack of a first layer 12A, a second layer 13, and a third layer 12B. For example, if the first layer 12A and the third layer 12B each include a silicon germanium layer and the second layer 13 each includes a single crystal silicon layer, the first stack SB1, the second stack SB2, and the third stack SB3 may each include a first silicon germanium / single crystal silicon / second silicon germanium (SiGe / Si / SiGe) stack. The third stack SB3 may also include a second layer 13 on the three-layer stack of the first layer 12A, the second layer 13, and the third layer 12B.

[0100] The second layer 13 may include a first single crystal silicon layer. The fourth layer 14 may include a second single crystal silicon layer. The second single crystal silicon layer may be thicker than the first single crystal silicon layer. Therefore, in the stacked body SB, the first stack SB1 may be disposed below the second single crystal silicon layer, and the second stack SB2 may be disposed above the second single crystal silicon layer. Both the first stack SB1 and the second stack SB2 may include a three-layer stack of a first silicon germanium layer / a first single crystal silicon layer / a second silicon germanium layer. The second single crystal silicon layer may be thicker than the first single crystal silicon layer.

[0101] The first layer 12A, the second layer 13, and the third layer 12B may also be referred to as “sacrificial layers.” The fourth layer 14 may also be referred to as a recess target layer.

[0102] The stack SB may also be referred to as a vertical stack. A plurality of sacrificial layers and a plurality of recessed target layers may be alternately formed on the stack SB. The sacrificial layers may include a first stack SB1, a second stack SB2, and a third stack SB3. The first stack SB1, the second stack SB2, and the third stack SB3 may each include a three-layer stack of a first layer 12A, a second layer 13, and a third layer 12B. The recessed target layer may include a fourth layer 14. The sacrificial layers may each include a three-layer stack of a first silicon germanium layer / a first single crystal silicon layer / a second silicon germanium layer. The recessed target layer may each include a single-layer second single crystal silicon layer. The second single crystal silicon layer may be thicker than the first single crystal silicon layer.

[0103] like Figures 2 to 3D As shown, if the memory cells MC are vertically stacked, the first stack SB1, the fourth layer 14, the second stack SB2, the fourth layer 14, and the third stack SB3 may be alternately stacked several times.

[0104] Next, if Figure 4A As shown, a plurality of sacrificial isolation openings 15A and 15B can be formed by etching a portion of the stack SB. The sacrificial isolation openings 15A and 15B are initial openings for unit isolation, and may include a large opening 15A and a small opening 15B. The size of each large opening 15A may be greater than the size of each small opening 15B. From a top view, the large opening 15A and the small opening 15B may each have a rectangular shape. However, the present invention is not limited thereto. For example, in another embodiment, the large opening 15A and the small opening 15B may each have a circular shape or an elliptical shape. In another embodiment, the sacrificial isolation openings 15A and 15B may be sacrificial isolation trenches. The large opening 15A and the small opening 15B may extend vertically in the first direction D1. The large opening 15A and the small opening 15B may be alternately arranged in the second direction D2. A plurality of large openings 15A may be arranged in the third direction D3. A plurality of small openings 15B may be arranged in the third direction D3. The large opening 15A and the small opening 15B may pass through the stack SB in the first direction D1.

[0105] After forming the sacrificial isolation openings 15A and 15B, the exposed portion of the lower structure 11 below the sacrificial isolation openings 15A and 15B may be etched. Therefore, the bottom of the sacrificial isolation openings 15A and 15B may extend into the lower structure 11. The bottoms of the sacrificial isolation openings 15A and 15B may each include a U-shaped profile. The fourth layer 14 may have a mesh pattern through the sacrificial isolation openings 15A and 15B.

[0106] Figure 5A 1 is a plan view of the hierarchy of the fourth layer 14 showing a method of forming the sacrificial isolation layers 16A and 16B. Figure 5B is along Figure 5A A cross-sectional view taken along line BB' in FIG.

[0107] like Figure 5A and Figure 5B As shown, sacrificial isolation layers 16A and 16B filling the sacrificial isolation openings 15A and 15B may be formed. The sacrificial isolation layers 16A and 16B may include a first sacrificial isolation layer 16A and a second sacrificial isolation layer 16B. The first sacrificial isolation layer 16A may fill the large openings 15A, respectively. The second sacrificial isolation layer 16B may fill the small openings 15B, respectively.

[0108] The first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B may include the same material. The first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B may be formed of a dielectric material. Forming the first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B may include forming a sacrificial isolation material on the stack SB so as to fill the sacrificial isolation openings 15A and 15B and flattening the sacrificial isolation material so that the highest layer of the stack SB is exposed. The first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B may have different sizes or different volumes. For example, the size (or volume) of each first sacrificial unit isolation layer 16A may be greater than the size (or volume) of each second sacrificial isolation layer 16B. The lengths of the first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B in the third direction D3 may be the same. The lengths of the first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B in the second direction D2 may be different from each other. The length of the first sacrificial isolation layer 16A in the second direction D2 may be greater than the length of the second sacrificial isolation layer 16B.

[0109] The first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B may extend vertically in the first direction D1. The first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B may be alternately arranged in the second direction D2. A plurality of first sacrificial isolation layers 16A may be arranged in the third direction D3. A plurality of second sacrificial isolation layers 16B may be arranged in the third direction D3. The first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B may pass through the stack SB in the first direction D1.

[0110] The first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B may include the same material. The first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B may be formed of a dielectric material. For example, the first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B may include silicon oxide, silicon nitride, silicon oxycarbide, silicon carbonitride, or any combination thereof.

[0111] Fig. 6A is a plan view of the hierarchy of the fourth layer 14 showing a method of forming the sacrificial vertical openings V1 ′ and V2 ′. Figure 6B is along Fig. 6A A cross-sectional view taken along line AA' in FIG.

[0112] like Fig. 6A and Figure 6B As shown, a hard mask layer pattern 17 may be formed on the stacked body SB, the first sacrificial isolation layer 16A, and the second sacrificial isolation layer 16B. The hard mask layer pattern 17 may include silicon nitride. The hard mask layer pattern 17 may be formed by etching using a mask layer and may define a plurality of hole-shaped openings.

[0113] Next, a portion of the stacked body SB may be etched by using the hard mask layer pattern 17 as an etching barrier to form a plurality of sacrificial vertical openings V1' and V2' in the stacked body SB. The sacrificial vertical openings V1' and V2' may include a first sacrificial vertical opening V1' and a second sacrificial vertical opening V2'. The first sacrificial vertical opening V1' and the second sacrificial vertical opening V1' may be hole-shaped openings. The first sacrificial vertical opening V1' and the second sacrificial vertical opening V2' may extend vertically in the first direction D1. The first sacrificial vertical opening V1' and the second sacrificial vertical opening V2' may be formed by etching the stacked body SB between the first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B. The first sacrificial vertical opening V1' may be formed by etching the stacked body SB between the second sacrificial isolation layer 16B. The second sacrificial vertical opening V2' may be formed by etching the stacked body SB between the first sacrificial isolation layers 16A. The first sacrificial vertical opening V1' may be disposed between the second sacrificial isolation layers 16B in the third direction D3. The second sacrificial vertical opening V2' may be disposed between the first sacrificial isolation layers 16A in the third direction D3. From a top view, a cross-section of each of the first sacrificial vertical opening V1 ′ and the second sacrificial vertical opening V2 ′ may be rectangular, circular, or elliptical.

[0114] Fig. 7A is a plan view showing a method of forming the preliminary horizontal layer 14A. Figure 7B is along Fig. 7A A cross-sectional view taken along line AA' in FIG. Figure 7C is along Fig. 7A A cross-sectional view taken along line BB' in FIG.

[0115] like 7A to 7C As shown, a portion of the hard mask layer pattern 17 (refer to reference numeral 17T) may be trimmed.

[0116] Next, the first layer 12A and the third layer 12B may be selectively removed through the first sacrificial vertical opening V1' and the second sacrificial vertical opening V2'. In order to selectively remove the first layer 12A and the third layer 12B, the difference between the etching selectivity of the second layer 13 and the fourth layer 14 and the first layer 12A and the third layer 12B may be utilized. The first layer 12A and the third layer 12B may be removed by using wet etching or dry etching. For example, if the first layer 12A and the third layer 12B both include silicon germanium layers and the second layer 13 and the fourth layer 14 both include single crystal silicon layers, the silicon germanium layers may be etched by using an etchant or etching gas that is selective to the single crystal silicon layer.

[0117] Next, the second layer 13 and the fourth layer 14 may be recessed. To recess the second layer 13 and the fourth layer 14, wet etching or dry etching may be used. In an embodiment, the fourth layer 14 may be partially etched while removing the second layer 13. Therefore, the second layer 13 may be removed, and the fourth layer 14 may be thinned, as shown in the reference numeral "14A". The recessing process for forming the thinned fourth layer 14A, i.e., the preliminary horizontal layer 14A, may also be referred to as a thinning process or a trimming process of the fourth layer 14. In order to form the preliminary horizontal layer 14A, the upper surface, the lower surface, and the side of the fourth layer 14 may be recessed. The preliminary horizontal layers 14A may also be referred to as thin-body active layers. The preliminary horizontal layers 14A may each include a single crystal silicon layer. For example, hot SC-1 (HSC1) may be used in the recessing process for forming the preliminary horizontal layer 14A. HSC1 may include a solution in which ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2), and water (H2O) are mixed in a ratio of 1:4:20, respectively. The second layer 13 and the fourth layer 14 can be selectively etched by using such an HSC1.

[0118] The preliminary horizontal layer 14A may be formed by a recessing process of the fourth layer 14, and horizontal-shaped recesses 18 are disposed between the preliminary horizontal layers 14A. The upper and lower surfaces of the preliminary horizontal layer 14A may be flat surfaces.

[0119] From a top view, the preliminary horizontal layers 14A may each have a cross shape. Side surfaces of the preliminary horizontal layers 14A may each have a bent shape or a rounded shape.

[0120] After forming the preliminary horizontal layer 14A, the first sacrificial vertical opening and the second sacrificial vertical opening may extend, as shown in reference numerals V1 and V2. The preliminary horizontal layers 14A may be isolated from each other in the second direction D2 by the first sacrificial vertical opening V1 and the second sacrificial vertical opening V2. The preliminary horizontal layers 14A may each have a shape in which a plurality of cross shapes are merged in the third direction D3.

[0121] When the preliminary horizontal layer 14A is formed, the surface of the lower structure 11 may be recessed by a predetermined depth (see reference numeral ' 11A'). Thus, the depths of the first sacrificial vertical openings V1 and the second sacrificial vertical openings V2 may be increased.

[0122] The first sacrificial vertical openings V1 and the second sacrificial vertical openings V2 may be alternately disposed between the preliminary horizontal layers 14A in the second direction D2. The first sacrificial vertical openings V1 may be disposed between the second sacrificial isolation layers 16B in the third direction D3. The second sacrificial vertical openings V2 may be disposed between the first sacrificial isolation layers 16A in the third direction D3.

[0123] Fig. 8A 1 is a plan view showing a method of forming the interlayer dielectric layer 19 and the horizontal conductive layer 20 . Figure 8B is along Fig. 8A A cross-sectional view taken along line AA' in FIG. Figure 8C is along Fig. 8A A cross-sectional view taken along line BB' in FIG.

[0124] like FIG. 8A to FIG. 8C As shown, an interlayer dielectric layer 19 may be formed to completely cover or surround the preliminary horizontal layer 14A. The interlayer dielectric layer 19 may also be referred to as a gate dielectric layer. The interlayer dielectric layer 19 may also be referred to as a horizontal layer side dielectric layer. The interlayer dielectric layer 19 may include silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicate, high-k material, ferroelectric material, antiferroelectric material, or any combination thereof. The interlayer dielectric layer 19 may include SiO2, Si3N4, HfO2, Al2O3, ZrO2, AlON, HfON, HfSiO, HfSiON, HfZrO, or any combination thereof.

[0125] The interlayer dielectric layer 19 may be formed by oxidizing the surface of the preliminary horizontal layer 14A. In another embodiment, the interlayer dielectric layer 19 may be formed by a process of depositing silicon oxide.

[0126] When the interlayer dielectric layer 19 is formed, a first protective layer 19D may be formed on the surface of the lower structure 11. The interlayer dielectric layer 19 and the first protective layer 19D may include the same material.

[0127] The horizontal conductive layer 20 may be formed on the interlayer dielectric layer 19. The horizontal conductive layer 20 may include a metal-based material, a semiconductor material, or any combination thereof. The horizontal conductive layer 20 may include titanium nitride, tungsten, polysilicon, or any combination thereof. For example, the horizontal conductive layer 20 may include a TiN / W stack in which titanium nitride and tungsten are sequentially stacked. The horizontal conductive layer 20 may include an N-type work function material or a P-type work function material. The N-type work function material may have a low work function of 4.5 eV or less. The P-type work function material may have a high work function greater than 4.5 eV. When forming the horizontal conductive layer 20, a dummy horizontal conductive layer 20D may be formed on the first protective layer 19D. The horizontal conductive layer 20 and the dummy horizontal conductive layer 20D may include the same material.

[0128] The inter-cell dielectric layer 21 may be formed on the horizontal conductive layer 20. The inter-cell dielectric layer 21 may be filled between the horizontal conductive layers 20 vertically adjacent to each other. The inter-cell dielectric layer 21 may include silicon oxide. Portions of the inter-cell dielectric layer 21 may be conformally formed on the surfaces of the first sacrificial vertical opening V1 and the second sacrificial vertical opening V2. The horizontally shaped recess ( Figure 7B and Figure 7C 18) in the example may be filled with a horizontal conductive layer 20 and an inter-cell dielectric layer 21.

[0129] The sacrificial column 22 may be formed on the inter-cell dielectric layer 21 disposed in the first sacrificial vertical opening V1 and the second sacrificial vertical opening V2. The sacrificial column 22 may include amorphous carbon as a sacrificial material. In another embodiment, a column cover layer may also be formed on the sacrificial column 22. The column cover layer may include a metal-based material. The column cover layer may include titanium nitride. Forming the sacrificial column 22 may include depositing a sacrificial material and planarizing the sacrificial material. Planarization for forming the sacrificial column 22 may be performed until the uppermost level horizontal conductive layer 20 is exposed. Subsequently, the uppermost level inter-cell dielectric layer 21 may also be planarized until the uppermost level horizontal conductive layer 20 is exposed. The sacrificial column 22 may not be formed between the vertically stacked horizontal conductive layers 20.

[0130] The inter-unit dielectric layer 21 and the sacrificial column 22 can form a first sacrificial column structure SV1 and a second sacrificial column structure SV2 filling the first sacrificial vertical opening V1 and the second sacrificial vertical opening V2. The first sacrificial column structure SV1 can fill the first sacrificial vertical opening V1. The second sacrificial column structure SV2 can fill the second sacrificial vertical opening V2. In another embodiment, the first sacrificial column structure SV1 and the second sacrificial column structure SV2 can both include a dielectric material, a carbon-containing material, a metal-based material, or any combination thereof. In another embodiment, the first sacrificial column structure SV1 and the second sacrificial column structure SV2 can both include silicon oxide, silicon nitride, titanium nitride, amorphous carbon, or any combination thereof. From a top view, the first sacrificial column structure SV1 and the second sacrificial column structure SV2 can both be hole-shaped sacrificial columns.

[0131] Return to reference Figure 8C , the horizontal conductive layer 20 may be formed between the preliminary horizontal layers 14A. The inter-cell dielectric layer 21 may be disposed within the horizontal conductive layer 20. The horizontal conductive layer 20 may surround the inter-cell dielectric layer 21. The horizontal conductive layer 20 may include a first surrounding portion and a second surrounding portion. In this case, the first surrounding portion may surround the preliminary horizontal layer 14A in the AA' direction, and the second surrounding portion may surround the inter-cell dielectric layer 21 in the BB' direction.

[0132] The sub-stacks of the stack SB can be FIG. 4A to FIG. 8C The series of processes shown in FIG. 1 are replaced by a unit mold. The first layer 12A, the second layer 13, and the third layer 12B can be replaced by a horizontal conductive layer 20 and an inter-unit dielectric layer 21. The fourth layer 14 can be changed into a preliminary horizontal layer 14A by a recess process. The horizontal conductive layers 20 can also be referred to as trimming target layers.

[0133] Fig.9A 2 is a plan view showing a method of forming the cell isolation openings 23A and 23B. Fig. 9B is along Fig.9A A cross-sectional view taken along line BB' in FIG.

[0134] like Fig.9A and Fig. 9B As shown, in order to form the cell isolation openings 23A and 23B, the first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B may be removed. When the first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B are removed, the first sacrificial column structure SV1 and the second sacrificial column structure SV2 may be covered by the mask layer. The side surfaces of the preliminary horizontal layer 14A and the horizontal conductive layer 20 may be exposed in the BB' direction through the cell isolation openings 23A and 23B.

[0135] Subsequently, a first trimming process may be performed. For example, the interlayer dielectric layer 19 may be exposed by the first trimming process. The first trimming process may include trimming (19T) the portion of the interlayer dielectric layer 19 exposed by the cell isolation openings 23A and 23B. The first trimming process may be performed horizontally in the third direction D3. Therefore, the width of each interlayer dielectric layer 19 in the third direction D3 may be reduced. All interlayer dielectric layers 19 may be removed in the second direction D2. The interlayer dielectric layer 19 may also be referred to as a dielectric target layer. The horizontal conductive layer 20 may also be referred to as a conductive target layer. The first trimming process may be performed horizontally in the second direction D2 between the cell isolation openings 23A and 23B.

[0136] Fig. 10A It is a plan view showing the second trimming process. Fig. 10B is along Fig. 10A A cross-sectional view taken along line BB' in FIG.

[0137] like Fig. 10A and Fig. 10B As shown, the preliminary horizontal layer 14A may be exposed to a second trimming process. The second trimming process may include trimming the side of the preliminary horizontal layer 14A in the second direction D2 and the third direction D3 through the cell isolation openings 23A and 23B. The second trimming process may be performed horizontally in the second direction D2 and the third direction D3. Therefore, the width of each preliminary horizontal layer 14A in the third direction D3 may be reduced. A horizontal level gap 14R may be formed on the side of the trimmed preliminary horizontal layer, that is, the side of the horizontal layer 14B. The horizontal level gap 14R may be set between the horizontal conductive layers 20 vertically adjacent to each other. The horizontal layer 14B may also be referred to as a "trimmed horizontal layer pattern".

[0138] When the horizontal layer 14B is formed, the surface of the lower structure 11 , for example, the bottoms of the cell isolation openings 23A and 23B may be extended.

[0139] After the second trimming process, a horizontal layer 14B may be formed along line BB'. All preliminary horizontal layers 14A between the cell isolation openings 23A and 23B adjacent to each other in the second direction D2 may be removed. When trimming the preliminary horizontal layer 14A, the surface of the lower structure 11 may be partially recessed (see reference numeral 11'). Therefore, a support member 11P may be formed under the first protective layer 19D. The support member 11P may include a thin protrusion 11B. The thin protrusion 11B may be in direct contact with the first protective layer 19D. The horizontal layer pattern 14B, the thin protrusion 11B, and the first protective layer 19D may have the same line width in the third direction D3.

[0140] The horizontal layer 14B may be arranged between the first sacrificial column structure SV1 and the second sacrificial column structure SV2 in the second direction D2. From a top view, the horizontal layers 14B may each have a cross shape. The horizontal layers 14B may each have a cross shape, the size of which is smaller than the cross shape of each preliminary horizontal layer 14A. The preliminary horizontal layer 14A may have a shape in which a plurality of cross shapes are merged. The horizontal layer 14B may have a shape in which its cross shape is individually separated in the third direction D3. The horizontal level gap 14R may be formed between the horizontal layers 14B arranged in the third direction D3. The first sacrificial column structure SV1 and the second sacrificial column structure SV2 may be arranged between the horizontal layers 14B in the second direction D2.

[0141] After the cell isolation openings 23A and 23B are opened as described above, trimming of the interlayer dielectric layer 19 (i.e., the first trimming process) and trimming of the preliminary horizontal layer 14A (i.e., the second trimming process) may be performed sequentially. The first trimming process and the second trimming process may be performed mainly in the third direction D3. The trimming width of the interlayer dielectric layer 19 and the trimming width of the preliminary horizontal layer 14A may be the same. If the preliminary horizontal layer 14A is trimmed by the second trimming process after the interlayer dielectric layer 19 is trimmed by the first trimming process, although a load effect occurs due to a reduction of the trimming target of the preliminary horizontal layer 14A by about 20 times, the attack on the lower structure 11 may be reduced. As a result, because the loss of the support member 11P is minimized, the supporting force of the support member 11P may be enhanced.

[0142] As a comparative example, if the interlayer dielectric layer 19 is trimmed after the preliminary horizontal layer 14A is trimmed, the loss of the support member 11P when trimming the preliminary horizontal layer 14A may thus be significantly increased.

[0143] As another comparative example, if the interlayer dielectric layer 19 is not trimmed after the preliminary horizontal layer 14A is trimmed, voids may be caused when forming subsequent horizontal-level spacers because the horizontal-level gap 14R has a small vertical height.

[0144] Fig.11A is a plan view showing a method of forming the horizontal-level spacer 23C. Fig. 11B is along Fig.11A A cross-sectional view taken along line BB' in FIG.

[0145] like Fig.11A and Fig. 11BAs shown, the horizontal level spacer 23C can be formed on the side of the horizontal layer 14B. Forming the horizontal level spacer 23C can include forming a spacer material on the side of the horizontal layer 14B and also etching the formed spacer material. The horizontal level spacer 23C may include a dielectric material, such as silicon oxide. The horizontal level spacer 23C can fill the horizontal level gap 14R. This method is advantageous because when forming the horizontal level spacer 23C, since the vertical height of the horizontal level gap 14R is large, the gap can be easily controlled. That is, a horizontal level spacer 23C without a gap can be formed.

[0146] The horizontal layers 14B disposed in the third direction D3 may be isolated from each other by the horizontal level spacers 23C.

[0147] When forming the horizontal level spacer 23C, the protection level spacer 23D may be formed on the side of the thin protrusion portion 11B and the first protection layer 19D.

[0148] Fig. 12A is a plan view showing the recess of the horizontal conductive layer. Fig. 12B is along Fig. 12A A cross-sectional view taken along line BB' in FIG.

[0149] like Fig. 12A and Fig. 12B As shown, portions of the horizontal conductive layer 20 may be horizontally trimmed by the cell isolation openings 23A and 23B. Therefore, when viewed from line BB', a pair of horizontal conductive layers 20 may be disposed between the horizontal layers 14B, and one inter-cell dielectric layer 21 may be disposed between the pair of horizontal conductive layers 20.

[0150] Reference Fig.9A and Fig. 9B , Fig. 10A and Fig. 10B , Fig.11A and Fig. 11B as well as Fig. 12A and Fig. 12B , the width of each horizontal conductive layer 20 between the cell isolation openings 23A and 23B in the third direction D3 may be greater than the width of each horizontal layer 14B. Incidentally, the trimming depth of each horizontal conductive layer 20 in the third direction D3 may be less than the trimming depth of each preliminary horizontal layer 14A.

[0151] A pair of horizontal conductive layers 20 may vertically overlap one horizontal layer 14B. The trimmed horizontal conductive layer 20 may also be referred to as a "trimming target layer" or a "trimmed horizontal conductive layer."

[0152] Fig.13A is a plan view illustrating a method of forming the cell isolation layers 24A and 24B. Fig. 13B is along Fig.13A A cross-sectional view taken along line BB' in FIG. Fig.14 is a plan view at the level of the horizontal conductive layer 20 showing a method of forming the cell isolation layers 24A and 24B.

[0153] like Fig.13A and Fig. 13B As shown, cell isolation layers 24A and 24B filling the cell isolation openings 23A and 23B may be formed. The cell isolation layers 24A and 24B may include a first cell isolation layer 24A and a second cell isolation layer 24B. The first cell isolation layer 24A and the second cell isolation layer 24B may include the same material, such as a dielectric material. The dielectric material for the first cell isolation layer 24A and the second cell isolation layer 24B may include silicon oxide, silicon nitride, silicon oxycarbide, silicon carbonitride, or any combination thereof. From a top view, the outermost material of the first cell isolation layer 24A and the second cell isolation layer 24B may include silicon oxycarbide.

[0154] Forming the first cell isolation layer 24A and the second cell isolation layer 24B may include forming a cell isolation material filling the cell isolation openings 22A and 22B and planarizing the cell isolation material and the highest horizontal conductive layer 20 so that the surface of the hard mask layer pattern 17 is exposed. The first cell isolation layer 24A and the second cell isolation layer 24B may have different sizes or different volumes. The first cell isolation layer 24A and the second cell isolation layer 24B may include a dual structure of silicon oxide and silicon oxycarbide. For example, after depositing silicon oxide, silicon oxycarbide may be deposited. In another embodiment, the first cell isolation layer 24A and the second cell isolation layer 24B may include an embedded air gap. An embedded air gap may be provided when silicon oxycarbide is deposited. The second sacrificial column structure SV2 may be disposed between the first cell isolation layer 24A in the third direction D3. The first sacrificial column structure SV1 may be disposed between the second cell isolation layer 24B in the third direction D3. The first cell isolation layer 24A and the second cell isolation layer 24B may extend vertically in the first direction D1.

[0155] The first cell isolation layer 24A and the second cell isolation layer 24B may correspond to, for example, Figures 2 to 3B Those shown are cell isolation layers ISOA and ISOB.

[0156] The first and second cell isolation layers 24A and 24B and the horizontal conductive layer 20 may directly contact each other. A horizontal level spacer 23C may be disposed between the horizontal layer 14B and the first and second cell isolation layers 24A and 24B.

[0157] Fig.14 2 is a plan view showing a method of forming the first hole-shaped vertical opening 27 . FIG. 15A to FIG. 15D Can be along Fig.14 A cross-sectional view taken along line AA' in FIG.

[0158] First, if Fig.15A As shown, in order to form the hard mask level recess 25 , the hard mask layer pattern 17 and the highest level horizontal conductive layer 20 may be removed.

[0159] like Fig. 15B As shown, a top dielectric layer 26 may be formed filling the hard mask level recess 25. The top dielectric layer 26 may include silicon oxide.

[0160] like Fig. 15C As shown, forming the vertical level path 27 ′ includes removing the sacrificial post 22 of the first sacrificial post structure SV1 .

[0161] The dummy horizontal conductive layer 20D may be exposed by etching the inter-cell dielectric layer 21 at the bottom of the vertical step path 27 ′.

[0162] Next, the lower-stage gap 20R may be formed by removing the dummy horizontal conductive layer 20D.

[0163] like Fig.15D As shown, the lower gap 20R may be filled with a second protective layer 28. The second protective layer 28 may include silicon oxide. The first protective layer 19D may be retained between the second protective layer 28 and the lower structure 11. The first protective layer 19D may also be referred to as a first lower protective layer. The second protective layer 28 may also be referred to as a second lower protective layer.

[0164] Next, in order to form the first hole-shaped vertical opening 27 , the inter-cell dielectric layer 21 may be horizontally cut.

[0165] Subsequently, one side of the horizontal conductive layer 20 may be selectively recessed from the first hole-shaped vertical opening 27. A portion of the interlayer dielectric layer 19 may be exposed by the partial recessing of the horizontal conductive layer 20.

[0166] The process of recessing the horizontal conductive layer 20 may be simply referred to as a first side recessing process of the horizontal conductive layer 20 .

[0167] Fig.16A is a plan view showing a method of forming the first cover layer 29 . Fig. 16B is along Fig.16A A cross-sectional view taken along line AA' in FIG. Fig.16A is a plan view at the level of the horizontal conductive layer 20 showing a method of forming the first cover layer 29 .

[0168] like Fig.16A and Fig. 16BAs shown, the first capping layer 29 may be formed on the recessed side of the horizontal conductive layer 20. The first capping layer 29 may include silicon oxide, silicon nitride, silicon oxycarbide, embedded air gaps, or any combination thereof. To form the first capping layer 29, deposition and etching back may be performed on the capping material.

[0169] When forming the first capping layer 29, a portion of the interlayer dielectric layer 19 may be cut. Thus, a first edge portion of each horizontal layer 14B may be exposed.

[0170] When the first cover layer 29 is formed or after the first cover layer 29 is formed, the first hole-shaped vertical opening 27 may be extended.

[0171] Fig.17A is a plan view showing a method of forming the vertical wire 32 . Fig. 17B is along Fig.17A A cross-sectional view taken along line AA' in FIG. Fig.17A is a plan view at the level of the horizontal conductive layer 20 showing a method of forming the vertical conductive line 32 .

[0172] like Fig.17A and Fig. 17B As shown, a vertical conductive line 32 connected to the first edge portion of each horizontal layer 14B may be formed. The vertical conductive line 32 may fill the first hole-shaped vertical opening 27. The vertical conductive line 32 may be commonly connected to the horizontal layers 14B arranged in the first direction D1. The vertical conductive line 32 may include titanium nitride, tungsten, or any combination thereof. The vertical conductive line 32 may also be referred to as a bit line or a vertical bit line.

[0173] Before forming the vertical conductive line 32, a first doped region 30 and a first contact node 31 may be formed. The first doped region 30 may be formed in a first edge portion of each horizontal layer 14B. Forming the first doped region 30 may include depositing polysilicon doped with N-type impurities, annealing the deposited polysilicon, and removing the doped polysilicon. The first doped region 30 may include impurities diffused from the doped polysilicon. In another embodiment, the first doped region 30 may be formed by a process of doping impurities.

[0174] The first contact node 31 may include doped polysilicon. The first doping region 30 may include impurities diffused from the first contact node 31.

[0175] The vertical conductors 32 may correspond to, for example, Figures 1A to 1D The first wire BL is shown.

[0176] Fig.18A 1 is a plan view showing a method of forming the preliminary second hole-shaped vertical opening 33 . Fig.18B is along Fig.18A A cross-sectional view taken along line AA' in FIG. Fig.18Ais a plan view at the level of the horizontal conductive layer 20 showing a method of forming the preliminary second hole-shaped vertical opening 33 .

[0177] like Fig.18A and Fig.18B As shown, a portion of the second sacrificial pillar structure SV2 may be removed to form the preliminary second hole-shaped vertical opening 33. One side of the horizontal conductive layer 20 may be exposed, and a portion of the inter-cell dielectric layer 20 may be cut through the preliminary second hole-shaped vertical opening 33.

[0178] Fig.19A is a plan view showing a method of forming the horizontal conductive line 35 . Fig.19B is along Fig.19A A cross-sectional view taken along line AA' in FIG.

[0179] like Fig.19A and Fig.19B As shown, the other side of the horizontal conductive layer 20 can be selectively recessed by the preliminary second hole-shaped vertical opening 33. Thus, the horizontal conductive line 35 can be formed.

[0180] The horizontal conductor 35 may include a pair of first horizontal conductors 35A and second horizontal conductors 35B facing each other and with the horizontal layer 14B disposed therebetween. The first horizontal conductor 35A and the second horizontal conductor 35B may each include a metal-based material, a semiconductor material, or any combination thereof. The first horizontal conductor 35A and the second horizontal conductor 35B may each include titanium nitride, tungsten, polysilicon, or any combination thereof. For example, the first horizontal conductor 35A and the second horizontal conductor 35B may include a TiN / W stack in which titanium nitride and tungsten are sequentially stacked. The first horizontal conductor 35A and the second horizontal conductor 35B may each include an N-type work function material or a P-type work function material. The N-type work function material may have a low work function of 4.5 eV or less. The P-type work function material may have a high work function greater than 4.5 eV.

[0181] The horizontal conductor 35 may correspond to, for example, Figures 1A to 1D The first horizontal wire 35A and the second horizontal wire 35B may correspond to the upper horizontal wire G1 and the lower horizontal wire G2. Figures 1A to 1D As shown, the first horizontal conductive line 35A and the second horizontal conductive line 35B may each have a cross shape, and may each include a channel overlapping portion WLP and a channel non-overlapping portion NOL.

[0182] As in the series of processes mentioned, forming the horizontal conductive line 35 may include forming an interlayer dielectric layer 19 covering the surface of the preliminary horizontal layer 14B, forming a horizontal conductive layer 20 surrounding the preliminary horizontal layer 14B on the interlayer dielectric layer 19, and performing a first side recess process and a second side recess process on the horizontal conductive layer 20. The first edge portion of the horizontal conductive line 35 (refer to Fig.15D The second edge portion of the horizontal conductive line 35 (see “E1” in FIG. 1 ) may be defined by a first side recess process. Fig.19A and Fig.19B "E2" in the figure can be defined by a second side recess process.

[0183] Since the horizontal conductive line 35 is formed using the first side recess process and the second side recess process, the gate oxide strength (GOI) characteristics of the interlayer dielectric layer 19 can be significantly improved. The thickness of the interlayer dielectric layer 19 can be uniformly maintained.

[0184] In another embodiment, the first horizontal conductive line 35A and the second horizontal conductive line 35B of the horizontal conductive line 35 may have a triple work function electrode structure. Therefore, the gate induced drain leakage (GIDL) may be significantly reduced.

[0185] After forming the horizontal conductive line 35 , the preliminary second hole-shaped vertical opening may be extended, as indicated by reference numeral “ 34 .” Hereinafter, the extended preliminary second hole-shaped vertical opening may be referred to as the second hole-shaped vertical opening 34 .

[0186] Fig. 20A is a plan view showing a method of forming the storage opening 37 . Fig. 20B is along Fig. 20A A cross-sectional view taken along line AA' in FIG.

[0187] like Fig. 20A and Fig. 20B As shown, forming the second capping layer 36 includes depositing and etching a capping material. The second capping layer 36 may include silicon oxide, silicon nitride, or any combination thereof.

[0188] After forming the second capping layer 36, the interlayer dielectric layer 19 may be horizontally recessed in the second direction D2. Subsequently, the second edge portion of the horizontal layer 14B may be horizontally recessed in the second direction D2. Therefore, the horizontal layer may remain, as indicated by reference numeral "HL".

[0189] When the second cover layer 36 and the horizontal layer HL are formed as described above, a storage opening 37 horizontally extending from the second hole-shaped vertical opening 34 may be formed. The storage opening 37 may also be referred to as a capacitor opening.

[0190] Each of the horizontal layers HL may include a first edge and a second edge. The first edge refers to a portion connected to the first contact node 31 and the vertical conductive line 32. The second edge refers to a portion exposed by the storage opening 37.

[0191] The storage opening 37 may be disposed between the inter-cell dielectric layers 21 vertically adjacent to each other. The second capping layer 36 may be disposed above and below each horizontal layer HL.

[0192] Fig.21A is a plan view showing a method of forming the second contact node 38 . Fig. 21B is along Fig.21A A cross-sectional view taken along line AA' in FIG.

[0193] like Fig.21A and Fig. 21B As shown, the second doped region 39 may be formed within the second edge of the horizontal layer HL. Forming the second doped region 39 may include depositing polysilicon doped with N-type impurities, annealing the deposited polysilicon, and removing the doped polysilicon. The second doped region 39 may include impurities diffused from the doped polysilicon. In another embodiment, after annealing, the doped polysilicon may remain.

[0194] The second contact node 38 may be formed on the second edge of the horizontal layer HL. The second contact node 38 may include doped polysilicon. The second doping region 39 may include impurities diffused from the second contact node 38.

[0195] The horizontal layer HL may include a first doping region 30, a second doping region 39, and a channel 40 horizontally disposed in the second direction D2. The channel 40 may be defined between the first doping region 30 and the second doping region 39. The channel 40 may vertically overlap the horizontal conductive line 35. Figures 1A to 1C As shown, the horizontal layer HL may have a cross shape, and the channel 40 may also have a cross shape.

[0196] Fig.22A is a plan view illustrating a method of forming the first electrode 41 . Fig. 22B is along Fig.22A A cross-sectional view taken along line AA' in FIG.

[0197] like Fig.22A and Fig. 22B As shown, a first electrode 41 of the data storage element may be formed on the second contact node 38. The first electrode 41 may have a horizontally oriented cylindrical shape.

[0198] Fig.23A 4 is a plan view showing a method of exposing the outer wall of the first electrode 41 . Fig. 23B is along Fig.23A A cross-sectional view taken along line AA' in FIG.

[0199] like Fig.23A and Fig. 23B As shown, the inter-cell dielectric layer 21 may be horizontally recessed (reference numeral 42) to expose the outer surface of the first electrode 41. The recessed inter-cell dielectric layer 21 may correspond to, for example, Figure 3B The inter-cell dielectric layer IL is shown.

[0200] Fig.24A 4 is a plan view showing a method of forming the dielectric layer 43 and the second electrode 44 . Fig. 24B is along Fig.24A A cross-sectional view taken along line AA' in FIG.

[0201] like Fig.24A and Fig. 24B As shown, a dielectric layer 43 may be formed on the first electrode 41. A second electrode 44 may be formed on the dielectric layer 43. The first electrode 41, the dielectric layer 43, and the second electrode 44 may become a data storage element CAP.

[0202] The separate first electrode 41 may include an inner space and a plurality of outer surfaces. The inner space of the first electrode 41 may include a plurality of inner surfaces. The outer surface of the first electrode 41 may include a vertical outer surface and a plurality of horizontal outer surfaces. The vertical outer surface of the first electrode 41 may extend vertically in the first direction D1. The horizontal outer surface of the first electrode 41 may extend horizontally in the second direction D2 or the third direction D3. The inner space of the first electrode 41 may be a 3D space. The dielectric layer 43 may conformally cover the inner and outer surfaces of the first electrode 41. The second electrode 44 may be disposed in the inner space of the first electrode 41 on the dielectric layer 43. Some outer surfaces of the first electrode 41 may be electrically connected to the second doping region 39 and the second contact node 38 of the horizontal layer HL.

[0203] The first electrode 41 may have a cylindrical shape. The cylindrical shape of the first electrode 41 may include a cylindrical inner surface and a cylindrical outer surface. Some of the cylindrical outer surface of the first electrode 41 may be electrically connected to the second doping region 39 and the second contact node 38 of the horizontal layer HL. The dielectric layer 43 and the second electrode 44 may be disposed on the cylindrical inner surface of the first electrode 41. The second electrode 44 may extend vertically in the first direction D1.

[0204] The first electrode 41 and the second electrode 44 may each include a metal, a noble metal, a metal nitride, a conductive metal oxide, a conductive noble metal oxide, a metal carbide, a metal silicide, or any combination thereof. For example, the first electrode 41 and the second electrode 44 may each include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), titanium nitride / tungsten (TiN / W) stacking, tungsten nitride / tungsten (WN / W) stacking, or any combination thereof. The second electrode 44 may include a combination of a metal-based material and a silicon-based material. For example, the second electrode 44 may be a titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stacking. In the titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stacking, silicon germanium may be a gap filling material filling the internal space of the first electrode 41. Titanium nitride (TiN) may be used as the second electrode 44 of the data storage element CAP. Tungsten nitride may be a low resistance material.

[0205] The dielectric layer 43 may also be referred to as a capacitor dielectric layer or a storage layer. The dielectric layer 43 may include silicon oxide, silicon nitride, a high-k material, a ferroelectric material, an antiferroelectric material, or any combination thereof. The high-k material of the dielectric layer 43 may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanate (SrTiO3). The dielectric layer 42 may include a ZrO2 / Al2O3 (ZA) stack, a ZrO2 / Al2O3 / ZrO2 (ZAZ) stack, a ZrO2 / Al2O3 / ZrO2 / Al2O3 (ZAZA) stack, a ZrO2 / Al2O3 / ZrO2 / Al2O3 / ZrO2 (ZAZAZ) stack, a HfO2 / Al2O3 (HA) stack, a HfO2 / Al2O3 / HfO2 (HAH) stack, a HfO2 / Al2O3 / HfO2 / Al2O3 (HAHA) stack, or a HfO2 / Al2O3 / HfO2 / Al2O3 / HfO2 (HAHAH) stack.

[0206] In another embodiment, an interface control layer for reducing leakage current may also be formed between the first electrode 41 and the dielectric layer 43. The interface control layer may include titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), niobium nitride (NbN), or any combination thereof. The interface control layer may also be formed between the second electrode 44 and the dielectric layer 43.

[0207] According to the aforementioned embodiment, since the interlayer dielectric layer 19 can uniformly cover the surface of the horizontal layer HL, the cell gate oxide integrity (GOI) characteristic can be significantly improved.

[0208] In addition, since the horizontal conductive line 35 is formed by a recessing process of the horizontal conductive layer 20 , the yield of forming the horizontal conductive line 35 can be significantly improved by suppressing smoke of the horizontal conductive layer 20 .

[0209] Furthermore, since the cross-shaped horizontal layer HL is formed, the channel width and the bridge between the memory cells can be significantly improved.

[0210] Furthermore, bridging between the vertically stacked horizontal conductive lines 35 can thereby be significantly improved.

[0211] Furthermore, therefore, even after the process of forming the cell isolation dielectric layers 24A and 24B and the plurality of openings, the bridge between cells and the channel width can be significantly improved.

[0212] FIG. 25A to FIG. 25C is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to another embodiment of the present disclosure.

[0213] like Fig.25A As shown, the stacked body SB10 may be formed on the lower structure 11. The stacked body SB10 may include an alternating stack of a first semiconductor layer and a second semiconductor layer. For example, a plurality of silicon germanium layers 12 and a plurality of single crystal silicon layers 14' may be alternately stacked in the alternating stack by epitaxial growth. The silicon germanium layer 12 may be a sacrificial layer. The single crystal silicon layer 14' may be a recessed target layer. That is, the silicon germanium layer 12 may correspond to Figure 4B The first layer 12A or the third layer 12B in the single crystal silicon layer 14' may correspond to Figure 4B The fourth layer 14. Figure 4B Different from the stacked body SB of FIG. 1 , the stacked body SB10 may have an alternating stack of silicon germanium layers 12 and single crystal silicon layers 14 ′.

[0214] Then, you can do something like FIG. 4A to FIG. 5B For example, sacrificial isolation openings 15A and 15B and sacrificial isolation layers 16A and 16B may be formed in the stacked body SB10.

[0215] like Fig.25B As shown, a hard mask layer pattern 17 may be formed on the stacked body SB10 .

[0216] The stacked body SB10 may be etched by using the hard mask layer pattern 17 as an etch barrier. Thus, a plurality of first sacrificial vertical openings V1 ′ and second sacrificial vertical openings V2 ′ may be formed in the stacked body SB10 .

[0217] like Fig.25C As shown, a preliminary horizontal layer 14A' and a horizontal shape recess 18 can be formed. The preliminary horizontal layer 14A' and the horizontal shape recess 18 can be formed by using Fig.25B The preliminary horizontal layer 14A' may be formed by a process of recessing the silicon germanium layer 12 and the single crystal silicon layer 14'. After removing the silicon germanium layer 12, a process of recessing the single crystal silicon layer 14' may be performed. Figure 7B The preliminary horizontal layer 14A in.

[0218] Wet etching or dry etching may be used to recess the silicon germanium layer 12. The silicon germanium layer 12 may be etched using an etchant or etching gas that is selective to the single crystal silicon layer 14'.

[0219] For example, hot SC-1 (HSC1) may be used in the process of recessing the single crystal silicon layer 14' to form the preliminary horizontal layer 14A'. HSC1 may include a solution in which ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2) and water (H2O) are mixed in a ratio of 1:4:20, respectively. The single crystal silicon layer 14' may be selectively etched by using such HSC1.

[0220] After forming the preliminary horizontal layer 14A', the first sacrificial vertical opening and the second sacrificial vertical opening may extend, as shown in the reference numerals V1 and V2. The preliminary horizontal layer 14A' may be isolated from each other in the second direction D2 by the first sacrificial vertical opening V1 and the second sacrificial vertical opening V2. The preliminary horizontal layer 14A' may have a shape in which a plurality of cross shapes are merged in the third direction D3. When forming the preliminary horizontal layer 14A', the surface of the lower structure 11 may be recessed to a predetermined depth (see reference numeral "11A"). Therefore, the depth of the first sacrificial vertical opening V1 and the second sacrificial vertical opening V2 may be increased.

[0221] Then, you can execute FIG. 8A to FIG. 24B A series of processes shown.

[0222] Figure 26 to Figure 28 1 is a perspective view showing a memory cell array according to another embodiment of the present disclosure. The memory cell arrays MCA100, MCA200 and MCA300 can be similar to Figure 3A The memory cell array MCA is shown. In the following, for the detailed description of the repeated components, reference can be made to the aforementioned embodiments.

[0223] like Fig.26 As shown, the memory cell array MCA100 may include a plurality of memory cells MC10.

[0224] The memory cell array MCA100 may include a 3D array of memory cells MC10. The 3D array of memory cells MC10 may include a column array of memory cells MC10 and a row array of memory cells MC10. In the column array of memory cells MC10, a plurality of memory cells MC10 may be stacked in a first direction D1. In the row array of memory cells MC10, a plurality of memory cells MC10 may be horizontally arranged in a second direction D2 and a third direction D3.

[0225] The individual memory cell MC10 may include a first conductive line BL, a switching element TR, and a data storage element CAP. For detailed description of the first conductive line BL and the data storage element CAP, reference may be made to the aforementioned embodiments.

[0226] The switching element TR may include a horizontal layer HL and a second conductive line DWL. The horizontal layer HL may extend in the second direction D2. The second conductive line DWL may extend in the third direction D3.

[0227] The second conductive line DWL may have a double structure. For example, the second conductive line DWL may include an upper horizontal line G1 and a lower horizontal line G2 facing each other with the horizontal layer HL interposed therebetween. Figure 3B As shown, an interlayer dielectric layer GD may be formed on upper and lower surfaces of the horizontal layer HL.

[0228] The upper horizontal line G1 and the lower horizontal line G2 may each include a pair of flat sidewalls FS extending in the third direction D3. The flat sidewalls FS may mean vertical sidewalls. The flat sidewalls FS may have a line shape extending in the third direction D3.

[0229] like Fig. 27 As shown, the memory cell array MCA200 may include a plurality of memory cells MC20.

[0230] The memory cell array MCA200 may include a 3D array of memory cells MC20. The 3D array of memory cells MC20 may include a column array of memory cells MC20 and a row array of memory cells MC20. In the column array of memory cells MC20, a plurality of memory cells MC20 may be stacked in a first direction D1. In the row array of memory cells MC20, a plurality of memory cells MC20 may be horizontally arranged in a second direction D2 and a third direction D3.

[0231] The individual memory cell MC20 may include a first conductive line BL, a switching element TR, and a data storage element CAP. For detailed description of the first conductive line BL and the data storage element CAP, reference may be made to the aforementioned embodiments.

[0232] The switching element TR may include a horizontal layer HL and a second conductive line SWL. The horizontal layer HL may extend in the second direction D2. The second conductive line SWL may extend in the third direction D3.

[0233] The second conductive line SWL may have a single structure. For example, the second conductive line SWL may be disposed above the horizontal layer HL. Figure 3B As shown, the interlayer dielectric layer GD may be formed between the upper surface of the horizontal layer HL and the second conductive line SWL. In another embodiment, the second conductive line SWL may be disposed below the horizontal layer HL.

[0234] The second conductive line SWL may include a pair of flat sidewalls FS extending in the third direction D3. The flat sidewalls FS may refer to vertical sidewalls.

[0235] In another embodiment, Figure 1C As shown, the second conductive line SWL may include a channel overlapping portion WLP and a channel non-overlapping portion NOL.

[0236] like Fig.28 As shown, the memory cell array MCA300 may include a plurality of memory cells MC30.

[0237] The memory cell array MCA300 may include a 3D array of memory cells MC30. The 3D array of memory cells MC30 may include a column array of memory cells MC30 and a row array of memory cells MC30. In the column array of memory cells MC30, a plurality of memory cells MC30 may be stacked in a first direction D1. In the row array of memory cells MC30, a plurality of memory cells MC30 may be horizontally arranged in a second direction D2 and a third direction D3.

[0238] The individual memory cell MC30 may include a first conductive line BL, a switching element TR, and a data storage element CAP. For detailed description of the first conductive line BL and the data storage element CAP, reference may be made to the aforementioned embodiments.

[0239] The switching element TR may include a horizontal layer HL and a second conductive line GAA-WL. The horizontal layer HL may extend in the second direction D2. The second conductive line GAA-WL may extend in the third direction D3.

[0240] The second conductive line GAA-WL may have a fully surrounding gate structure GAA. For example, the second conductive line GAA-WL may extend in the third direction D3 while surrounding the horizontal layer HL. An interlayer dielectric layer GD may be formed between the horizontal layer HL and the second conductive line GAA-WL. The interlayer dielectric layer GD may surround each horizontal layer HL.

[0241] The second conductive line GAA-WL may include a pair of flat sidewalls FS extending in the third direction D3. The flat sidewalls FS may refer to vertical sidewalls.

[0242] Since the present technology trims the pattern of the preliminary horizontal layer after trimming the interlayer dielectric layer, the supporting force of the support member can be enhanced by minimizing the loss of the support member.

[0243] It is obvious to those skilled in the art that the embodiments of the present disclosure are not limited to the aforementioned embodiments and drawings, and the embodiments may be modified and changed in various ways without departing from the technical spirit of the present disclosure.

[0244] Although the present disclosure has been shown and described with reference to certain embodiments of the present disclosure, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the scope of the present disclosure and any equivalents. Therefore, the scope of the present disclosure should not be limited to the above-described embodiments, but should include equivalents thereof.

[0245] In the above-described embodiments, all operations may be selectively performed, or some operations may be omitted. In each embodiment, the operations are not necessarily performed in the order described, and may be rearranged. The embodiments disclosed in this specification and the accompanying drawings are only examples for facilitating understanding of the present disclosure, and the present disclosure is not limited thereto. That is, it is obvious to those skilled in the art that various modifications may be made on the basis of the technical scope of the present disclosure.

[0246] Embodiments of the present disclosure have been described in the drawings and the specification. Although specific terms are used herein, this is only for the purpose of describing embodiments of the present disclosure. Therefore, the present disclosure is not limited to the above-described embodiments, and there may be many changes within the scope of the present disclosure. It will be apparent to those skilled in the art that, in addition to the embodiments disclosed herein, multiple modifications may also be made based on the technical scope of the present disclosure. In addition, these embodiments may be combined to form additional embodiments.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: forming a vertical stack above the lower structure, the vertical stack comprising a plurality of recessed target layers spaced apart from each other in a first direction; forming a preliminary horizontal layer by recessing the recess target layer in a second direction perpendicular to the first direction; forming a dielectric target layer on the preliminary horizontal layer; forming a conductive target layer on the dielectric target layer; forming an interlayer dielectric layer by trimming the dielectric target layer in a third direction intersecting the second direction; forming a horizontal layer by trimming the preliminary horizontal layer in the third direction; as well as A trimming target layer is formed by trimming the conductive target layer in the third direction.

2. The method according to claim 1, wherein: A trimming width of the dielectric target layer and a trimming width of the preliminary horizontal layer are equal to each other.

3. The method according to claim 1, further comprising: A horizontal level spacer is formed on a trimmed side of the horizontal layer prior to trimming the conductive target layer.

4. The method according to claim 1, wherein: The dielectric target layer includes silicon oxide, and The preliminary horizontal layers each include single crystal silicon.

5. The method according to claim 1, wherein: Forming the preliminary horizontal layer comprises: forming a plurality of sacrificial vertical openings by etching the vertical stack, the plurality of sacrificial vertical openings extending vertically in the first direction and spaced apart from each other in the second direction perpendicular to the first direction; and The recess target layer is recessed from the sacrificial vertical opening in the second direction.

6. The method according to claim 1, further comprising: Before forming the preliminary horizontal layer, forming a sacrificial isolation opening extending vertically in the first direction by etching the vertical stack; forming a sacrificial isolation layer filling the sacrificial isolation opening; as well as A plurality of sacrificial vertical openings are formed by etching the vertical stack, the plurality of sacrificial vertical openings vertically extending in the first direction and spaced apart from each other in the second direction perpendicular to the first direction.

7. The method according to claim 1, further comprising: After forming the conductive target layer on the dielectric target layer, a cell isolation opening is formed, the cell isolation opening exposing the preliminary horizontal layer, the dielectric target layer, and the conductive target layer in the third direction.

8. The method according to claim 1, wherein: The conductive target layers each include: a metal-based material surrounding the preliminary horizontal layer on the dielectric target layer.

9. The method according to claim 1, further comprising: After forming the trimming target layer, forming a horizontal conductive line extending in a direction intersecting the horizontal layer on the interlayer dielectric layer by horizontally recessing edge portions on both sides of the trimming target layer; forming a vertical conductive line connected to a first edge of the horizontal layer; as well as A data storage element is formed coupled to the second edge of the horizontal layer.

10. The method according to claim 9, further comprising: forming a first contact node between the vertical conductive line and the first edge of the horizontal layer; as well as A second contact node is formed between the second edge of the horizontal layer and the data storage element.

11. The method according to claim 10, wherein: The first contact node and the second contact node each include polysilicon doped with impurities.

12. The method according to claim 10, further comprising: forming a first doped region within each of the first edges of the horizontal layer; as well as A second doped region is formed within each of the second edges of the horizontal layer.

13. The method according to claim 1, wherein: A cross section of each of the horizontal layers has a cross shape.

14. A semiconductor device comprising: Lower structure; a memory cell array disposed at a level higher than the lower structure and comprising a plurality of memory cells; as well as A support member is disposed between the lower structure and the storage cell array and supports the storage cell array.

15. The semiconductor device according to claim 14, wherein: Each of the storage units comprises: a cell isolation layer in contact with the support member and oriented vertically; a horizontal layer disposed between the cell isolation layers; a bit line connected to a first edge of the horizontal layer and oriented vertically over the lower structure; a data storage element isolated from the bit line horizontally and connected to a second edge of the horizontal layer; and A word line is horizontally oriented in a direction intersecting the horizontal layer.

16. The semiconductor device according to claim 15, wherein: The horizontally oriented length of the horizontal layer is smaller than the horizontally oriented length of the support member.

17. The semiconductor device according to claim 15, further comprising: an interlayer dielectric layer disposed between the word line and the horizontal layer; as well as A horizontal level spacer is disposed on one side of the horizontal layer.

18. The semiconductor device according to claim 17, wherein: The horizontal level spacer is disposed between the cell isolation layer and the horizontal layer.

19. The semiconductor device according to claim 15, wherein: The cross section of the horizontal layer has a cross shape.

20. The semiconductor device according to claim 15, wherein The word lines include double word lines facing each other in a first direction, and the horizontal layer is interposed between the double word lines.

21. The semiconductor device according to claim 15, further comprising: a first contact node disposed between the vertical conductive line and a first edge of the horizontal layer; as well as A second contact node is disposed between the second edge of the horizontal layer and the data storage element.

22. The semiconductor device according to claim 14, wherein: The support member and the lower structure include a semiconductor substrate, and The horizontal layer includes single crystal silicon.

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