Memory structure and forming method thereof

Abstract

The invention discloses a memory structure and a forming method thereof, and the method comprises the steps: forming a control gate layer on a source electrode layer, the control gate layer is internally provided with a plurality of first openings, and each first opening exposes the surface of the source electrode layer; forming a floating gate layer on the side wall of each first opening, wherein each floating gate layer is internally provided with a second opening for exposing the source electrode layer; forming a channel layer filling each second opening in each second opening, wherein the channel layer has a first projection on the surface of the substrate; forming a selection layer on the surface of the channel layer, wherein the selection layer has a second projection on the surface of the substrate; a plurality of mutually separated selection gates are formed on the surface of the control gate layer, the selection gates extend in the second direction and are arranged in parallel in the first direction, the top surfaces of the selection gates are flush with the selection layer, the selection gates have third projections on the surface of the substrate, and the adjacent selection gates have a plurality of third openings in the first direction; each third opening exposes the surface of the control gate layer. The control gate layer and the floating gate layer are sequentially distributed along the surface of the vertical substrate, and the storage unit area is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a memory structure and a forming method thereof. Background Art

[0002] With the rapid growth of the semiconductor integrated circuit (IC) industry, semiconductor technology continues to move towards smaller process nodes driven by Moore's Law, making integrated circuits smaller, with higher circuit precision and higher circuit complexity. In the development of integrated circuits, the functional density usually increases while the geometric size decreases, which increases the difficulty and complexity of integrated circuit manufacturing.

[0003] Flash memory has been rapidly promoted as the mainstream storage medium today, and its technology has also been rapidly developed. Flash memory is divided into NOT OR (NOR) type flash memory and NOT AND (NAND) type flash memory. As a type of flash memory, NOR type flash memory has received widespread attention due to its efficient programming speed and erasing ability. At present, NOR type flash memory has been widely used in personal computers, digital equipment, mobile terminals, automotive devices and other products.

[0004] However, there are still many limitations in reducing the size of the stack gate of the current NOR-type flash memory. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a memory structure and a method for forming the same, which can reduce the area of ​​the memory cell under the premise of sufficient channel length.

[0006] In order to solve the above technical problems, the present invention provides a method for forming a memory structure, comprising: providing a substrate; providing a substrate and a source layer located on the surface of the substrate; forming a control gate layer on the source layer, wherein the control gate layer has a plurality of first openings, each of the first openings exposes the surface of the source layer, and each of the first openings is arranged in an array along a second direction and the first direction, and the first direction is perpendicular to the second direction; forming a floating gate layer on the sidewall of each of the first openings, wherein each of the floating gate layers has a second opening exposing the source layer; forming a channel layer filling each of the second openings in each of the second openings, wherein the channel layer has a first projection on the surface of the substrate; forming a selection layer on the surface of the channel layer, wherein the selection layer has a second projection on the surface of the substrate, and the first projection is within the range of the second projection; forming a plurality of mutually discrete selection gates on the surface of the control gate layer, wherein each of the selection gates extends along the second direction and is arranged in parallel along the first direction, wherein the top surface of each of the selection gates is flush with the selection layer, each of the selection gates has a third projection on the surface of the substrate, and the second projection is within the range of the third projection, and adjacent selection gates have a plurality of third openings in the first direction, and each of the third openings exposes the surface of the control gate layer.

[0007] Optionally, after forming the source layer and before forming the control gate layer, the method further includes: forming a first dielectric layer on the surface of the source layer.

[0008] Optionally, the method for forming the control gate layer includes: forming an initial control gate layer on the surface of the first dielectric layer; forming a first mask layer on the surface of the initial control gate layer, the first mask layer exposing a portion of the surface of the initial control gate layer; using the first mask layer as a mask, etching the initial control gate layer until the surface of the first dielectric layer is exposed to form the control gate layer.

[0009] Optionally, after forming the control gate layer and before forming the floating gate layer, the method further includes: forming a second dielectric layer located on a surface of the first opening and a top surface of the control gate layer.

[0010] Optionally, the method for forming the floating gate layer includes: forming an initial floating gate layer filling the first opening on the surface of the second dielectric layer on the surface of the first opening, the initial floating gate layer being flush with the top surface of the second dielectric layer; forming a second mask layer on the surface of the initial floating gate layer and the surface of the second dielectric layer on the surface of the control gate layer, the second mask layer exposing a portion of the surface of the initial floating gate layer; using the second mask layer as a mask, etching the initial floating gate layer until the bottom surface of the second dielectric layer is exposed, thereby forming a second opening located in the initial floating gate layer and the floating gate layer.

[0011] Optionally, after forming the second opening and before forming the channel layer, it also includes: forming an initial third dielectric layer on the surface of the second opening, the top surface of the floating gate layer, and the surface of the control gate layer; etching back the initial third dielectric layer on the bottom surface of the second opening until the surface of the source layer is exposed, forming a third dielectric layer on the surface of the second dielectric layer on the top surface of the control gate layer, the top surface of the floating gate layer, and the sidewall surface of the floating gate layer.

[0012] Optionally, the method for forming the channel layer includes: forming an initial channel layer in the second opening and on the surface of the third dielectric layer; and planarizing the initial channel layer until the top surface of the third dielectric layer is exposed to form the channel layer.

[0013] Optionally, after forming the channel layer and before forming the selection layer, the method further includes: performing ion implantation on the top of the channel layer to form a common electrical doping region in the channel layer.

[0014] Optionally, the method for forming the selection layer includes: forming an initial selection layer on the surface of the third dielectric layer; forming a third mask layer on the surface of the initial selection layer, wherein the third mask layer exposes a portion of the surface of the initial selection layer; and etching the initial selection layer using the third mask layer as a mask until the surface of the third dielectric layer is exposed to form the selection layer.

[0015] Optionally, after forming the selection layer and before forming the selection gate, the method further includes: forming an initial selection gate oxide layer on the top surface of the selection layer, the sidewall surface of the selection layer, and the surface of the third dielectric layer.

[0016] Optionally, the method for forming the select gate includes: after forming the initial select gate oxide layer, forming a select gate material layer on the surface of the initial select gate oxide layer; flattening the surface of the select gate material layer until the surface of the select layer is exposed to form the initial select gate layer; forming a fourth mask layer on the initial select gate layer and the surface of the select layer, the fourth mask layer exposing a portion of the surface of the initial select gate layer; using the fourth mask layer as a mask, etching the initial select gate layer until the surface of the control gate layer is exposed to form a plurality of third openings located in the initial select gate layer, the third openings extending along the second direction and arranged in parallel along the first direction.

[0017] Optionally, after forming the selection gate, it also includes: forming an initial selection gate dielectric layer in each of the third openings, on the surface of the selection layer and on the surface of the selection gate; forming a fifth mask layer on the surface of the initial selection gate dielectric layer, wherein the fifth mask layer exposes a portion of the surface of the selection layer; using the fifth mask layer as a mask, etching the initial selection gate dielectric layer until a portion of the surface of the selection layer is exposed, thereby forming a selection gate dielectric layer and a fourth opening.

[0018] Optionally, after forming the fourth opening, the method further includes: forming a source interconnection layer filling the fourth opening in the fourth opening; and forming a conductive layer on the surfaces of the select gate dielectric layer and the source interconnection layer.

[0019] Optionally, a cross section of the first opening along a direction parallel to the substrate surface is circular.

[0020] Optionally, after forming the fourth opening and before forming the source interconnection layer, the method further includes: performing ion implantation on the top of the selection layer to form a drain doping region in the selection layer.

[0021] Correspondingly, the technical solution of the present invention also provides a memory structure, including: a substrate; a source layer located on the substrate; a control gate layer located on the source layer, the control gate layer having a plurality of first openings, each of the first openings exposing the surface of the source layer, each of the first openings being arranged in an array along the second direction and the first direction, the first direction being perpendicular to the second direction; a floating gate layer located on the sidewalls of each of the first openings, each of the floating gate layers having a second opening exposing the source layer; a channel layer filling each of the second openings, the channel layer having a first projection on the substrate surface; a selection layer located on the surface of the channel layer, the selection layer having a second projection on the substrate surface, the first projection being within the range of the second projection; a plurality of mutually separate selection gates located on the surface of the control gate layer, each of the selection gates extending along the second direction and arranged in parallel along the first direction, the top surface of each of the selection gates being flush with the selection layer, each of the selection gates having a third projection on the substrate surface, the second projection being within the range of the third projection, and adjacent selection gates having a plurality of third openings in the first direction, each of the third openings exposing the surface of the control gate layer.

[0022] Optionally, it also includes: a co-electrically doped region located in the channel layer; the distance range from the co-electrically doped region to the top surface of the channel layer is: 10nm to 50nm; the ion implantation parameters of the co-electrically doped region include: the ion implantation energy range is: 10KeV to 50KeV; the ion implantation dose range is: 5E13atoms / cm 2 ~5E15atoms / cm 2; The ion types injected into the common electrical doping region include: N-type ions and P-type ions; The ion types injected into the common electrical doping region are opposite to the conductivity type of the channel layer.

[0023] Optionally, it also includes: a drain doping region located in the selection layer; the distance range from the drain doping region to the top surface of the selection layer is: 10nm~50nm; the ion implantation parameters of the drain doping region include: ion implantation energy range: 10KeV~50KeV; ion implantation dose range: 5E13atoms / cm 2 ~5E15atoms / cm 2 ; The ion types injected into the drain doping region include: N-type ions and P-type ions; The ion type injected into the drain doping region is opposite to the conductivity type of the selection layer.

[0024] Optionally, it further includes: a selection gate dielectric layer located in the third opening, on the surface of the selection gate and on the surface of the selection layer, wherein the selection gate dielectric layer has a plurality of fourth openings, and each of the fourth openings exposes a portion of the surface of the selection layer.

[0025] Optionally, the method further includes: a source interconnection layer filling the fourth opening.

[0026] Optionally, it also includes: a conductive layer located on the surface of the selection gate dielectric layer and the source interconnect layer.

[0027] Optionally, it further includes: a first dielectric layer located between the source layer and the control gate layer; the material of the first dielectric layer includes: silicon oxide, silicon nitride and aluminum oxide.

[0028] Optionally, the material of the substrate includes: silicon, polycrystalline silicon and silicon carbide; the conductivity type of the substrate includes: P type and N type; the material of the source layer includes: silicon, polycrystalline silicon and silicon carbide; the conductivity type of the source layer includes: P type and N type; the conductivity type of the source layer is opposite to the conductivity type of the substrate, and the conductivity type of the source layer is opposite to the conductivity type of the channel layer.

[0029] Optionally, it further includes: a second dielectric layer located on the top surface of the control gate layer, between the floating gate layer and the control gate layer, and between the bottom surface of the floating gate layer and the first dielectric layer; the material of the second dielectric layer includes: silicon oxide, silicon nitride and aluminum oxide; the thickness range of the second dielectric layer is:

[0030] Optionally, the method further includes: a surface of a second dielectric layer located on the surface of the control gate layer, a top surface of the floating gate layer, and a third dielectric layer between the channel layer and the floating gate layer.

[0031] Optionally, a size range of the first opening along a direction parallel to the first direction is 200 nm to 1000 nm; a cross section of the first opening along a direction parallel to the substrate surface is circular; and a thickness range of the channel layer is 50 nm to 200 nm.

[0032] Optionally, the floating gate material includes: polysilicon, silicon nitride and hafnium oxide; the control gate layer material includes: polysilicon; the select gate material includes: single crystal silicon, polysilicon and silicon carbide.

[0033] Optionally, the channel layer material includes: single crystal silicon, polycrystalline silicon and silicon carbide; the conductivity type of the channel layer includes: P type and N type; the selection layer material includes: single crystal silicon, polycrystalline silicon and silicon carbide; the conductivity type of the selection layer includes: P type and N type; the conductivity type of the selection layer is the same as the conductivity type of the channel layer.

[0034] Optionally, the floating gate layer has a thickness ranging from 10 nm to 100 nm.

[0035] Optionally, it also includes: a selection gate oxide layer located between the selection gate and the selection layer.

[0036] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0037] In the memory structure of the technical solution of the present invention, on the one hand, the control gate layer has a plurality of first openings, and the floating gate layer is located on the side wall of the first opening, so that the control gate layer and the floating gate layer are distributed in sequence along the vertical substrate surface. Compared with the memory structure in which the control gate layer is formed on the surface of the floating gate layer, the area of ​​the control gate layer and the floating gate layer in the direction parallel to the substrate surface is reduced; on the other hand, the channel layer fills the second openings and is distributed in sequence with the control gate layer and the floating gate layer along the vertical substrate surface, and the channel layer is connected to the source layer. The channel length can be controlled by adjusting the thickness of the channel layer, which is beneficial to reducing the storage unit area while ensuring the channel length.

[0038] Furthermore, the cross section of the first opening along the direction parallel to the substrate surface is circular, which reduces the area of ​​each of the floating gate layer and the channel layer along the direction parallel to the substrate surface.

[0039] In the method for forming a memory structure of the technical solution of the present invention, on the one hand, a control gate layer is formed on the source layer, the control gate layer has a plurality of first openings, and then a floating gate layer is formed on the sidewalls of the first openings, so that the control gate layer and the floating gate layer are sequentially distributed along a vertical substrate surface. Compared with the memory structure in which the control gate layer is formed on the surface of the floating gate layer, the area of ​​the control gate layer and the floating gate layer along a direction parallel to the substrate surface is reduced; on the other hand, the channel layer fills the second openings and is sequentially distributed with the control gate layer and the floating gate layer along a vertical substrate surface, and the channel layer is connected to the source layer, and the channel length can be controlled by adjusting the thickness of the channel layer, which is beneficial to reducing the storage unit area while ensuring the channel length.

[0040] Furthermore, the cross section of the first opening along the direction parallel to the substrate surface is circular, which reduces the area of ​​each of the floating gate layer and the channel layer along the direction parallel to the substrate surface. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figures 1 to 54 It is a schematic structural diagram of each step of a method for forming a memory structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0042] As described in the background art, the prior art NOT OR (NOR) type flash memory structure still has many problems.

[0043] In an embodiment of a flash memory, there are still many limitations to reducing the size of the stacked gate.

[0044] In order to solve the above technical problems, the technical solution of the present invention provides a memory structure and a method for forming the same. On the one hand, a control gate layer is formed on the source layer, and a plurality of first openings are provided in the control gate layer. Subsequently, a floating gate layer is formed on the sidewalls of the first openings, so that the control gate layer and the floating gate layer are sequentially distributed along a surface perpendicular to the substrate. Compared with the memory structure in which the control gate layer is formed on the surface of the floating gate layer, the area of ​​the control gate layer and the floating gate layer along a direction parallel to the substrate surface is reduced. On the other hand, the channel layer fills the second openings and is sequentially distributed with the control gate layer and the floating gate layer along the surface perpendicular to the substrate, and the channel layer is connected to the source layer. The channel length can be controlled by adjusting the thickness of the channel layer, which is beneficial to reducing the storage unit area while ensuring the channel length.

[0045] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0046] Figures 1 to 54 It is a structural schematic diagram of the formation process of the memory structure of an embodiment of the present invention.

[0047] Please refer to Figure 1 and Figure 2 , Figure 1 for Figure 2 A top view of Figure 2 yes Figure 1 A cross-sectional view along the AA′ direction is provided, showing a substrate 100 and a source layer 101 located on the surface of the substrate 100 .

[0048] The material of the substrate 100 includes silicon, polysilicon and silicon carbide.

[0049] The substrate 100 provides a structural basis for forming a source layer 101 .

[0050] The conductivity type of the substrate 100 includes: P type and N type. Specifically, in this embodiment, the conductivity type of the substrate 100 is P type.

[0051] In other embodiments, the conductivity type of the substrate may be N-type.

[0052] The material of the source layer 101 includes silicon, polysilicon and silicon carbide.

[0053] The source layer 101 provides a basis for the subsequent formation of a floating gate layer 109 and a control gate layer 104 .

[0054] The conductivity type of the source layer 101 includes: P type and N type. The conductivity type of the source layer 101 is opposite to the conductivity type of the substrate 100. Specifically, in this embodiment, the conductivity type of the source layer 101 is N type.

[0055] In other embodiments, the conductivity type of the source layer may be P type.

[0056] The method for forming the source layer 101 includes: performing ion implantation on the substrate 100 or in-situ deposition on the surface of the substrate 100 .

[0057] The memory structure is divided into a storage part and a selection switch part. The storage part includes: a substrate 100, a source layer 101, a control gate layer 104, a floating gate layer 109 and a channel layer 110; the selection switch part includes: a selection layer 115, a selection gate 119, a source interconnection layer 123 and a conductive layer 124.

[0058] A control gate layer 104 is formed on the source layer 101. The control gate layer 104 has a plurality of first openings 105. Each of the first openings 105 exposes the surface of the source layer 101. Each of the first openings 105 is arranged in an array along the second direction and the first direction. The first direction is perpendicular to the second direction. Figures 3 to 10 .

[0059] Please refer to Figure 3 and Figure 4 , Figure 3 for Figure 4 A top view of Figure 4 yes Figure 3 The cross-sectional view along the AA′ direction, after forming the source layer 101 and before forming the control gate layer 104 , further includes: forming a first dielectric layer 102 on the surface of the source layer 101 .

[0060] The material of the first dielectric layer 102 includes silicon oxide, silicon nitride and aluminum oxide.

[0061] The method for forming the first dielectric layer 102 includes: depositing or oxidizing the surface of the source layer 101 to form the first dielectric layer 102 .

[0062] The first dielectric layer 102 is used to isolate the source layer 101 from a control gate layer 104 formed subsequently.

[0063] Please refer to Figure 5 and Figure 6 , Figure 5 for Figure 6 A top view of Figure 6 yes Figure 5 In the cross-sectional view along the AA′ direction, an initial control gate layer 103 is formed on the surface of the first dielectric layer 102 ; a first mask layer (not shown) is formed on the surface of the initial control gate layer 103 , and the first mask layer (not shown) exposes part of the surface of the initial control gate layer 103 .

[0064] The initial control gate layer 103 provides a structural basis for the subsequent formation of the control gate layer 104 .

[0065] The material of the initial control gate layer 103 includes: polysilicon.

[0066] The initial control gate layer 103 is formed by deposition, which may be atomic layer deposition, physical vapor deposition, or chemical vapor deposition.

[0067] Please refer to Figures 7 to 10 , Figure 7 for Figure 8 A top view of Figure 8 yes Figure 7 Cross-sectional view along AA' direction, Fig. 9 yes Figure 7 A partial enlarged view of Fig.10 yes Figure 8 The local enlarged view of the first mask layer (not shown) is used as a mask to etch the initial control gate layer 103 (such as Figure 6 As shown), until the surface of the first dielectric layer 102 is exposed, the control gate layer 104 is formed.

[0068] The etching method includes dry etching.

[0069] The material of the control gate layer 104 includes: polysilicon.

[0070] The control gate layer 104 has a plurality of first openings 105 therein.

[0071] The first opening 105 provides a structural basis for the subsequent formation of a floating gate layer 109 .

[0072] The control gate layer 104 has a plurality of first openings 105, and then a floating gate layer 109 is formed on the sidewalls of the first openings 105, so that the control gate layer 104 and the floating gate layer 109 are sequentially distributed along a surface perpendicular to the substrate. Compared with a memory structure in which the control gate layer is formed on the surface of the floating gate layer, the area of ​​the control gate layer and the floating gate layer along a direction parallel to the substrate surface is reduced.

[0073] The memory structure is divided into a storage part and a selection switch part. The storage part includes: a substrate 100, a source layer 101, a control gate layer 104, a floating gate layer 109 and a channel layer 110; the selection switch part includes: a selection layer 115, a selection gate 119, a source interconnection layer 123 and a conductive layer 124.

[0074] Specifically, in this embodiment, the size range of the first opening 105 parallel to the first direction is: 200nm-1000nm.

[0075] Specifically, in this embodiment, the cross section of the first opening 105 along a direction parallel to the surface of the substrate 100 is circular.

[0076] In other embodiments, the cross section of the first opening along a direction parallel to the substrate surface may be in other shapes.

[0077] The cross section of the first opening 105 along the direction parallel to the surface of the substrate 100 is circular, which reduces the area of ​​the subsequently formed floating gate layer 109 and the channel layer 110 along the direction parallel to the surface of the substrate 100 and reduces the area of ​​the memory cell.

[0078] Please refer to Fig.11 and Fig.12 , Fig.11 Perspective and Fig. 9 Consistent, Fig.12 Perspective and Fig.10 Consistent, Fig.11 for Fig.12 A top view of Fig.12 yes Fig.11 In the cross-sectional view along the A1A1′ direction, after the control gate layer 104 is formed, a second dielectric layer 106 is formed on the surface of the first opening 105 and the top surface of the control gate layer 104 .

[0079] The material of the second dielectric layer 106 includes silicon oxide, silicon nitride and aluminum oxide.

[0080] The thickness range of the second dielectric layer 106 is:

[0081] The second dielectric layer 106 is used to isolate the control gate layer 104 from a subsequently formed floating gate layer 109 .

[0082] A floating gate layer 109 is formed on the sidewall of each of the first openings 105, and each of the floating gate layers 109 has a second opening 108 exposing the source layer 101. Figures 13 to 16 .

[0083] Please refer to Fig.13 and Fig.14 , Fig.13 Perspective and Fig.11 Consistent, Fig.14 Perspective and Fig.12 Consistent, Fig.13 for Fig.14 A top view of Fig.14 yes Fig.13 In the cross-sectional view along the A1A1′ direction, an initial floating gate layer 107 filling the first opening 105 is formed on the surface of the second dielectric layer 106 on the surface of the first opening 105 , and the initial floating gate layer 107 is flush with the top surface of the second dielectric layer 106 .

[0084] The material of the initial floating gate layer 107 includes polysilicon, silicon nitride and hafnium oxide.

[0085] The initial floating gate layer 107 provides a structural basis for the subsequent formation of a floating gate layer 109 .

[0086] The thickness of the initial floating gate layer 107 ranges from 10 nm to 100 nm.

[0087] The initial floating gate layer 107 is formed by deposition, which may be atomic layer deposition, physical vapor deposition, or chemical vapor deposition.

[0088] Please refer to Fig.15 and Fig.16 , Fig.15 Perspective and Fig.13 Consistent, Fig.16 Perspective and Fig.14 Consistent, Fig.15 for Fig.16 A top view of Fig.16 yes Fig.15In the cross-sectional view along the A1A1' direction, a second mask layer (not shown) is formed on the surface of the initial floating gate layer 107 and the second dielectric layer 106 on the surface of the control gate layer 104, and the second mask layer (not shown) exposes a portion of the surface of the initial floating gate layer 107; using the second mask layer (not shown) as a mask, the initial floating gate layer 107 is etched until the bottom surface of the second dielectric layer 106 is exposed, thereby forming a second opening 108 located in the initial floating gate layer 107 and the floating gate layer 109.

[0089] The etching method includes dry etching.

[0090] The material of the floating gate layer 109 includes polysilicon, silicon nitride and hafnium oxide.

[0091] The thickness of the floating gate layer 109 is in the range of 10 nm to 100 nm.

[0092] The floating gate layer 109 is used to store electrons.

[0093] The floating gate layer 109 and the control gate layer 104 are sequentially distributed along the surface of the substrate 100 vertically. Compared with the memory structure in which the control gate layer is formed on the surface of the floating gate layer, the area of ​​the control gate layer and the floating gate layer along the direction parallel to the substrate surface is reduced.

[0094] The memory structure is divided into a storage part and a selection switch part. The storage part includes: a substrate 100, a source layer 101, a control gate layer 104, a floating gate layer 109 and a channel layer 110; the selection switch part includes: a selection layer 115, a selection gate 119, a source interconnection layer 123 and a conductive layer 124.

[0095] A channel layer 110 is formed in each of the second openings 108 to fill each of the second openings 108 , and the channel layer 110 has a first projection I on the surface of the substrate 100 . Figures 17 to 25 .

[0096] Please refer to Fig.17 and Fig.18 , Fig.17 Perspective and Fig.15 Consistent, Fig.18 Perspective and Fig.16 Consistent, Fig.17 for Fig.18 A top view of Fig.18 yes Fig.17 In the cross-sectional view along the A1A1′ direction, an initial third dielectric layer 111 is formed on the surface of the second opening 108 , the top surface of the floating gate layer 109 , and the surface of the second dielectric layer 106 on the surface of the control gate layer 104 .

[0097] The material of the initial third dielectric layer 111 includes silicon oxide, aluminum oxide and silicon nitride.

[0098] The initial third dielectric layer 111 has the function of providing a structural basis for the subsequent formation of a third dielectric layer 112 and isolating the floating gate layer 109 from the subsequently formed channel layer 110 .

[0099] Please refer to Fig.19 and Fig. 20 , Fig.19 Perspective and Fig.17 Consistent, Fig. 20 Perspective and Fig.18 Consistent, Fig.19 for Fig. 20 A top view of Fig. 20 yes Fig.19 In the cross-sectional view along the A1A1' direction, the initial third dielectric layer 111 on the bottom surface of the second opening 108 is etched back until the surface of the source layer 101 is exposed, forming a third dielectric layer 112 on the surface of the second dielectric layer 106 located on the top surface of the control gate layer 104, the top surface of the floating gate layer 109, and the side wall surface of the floating gate layer 109.

[0100] The material of the third dielectric layer 112 includes silicon oxide, aluminum oxide and silicon nitride.

[0101] The third dielectric layer 112 is used to isolate the floating gate layer 109 from a subsequently formed channel layer 110 .

[0102] The back etching method is dry etching.

[0103] The purpose of the etch-back is to etch back the initial third dielectric layer 111 until the surface of the source layer 101 is exposed, so that the subsequently formed channel layer 110 is connected to the source layer 101 .

[0104] Please refer to Fig.21 and Fig. 22 , Fig.21 Perspective and Fig.19 Consistent, Fig. 22 Perspective and Fig. 20 Consistent, Fig.21 for Fig. 22 A top view of Fig. 22 yes Fig.21 The cross-sectional view along the A1A1' direction is as follows: Fig. 20 An initial channel layer (not shown) is formed inside the third dielectric layer 110 and on the surface of the third dielectric layer 112; the initial channel layer (not shown) is planarized until the top surface of the third dielectric layer 112 is exposed to form the channel layer 110.

[0105] The material of the channel layer 110 includes: single crystal silicon, polycrystalline silicon and silicon carbide.

[0106] The planarization method includes mechanical polishing, chemical polishing, fluid polishing, and chemical mechanical polishing. Specifically, in this embodiment, the planarization method is chemical mechanical polishing. Different from the traditional pure mechanical or pure chemical polishing method, the chemical mechanical polishing method avoids the surface damage caused by pure mechanical polishing and the shortcomings of slow polishing speed, poor surface flatness and polishing consistency caused by pure chemical polishing through the combined action of chemistry and mechanics.

[0107] The conductivity type of the channel layer 110 includes: P type and N type; the conductivity type of the source layer 101 is opposite to the conductivity type of the channel layer 110; specifically, in this embodiment, the conductivity type of the channel layer 110 is P type.

[0108] In other embodiments, the conductivity type of the channel layer may be N-type.

[0109] The channel layer 110 fills the second opening 108 and is distributed in sequence with the control gate layer 104 and the floating gate layer 109 along the surface of the vertical substrate 100, and the channel layer 110 is connected to the source layer 101. The channel length can be controlled by adjusting the thickness of the channel layer 110, which is beneficial to reducing the storage unit area while ensuring the channel length.

[0110] The memory structure is divided into a storage part and a selection switch part. The storage part includes: a substrate 100, a source layer 101, a control gate layer 104, a floating gate layer 109 and a channel layer 110; the selection switch part includes: a selection layer 115, a selection gate 119, a source interconnection layer 123 and a conductive layer 124.

[0111] Please refer to Fig.23 and Fig.24 , Fig.23 Perspective and Fig.21 Consistent, Fig.24 Perspective and Fig. 22 Consistent, Fig.23 for Fig.24 A top view of Fig.24 yes Fig.23 In the cross-sectional view along the AA′ direction, ion implantation is performed on the top of the channel layer 110 to form a co-electrically doped region 113 in the channel layer 110 .

[0112] The distance between the common electrical doping region 113 and the top surface of the channel layer 110 is in the range of 10 nm to 50 nm.

[0113] The ion implantation parameters of the common electrical doping region 113 include: ion implantation energy range: 10KeV~50KeV; ion implantation dose range: 5E13atoms / cm 2 ~5E15atoms / cm 2 .

[0114] The ion types implanted into the common electrical doping region 113 include: N-type ions and P-type ions; the ion types implanted into the common electrical doping region 113 are opposite to the conductivity type of the channel layer 110. Specifically, in this embodiment, the conductivity type of the common electrical doping region 113 is N-type.

[0115] In other embodiments, the conductivity type of the common electrical doping region may be P type.

[0116] The purpose of performing ion implantation on the top of the channel layer 110 to form the common electrical doping region 113 is to enable the common electrical doping region 113 to serve as both a drain of the storage part and a source of the selection switch part.

[0117] A selection layer 115 is formed on the surface of the channel layer 110, and the selection layer 115 has a second projection II on the surface of the substrate 100, and the first projection I is within the range of the second projection II. Figures 25 to 30 .

[0118] Please refer to Fig.25 and Fig.26 , Fig.25 Perspective and Fig.23 Consistent, Fig.26 Perspective and Fig.24 Consistent, Fig.25 for Fig.26 A top view of Fig.26 yes Fig.25 In the cross-sectional view along direction A1A1′, an initial selection layer 114 is formed on the surface of the third dielectric layer 112 ; a third mask layer (not shown) is formed on the surface of the initial selection layer 114 , and the third mask layer (not shown) exposes a portion of the surface of the initial selection layer 114 .

[0119] The initial selection layer 114 provides a structural basis for the subsequent formation of the selection layer 115 .

[0120] The material of the initial selection layer 114 includes: single crystal silicon, polycrystalline silicon and silicon carbide.

[0121] The conductivity type of the initial selection layer 114 includes: P type and N type; the conductivity type of the initial selection layer 114 is the same as the conductivity type of the channel layer 110. Specifically, in this embodiment, the conductivity type of the initial selection layer 114 is P type.

[0122] In other embodiments, the conductivity type of the initial selection layer may be N-type.

[0123] Please refer to Fig. 27 and Fig.28 , Fig. 27 Perspective and Fig.25 Consistent, Fig.28 Perspective and Fig.26 Consistent, Fig. 27 for Fig.28 A top view of Fig.28 yes Fig. 27 In the cross-sectional view along the A1A1′ direction, the initial selection layer 114 is etched using the third mask layer (not shown) as a mask until the surface of the third dielectric layer 112 is exposed, thereby forming the selection layer 115 .

[0124] The material of the selection layer 115 includes: single crystal silicon, polycrystalline silicon and silicon carbide.

[0125] The conductivity type of the selection layer 115 includes: P type and N type; the conductivity type of the selection layer 115 is the same as the conductivity type of the channel layer 110. Specifically, in this embodiment, the conductivity type of the selection layer 115 is P type.

[0126] In other embodiments, the conductivity type of the selection layer may be N-type.

[0127] The etching method includes dry etching.

[0128] The selection layer 115 has a second projection II on the surface of the substrate 100 , and the first projection I is located within the range of the second projection II.

[0129] The memory structure is divided into a storage part and a selection switch part. The storage part includes: a substrate 100, a source layer 101, a control gate layer 104, a floating gate layer 109 and a channel layer 110; the selection switch part includes: a selection layer 115, a selection gate 119, a source interconnection layer 123 and a conductive layer 124.

[0130] Please refer to Fig.29 and Fig.30 , Fig.29 Perspective and Fig. 27 Consistent, Fig.30 Perspective and Fig.28 Consistent, Fig.29 for Fig.30 A top view of Fig.30 yes Fig.29 In the cross-sectional view along the A1A1′ direction, an initial selection gate oxide layer 116 is formed on the top surface of the selection layer 115 , the sidewall surface of the selection layer 115 , and the surface of the third dielectric layer 112 .

[0131] The initial selection gate oxide layer 116 provides a structural basis for the subsequent formation of an initial selection gate layer 117 .

[0132] The material of the initial selection gate oxide layer 116 includes silicon oxide, silicon nitride and aluminum oxide.

[0133] The initial selection gate oxide layer 116 is used to isolate the subsequently formed selection gate 119 from the selection layer 115 .

[0134] A plurality of mutually separated selection gates 119 are formed on the surface of the control gate layer 104, each of the selection gates 119 extends along the second direction and is arranged in parallel along the first direction, the top surface of each selection gate 119 is flush with the selection layer 115, each selection gate 119 has a third projection III on the surface of the substrate 100, the second projection II is within the range of the third projection III, and adjacent selection gates 119 have a plurality of third openings 118 in the first direction, each of the third openings 118 exposes the surface of the control gate layer 104. For details, please refer to Figures 31 to 38 .

[0135] Please refer to Figure 31 to Figure 34 , Fig.31 for Fig.32 A top view of Fig.32 yes Fig.31 Cross-sectional view along AA' direction, Fig.33 yes Fig.31 A partial enlarged view of Fig.34 yes Fig.32 A partial enlarged view of Fig.31 Perspective and Figure 7 Consistent, Fig.32 Perspective and Figure 8 Consistent, Fig.33 Perspective and Fig. 9 Consistent, Fig.34 Perspective and Fig.10 Consistent with the initial selection of the gate oxide layer 116 ( Fig.30 A select gate material layer (not shown) is formed on the surface; the surface of the select gate material layer (not shown) is planarized until the surface of the select layer 115 is exposed, thereby forming the initial select gate layer 117.

[0136] When the initial selection gate layer 117 is formed, the selection gate oxide layer 126 is formed from the initial selection gate oxide layer 116 .

[0137] The material of the initial selection gate layer 117 includes: single crystal silicon, polycrystalline silicon and silicon carbide.

[0138] The material of the selection gate oxide layer 126 includes silicon oxide, silicon nitride and aluminum oxide.

[0139] The initial selection gate layer 117 provides a structural basis for the subsequent formation of the selection gate 119 .

[0140] The planarization method includes mechanical polishing, chemical polishing, fluid polishing, and chemical mechanical polishing. Specifically, in this embodiment, the planarization method is chemical mechanical polishing. Different from the traditional pure mechanical or pure chemical polishing method, the chemical mechanical polishing method avoids the surface damage caused by pure mechanical polishing and the shortcomings of slow polishing speed, poor surface flatness and polishing consistency caused by pure chemical polishing through the combined action of chemistry and mechanics.

[0141] Please refer to Figures 35 to 38 , Fig.35 for Fig.36 A top view of Fig.36 yes Fig.35 Cross-sectional view along AA' direction, Fig.37 yes Fig.35 A partial enlarged view of Fig.38 yes Fig.36 In the locally enlarged view, a fourth mask layer (not shown) is formed on the surface of the initial selection gate layer 117 and the selection layer 115, and the fourth mask layer (not shown) exposes a portion of the surface of the initial selection gate layer 117; using the fourth mask layer (not shown) as a mask, the initial selection gate layer 117 is etched until the surface of the control gate layer 104 is exposed, forming a plurality of third openings 118 located in the initial selection gate layer 117, and the third openings 118 extend along the second direction and are arranged in parallel along the first direction.

[0142] The third opening 118 exposes the surface of the control gate layer 104 . When the third opening 118 is formed, a select gate 119 is formed with the initial select gate layer 117 .

[0143] The material of the select gate 119 includes: single crystal silicon, polycrystalline silicon and silicon carbide.

[0144] The memory structure is divided into a storage part and a selection switch part. The storage part includes: a substrate 100, a source layer 101, a control gate layer 104, a floating gate layer 109 and a channel layer 110; the selection switch part includes: a selection layer 115, a selection gate 119, a source interconnection layer 123 and a conductive layer 124.

[0145] The etching method includes dry etching.

[0146] The third opening 118 provides a structural basis for the subsequent formation of a select gate dielectric layer 121 .

[0147] Please refer to Figure 39 to Figure 42 , Fig.39 for Fig.40 A top view of Fig.40 yes Fig.39 Cross-sectional view along AA' direction, Fig.41 yes Fig.39 A partial enlarged view of Fig.42 yes Fig.40 A local enlarged view shows that an initial selection gate dielectric layer 120 is formed in each of the third openings 118, on the surface of the selection layer 115, and on the surface of the selection gate 119; a fifth mask layer (not shown) is formed on the surface of the initial selection gate dielectric layer 120, and the fifth mask layer (not shown) exposes a portion of the surface of the selection layer 115.

[0148] The material of the initial selection gate dielectric layer 120 includes silicon oxide, silicon nitride and aluminum oxide.

[0149] The initial selection gate dielectric layer 120 provides a structural basis for the subsequent formation of the selection gate dielectric layer 121 .

[0150] Please refer to Figure 43 to Figure 46 , Fig.43 for Fig.44 A top view of Fig.44 yes Fig.43 Cross-sectional view along AA' direction, Fig.45 yes Fig.43 A partial enlarged view of Fig.46 yes Fig.44 The partial enlarged view of the fifth mask layer (not shown) is used as a mask to etch the initial selection gate dielectric layer 120 (such as Fig.42 As shown), until a portion of the surface of the selection layer 115 is exposed, a selection gate dielectric layer 121 and a fourth opening 122 are formed, and ion implantation is performed on the top of the selection layer 115 to form a drain doped region 125 in the selection layer 115.

[0151] The etching method includes dry etching.

[0152] The material of the select gate dielectric layer 121 includes silicon oxide, silicon nitride and aluminum oxide.

[0153] The fourth opening 122 provides a structural basis for the subsequent formation of a source interconnection layer 123 .

[0154] The depth of the fourth opening 122 ranges from 100 nm to 300 nm.

[0155] The distance between the drain doping region 125 and the top surface of the selection layer 115 ranges from 10 nm to 50 nm.

[0156] The ion implantation parameters of the drain doping region 125 include: ion implantation energy range: 10KeV~50KeV; ion implantation dose range: 5E13atoms / cm2 ~5E15atoms / cm 2 .

[0157] The ion types implanted into the drain doping region 125 include: N-type ions and P-type ions; the ion types implanted into the drain doping region 125 are opposite to the conductivity type of the selection layer 115. Specifically, in this embodiment, the conductivity type of the drain doping region 125 is N-type.

[0158] In other embodiments, the conductivity type of the drain doping region may be P type.

[0159] The purpose of performing ion implantation on the top of the selection layer 115 to form the drain doping region 125 is to form a complete MOS structure for the selection switch to be contacted with the conductive plug later.

[0160] Please refer to Figures 47 to 50 , Fig.47 for Fig.48 A top view of Fig.48 yes Fig.47 Cross-sectional view along AA' direction, Fig.49 yes Fig.47 A partial enlarged view of Fig.50 yes Fig.48 A local enlarged view of the fourth opening 122 shows a source interconnection layer 123 filling the fourth opening 122 .

[0161] The material of the source interconnection layer 123 includes tungsten and copper.

[0162] The source interconnection layer 123 is electrically connected to a conductive layer 124 formed subsequently.

[0163] Please refer to Figure 51 to Figure 54 , Fig.51 for Fig.52 A top view of Fig.52 yes Fig.51 Cross-sectional view along AA' direction, Fig.53 yes Fig.51 A partial enlarged view of Fig.54 yes Fig.52 In the local enlarged view, a conductive layer 124 is formed on the surface of the selection gate dielectric layer 121 and the source interconnection layer 123.

[0164] The material of the conductive layer 124 includes copper, aluminum and ruthenium.

[0165] The conductive layers 124 extend along the first direction and are arranged in parallel along the second direction.

[0166] Accordingly, the embodiment of the present invention further provides a memory structure, please continue to refer to Figure 51 to Figure 54 , Fig.51 for Fig.52 A top view of Fig.52 yes Fig.51 Cross-sectional view along AA' direction, Fig.53 yes Fig.51 A partial enlarged view of Fig.54 yes Fig.52 1 is a partial enlarged view, comprising a substrate 100; a source layer 101 located on the substrate 100; a control gate layer 104 located on the source layer 101, wherein the control gate layer 104 has a plurality of first openings 105, each of the first openings 105 exposing a surface of the source layer 101, and each of the first openings 105 is arranged in an array along a second direction and a first direction, wherein the first direction is perpendicular to the second direction; a floating gate layer 109 located on a side wall of each of the first openings 105, wherein each of the floating gate layers 109 has a second opening 108 exposing the source layer 101; a channel layer 110 filling each of the second openings 108, wherein the channel layer 110 has a first projection I on the surface of the substrate 100; and a first projection I on the surface of the substrate 100. A selection layer 115 is provided on the surface of the channel layer 110, wherein the selection layer 115 has a second projection II on the surface of the substrate 100, and the first projection I is located within the range of the second projection II; a plurality of mutually discrete selection gates 119 are provided on the surface of the control gate layer 104, wherein each of the selection gates 119 extends along the second direction and is arranged in parallel along the first direction, and the top surface of each of the selection gates 119 is flush with the selection layer 115, and each of the selection gates 119 has a third projection III on the surface of the substrate 100, and the second projection II is located within the range of the third projection III, and adjacent selection gates 119 have a plurality of third openings 118 in the first direction, and each of the third openings 118 exposes the surface of the control gate layer 104.

[0167] The memory structure includes: a substrate 100 .

[0168] The material of the substrate 100 includes silicon, polysilicon and silicon carbide.

[0169] The substrate 100 provides a structural basis for forming a source layer 101 .

[0170] The conductivity type of the substrate 100 includes: P type and N type. Specifically, in this embodiment, the conductivity type of the substrate 100 is P type.

[0171] In other embodiments, the conductivity type of the substrate may be N-type.

[0172] The memory structure includes: a source layer 101 located on the substrate 100 .

[0173] The material of the source layer 101 includes silicon, polysilicon and silicon carbide.

[0174] The source layer 101 provides a basis for the subsequent formation of a floating gate layer 109 and a control gate layer 104 .

[0175] The conductivity type of the source layer 101 includes: P type and N type. The conductivity type of the source layer 101 is opposite to the conductivity type of the substrate 100. Specifically, in this embodiment, the conductivity type of the source layer 101 is N type.

[0176] In other embodiments, the conductivity type of the source layer may be P type.

[0177] The memory structure includes: a control gate layer 104 located on the source layer 101, and a plurality of first openings 105 are provided in the control gate layer 104, each of the first openings 105 exposes the surface of the source layer 101, and each of the first openings 105 is arranged in an array along a second direction and the first direction, and the first direction is perpendicular to the second direction.

[0178] The material of the control gate layer 104 includes: polysilicon.

[0179] Specifically, in this embodiment, the size range of the first opening 105 parallel to the first direction is: 200nm-1000nm.

[0180] Specifically, in this embodiment, the cross section of the first opening 105 along a direction parallel to the surface of the substrate 100 is circular.

[0181] In other embodiments, the cross section of the first opening along a direction parallel to the substrate surface may be in other shapes.

[0182] The memory structure includes: a first dielectric layer 102 located between the source layer 101 and the control gate layer 104 .

[0183] The material of the first dielectric layer 102 includes silicon oxide, silicon nitride and aluminum oxide.

[0184] The memory structure includes: a floating gate layer 109 located on the sidewall of each of the first openings 105 , and each of the floating gate layers 109 has a second opening 108 exposing the source layer 101 .

[0185] The material of the floating gate layer 109 includes polysilicon, silicon nitride and hafnium oxide.

[0186] The thickness of the floating gate layer 109 is in the range of 10 nm to 100 nm.

[0187] The memory structure includes a second dielectric layer 106 located on the top surface of the control gate layer 104 , between the floating gate layer 109 and the control gate layer 104 , and between the bottom surface of the floating gate layer 109 and the first dielectric layer 102 .

[0188] The material of the second dielectric layer 106 includes silicon oxide, silicon nitride and aluminum oxide; the thickness range of the second dielectric layer 106 is:

[0189] The memory structure includes: a channel layer 110 filling each of the second openings 108 , and the channel layer 110 has a first projection I on the surface of the substrate 100 .

[0190] The material of the channel layer 110 includes: single crystal silicon, polycrystalline silicon and silicon carbide.

[0191] The conductivity type of the channel layer 110 includes: P type and N type; the conductivity type of the source layer 101 is opposite to the conductivity type of the channel layer 110; specifically, in this embodiment, the conductivity type of the channel layer 110 is P type.

[0192] In other embodiments, the conductivity type of the channel layer may be N-type.

[0193] The memory structure includes: a common electrical doping region 113 located in the channel layer 110 .

[0194] The distance between the common electrical doping region 113 and the top surface of the channel layer 110 is in the range of 10 nm to 50 nm.

[0195] The ion implantation parameters of the common electrical doping region 113 include: ion implantation energy range: 10KeV~50KeV; ion implantation dose range: 5E13atoms / cm 2 ~5E15atoms / cm 2 .

[0196] The ion types implanted into the common electrical doping region 113 include: N-type ions and P-type ions; the ion types implanted into the common electrical doping region 113 are opposite to the conductivity type of the channel layer 110. Specifically, in this embodiment, the conductivity type of the common electrical doping region 113 is N-type.

[0197] In other embodiments, the conductivity type of the common electrical doping region may be P type.

[0198] The memory structure includes: a surface of a second dielectric layer 106 located on a surface of the control gate layer 104 , a top surface of the floating gate layer 109 , and a third dielectric layer 112 between the channel layer 110 and the floating gate layer 109 .

[0199] The material of the third dielectric layer 112 includes silicon oxide, aluminum oxide and silicon nitride.

[0200] The memory structure includes: a selection layer 115 located on the surface of the channel layer 110, the selection layer 115 has a second projection II on the substrate surface, and the first projection I is located within the range of the second projection II.

[0201] The material of the selection layer 115 includes: single crystal silicon, polycrystalline silicon and silicon carbide.

[0202] The conductivity type of the selection layer 115 includes: P type and N type; the conductivity type of the selection layer 115 is the same as the conductivity type of the channel layer 110. Specifically, in this embodiment, the conductivity type of the selection layer 115 is P type.

[0203] In other embodiments, the conductivity type of the selection layer may be N-type.

[0204] The memory structure includes a drain doping region 125 located in the selection layer 115 .

[0205] The distance between the drain doping region 125 and the top surface of the selection layer 115 ranges from 10 nm to 50 nm.

[0206] The ion implantation parameters of the drain doping region 125 include: ion implantation energy range: 10KeV~50KeV; ion implantation dose range: 5E13atoms / cm 2 ~5E15atoms / cm 2 .

[0207] The ion types implanted into the drain doping region 125 include: N-type ions and P-type ions; the ion types implanted into the drain doping region 125 are opposite to the conductivity type of the selection layer 115. Specifically, in this embodiment, the conductivity type of the drain doping region 125 is N-type.

[0208] In other embodiments, the conductivity type of the drain doping region may be P type.

[0209] The memory structure includes: a plurality of mutually independent selection gates 119 located on the surface of the control gate layer 104, each of the selection gates 119 extends along the second direction and is arranged in parallel along the first direction, the top surface of each of the selection gates 119 is flush with the selection layer 115, each of the selection gates 119 has a third projection III on the surface of the substrate 100, the second projection II is located within the range of the third projection III, and adjacent selection gates 119 have a plurality of third openings 118 in the first direction, and each of the third openings 118 exposes the surface of the control gate layer 104.

[0210] The material of the select gate 119 includes: single crystal silicon, polycrystalline silicon and silicon carbide.

[0211] The memory structure includes a select gate oxide layer 126 located between the select gate 119 and the select layer 115 .

[0212] The material of the selection gate oxide layer 126 includes silicon oxide, silicon nitride and aluminum oxide.

[0213] The memory structure includes a selection gate dielectric layer 121 located in the third opening 118 , on the surface of the selection gate 119 and on the surface of the selection layer 115 , and the selection gate dielectric layer 121 has a plurality of fourth openings 122 , each of which exposes a portion of the surface of the selection layer 115 .

[0214] The material of the select gate dielectric layer 121 includes silicon oxide, silicon nitride and aluminum oxide.

[0215] The depth of the fourth opening 122 ranges from 100 nm to 300 nm.

[0216] The memory structure includes a source interconnection layer 123 filling up the fourth opening 122 .

[0217] The material of the source interconnection layer 123 includes tungsten and copper.

[0218] The memory structure includes: a conductive layer 124 located on the surfaces of the select gate dielectric layer 121 and the source interconnect layer 123 .

[0219] The material of the conductive layer 124 includes copper, aluminum and ruthenium.

[0220] The conductive layers 124 extend along the first direction and are arranged in parallel along the second direction.

[0221] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A memory structure, characterized in that: include: substrate; a source layer located on the substrate; a control gate layer located on the source layer, wherein the control gate layer has a plurality of first openings, each of the first openings exposes a surface of the source layer, and each of the first openings is arranged in an array along a second direction and the first direction, and the first direction is perpendicular to the second direction; A floating gate layer located on a side wall of each of the first openings, each of the floating gate layers having a second opening exposing a source layer; A channel layer filling each of the second openings, wherein the channel layer has a first projection on the substrate surface; a selection layer located on the surface of the channel layer, the selection layer having a second projection on the substrate surface, and the first projection being located within the range of the second projection; A plurality of mutually independent selection gates are located on the surface of the control gate layer, each of the selection gates extends along the second direction and is arranged in parallel along the first direction, the top surface of each selection gate is flush with the selection layer, each selection gate has a third projection on the substrate surface, the second projection is located within the range of the third projection, and adjacent selection gates have a plurality of third openings in the first direction, and each of the third openings exposes the surface of the control gate layer.

2. The memory structure according to claim 1, characterized in that: The invention also includes: a co-electrically doped region located in the channel layer; a distance range from the co-electrically doped region to the top surface of the channel layer is: 10nm to 50nm; ion implantation parameters of the co-electrically doped region include: an ion implantation energy range of: 10KeV to 50KeV; an ion implantation dose range of: 5E13atoms / cm 2 ~5E15atoms / cm 2 ; The ion types injected into the common electrical doping region include: N-type ions and P-type ions; The ion types injected into the common electrical doping region are opposite to the conductivity type of the channel layer.

3. The memory structure according to claim 1, characterized in that: It also includes: a drain doping region located in the selection layer; the distance range from the drain doping region to the top surface of the selection layer is: 10nm to 50nm; the ion implantation parameters of the drain doping region include: the ion implantation energy range is: 10KeV to 50KeV; the ion implantation dose range is: 5E13atoms / cm 2 ~5E15atoms / cm 2 ; The ion types injected into the drain doping region include: N-type ions and P-type ions; The ion type injected into the drain doping region is opposite to the conductivity type of the selection layer.

4. The memory structure according to claim 1, characterized in that: Also includes: The select gate dielectric layer is located in the third opening, on the surface of the select gate and on the surface of the select layer. The select gate dielectric layer has a plurality of fourth openings, and each of the fourth openings exposes a portion of the surface of the select layer.

5. The memory structure according to claim 4, characterized in that: Also includes: A source interconnection layer fills the fourth opening.

6. The memory structure according to claim 5, characterized in that: Also includes: A conductive layer located on the surface of the select gate dielectric layer and the source interconnect layer.

7. The memory structure according to claim 1, characterized in that: Also includes: a first dielectric layer located between the source layer and the control gate layer; The material of the first dielectric layer includes silicon oxide, silicon nitride and aluminum oxide.

8. The memory structure according to claim 1, characterized in that: The materials of the substrate include: silicon, polycrystalline silicon and silicon carbide; the conductivity types of the substrate include: P type and N type; the materials of the source layer include: silicon, polycrystalline silicon and silicon carbide; the conductivity types of the source layer include: P type and N type; the conductivity type of the source layer is opposite to the conductivity type of the substrate, and the conductivity type of the source layer is opposite to the conductivity type of the channel layer.

9. The memory structure according to claim 7, characterized in that: Also includes: A second dielectric layer located on the top surface of the control gate layer, between the floating gate layer and the control gate layer, and between the bottom surface of the floating gate layer and the first dielectric layer; The material of the second dielectric layer includes: silicon oxide, silicon nitride and aluminum oxide; The thickness range of the second dielectric layer is:

10. The memory structure according to claim 1, characterized in that: Also includes: A third dielectric layer is located on the surface of the second dielectric layer on the surface of the control gate layer, the top surface of the floating gate layer, and between the channel layer and the floating gate layer.

11. The memory structure according to claim 1, characterized in that: The size range of the first opening along the direction parallel to the first direction is: 200nm~1000nm; the cross section of the first opening along the direction parallel to the substrate surface is circular; the thickness range of the channel layer is: 50nm~200nm.

12. The memory structure according to claim 1, characterized in that: The floating gate material includes: polysilicon, silicon nitride and hafnium oxide; the control gate layer material includes: polysilicon; the select gate material includes: single crystal silicon, polysilicon and silicon carbide.

13. The memory structure according to claim 8, characterized in that: The channel layer materials include: single crystal silicon, polycrystalline silicon and silicon carbide; the conductivity types of the channel layer include: P type and N type; the selection layer materials include: single crystal silicon, polycrystalline silicon and silicon carbide; the conductivity types of the selection layer include: P type and N type; the conductivity type of the selection layer is the same as the conductivity type of the channel layer.

14. The memory structure according to claim 1, wherein: The thickness of the floating gate layer ranges from 10 nm to 100 nm.

15. The memory structure according to claim 1, characterized in that: Also includes: A select gate oxide layer is located between the select gate and the select layer.

16. A method for forming a memory structure, characterized in that: include: Providing a substrate and a source layer located on a surface of the substrate; A control gate layer is formed on the source layer, wherein the control gate layer has a plurality of first openings, each of the first openings exposes a surface of the source layer, and each of the first openings is arranged in an array along a second direction and the first direction, and the first direction is perpendicular to the second direction; Forming a floating gate layer on the sidewall of each of the first openings, each of the floating gate layers having a second opening exposing the source layer; forming a channel layer filling each of the second openings in each of the second openings, wherein the channel layer has a first projection on the surface of the substrate; forming a selection layer on the surface of the channel layer, wherein the selection layer has a second projection on the surface of the substrate, and the first projection is located within the range of the second projection; A plurality of mutually independent selection gates are formed on the surface of the control gate layer, each of the selection gates extends along the second direction and is arranged in parallel along the first direction, a top surface of each selection gate is flush with the selection layer, each selection gate has a third projection on the substrate surface, the second projection is within the range of the third projection, and adjacent selection gates have a plurality of third openings in the first direction, each of the third openings exposes the surface of the control gate layer.

17. The method for forming a memory structure according to claim 16, wherein: After forming the source layer and before forming the control gate layer, the method further includes: forming a first dielectric layer on the surface of the source layer.

18. The method for forming a memory structure according to claim 17, wherein: The method for forming the control gate layer includes: forming an initial control gate layer on the surface of the first dielectric layer; forming a first mask layer on the surface of the initial control gate layer, wherein the first mask layer exposes a portion of the surface of the initial control gate layer; using the first mask layer as a mask, etching the initial control gate layer until the surface of the first dielectric layer is exposed, thereby forming the control gate layer.

19. The method for forming a memory structure according to claim 16, wherein: After forming the control gate layer and before forming the floating gate layer, the method further includes: forming a second dielectric layer located on a surface of the first opening and a top surface of the control gate layer.

20. The method for forming a memory structure according to claim 19, wherein: The method for forming the floating gate layer comprises: forming an initial floating gate layer filling the first opening on the surface of the second dielectric layer on the surface of the first opening, wherein the initial floating gate layer is flush with the top surface of the second dielectric layer; forming a second mask layer on the surface of the initial floating gate layer and the surface of the second dielectric layer on the surface of the control gate layer, wherein the second mask layer exposes a portion of the surface of the initial floating gate layer; etching the initial floating gate layer using the second mask layer as a mask until the bottom surface of the second dielectric layer is exposed, thereby forming a second opening located in the initial floating gate layer and the floating gate layer.

21. The method for forming a memory structure according to claim 20, wherein: After forming the second opening and before forming the channel layer, the method further includes: forming an initial third dielectric layer on the surface of the second opening, the top surface of the floating gate layer, and the surface of the second dielectric layer on the surface of the control gate layer; etching back the initial third dielectric layer on the bottom surface of the second opening until the surface of the source layer is exposed, thereby forming a third dielectric layer on the surface of the second dielectric layer on the top surface of the control gate layer, the top surface of the floating gate layer, and the sidewall surface of the floating gate layer.

22. The method for forming a memory structure according to claim 21, wherein: The method for forming the channel layer includes: forming an initial channel layer in the second opening and on the surface of the third dielectric layer; and planarizing the initial channel layer until the top surface of the third dielectric layer is exposed to form the channel layer.

23. The method for forming a memory structure according to claim 22, wherein: After forming the channel layer and before forming the selection layer, the method further includes: performing ion implantation on the top of the channel layer to form a common electrical doping region in the channel layer.

24. The method for forming a memory structure according to claim 23, wherein: The method for forming the selection layer includes: forming an initial selection layer on the surface of the third dielectric layer; forming a third mask layer on the surface of the initial selection layer, wherein the third mask layer exposes a portion of the surface of the initial selection layer; using the third mask layer as a mask, etching the initial selection layer until the surface of the third dielectric layer is exposed, thereby forming the selection layer.

25. The method for forming a memory structure according to claim 24, wherein: After forming the selection layer and before forming the selection gate, the method further includes: forming an initial selection gate oxide layer on the top surface of the selection layer, the side wall surface of the selection layer, and the surface of the third dielectric layer.

26. The method for forming a memory structure according to claim 25, wherein: The method for forming the select gate includes: after forming the initial select gate oxide layer, forming a select gate material layer on the surface of the initial select gate oxide layer; flattening the surface of the select gate material layer until the surface of the select layer is exposed to form the initial select gate layer; forming a fourth mask layer on the initial select gate layer and the surface of the select layer, the fourth mask layer exposing a portion of the surface of the initial select gate layer; using the fourth mask layer as a mask, etching the initial select gate layer until the surface of the control gate layer is exposed to form a plurality of third openings located in the initial select gate layer, the third openings extending along the second direction and arranged in parallel along the first direction.

27. The method for forming a memory structure according to claim 26, wherein: After forming the selection gate, it also includes: forming an initial selection gate dielectric layer in each of the third openings, on the surface of the selection layer and on the surface of the selection gate; forming a fifth mask layer on the surface of the initial selection gate dielectric layer, wherein the fifth mask layer exposes a portion of the surface of the selection layer; using the fifth mask layer as a mask, etching the initial selection gate dielectric layer until a portion of the surface of the selection layer is exposed, thereby forming a selection gate dielectric layer and a fourth opening.

28. The method for forming a memory structure according to claim 27, wherein: After forming the fourth opening, the method further includes: forming a source interconnection layer filling the fourth opening in the fourth opening; A conductive layer is formed on the surfaces of the select gate dielectric layer and the source interconnect layer.

29. The method for forming a memory structure according to claim 16, wherein: The cross section of the first opening along a direction parallel to the substrate surface is circular.

30. The method for forming a memory structure according to claim 28, wherein: After forming the fourth opening and before forming the source interconnection layer, the method further includes: performing ion implantation on the top of the selection layer to form a drain doping region in the selection layer.

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