A method for forming a memory structure of a 3D NAND flash memory

Abstract

According to one aspect, a method for forming a memory structure of a 3D NAND flash memory is provided, the method comprising: forming a layer stack on a substrate; forming a first recessed region in a sidewall surrounding a memory hole in the layer stack by laterally etching back a gate layer of the layer stack from a memory hole in the layer stack; forming a lateral memory stack in each first recessed region by depositing a blocking oxide and then depositing a charge trap material; forming a second recessed region in the sidewall by laterally etching back an inter-gate spacer layer from the memory hole; forming a dummy layer in the second recessed region; lining the sidewall of the memory hole with a liner layer; performing a heat treatment process on the dummy layer, the heat treatment process being adapted to convert each dummy layer into an air gap structure; forming a tunneling oxide layer in the memory hole along the liner layer, and forming a channel layer along the tunneling oxide layer.

Description

Technical Field

[0001] The present invention generally relates to a method for forming a memory structure of a 3D NAND flash memory. Background Art

[0002] The bit density in the 3D NAND Flash memory roadmap is increasing every year. So far, this growth has been achieved by increasing the number of memory cells stacked along the vertical dimension. However, this route is becoming increasingly difficult and expensive. As a result, there is growing interest in technologies that scale cells along the vertical dimension. Vertical scaling ("z-pitch scaling") is achieved by reducing the thickness of individual layers in the layer stack, such as the wordline (gate) layer and the oxide gate spacer layer.

[0003] However, Z scaling results in a reduction in inter-cell spacing, which in turn results in an increase in parasitic capacitance between cell word lines, making it difficult to control inter-cell interference. Increased inter-cell interference may degrade performance-related parameters of memory devices, significantly reduce threshold voltages and increase programming voltages. Therefore, scalable techniques are needed to allow for better control of inter-cell interference. Summary of the invention

[0004] As the inventors have recognized, an effective way to control cell-to-cell interference is to introduce an air gap structure between the gate / word line layers. Therefore, an object of the present invention is to provide a method for forming a memory structure of a 3D NAND flash memory to allow the formation of an air gap structure in the memory structure also under aggressive z-pitch scaling.

[0005] Therefore, according to one aspect of the present invention, there is provided a method for forming a memory structure of a 3D NAND flash memory, the method comprising:

[0006] forming a layer stack on a substrate, the layer stack comprising an alternating sequence of gate layers and inter-gate spacer layers;

[0007] forming a first recessed region in a sidewall surrounding the memory hole by laterally etching back the gate layer from the memory hole in the layer stack;

[0008] forming a lateral memory stack in each first recessed region by depositing a blocking oxide and subsequently depositing a charge trapping material;

[0009] forming a second recessed region in the sidewall by laterally etching back the inter-gate spacer layer from the memory hole;

[0010] forming a dummy layer in the second recessed region;

[0011] After forming the lateral memory stack and the dummy layer, lining the sidewalls of the memory hole with a lining layer;

[0012] After lining the sidewalls, performing a thermal treatment process on the dummy layers, the thermal treatment process being adapted to convert each dummy layer into an air gap structure, wherein the air gap structure is laterally formed between the liner layer and the gate spacer layer;

[0013] forming a tunnel oxide layer in the memory hole along the liner layer; and

[0014] A channel layer is formed along the tunnel oxide layer.

[0015] Therefore, the method according to the present invention can form a memory structure including discrete lateral memory stacks in each gate / word line layer (equivalent to each memory cell), wherein the lateral memory stacks are vertically separated by air gap structures. Due to the low dielectric constant (low k) of the air gap structure, inter-cell interference can be effectively reduced. Specifically, the air gap structure has a lower k than the oxide suitable for forming the inter-gate spacer layer.

[0016] The term "air gap structure" herein means a space or void enclosed by a pair of lateral memory stacks, i.e., a liner layer and an inter-gate spacer layer. The space may contain air and / or other ambient gases that may be present in the process environment in which the steps of the method are performed or traces of non-polymer material remaining from the converted dummy layer (e.g., in a solid phase, forming a porous structure in the second recessed region).

[0017] Another advantage of the present method aspects is that the air gap separates the charge trap layers. Traditionally, the charge trap layers have been deposited as a continuous layer along the sidewalls of the memory holes in the layer stack. The reduction in inter-cell spacing involving z scaling results in a reduction in inter-cell spacing, which in turn can reduce the retention performance of the continuous charge trap layer. However, with the present method aspects, a separate discrete charge trap layer is formed for each gate layer, thereby enabling improved retention performance for each cell.

[0018] Although the dummy layer is encapsulated by the lateral memory stack, the liner layer and the inter-gate spacer layer, the use of a thermal process allows the dummy layer to be reliably converted into an air gap structure (e.g., by heating to remove the dummy layer). At the same time, the liner layer ensures that subsequently deposited materials will not fill the air gap structure.

[0019] A possible challenge introduced by the presence of a dummy layer in a layer stack is that materials (e.g., polymers) that can be converted into an air gap structure may have poor compatibility with other materials of the layer stack. For example, a dummy material suitable for a thermal treatment process may introduce mechanical stress into the layer stack or reduce the adhesion between the layers of the stack. Since the inter-gate spacer layer according to aspects of the present method is partially retained in the layer stack (i.e., meaning that a dummy layer is locally introduced between the lateral memory stacks and thereby introduces an air gap structure), the risk of the dummy layer introducing structural defects into the layer stack is reduced. As an illustrative comparative example, consider a hypothetical process that includes completely replacing the inter-gate spacer layer with a dummy layer, in which the risk of deformation or delamination of the layer stack will be much greater than in aspects of the present method.

[0020] Furthermore, by forming the air gap structure prior to the channel layer, the thermal budget for forming the channel layer may be selected without risk of inadvertently affecting the dummy layer (eg, the thermal budget for polysilicon deposition may exceed the decomposition temperature of many suitable polymer dummy materials).

[0021] Reference is made herein to a "first recessed region" and a "second recessed region". It should be noted that the "first" and "second" herein are merely labels and do not imply any particular temporal order in which the respective recessed regions are formed. That is, as will be apparent from the following disclosure, in some embodiments, the "first" recessed region may be formed before the "second" recessed region, and in some embodiments, the "second" recessed region may be formed before the "first" recessed region.

[0022] In some embodiments, the dummy layer may be formed of a polymer-containing material. There are many polymers that can be effectively and reliably removed using thermal processes, such as by evaporation, leaving substantially no organic residue in the layer stack (although non-polymer traces may remain, as described below).

[0023] In some embodiments, the treating process removes the polymer-containing material of the dummy layer from the second recessed region.

[0024] Alternatively, trace amounts of dummy material (eg, decomposed dummy material) may remain in the second recessed region to form an air gap structure, such as a silicate compound.

[0025] In some embodiments, the liner layer is deposited at a temperature below the temperature that results in the conversion of the dummy layer into the air gap structure. Unintended conversion of the dummy layer before the second recessed region is "sealed" by the liner layer can thus be avoided.

[0026] In some embodiments, the liner layer is formed of a low thermal oxide (LTO). 2 ) can be reliably deposited without triggering the transformation of the dummy layer.

[0027] In some embodiments, the thickness of the liner layer is in the range of 1-4 nm or 1-2 nm.

[0028] In some embodiments, the lateral depth of the second recessed region is such that the air gap structure at least undercuts the charge trapping material of the lateral memory stack. Thus, the air gap structures can be formed where they have the greatest impact on inter-cell interference, ie, between the charge trapping materials.

[0029] In some embodiments, the lateral depth of the second recessed region is such that the air gap structure further undercuts the blocking oxide of the lateral memory stack. Thus, the air gap structure can extend laterally along the entire (lateral) thickness direction of the lateral memory stack, further reducing inter-cell interference.

[0030] In some embodiments, the gate layer is a sacrificial gate layer, and the method further comprises replacing the sacrificial gate layer with a replacement metal gate stack after forming the air gap structure. The sacrificial gate layer can be removed by etching back the sacrificial gate layer from a second hole in the layer stack that is different from the memory hole and then forming a replacement metal gate stack that replaces the sacrificial gate layer.

[0031] In some embodiments, the lateral depth of the second recessed region is such that the air gap structure undercuts the charge trap material of the lateral memory stack but does not undercut the blocking oxide of the lateral memory stack. Thus, the air gap structure can be protected during the deposition of the replacement metal gate stack.

[0032] In some embodiments, the method further comprises depositing a further liner layer of a dielectric material in the second recessed region before forming the dummy layer, wherein the further liner layer is used as an etch stop layer when replacing the sacrificial gate layer with the replacement metal gate stack. Thus, even if the second recessed region also undercuts the blocking oxide, the air gap structure can be protected during the deposition of the replacement metal gate stack.

[0033] In some embodiments, the second recessed region is formed after forming the lateral memory stack in the first recessed region. Thus, the risk of unintended conversion of the dummy layer due to deposition of blocking oxide and deposition of charge trapping material before the second recessed region is "sealed" by the liner layer can be avoided.

[0034] In some embodiments, the method further comprises, before forming the first recessed region:

[0035] forming an initial recessed region in a sidewall surrounding the memory hole by etching back the inter-gate spacer layer laterally from the memory hole; and

[0036] forming a sacrificial layer in the initial recessed region;

[0037] Wherein the first recessed region is formed after forming a sacrificial layer, and wherein the lateral memory stack is formed by depositing a blocking oxide in the first recessed region and subsequently depositing a charge trapping material, wherein the sacrificial layer defines a deposition inhibition region for selective deposition of the blocking oxide and the charge trapping material.

[0038] Therefore, the method uses an area selective deposition process (ASD) to "directly" deposit discrete charge trap layers, rather than depositing a continuous charge trap layer and then "cutting" the charge trap layer into multiple discrete parts, where a sacrificial layer is used to define deposition inhibition areas ("non-growth areas"). Deposition of charge trap material in the areas vertically between gate layers can therefore be avoided, thereby eliminating the need to cut the charge trap material by etching. By eliminating the need for etching, the thickness size of the charge trap layer (seen in the lateral dimension) can be precisely controlled by maintaining the growth conditions of the selective deposition until the target thickness is reached. The previous discussion applies correspondingly to the blocking oxide.

[0039] Since the inter-gate spacer layer is formed of a dielectric material (typically an oxide), it is conceivable that selectively depositing a blocking oxide and a charge trapping material in the first recessed region (i.e., in each vertical layer of the gate layers) without any significant concurrent deposition on the inter-gate spacer layer will be challenging. However, by etching back the inter-gate spacer layer to form an initial recessed region in the sidewall and then forming a sacrificial layer in the initial recessed region (e.g., filling the initial recessed region with a sacrificial layer material), significantly improved areal selectivity can be achieved. That is, the sacrificial layer material can be selected to promote areal selective deposition regardless of its suitability in a finished functional memory device. In general, the sacrificial layer can be formed of a sacrificial layer material that is selected to be deposition inhibiting for selective deposition of a blocking oxide.

[0040] Another advantage of the deposition inhibiting property of the sacrificial layer is that the risk of pinching off the first recessed region due to deposition of blocking oxide or charge trapping material can be avoided.

[0041] In some embodiments, the initial recessed region is a second recessed region, and the method further includes removing the sacrificial layer from the second recessed region by etching from the memory hole and thereafter forming a dummy layer in the second recessed region after forming the lateral memory stack.

[0042] Thus, the regrowth of the inter-gate spacer layer in the initial recessed region and the subsequent lateral etching back thereof to form the second recessed region can be omitted in the method. Thus, in addition to the deposition inhibition function when forming the lateral memory stack, the sacrificial layer can also act as a placeholder for the dummy layer and thus be replaced by the dummy layer after the lateral memory stack is formed. In the method, the sacrificial layer material can also be selected to be selectively etchable to the charge trap material, the blocking oxide and the gate layer material (i.e., the sacrificial layer material can be etched at a greater rate than each of the charge trap material, the blocking oxide and the gate layer material) to allow the sacrificial layer to be selectively removed from the initial / second recessed region.

[0043] Alternatively, in some embodiments, the method further comprises, after forming the lateral memory stack:

[0044] removing the sacrificial layer by etching from the memory hole;

[0045] After removing the sacrificial layer, regrowing the inter-gate spacer layer so that the lateral memory stacks are vertically spaced apart by the regrown inter-gate spacer layer;

[0046] And wherein after regrowing the inter-gate spacer layer, the method continues to form a second recessed region by laterally etching back the regrown inter-gate spacer layer.

[0047] Thus, the materials of the sacrificial layer and the dummy layer can be selected independently of each other, for example, to optimize the deposition inhibition characteristics of the sacrificial layer and the conversion of the dummy layer to the air gap structure, respectively, and to form an initial recessed region and a second recessed region having respective depths selected independently of each other. In this method, the sacrificial layer material can also be selected to be selectively etchable to the charge trap material, the blocking oxide, and the gate layer material (i.e., the sacrificial layer material can be etched at a greater rate than each of the charge trap material, the blocking oxide, and the gate layer material) to allow the sacrificial layer to be selectively removed from the initial recessed region. In some embodiments, the sacrificial layer is a metal oxide layer (such as Al 2 O 3 or TiO 2 The sacrificial materials may be a layer of a metal nitride (such as an AlN or TiN layer), a metal layer (such as a Co, Ru, Cu, W or Mo layer), or a carbon-containing layer (such as an amorphous carbon or organic spin-on layer). Any of these types of sacrificial materials facilitate process control because they tend to define a deposition inhibiting surface relative to the ASD of the blocking oxide and charge trapping material. These sacrificial materials further achieve etch selectivity relative to the charge trapping material, the blocking oxide, and the gate layer material (whether polysilicon or a nitride-containing material). This is particularly applicable to carbon-containing layers, such as amorphous carbon or an organic spin-on layer.

[0048] Alternatively, in some embodiments, the initial recessed region and the second recessed region and the sacrificial layer are dummy layers. The dummy layer (e.g., formed of a polymer-containing material) can thus be used as a deposition inhibition layer to block the ASD of oxide and charge trap materials, and then converted into an air gap structure by a thermal treatment process. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] This and other aspects of the present invention will now be described in more detail, with reference to the appended drawings showing embodiments of the invention.

[0050] Figure 1a -b schematically illustrate a schematic cross-sectional view and a top view, respectively, of a starting structure for forming a memory structure according to an embodiment.

[0051] Figure 2 The structure is shown after forming the first recessed region.

[0052] Figure 3 The structure is shown after forming a lateral memory stack in the first recessed region.

[0053] Figure 4 The structure is shown after forming the second recessed region.

[0054] Figure 5-6 The formation of a dummy layer in the second recessed region is shown.

[0055] Figure 7 The structure is shown after lining the sidewalls of the memory hole.

[0056] Figure 8 The structure is shown after converting the dummy layer into an air gap structure.

[0057] Fig. 9 The structure is shown after forming a tunnel oxide layer and a channel layer.

[0058] Fig.10 The structure is shown after forming a dielectric liner in the first recessed region before depositing a blocking oxide according to another embodiment.

[0059] Fig.11 Shown according to Fig.10 A lateral memory stack is formed.

[0060] Fig.12 A lateral memory stack formed in accordance with another embodiment is shown.

[0061] Figure 13-16 A series of optional process steps are shown that facilitate the selective deposition of blocking oxide and charge trapping material. DETAILED DESCRIPTION

[0062] An embodiment of a method for forming a memory structure of a 3D NAND flash memory will now be described with reference to the accompanying drawings. The accompanying drawings are schematic only, and the relative sizes of certain structures and layers may be exaggerated and not drawn to scale. Instead, the dimensions may be adjusted to make the illustration clear and to facilitate understanding of the following description. When present in the figures, the indicated axes X, Y, and Z refer to the first horizontal or lateral direction, the second horizontal or lateral direction, and the vertical direction, respectively. As used herein, the terms "horizontal" and "lateral" refer to the direction parallel to the supporting substrate of the memory structure. The term "vertical" refers to the direction parallel to the substrate normal, i.e., the direction transverse to the substrate.

[0063] Figure 1a -b schematically show a schematic cross-sectional view and a top view, respectively, of a structure 1 at an initial stage of the method. The structure 1 comprises a layer stack 10 representing a precursor or starting structure of a memory structure which will be subjected to the processing steps of the method disclosed below.

[0064] The layer stack 10 is formed on a substrate 2 and comprises an alternating sequence of gate layers 14 and inter-gate spacer layers 12 .

[0065] The substrate 2 may be a conventional substrate suitable for semiconductor processing and for supporting a memory structure of a 3D NAND flash memory. The substrate 2 may be, for example, a Si substrate, a Ge substrate, or a SiGe substrate. Other examples include a silicon-on-insulator (SOI) substrate, a GeOI substrate, or a SiGeOI substrate.

[0066] The gate layer 14 may be a nitride-containing layer, such as a SiN layer, thereby forming a sacrificial gate layer 14 intended to be replaced by the RMG stack in a subsequent process step. The gate layer 14 may also be a functional gate layer, such as a layer containing highly doped polysilicon.

[0067] The inter-gate spacer layer 12 may be a layer containing an oxide, such as SiO 2 A layer or another suitable interlayer dielectric (eg, low-k) is provided. An inter-gate spacer layer 12 is disposed in the layer stack 10 to provide vertical separation between memory cells / word lines of a memory device to be formed.

[0068] The layer stack 10 may be formed by alternately depositing layers of gate material (eg nitride) and inter-gate spacer material (eg oxide) using deposition processes known in the art such as chemical vapor deposition (CVD), physical vapor deposition or atomic layer deposition (ALD).

[0069] The inter-gate spacer layer 12 and the gate layer 14 can be formed in large quantities depending on the expected number of stacked memory cells of the memory device. It should be noted that the number of layers 12, 14 in the layer stack 10 shown is only a non-limiting example, and the method disclosed herein is compatible with stacking of substantially any number of memory cells currently used or expected in the industry (such as 64, 128, 256 or more).

[0070] As an example, the inter-gate spacer layer 12 and the gate layer 14 may be formed to have respective layer thicknesses in the range of 5-25 nm. The z-pitch of the layer stack 10 (ie, the combined thickness of one inter-gate spacer layer and one gate layer 14) may be in the range of about 45 nm to 15 nm or less.

[0071] As shown, the layer stack 10 may further comprise a capping layer in the form of a semiconductor layer 16, which is deposited over the topmost gate spacer layer 12. The semiconductor layer 16 may be formed of Si, for example.

[0072] After deposition of layers 12 and 14 (and optionally 16) in layer stack 10, memory holes 4 may be patterned in layer stack 14, for example, by photolithography and etching processes. Figure 1a -b shows a portion of the layer stack 10 surrounding a single memory hole 4, but it should be noted that a corresponding memory hole 4 can be patterned at each location where a corresponding vertical memory cell string is needed. As shown, the memory hole 4 can be formed to extend through each of the inter-gate spacer layer 12 and the gate layer 14 in the layer stack 10. As shown in Figure 1b As further shown in the top view of , the memory hole 4 can be formed to have a circular cross-sectional shape, so that the memory hole 4 can be formed to have a substantially circular cylindrical shape. However, the memory hole 4 can also be formed to have other cross-sectional shapes, such as an ellipse or a polygon.

[0073] Although not in Figure 1a 1 , but as is known in the art, the layer stack 10 may further include a sub-stack of select and source layers below the layers 12, 14 for forming the select and source plates of the memory device, respectively. The select and source layers may thus form a bottom sub-stack of the layer stack 10. The select and source layers may be formed by conventional techniques and materials, such as doped semiconductor layers (e.g., polysilicon) and separated by an interlayer dielectric layer.

[0074] exist Figure 2 In FIG. 4 , the first recessed region 18 has been formed in the sidewalls surrounding the memory hole 4 by etching back the gate layer 14 laterally from the memory hole 4 relative to the inter-gate spacer layer 12 .

[0075] The gate layer 14 is laterally etched back (along the X-axis) selectively to the inter-gate spacer layers 12 so that a first recessed region 18 is formed between the inter-gate spacer layers 12. That is, each recessed region / recess in the first recessed regions 18 is formed between a pair of inter-gate spacer layers 12. Since the sidewalls extend around the circumference of the memory hole 4, the first recessed region 18 may extend around the circumference of the memory hole 4. In the example of a circular memory hole 4, the first recessed region 18 may be annular.

[0076] The gate layer 14 may be etched back using an etching process adapted to selectively etch the gate layer 14 with respect to the inter-gate spacer layer 12. That is, the etching process may be adapted to selectively etch (i.e., remove) the material (e.g., nitride material) of the gate layer 14 with respect to the material (e.g., oxide material) of the inter-gate spacer layer 12, for example, such that the gate layer 14 may be laterally etched back without causing any substantial etching back of the inter-gate spacer layer 12. The etching process may be applied to the sidewalls of the layer stack 10 via the memory hole 4. Any suitable selective etching process (such as an isotropic etching process) that provides a sufficient lateral etching component with respect to the gate layer 14 may be used, whether wet or dry.

[0077] The first recessed region 18 may be formed to have a shape similar to that at each layer to be formed in the gate layers 14 (see, for example, Figure 3 ) of the lateral memory stack 19. The depth of the first recessed region 18 (i.e., the amount of lateral etch back) may be, for example, in the range of 6-20 nm. The depth of the first recessed region 18 may be controlled by timing the lateral etch back.

[0078] Figure 3 The structure is depicted after forming a lateral memory stack 19 in each first recessed region 18 by depositing a blocking oxide 20 in the first recessed regions 18 and subsequently depositing a charge trapping material 21 .

[0079] As shown in the figure, each lateral memory stack 19 can form a discrete lateral memory stack 19 in the corresponding recessed area 18, and each discrete lateral memory stack 19 includes a discrete blocking oxide portion or layer (which may also be referred to by the figure mark 20 below) and a discrete charge trap material portion or layer (which may also be referred to by the figure mark 21 below).

[0080] The blocking oxide 20 may be formed to have a lateral thickness (along the X-axis) in the range of 4-12 nm. The charge trap material (layer) 21 may be formed to have a lateral thickness (along the X-axis) in the range of 4-8 nm. More generally, the blocking oxide 20 and the charge trap material 21 may fill the first recessed region 18 so that the inner end surface (i.e., facing inward relative to the memory hole 4) of the charge trap material (layer) 21 is substantially flush with the inner end surface of the inter-gate spacer layer 12. The lateral memory stack 19 may thereby fill the lateral depth of the first recessed region 18, thereby restoring the sidewalls surrounding the memory hole 4 to a substantially straight profile.

[0081] The blocking oxide 24 may include or may include SiOx (eg, SiO 2 ) or some other oxide material suitable for use as a blocking oxide. The charge trap material 26 may include SiN (ie, Si 3 N 4 ) or some other oxide material suitable for use as a charge trap material.

[0082] The lateral memory stack 19 may be formed using both area-selective and non-area-selective deposition techniques.

[0083] Using a non-area-selective deposition technique, the formation of the lateral memory stack 19 may include conformally depositing (e.g., using ALD) an initial blocking oxide layer in each first recessed region 18 and covering the sidewalls of the memory hole 4, for example, including the inner end surface of the gate spacer layer 12. The initial blocking oxide layer may then be laterally etched back (e.g., using an isotropic etch) so that the inner end surface of the gate spacer layer 12 at the sidewalls of the memory hole 4 is exposed, and discrete portions of the blocking oxide remain in the first recessed region 12. Subsequently, an initial charge trap material layer may be conformally deposited (e.g., using ALD) in each first recessed region 18 (e.g., on the blocking oxide 20) in a corresponding manner and covering the sidewalls of the memory hole 4, for example, including the inner end surface of the gate spacer layer 12. The initial blocking oxide layer may then be laterally etched back (e.g., using an isotropic etch) so that the inner end surface of the gate spacer layer 12 at the sidewalls of the memory hole 4 is exposed, and discrete portions of the charge trap material 21 remain in the first recessed region 18, for example, on the blocking oxide 20.

[0084] Using the area selective deposition technique, the lateral memory stack 19 can be formed by selectively depositing the blocking oxide 20 in the first recessed region 18 and subsequently depositing the charge trap material 21. Therefore, both the blocking oxide 20 and the charge trap material 21 are selectively deposited, wherein the inter-gate spacer layer 12 defines a deposition inhibition region (non-growth region) for the selective deposition of the blocking oxide 20 and the charge trap material 21. Since the blocking oxide 20 and the charge trap material 21 are selectively deposited in the first recessed region 18, the blocking oxide 20 can be directly deposited to define a discrete blocking oxide layer in each first recessed region 18, and the charge trap material 21 can be directly deposited to form a discrete charge trap layer in each first recessed region 18. The blocking oxide 20 can be deposited using any deposition process (e.g., ALD or CVD process) that allows for area selective deposition of the blocking oxide 20 (e.g., SiO2), so that the blocking oxide 20 is deposited on the growth promoting or seed surface portion in the first recessed region 18, but not deposited on the growth inhibition region of the inter-gate spacer layer 12. The growth promoting surface portion may specifically be a surface portion of the etched-back gate layer 14 exposed in the first recessed region 18 (ie, Figure 2 The charge trap material 21 may be deposited using any deposition process (e.g., an ALD or CVD process) that allows for area-selective deposition of the charge trap material 21 (e.g., SiN) so that the charge trap material 21 is deposited on a growth-promoting or seed surface portion in the first recessed region 18 but not on a growth-inhibiting region of the inter-gate spacer layer 12. The growth-promoting surface portion may in particular be defined by an already deposited blocking oxide 20.

[0085] In order to promote the selective deposition of the blocking oxide 20, a processing step may be performed on the layer stack 10 before depositing the blocking oxide 20, which processing step is adapted to functionalize the surface portion / end face 14a of the etched-back gate layer 14 in the first recessed region 18 and then deposit the blocking oxide 20 on the functionalized surface portion in the first recessed region 8. For example, Figure 2As schematically indicated in one of the recessed regions 18 of the gate layer 14, the functionalization may include depositing a deposition promoting layer 15 on a surface portion 14a of the etched-back gate layer 14 in the first recessed region 18. Additionally or alternatively, a treatment process adapted to passivate the exposed surface portion of the inter-gate spacer layer 12 relative to the selective deposition of the blocking oxide 20 and the charge trap material 21 may be performed on the layer stack 10. For example, as is known in the art, certain deposition processes favor deposition on hydrogen-terminated surfaces (e.g., the deposition process preferentially deposits material on hydrogen-terminated surfaces). Therefore, the treatment process may be adapted to increase the occurrence of hydrogen-terminated bonds on the gate layer 14 (thereby promoting deposition thereon) and / or reduce the occurrence of hydrogen-terminated bonds on the inter-gate spacer layer 12 (thereby inhibiting deposition thereon). However, this is merely a non-limiting example, and other techniques are known to those skilled in the art.

[0086] exist Figure 4 In the embodiment of the present invention, a second recessed region 22 is formed in the sidewall of the layer stack 10 surrounding the memory hole 4 by laterally etching back the inter-gate spacer layer 12 from the memory hole 4 relative to the lateral memory stack 19 (e.g., the charge trap material 21). The inter-gate spacer layer 12 is laterally etched back (along the X-axis) selectively to the charge trap material 21 so that the second recessed region 22 is formed between the lateral memory stacks 19. That is, each recessed region / recess in the second recessed region 22 is formed between a pair of lateral memory stacks 19. Since the sidewalls extend around the circumference of the memory hole 4, the second recessed region 22 can extend around the circumference of the memory hole 4. In the example of a circular memory hole 4, the second recessed region 22 can be annular.

[0087] The inter-gate spacer layer 12 may be etched back using an etching process adapted to selectively etch the inter-gate spacer layer 12 with respect to the charge trap material 21. That is, the etching process may be adapted to selectively etch (i.e., remove) the material (e.g., oxide material) of the inter-gate spacer layer 12 with respect to the material (e.g., SiN) of the charge trap material 21, for example so that the inter-gate spacer layer 12 may be etched back laterally without causing any substantial etching back of the charge trap material 21. The etching process may be applied to the sidewalls of the layer stack 10 via the memory hole 4. Any suitable selective etching process (such as an isotropic etching process) that provides a sufficient lateral etching component with respect to the inter-gate spacer layer 12 may be used, whether wet or dry.

[0088] Providing semiconductor layer 16 as the top layer of layer stack 10 ensures that the topmost inter-gate spacer layer 12 can also be recessed. That is, semiconductor layer 16 can act as an etch mask for the topmost inter-gate spacer layer 12 to counteract vertical etching thereof during lateral etching back.

[0089] The second recessed region 22 may be formed to have a depth (along the X-axis) to undercut at least the charge trap material 21. This allows the air gap structure 28 to be formed (see, for example, Figure 8 ) can undercut at least the charge trap material 21. The extent of the undercut can be partial or complete relative to the lateral thickness of the charge trap material. Complete undercutting can be more advantageous than partial undercutting because inter-cell interference can be more effectively reduced. Figure 4 As shown, the second recessed region 22 can be formed to have a depth to further undercut the blocking oxide 20 of the lateral memory stack 19. This enables the air gap structure 28 to also undercut the blocking oxide 20, specifically the entire lateral thickness / depth of the lateral memory stack 21. The depth of the second recessed region 22 (i.e., the amount of lateral etch back) can be, for example, in the range of 4-40 nm. The depth of the second recessed region 22 can be controlled by timing the lateral etch back.

[0090] Figure 5-6 2 shows the processing steps for forming the dummy layer 24 in the second recessed area 22. Figure 5 In the embodiment, the initial dummy layer 23 has been conformally deposited (e.g., using ALD) to fill the second recessed region 24. For example, the initial dummy layer 23 may be deposited to a certain thickness so that the initial dummy layer 24 closes or "pinches off" the second recessed region 22. Due to the conformal nature of the deposition, the initial dummy layer 23 also covers the sidewalls of the memory hole 4, such as the inner end surface including the charge trap material 21. Figure 6 , the initial dummy layer 23 has been laterally etched back (e.g., using isotropic etching) so that the inner ends of the charge trap material 21 at the sidewalls of the memory hole 4 are exposed, and the discrete dummy layer 24 remains in the second recessed region 22. As an alternative to the deposition of the initial dummy layer 23 based on conformal ALD, the initial dummy layer can also be deposited non-conformally using spin coating so that the dummy material can enter and fill the second recessed region 22. Subsequently, the spun-on initial dummy layer can be patterned (e.g., using photolithography and etching) using anisotropic etching oriented from top to bottom (opposite to the Z-axis direction) to remove the dummy material deposited on the horizontally oriented surface of the structure 1, while the dummy material within the second recessed region 22 can be masked and therefore retained to form the dummy layer 24. In any case, as Figure 6 As shown, the side walls surrounding the reservoir hole 4 may be restored to a substantially straight profile.

[0091] The dummy layer 24 defines a temporary placeholder for the air gap structure 28 to be formed later. The dummy layer 28 is formed of a dummy material selected to be convertible into the air gap structure 28 by a thermal treatment process. Example materials for the dummy layer 18 include polymer-containing materials such as tetracyclododecene (TD)-based sacrificial polymers, polycycloolefin polymers (such as polynorbornene polymers), or some other conventional heat-degradable polymers that can be deposited to fill the second recessed region 22.

[0092] Figure 7 The structure 1 is shown after lining the sidewalls of the memory hole 4 with a liner layer 26. The liner layer 26 is conformally deposited (e.g., using ALD) to cover the sidewalls of the memory hole 4 and thereby the inner end faces of the dummy layers 24. After depositing the liner layer 26, the dummy layers 24 are thus sealed from the memory hole 4. Each dummy layer 24 is more specifically surrounded / sandwiched between the liner layer 26 and the corresponding inter-gate spacer layer 12.

[0093] The liner layer 26 is deposited to a certain thickness to allow decomposed components (e.g., gas phase components) of the dummy layer 24 to leave (i.e., diffuse) through the liner layer 26, and when the dummy layer 24 is converted into the air gap structure 28 during a subsequent heat treatment process, the decomposed components of the dummy layer 24 are formed. The liner layer 26 can be formed to have a thickness in the range of 1-4nm or 1-2nm. The liner layer 26 can be a material such as LTO SiO 2 By depositing liner layer 26 at a thermal budget with sufficient margin toward the transformation temperature of the dummy material of dummy layer 24, premature transformation of dummy layer 24 can be avoided. For example, for any of the dummy material examples described above, a deposition temperature of liner layer 26 of 300° C. or less can generally provide sufficient margin.

[0094] Figure 8 The structure after converting the dummy layer 24 into the air gap structure 28 is shown. The conversion is achieved by performing a thermal treatment process on the dummy layer 24, which is adapted to convert the dummy material (e.g., polymer) of each dummy layer 24 into the air gap structure 28. Each air gap structure 28 is formed laterally between the liner layer 26 and the corresponding gate spacer layer 12. Therefore, the lateral memory stack 19 is vertically separated by the air gap structure 28. The treatment process can be performed by performing a thermal anneal (e.g., in a reaction chamber or furnace). As will be understood by those skilled in the art, the thermal energy required to achieve a sufficient conversion ratio depends on the specific dummy material of the dummy layer 24. For example, for any of the dummy material examples described above, heating the structure 1 or the environment of the structure to about 500°C is generally sufficient to completely convert the dummy layer 24 without forming any significant residue in the resulting air gap 28.

[0095] It is further contemplated that the dummy material may include components or additives (organic or inorganic) that are converted or retained during the thermal treatment process to form a low-k sparse matrix or porous air gap structure 28, such as a silicate compound such as a (low-k) organic silicate (SiOC) or a fluorinated silicate (SiOF). Thus, the air gap structure 28 is not limited to voids spanning the entire volume previously occupied by the dummy material, but may also include a low-k sparse structure surrounded by air or including pores with air. However, even in the case where a sparse structure is retained, at least a majority of the volume spanned by the air gap structure 28 will typically be filled with air.

[0096] The lateral depth or extent (along the X-axis) of the air gap structure 28 is determined by the lateral thickness or extent (along the X-axis) of the dummy layer 24, and therefore also by the lateral depth and extent of the second recessed region 22. This applies correspondingly to the extent to which the air gap structure 28 will undercut the lateral memory stack 19. In the example shown, the air gap structure 28 undercuts the lateral memory stack 19 along its entire lateral thickness, i.e., the blocking oxide 20 and the charge trapping material 21. However, by forming the second recessed structure 22 to undercut only the charge trapping material 21, the air gap structure 28 will not undercut the blocking oxide 20.

[0097] exist Fig. 9 , a tunnel oxide layer 30 is formed in the memory hole 4 along the sidewall of the memory hole 4, and then a channel layer 32 is formed. Therefore, the tunnel oxide layer 30 is formed along the liner layer 26, and the channel layer 32 is formed along the tunnel oxide layer 30. The tunnel oxide layer 30 and the channel layer 32 may be respectively conformally deposited, for example, using a corresponding ALD process.

[0098] Tunnel oxide layer 30 may be formed of any material commonly used in the industry, one non-limiting example being SiON. Channel layer 32 may similarly be formed of any suitable channel material commonly used in the industry for channel layers, typically a semiconductor material such as Si, SiGe, or Ge. Fig. 9 Not shown, channel layer 32 may exhibit extensions beyond the shown portion of structure 1 to facilitate connections to peripheral semiconductor devices and circuits (such as select transistors), as known to those skilled in the art.

[0099] If the gate layer 14 is a sacrificial gate layer, the method can be as follows Fig. 9The sacrificial gate layer 14 is replaced with a replacement metal gate stack 34 as shown. The sacrificial gate layer 14 may be removed by etching back the sacrificial gate layer 14 from a second hole (not shown) in the layer stack 10 (e.g., the memory hole 4 is represented as a front hole or opening, and the second hole may be referred to as a back hole or opening). Subsequently, the lateral cavities thus formed, which are formed at various layers in the sacrificial gate layers 14, may be filled with a replacement metal gate stack that replaces the sacrificial gate layer 14. As is known in the art, the replacement metal gate stack deposition may include depositing one or more conductive layers, such as metals, such as one or more of TiN and W. Prior to depositing the conductive layer(s), a (conformal) high-k gate dielectric may be deposited.

[0100] Provided that the lateral depth of the second recessed region 22 is such that the second recessed region 22 (completely or partially) undercuts the charge trap material 21 but does not undercut the blocking oxide 20, the air gap structure 28 may thus be sealed or closed from the gate cavity formed by removing the sacrificial gate layer 14. Thus, the risk of RMG causing metal gate stack deposition in the air gap structure 28 may be mitigated.

[0101] If the second recessed region 22 is formed to also undercut the blocking oxide 20, the air gap structure 28 may be formed during RMG before forming the dummy layer 24 by depositing another liner layer 27 of dielectric material in the second recessed region 22 before forming the dummy layer 24 (e.g., Figure 4 The first dummy layer 23 is formed by a liner layer 27 in one of the second recessed regions 21. The first dummy layer 23 is formed by a liner layer 27 in one of the second recessed regions 21. The second liner layer 27 may be conformally deposited (e.g., by ALD) with the initial dummy layer 23 and laterally etched back or patterned and thus removed from the inner end faces of the charge trap material 21. The second liner layer 27 may then be used as an etch stop layer when removing the sacrificial gate layer 14 to be replaced by a replacement metal gate stack.

[0102] Fig.10 A variation of the aforementioned process flow is shown, in which a dielectric liner layer 101 is formed in the second recessed region 22 after etching back the gate layer 14 and before depositing the blocking oxide 20. The dielectric liner 101 may be a high-k dielectric (e.g., Al 2 O 3 or HfO 2 ), wherein the liner 101 may define a gate dielectric. In addition to this function, in the case of an RMG process, when the sacrificial gate layer 14 is removed during RMG, the dielectric liner 101 may serve as an etch stop layer (e.g., together with the above-mentioned further liner layer 27), thereby masking the lateral memory stack 19 from the etching chemistry used when removing the sacrificial gate layer 14.

[0103] As with the blocking oxide 20, the dielectric liner 101 may be selectively deposited in the first recessed region 18, i.e., using a deposition process that allows for selective deposition of the liner material of the dielectric liner 101 on portions of the growth promoting or seeding surface, but not on the growth inhibiting region defined by the inter-gate spacer layer 12. The deposition of the dielectric liner 101 may be preceded by one or more treatment processes for functionalizing and / or inhibiting the gate layer 14 and the inter-gate spacer layer 12, respectively, as discussed above in connection with the selective deposition of the blocking oxide 20. Thus, the dielectric liner 101 may be deposited on the end face 14a of the etched-back gate layer 14 (see Figure 2 ), or is deposited on a deposition promoting layer 15 formed on the gate layer 14.

[0104] Fig.11 The resulting lateral memory stack 119 is shown after deposition of a blocking oxide 20 and then a charge trapping material 21 on the dielectric liner 101 .

[0105] Fig.12 A lateral memory stack 219 according to yet another variation is shown, wherein a (second) dielectric liner 102 (e.g. also a high-k dielectric) is selectively deposited on the blocking oxide 20 in the first recessed region 18 after depositing the blocking oxide 20 and before depositing the charge trap material 21. The charge trap material 21 is then selectively deposited on the dielectric liner 102. Thus, each lateral memory stack 219 comprises a lateral stack of the blocking oxide 20, the dielectric liner 102 and the charge trap material 21.

[0106] In the example method described above, the first recessed region 18 is formed before the second recessed region 22. While this may have the advantage of allowing the thermal budget for depositing the blocking oxide and charge trap material to be increased, the reverse order is also possible if the thermal budget for depositing the blocking oxide layer and the charge trap is below the conversion temperature of the dummy material.

[0107] Figure 13-16 A series of optional process steps are shown for promoting selective deposition of blocking oxide 20 and charge trap material 21. These process steps are intended to improve deposition inhibition characteristics at various layers in the inter-gate spacer layers 12, thereby increasing the areal selectivity of blocking oxide 20 and charge trap material 21.

[0108] Fig.13A structure 1″ corresponding to structure 1 is shown, wherein before forming the first recessed region 18, an initial recessed region 118 has been formed in the sidewalls of the layer stack 10 surrounding the memory hole 4 by laterally etching back the inter-gate spacer layer 12 from the memory hole 4 relative to the gate layer 14. The inter-gate spacer layer 12 is laterally etched back (along the X-axis) selectively to the gate layer 14 so that the initial recessed region 118 is formed between the gate layers 14. That is, each recessed region / recess in the initial recessed region 118 is formed between a pair of gate layers 14. Since the sidewalls extend around the circumference of the memory hole 4, the initial recessed region 118 may extend around the circumference of the memory hole 4. In the example of a circular memory hole 4, the initial recessed region 118 may be annular.

[0109] The inter-gate spacer layer 12 may be etched back using an etching process adapted to selectively etch the inter-gate spacer layer 12 with respect to the gate layer 14. That is, the etching process may be adapted to selectively etch (i.e., remove) the material (e.g., oxide material) of the inter-gate spacer layer 12 with respect to the material (e.g., nitride material) of the gate layer 14, for example so that the inter-gate spacer layer 12 may be etched back laterally without causing any substantial etching back of the gate layer 14. The etching process may be applied to the sidewalls of the layer stack 10 via the memory hole 4. Any suitable selective etching process (such as an isotropic etching process) that provides a sufficient lateral etching component with respect to the inter-gate spacer layer 12 may be used, whether wet or dry.

[0110] The initial recessed region 118 may be formed to have a thickness (along the X-axis) that matches or exceeds the expected lateral thickness of at least the charge trap material 21 of the lateral memory stack 19 to be formed at each layer in the gate layers 14, and optionally the expected lateral thickness of the complete lateral memory stack 19. The depth of the initial recessed region 118 (i.e., the amount of lateral etch back) may be, for example, in the range of 4-40 nm. The depth of the second recessed region 118 may be controlled by timing the lateral etch back.

[0111] exist Fig.14, a sacrificial layer 120 has been formed in the initial recessed area 118. As shown, the sacrificial layer 120 can be formed to fill (i.e., refill) the initial recessed area 118. The sidewalls surrounding the memory hole 4 can thus be restored to a substantially straight profile. The sacrificial layer 120 defines a temporary deposition inhibition region for blocking subsequent selective deposition of oxide and charge trap materials. The sacrificial layer 120 is thus formed of a sacrificial material selected to be deposition inhibiting for blocking subsequent selective deposition of oxide and charge trap materials. The sacrificial material can also be selected to be a material that can be selectively etched for the material of the lateral memory stack 19, so that the sacrificial layer 120 can be removed at a later stage of the method without removing the lateral memory stack 19. Examples of sacrificial layer 120 include metal oxide layers (such as Al 2 O 3 or TiO 2 layer), a metal nitride layer (such as an AlN or TiN layer), a metal layer (such as a Co, Ru, Cu, W or Mo layer), or a carbon-containing layer (such as an amorphous carbon or an organic spin-coated layer).

[0112] The sacrificial layer 120 may be formed by selectively depositing a sacrificial material using an ASD process to fill the initial recessed region 118, wherein the gate layer 14 defines a non-growth region and the inter-gate spacer layer 12 defines a growth region relative to the ASD process. The deposition of the sacrificial material may continue until the initial recessed region 118 is filled with the sacrificial material and the inner end surface of the sacrificial layer 120 is substantially flush with the inner end surface of the gate layer 14. Alternatively, forming the sacrificial layer 120 may include co-conformingly depositing a sacrificial material (e.g., by ALD) to fill the initial recessed region 118 and cover the sidewalls of the memory hole 4. The sacrificial material layer may then be etched back (e.g., using isotropic etching) so as to expose the inner end surface of the gate layer 14 at the sidewalls of the memory hole 4.

[0113] exist Fig.15 In the embodiment, the first recessed region 18 has been formed in the sidewall surrounding the memory hole 4 by etching back the gate layer 14 laterally from the memory hole 4 relative to the sacrificial layer 120. Figure 2 The discussion of the first recessed region 18 forming structure 1 applies correspondingly to structures 1″ and Fig.15, except that here the gate layer 14 can instead be etched back using an etching process adapted to selectively etch the gate layer 14 with respect to the sacrificial layer 120. That is, the etching process can be adapted to selectively etch (i.e., remove) the material (e.g., nitride material) of the gate layer 14 with respect to the sacrificial material of the sacrificial layer 120, for example so that the gate layer 14 can be etched back laterally without causing any substantial etching back of the sacrificial layer 120. The etching process can be applied to the sidewalls of the layer stack 10 via the memory hole 4. Any suitable selective etching process (such as an isotropic etching process) that provides a sufficient lateral etching component with respect to the gate layer 14 can be used, whether wet or dry.

[0114] By forming the first recessed region 18 with a smaller lateral depth than the initial recessed region 118, the inter-gate spacer layer 12 may be masked during the etch-back of the gate layer 14, for example because the inter-gate spacer layer 12 may then be masked by the sacrificial layer 120 and the (etched-back) gate layer 14. If this is not the case, the etching process used to etch the gate layer 14 may advantageously be adapted to etch the material of the gate layer 14 (e.g., nitride material) selectively to both the sacrificial material of the sacrificial layer 120 and the material of the inter-gate spacer layer 12 (e.g., oxide).

[0115] like Fig.16 As shown, the method may then continue to form a lateral memory stack 19 in each first recessed region 18 by selectively depositing a blocking oxide 20 and subsequently depositing a charge trap material 21 in the first recessed region 18. Thus, both the blocking oxide 20 and the charge trap material 21 are selectively deposited, wherein the sacrificial layer 120 defines a deposition inhibition region (non-growth region) for the selective deposition of the blocking oxide 20 and the charge trap material 21.

[0116] The blocking oxide 20 may be deposited using any deposition process (e.g., an ALD process) that allows for regional selective deposition of the blocking oxide 20 (e.g., SiO2) so that the blocking oxide 20 is deposited on a growth promoting or seeding surface portion in the first recessed region 18 (e.g., an end surface of the etched-back gate layer exposed in the first recessed region 18) but not deposited on a growth inhibiting region defined by the sacrificial layer 120. Accordingly, the charge trap material 21 may be deposited using any deposition process (e.g., an ALD process) that allows for regional selective deposition of the charge trap material 21 (e.g., SiN) so that the charge trap material 21 is deposited on a growth promoting or seeding surface portion in the first recessed region 18 (e.g., the deposited blocking oxide 20) but not deposited on a growth inhibiting region defined by the sacrificial layer 120.

[0117] The above discussion of the possibility of implementing a treatment step before depositing the blocking oxide 20 and subsequently depositing the blocking oxide 20 is correspondingly applicable to the structure 1″ and the sacrificial layer 120, the treatment step being adapted to functionalize the end surface 14a of the etched-back gate layer 14 and / or to passivate the exposed surface portion of the inter-gate spacer layer 12. Therefore, the treatment process can be adapted to increase the occurrence of hydrogen termination bonds on the gate layer 14 (thereby promoting deposition thereon) and / or reduce the occurrence of hydrogen termination bonds on the sacrificial layer 120 (thereby inhibiting deposition thereon). However, this is only a non-limiting example, and other techniques are known to those skilled in the art.

[0118] As an illustrative example, gate layer 14 may be a SiN layer and sacrificial layer 20 may be an Al 2 O 3 layer, where a plasma enhanced ALD (PEALD) process can be used to selectively deposit SiO 2 The PEALD process includes a deposition cycle of repeatedly performing the following operations: A) passivating the sacrificial layer 120 using acetylacetone, B) introducing a Si precursor bis(diethylamino)silane (BDEAS), and C) providing an O 2 Plasma as a co-reactant. Acetylacetone will lead to Al 2 O 3 The surface of the sacrificial layer 120 (but not the SiN of the gate layer 14) is transplanted to make the surface of the sacrificial layer 120 relatively inert to the Si precursor so that the SiO 2 The blocking oxide is selectively deposited in the first recessed region 18. The selective deposition of the charge trap material 21 of SiN can be achieved in a corresponding manner, namely using a PEALD process, which includes repeatedly performing A) passivation of the sacrificial layer 120, B) introduction of a Si precursor and C) providing N 2 or NH 3 Various variations of these methods are contemplated. For example, the sacrificial layer 120 may be made of a material such as TiO 2 The passivation of the sacrificial layer 120 can be achieved using an organic carboxylic acid such as pivalic acid, butyric acid, etc. Some other relatively bulky silicon precursor can be used instead of BDEAS. In addition, a thermal ALD process can be used instead of a PEALD process.

[0119] After forming the lateral memory stack 19, the method can continue to remove the sacrificial layer 120 using a selective etch that etches the sacrificial material selectively to the charge trap material 21 and the blocking oxide 20. Any suitable selective etch process, such as an isotropic etch process, whether wet or dry, that provides a sufficient lateral etch component relative to the sacrificial layer 120 can be used. By removing the sacrificial layer 120, the initial recessed area 118 can be restored or reopened.

[0120] Subsequently, the inter-gate spacer layer 12 may be regrown in the restored initial recessed region 118. The lateral memory stack 21 (including the blocking oxide 20 and the charge trap material 21) in the first recessed region 18 is thus vertically spaced apart by the regrown inter-gate spacer layer 12, which corresponds to the following example. Figure 3 The structure 1 shown. The gate spacer layer 12 may be deposited by, for example, using a conformal deposition process (such as ALD) to deposit an oxide material (eg, SiO 2 ) to re-grow. Both area-selective and non-area-selective deposition techniques are possible. For example, a selective oxide-on-oxide deposition process can be used to re-deposit oxide material on the inter-gate spacer layer 12. Using a non-area-selective deposition technique, the oxide material can be conformally deposited to fill the initial recessed region 18 and cover the sidewalls of the memory hole 4 (e.g., including the charge trap material 21), and then laterally etched back to expose the inner end surface of the charge trap material 21 at the sidewall of the memory hole 4. Then, the structure 1" can be as described in reference Figure 4 and are further processed as discussed later.

[0121] According to an example variation of the previous flow, the method may directly continue to form the dummy layer 24 in the initial recessed region 118 after removing the sacrificial layer 120, instead of regrowing the inter-gate spacer layer 12. The initial recessed region 118 in this example may accordingly define a reference Figure 4-6 A second recessed area 22 is shown and discussed.

[0122] According to yet another example variation, if the sacrificial layer 120 is formed of any of the example dummy materials of the dummy layer 18, the sacrificial layer 120 does not need to be removed after forming the lateral memory stack 19, but remains in the structure 1″ to define the dummy layers 18, which can be converted into air gap structures 28 after lining the sidewalls of the memory holes 4 with the lining layer 26. This method can be applied if the dummy material (e.g., containing a polymer) provides the desired deposition inhibition properties during the deposition of the blocking oxide 20 and the charge trap material 21.

[0123] Those skilled in the art realize that the present invention is by no means limited to the embodiments described above. On the contrary, many modifications and variations are possible within the scope of the appended claims.

Claims

1. A method for forming a memory structure of a 3D NAND flash memory, the method comprising: forming a layer stack on a substrate, the layer stack comprising an alternating sequence of gate layers and inter-gate spacer layers; forming a first recessed region in a sidewall surrounding a memory hole by laterally etching back the gate layer from the memory hole in the layer stack; forming a lateral memory stack in each first recessed region by depositing a blocking oxide and subsequently depositing a charge trapping material; forming a second recessed region in the sidewall by laterally etching back the inter-gate spacer layer from the memory hole; forming a dummy layer in the second recessed area; After forming the lateral memory stack and the dummy layer, lining the sidewalls of the memory hole with a lining layer; After lining the sidewalls, performing a thermal treatment process on the dummy layers, the thermal treatment process being adapted to convert each dummy layer into an air gap structure, wherein the air gap structure is laterally formed between the liner layer and the gate spacer layer; forming a tunneling oxide layer in the memory hole along the liner layer; as well as A channel layer is formed along the tunnel oxide layer. The method of claim 1 , wherein the dummy layer is formed of a material including a polymer.

3. The method of claim 2, wherein the treating process removes the polymer-containing material of the dummy layer from the second recessed region, wherein optionally, trace amounts of material of the dummy layer remain in the second recessed region to form the air gap structure. 4 . The method of claim 1 , wherein the liner layer is deposited at a temperature below a temperature that results in conversion of the dummy layer into the air gap structure. The method of claim 4 , wherein the liner layer is formed of a low thermal oxide. The method of claim 4 , wherein the thickness of the liner layer is in the range of 1-4 nm or 1-2 nm. 7 . The method of claim 1 , wherein the lateral depth of the second recessed region is such that the air gap structure undercuts at least the charge trap material of the lateral memory stack. 8 . The method of claim 7 , wherein the lateral depth of the second recessed region is such that the air gap structure further undercuts the blocking oxide of the lateral memory stack.

9. The method of claim 1, wherein the gate layer is a sacrificial gate layer, and the method further comprises, after forming the air gap structure, replacing the sacrificial gate layer with a replacement metal gate stack.

10. The method of claim 9, wherein a lateral depth of the second recessed region is such that the air gap structure undercuts the charge trap material of the lateral memory stack but does not undercut the blocking oxide of the lateral memory stack.

11. The method of claim 11, wherein the method further comprises depositing another liner layer of a dielectric material in the second recessed area before forming the dummy layer, wherein the another liner layer is used as an etch stop layer when the sacrificial gate layer is replaced with the replacement metal gate stack.

12. The method of claim 1, further comprising, before forming the first recessed region: forming an initial recessed region in the sidewall surrounding the memory hole by laterally etching back the inter-gate spacer layer from the memory hole; as well as forming a sacrificial layer in the initial recessed region; wherein the first recessed region is formed after forming the sacrificial layer, and wherein the lateral memory stack is formed by depositing the blocking oxide in the first recessed region and then depositing the charge trap material, wherein the sacrificial layer defines a deposition inhibition region for selective deposition of the blocking oxide and the charge trap material.

13. The method according to claim 12, wherein the initial recessed region is a second recessed region, and the method further comprises, after forming the lateral memory stack, removing the sacrificial layer from the second recessed region by etching from the memory hole and thereafter forming the dummy layer in the second recessed region; or The method further comprises, after forming the lateral memory stack: removing the sacrificial layer by etching from the memory hole; after removing the sacrificial layer, regrowing the inter-gate spacer layer such that the lateral memory stacks are vertically spaced apart by the regrown inter-gate spacer layer; And wherein after regrowing the inter-gate spacer layer, the method continues to form the second recessed region by laterally etching back the regrown inter-gate spacer layer.

14. The method of claim 13, wherein the sacrificial layer is a metal oxide layer such as an Al2O3 or TiO2 layer, a metal nitride layer such as an AlN or TiN layer, a metal layer such as a Co, Ru, Cu, W or Mo layer, or a carbon-containing layer such as an amorphous carbon or organic spin-coated layer. 15 . The method of claim 12 , wherein the initial recessed region and the second recessed region and the sacrificial layer are the dummy layer.

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