Memory device and method of manufacturing the same

Abstract

The invention relates to a memory device and a manufacturing method thereof. The memory device includes: a discharge contact; a source pattern surrounding a periphery of the discharge contact and floating; and a source line surrounding a periphery of the source pattern and to which a source voltage is applied. The memory device further includes a separation pattern electrically isolating the source pattern and the source line; a main support pattern on the source pattern; a sub-support pattern on the source line; and a contact on the discharge contact.

Description

Technical Field

[0001] The present disclosure relates to a memory device and a method of manufacturing the same, and more particularly, to a memory device including a discharge contact and a method of manufacturing the same. Background Art

[0002] The memory device may include a memory cell array in which data is stored, a peripheral circuit configured to perform a program operation, a read operation, or an erase operation of the memory cell array, and a control circuit configured to control the peripheral circuit.

[0003] The memory cell array may include a plurality of memory blocks. When the memory blocks are formed in a three-dimensional structure, the memory blocks may be distinguished from each other by slit regions.

[0004] A memory block formed in a three-dimensional structure may include a stacked structure stacked in a vertical direction from a substrate. The stacked structure may include a plurality of gate lines and a plurality of insulating layers stacked alternately. The memory block may be divided into a cell region including a memory cell and a connection region including a contact. For example, in a structure in which a memory cell array is stacked on a peripheral circuit, the peripheral circuit and the memory cell array may be electrically connected through a contact included in the connection region.

[0005] A discharge contact for removing dummy ions that may occur during the manufacturing process of the memory device may be located in the connection area. The source line may be located around the discharge contact. The discharge contact may be formed of a conductive material to discharge the dummy ions. Therefore, the discharge contact needs to be spaced apart from the source line.

[0006] When the distance between the source line and the discharge contact is much smaller than the reference distance, a bridge may occur between the source line and the discharge contact during the manufacturing steps of the memory device. When the distance between the source line and the discharge contact is much larger than the reference distance, the size of the memory device increases. Summary of the invention

[0007] According to one embodiment of the present disclosure, a memory device includes: a discharge contact; a source pattern that surrounds the periphery of the discharge contact and floats; a source line that surrounds the periphery of the source pattern and is applied with a source voltage; a separation pattern that electrically isolates the source pattern and the source line; a main support pattern that is located on the source pattern; a sub-support pattern that is located on the source line; and a contact that is located on the discharge contact.

[0008] According to one embodiment of the present disclosure, a memory device includes: an opening area insulating layer extending along a first direction; a discharge contact included in the opening area insulating layer; a source pattern surrounding an outer surface of the opening area insulating layer; a separation pattern surrounding an outer surface of the source pattern; and a source line surrounding an outer surface of the separation pattern.

[0009] According to an embodiment of the present disclosure, a method for manufacturing a memory device may include: stacking a source layer on a lower structure; separating the source layer into a source pattern and a preliminary pattern; forming a separation pattern between the source pattern and the preliminary pattern; forming a discharge contact in contact with the lower structure in a region spaced apart from the source pattern; forming a main support pattern on the source pattern and a sub-support pattern on the preliminary pattern; and forming the preliminary pattern into a source line. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a diagram illustrating a memory device.

[0011] Figure 2 is a schematic diagram illustrating a peripheral circuit and a memory cell array.

[0012] Figure 3 is a layout illustrating the arrangement of a discharge contact and a support pattern according to an embodiment of the present disclosure.

[0013] Figure 4 exemplifies a layout of a discharge contact, a source pattern, and a source line according to an embodiment of the present disclosure.

[0014] Figure 5 is a cross-sectional view illustrating a memory device according to an embodiment of the present disclosure.

[0015] FIG. 6A to FIG. 6O is a diagram illustrating a method of manufacturing a memory device according to an embodiment of the present disclosure.

[0016] Figure 7 is a diagram illustrating a memory card system to which the memory device of the present disclosure is applied.

[0017] Figure 8 is a diagram illustrating a solid state drive (SSD) system to which the memory device of the present disclosure is applied. DETAILED DESCRIPTION

[0018] The specific structural or functional description disclosed below is illustrative to describe the embodiments according to the concept of the present disclosure. The embodiments according to the concept of the present disclosure should not be interpreted as being limited to the embodiments described below, and various modifications may be made and replaced with other equivalent embodiments.

[0019] Hereinafter, terms such as first and second may be used to describe various components, but the components are not limited by the terms. These terms are used to distinguish one component from another component, and do not imply the number or order of the components.

[0020] Embodiments of the present disclosure provide a memory device capable of preventing a discharge contact from being reduced in size and ensuring a margin between a source line and a discharge contact, and a method for manufacturing the memory device. The present technology can reduce the resistance of the discharge contact by preventing a discharge contact from being reduced in size. The present technology can prevent a bridge from occurring between the source line and the discharge contact by ensuring a margin between the source line and the discharge contact.

[0021] Figure 1 is a diagram illustrating a memory device.

[0022] Reference Figure 1 , the memory device 100 may include a memory cell array 110 and a peripheral circuit 180 .

[0023] The memory cell array 110 may include first to j-th memory blocks BLK1 to BLKj. Each of the first to j-th memory blocks BLK1 to BLKj may include a memory cell capable of storing data. A drain select line DSL, a word line WL, a source select line SSL, and a source line SL may be connected to each of the first to j-th memory blocks BLK1 to BLKj, and a bit line BL may be commonly connected to the first to j-th memory blocks BLK1 to BLKj.

[0024] The first to j-th memory blocks BLK1 to BLKj may be formed in a three-dimensional structure. The memory block having the three-dimensional structure may include memory cells stacked on a substrate in a vertical direction.

[0025] According to the programming method, the memory cell can store 1 bit or 2 bits or more bits of data. For example, the method of storing 1 bit of data in one memory cell is called a single-level cell method, and the method of storing 2 bits of data in one memory cell is called a multi-level cell method. The method of storing 3 bits of data in one memory cell is called a three-level cell method, and the method of storing 4 bits of data in one memory cell is called a four-level cell method. In addition, 5 bits or more of data can be stored in one memory cell.

[0026] The peripheral circuit 180 may be configured to perform a program operation of storing data in the memory cell array 110, a read operation of outputting data stored in the memory cell array 110, and an erase operation of erasing data stored in the memory cell array 110. For example, the peripheral circuit 180 may include a voltage generator 120, a row decoder 130, a page buffer group 140, a column decoder 150, an input / output circuit 160, and a control circuit 170.

[0027] The voltage generator 120 may generate various operation voltages Vop for a programming operation, a reading operation, or an erasing operation in response to the operation code OPCD. For example, the voltage generator 120 may be configured to generate a programming voltage, a turn-on voltage, a turn-off voltage, a negative voltage, a precharge voltage, a verification voltage, a read voltage, a pass voltage, or an erase voltage in response to the operation code OPCD. The operation voltage Vop generated by the voltage generator 120 may be applied to the drain selection line DSL, the word line WL, the source selection line SSL, and the source line SL of the memory block selected by the row decoder 130.

[0028] The programming voltage may be a voltage applied to a selected word line among word lines WL during a programming operation, and may be used to increase the threshold voltage of a memory cell connected to the selected word line. A turn-on voltage may be applied to a drain select line DSL or a source select line SSL, and may be used to turn on a drain select transistor or a source select transistor. A cut-off voltage may be applied to a drain select line DSL or a source select line SSL, and may be used to turn off a drain select transistor or a source select transistor. For example, the cut-off voltage may be set to 0V. A precharge voltage may be a voltage higher than 0V, and may be applied to a bit line during a read operation. A verification voltage may be used during a verification operation for determining whether the threshold voltage of a selected memory cell has increased to a target level. The verification voltage may be set to various levels according to the target level, and may be applied to a selected word line.

[0029] During a read operation of a selected memory cell, a read voltage may be applied to the selected word line. For example, the read voltage may be set to various levels according to a programming method of the selected memory cell. The pass voltage may be a voltage applied to an unselected word line among word lines WL during a programming or read operation, and may be used to turn on a memory cell connected to the unselected word line.

[0030] During an erase operation for erasing memory cells included in a selected memory block, an erase voltage may be used and applied to the source line SL.

[0031] The row decoder 130 may be configured to transmit an operation voltage Vop to a drain select line DSL, a word line WL, a source select line SSL, and a source line SL connected to a selected memory block according to a row address RADD. For example, the row decoder 130 may be connected to the voltage generator 120 through a global line, and may be connected to the first memory block BLK1 to the j-th memory block BLKj through the drain select line DSL, the word line WL, the source select line SSL, and the source line SL.

[0032] The page buffer group 140 may include page buffers PB1 to PBn (not shown) connected to the first to j-th memory blocks BLK1 to BLKj. Each page buffer (not shown) may be connected to the first to j-th memory blocks BLK1 to BLKj through a bit line BL. During a read operation, the page buffer (not shown) may sense a current or voltage of a bit line that varies according to a threshold voltage of a selected memory cell in response to a page buffer control signal PBSIG and temporarily store the sensed data.

[0033] The column decoder 150 may be configured so that data is transmitted between the page buffer group 140 and the input / output circuit 160 in response to the column address CADD. For example, the column decoder 150 may be connected to the page buffer group 140 through the column line CL, and an enable signal may be transmitted through the column line CL. A page buffer (not shown) included in the page buffer group 140 may receive or output data through the data line DL in response to the enable signal.

[0034] The input / output circuit 160 may be configured to receive or output a command CMD, an address ADD, or data through an input / output line I / O. For example, the input / output circuit 160 may transmit a command CMD and an address ADD received from an external controller through the input / output line I / O to the control circuit 170, and transmit data received from the external controller through the input / output line I / O to the page buffer group 140. Alternatively, the input / output circuit 160 may output data received from the page buffer group 140 to the external controller through the input / output line I / O.

[0035] The control circuit 170 may output an operation code OPCD, a row address RADD, a page buffer control signal PBSIG, and a column address CADD in response to a command CMD and an address ADD. For example, when the command CMD input to the control circuit 170 is a command corresponding to a programming operation, the control circuit 170 may control the peripheral circuit 180 to perform a programming operation of a storage block selected by the address ADD. When the command CMD input to the control circuit 170 is a command corresponding to a read operation, the control circuit 170 may control the peripheral circuit 180 to perform a read operation of a storage block selected by the address and output read data. When the command CMD input to the control circuit 170 is a command corresponding to an erase operation, the control circuit 170 may control the peripheral circuit 180 to perform an erase operation of the selected storage block.

[0036] Figure 2 is a diagram illustrating a peripheral circuit and a memory cell array.

[0037] Reference Figure 2 , the memory cell array 110 may be located on the peripheral circuit 180. For example, the peripheral circuit 180 may be located on one substrate, and the memory cell array 110 may be located on the peripheral circuit 180. Alternatively, the peripheral circuit 180 and the memory cell array 110 may be formed on different substrates and then contact each other.

[0038] The memory cell array 110 may include first to j-th memory blocks BLK1 to BLKj. The first to j-th memory blocks BLK1 to BLKj may be arranged to be spaced apart from each other along the Y direction. The first to j-th memory blocks BLK1 to BLKj may be constructed to be identical to each other and may be distinguished from each other by slit regions 1SR, 2SR, 3SR, ... Each of the slit regions 1SR, 2SR, 3SR, ... may extend along the X direction. For example, the first memory block BLK1 may be located between the first slit region 1SR and the second slit region 2SR, and the second memory block BLK2 may be located between the second slit region 2SR and the third slit region 3SR. The first memory block BLK1 and the second memory block BLK2 may be separated from each other by the second slit region 2SR.

[0039] Each of the first storage block BLK1 to the j-th storage block BLKj may include a cell region CE and a connection region CN. A memory cell configured to store data may be located in the cell region CE, and a plurality of connection structures connected to the peripheral circuit 180 may be located in the connection region CN. For example, the connection structure may include a contact, a line, a support pattern, and a discharge contact. The contact may be configured to contact a gate line extending from the cell region CE or to contact the peripheral circuit 180 located below the memory cell array 110. The line may be configured to be electrically connected to the contact. The support pattern may be configured to support a stacked structure located in the connection region CN. The discharge contact may be configured to discharge dummy ions that may occur during the manufacturing process of the memory device to the ground terminal. For example, dummy ions may mainly occur during the etching process. When dummy ions remain in a local area of ​​the memory device, during the programming operation, read operation, or erase operation of the memory device, the reliability of the operation may be reduced due to the dummy ions. Therefore, the discharge contact may discharge dummy ions that may occur during the manufacturing process of the memory device through the ground terminal.

[0040] Figure 3 is a layout illustrating the arrangement of a discharge contact and a support pattern according to an embodiment of the present disclosure.

[0041] Reference Figure 3 , showing Figure 2 1 and 2 show a layout of a first memory block BLK1 among first to j-th memory blocks BLKj.

[0042] The first memory block BLK1 may be located between the first slit structure 1SLT and the second slit structure 2SLT. The first slit structure 1SLT may be formed in the first slit region 1SR, and the second slit structure 2SLT may be formed in the second slit region 2SR. The first slit structure 1SLT and the second slit structure 2SLT may be formed of an insulating material or a conductive material, or may be formed of an insulating material and a conductive material.

[0043] The first memory block BLK1 may be divided into a cell region CE and a connection region CN.

[0044] The cell plug CP including the memory cell may be located between the first slit structure 1SLT and the second slit structure 2SLT of the cell region CE. Each cell plug CP may include a core column CR, a channel layer CH, and a memory layer ML that construct a memory cell or a selection transistor. The memory layer ML may include a tunnel insulating layer TX, a charge trapping layer CTL, and a barrier layer BX. The core column CR may have a cylindrical shape and may be formed of an insulating material or a conductive material. The channel layer CH may have a cylindrical shape surrounding the side surface of the core column CR and may be formed of polysilicon. The tunnel insulating layer TX may have a cylindrical shape surrounding the side surface of the channel layer CH and may be formed of an oxide layer. The charge trapping layer CTL may have a cylindrical shape surrounding the side surface of the tunnel insulating layer TX and may be formed of a nitride layer. The barrier layer BX may have a cylindrical shape surrounding the side surface of the charge trapping layer CTL and may be formed of an oxide layer. Assuming that the first and second slit structures 1SLT and 2SLT extend in the X direction and are spaced apart from each other in the Y direction, the cell plugs CP may be disposed to be spaced apart from each other in the X direction and the Y direction.

[0045] The first sub-support pattern 1SSP and the second sub-support pattern 2SSP, the first auxiliary support pattern 1ASP to the third auxiliary support pattern 3ASP, the separation pattern DP, the main support pattern MSP, the discharge contact DCC and the contact CT may be located between the first slit structure 1SLT and the second slit structure 2SLT of the connection area CN. The first sub-support pattern 1SSP and the second sub-support pattern 2SSP, the first auxiliary support pattern 1ASP to the third auxiliary support pattern 3ASP and the main support pattern MSP may be constructed as a stacked structure supporting the storage block, and may be formed of an insulating material. For example, the insulating material may be an oxide material, more specifically, a silicon oxide material. The first sub-support pattern 1SSP and the second sub-support pattern 2SSP may be located between the first slit structure 1SLT and the second slit structure 2SLT, and may be spaced apart from the first slit structure 1SLT and the second slit structure 2SLT. The first sub-support pattern 1SSP may be spaced apart from each other along the X direction in the region adjacent to the first slit structure 1SLT. The second sub-support pattern 2SSP may be spaced apart from each other along the X direction in the region adjacent to the second slit structure 2SLT.

[0046] The first auxiliary support pattern 1ASP and the second auxiliary support pattern 2ASP may be located in a region near the cell region CE between the first sub-support pattern 1SSP and the second sub-support pattern 2SSP. The first auxiliary support pattern 1ASP may be arranged along the X direction, and the second auxiliary support pattern 2ASP may also be arranged along the X direction. The third auxiliary support pattern 3ASP may be formed in a line shape extending along the X direction between the first auxiliary support pattern 1ASP and the second auxiliary support pattern 2ASP.

[0047] The first sub-support pattern 1SSP and the second sub-support pattern 2SSP and the first auxiliary support pattern 1ASP and the second auxiliary support pattern 2ASP may be formed into an island shape spaced apart from each other. For example, the plane of each of the first sub-support pattern 1SSP and the second sub-support pattern 2SSP and the first auxiliary support pattern 1ASP and the second auxiliary support pattern 2ASP may be a quadrilateral shape or a circular shape, and may have a shape in which a portion protrudes. For example, assuming that the axis extending along the X direction between the first slit structure 1SLT and the second slit structure 2SLT is the central axis Ac, the protrusion of each of the first sub-support pattern 1SSP and the second sub-support pattern 2SSP and the first auxiliary support pattern 1ASP and the second auxiliary support pattern 2ASP may protrude in the direction toward the central axis Ac as shown in the figure.

[0048] The main support pattern MSP may be located between the first sub-support pattern 1SSP and the second sub-support pattern 2SSP. The main support pattern MSP may be formed in a line shape connected to each other. For example, the main support pattern MSP may include patterns 31 and 32 extending in the X direction and arranged in parallel, and a pattern 33 connecting the parallel patterns 31 and 32 in the Y direction. The pattern 33 is located in an area adjacent to the third auxiliary support pattern 3ASP and does not contact the third auxiliary support pattern 3ASP. A protrusion for improving the support function may be included in the portion extending in the ±Y direction in the patterns 31 and 32.

[0049] The contact CT and the discharge contact DCC may be located in an area surrounded by the main support pattern MSP. The contact CT and the discharge contact DCC may be formed of a conductive material. The contact CT may be stacked in the Z direction from the discharge contact DCC. Therefore, in a plan view, the contact CT overlaps with the discharge contact DCC. The contact CT may electrically connect structures spaced apart from each other in the Z direction. Although not shown in the figure, in addition to the area surrounded by the main support pattern MSP, the contact CT may also be located in an area adjacent to the first sub-support pattern 1SSP or the second sub-support pattern 2SSP.

[0050] The discharge contact DCC is a structure for removing dummy ions that may appear during the manufacturing process of the memory device through a ground terminal. Dummy ions may mainly appear during the dry etching process. For example, the dry etching process may be mainly performed in a reactive ion etching (RIE) method or a method applying the RIE method. Plasma is used in the etching process of the RIE method or the method applying the RIE method. The positive ions generated by the plasma may collide with the etching target layer, thereby weakening the binding force of the surface of the etching target layer. The molecules of the weakened binding force in the etching target layer may be discharged to the outside of the chamber together with the free radicals. At this time, some positive ions may remain in the etching target layer. The positive ions left may become dummy ions and may affect the operation of the memory device after the manufacturing of the memory device is completed. Therefore, the discharge contact DCC may be located in the region where the dummy ions are left and may be electrically connected to the ground terminal. The dummy ions may be discharged through the discharge contact DCC and the ground terminal and may be removed from the memory device.

[0051] The separation pattern DP may be formed around the main support pattern MSP. The separation pattern DP is a structure for separating the source lines located in the connection region CN. Therefore, the separation pattern DP may be formed of an insulating material. For example, the insulating material configuring the separation pattern DP may be an oxide material, specifically, a silicon oxide material. The separation pattern DP may be a pattern for dividing a local source line adjacent to the discharge contact DCC among the source lines extending in the cell region CE and the connection region CN into a source pattern. Figure 4 The source lines and source patterns divided by the separation pattern DP are described in detail.

[0052] Figure 4 exemplifies a layout of a discharge contact, a source pattern, and a source line according to an embodiment of the present disclosure.

[0053] Reference Figure 4 , the cell region CE and the connection region CN may be divided into a first region 1R, an open contact region OFC, and a second region 2R along the Y direction. The open contact region OFC may be located between the first region 1R and the second region 2R.

[0054] The source line SL may be a conductive material and may extend from the cell region CE to the connection region CN. The source line SL of the cell region CE may be electrically connected to the cell plug CP, and the source line SL of the connection region CN may contact the first and second sub-support patterns 1SSP and 2SSP and the first to third auxiliary support patterns 1ASP to 3ASP. Because the first and second sub-support patterns 1SSP and 2SSP and the first to third auxiliary support patterns 1ASP to 3ASP located in the connection region CN are formed of an insulating material, the first and second sub-support patterns 1SSP and 2SSP and the first to third auxiliary support patterns 1ASP to 3ASP located in the connection region CN may not electrically contact the source line SL. In the connection region CN, the source line SL may be located outside the separation pattern DP.

[0055] The source pattern Sp may be located in an area surrounded by the separation pattern DP. The source pattern Sp may be separated from the source line SL by the separation pattern DP. For example, the source pattern Sp may be located in the open contact region OFC. The source line SL and the source pattern Sp may be symmetrical with each other about the central axis Ac. Since the separation pattern DP is formed of an insulating material, the source pattern Sp and the source line SL may be electrically isolated from each other. The source line SL may be electrically connected to a cell plug CP located in the cell region CE, and a source voltage generated by a voltage generator may be transmitted to the cell plug CP.

[0056] The source pattern Sp may be located between the separation pattern DP and the discharge contact DCC and may be electrically floating. The source pattern Sp contacts the separation pattern DP and is spaced apart from the discharge contact DCC. Therefore, an insulating material may be filled between the source pattern Sp and the discharge contact DCC. During the manufacturing process of the main support pattern MSP, the source pattern Sp may be used as an etching stop layer. Even if a bridge occurs between the source pattern Sp and the discharge contact DCC, the discharge contact DCC and the source line SL are not electrically connected because the source pattern Sp and the source line SL are electrically isolated from each other by the separation pattern DP. Therefore, because the distance between the discharge contact DCC and the source pattern Sp may be reduced, the size of each discharge contact DCC may be increased, or the size of the memory device may be reduced.

[0057] Refer to the following Figure 3 or Figure 4 The cross-sectional view cut along the A1-A2 direction specifically describes the structure of the connection area.

[0058] Figure 5 is a cross-sectional view illustrating a memory device according to an embodiment of the present disclosure.

[0059] Reference Figure 5 , the source line SL and the upper structure TST may be located on the lower structure LST. The lower structure LST may include a substrate SUB and peripheral circuit structures pCT, pMN, and DCC.

[0060] The substrate SUB may be a silicon substrate and may include a ground terminal GTN. The ground terminal GTN may be a junction into which impurities are injected in the substrate SUB, or may be a line formed of a conductive material. A ground voltage may be supplied to the ground terminal GTN. The peripheral circuit structures pCT, pMN, and DCC may include a peripheral contact pCT, a peripheral line pMN, and a discharge contact DCC. The peripheral insulating layer pIS may be filled around the peripheral contact pCT, the peripheral line pMN, and the discharge contact DCC. The peripheral contact pCT may be located on the ground terminal GTN and may be formed of a conductive material. The peripheral line pMN may be located on the peripheral contact pCT and may be formed of a conductive material. The peripheral line pMN may have a width wider than that of the peripheral contact pCT.

[0061] The discharge contact DCC may be located on the peripheral line pMN and may be formed of a conductive material. Therefore, the discharge contact DCC may be electrically connected to the peripheral line pMN, the peripheral contact pCT, and the ground terminal GTN. The discharge contact DCC may be configured to discharge dummy ions that may occur during the manufacturing process of the memory device through the ground terminal GTN. Dummy ions may mainly appear during the dry etching process. For example, the dry etching process may be mainly performed in an RIE method or a method applying the RIE method. Plasma is used in the etching process of the RIE method or the method applying the RIE method. The positive ions generated by the plasma may collide with the etching target layer, thereby weakening the bonding force of the surface of the etching target layer. The molecules of the part with weakened bonding force in the etching target layer may be discharged to the outside of the chamber together with the free radicals. At this time, some positive ions may remain around the etching target layer 51. The positive ions left behind may become dummy ions and may affect the operation of the memory device after the manufacturing of the memory device is completed. Therefore, the discharge contact DCC may be located in the region where the dummy ions remain, and the dummy ions may be discharged through the discharge contact DCC, the peripheral line pMN, the peripheral contact pCT, and the ground terminal GTN, and the dummy ions may be removed from the memory device.

[0062] The source line SL may include a first source layer SL1 to a third source layer SL3, a sacrificial layer SC, and a first buffer layer BF1 and a second buffer layer BF2. The first source layer SL1 to the third source layer SL3 may be located in the first region 1R and the second region 2R, and the first source layer SL1 and the second source layer SL2, the sacrificial layer SC, and the first buffer layer BF1 and the second buffer layer BF2 may be located in the open contact region OFC. The first region 1R and the second region 2R may be divided along the Y direction around the central axis Ac of the A1-A2 cross section. For example, a portion of the region to the left of the central axis Ac may be defined as the first region 1R, and a portion of the region to the right of the central axis Ac may be defined as the second region 2R. The open contact region OFC may be defined as the region between the first region 1R and the second region 2R. For example, the open contact region OFC may be defined by a first separation pattern aDP and a second separation pattern bDP. The first separation pattern aDP may distinguish the first region 1R from the open contact region OFC, and the second separation pattern bDP may distinguish the second region 2R from the open contact region OFC.

[0063] The first separation pattern aDP and the second separation pattern bDP may be formed of an insulating material. Therefore, the first source layer SL1 and the second source layer SL2 included in the open contact region OFC may be electrically isolated from the first source layer SL1 and the second source layer SL2 included in the first region 1R and the second region 2R. During a programming operation, a read operation, or an erase operation of the memory device, a source voltage may be applied to the first source layer SL1 to the third source layer SL3 included in the first region 1R and the second region 2R, and the first source layer SL1 and the second source layer SL2 included in the open contact region OFC may be floated. The first buffer layer BF1 and the second buffer layer BF2 and the sacrificial layer SC may be located between the first source layer SL1 and the second source layer SL2 of the open contact region OFC. For example, the first buffer layer BF1 may be located on the first source layer SL1, the sacrificial layer SC may be located on the first buffer layer BF1, the second buffer layer BF2 may be located on the sacrificial layer SC, and the second source layer SL2 may be located on the second buffer layer BF2. The first source layer SL1 and the second source layer SL2, the first buffer layer BF1 and the second buffer layer BF2, and the sacrificial layer SC located on the left side of the central axis Ac may become the first source pattern aSp. The first source layer SL1 and the second source layer SL2, the first buffer layer BF1 and the second buffer layer BF2, and the sacrificial layer SC located on the right side of the central axis Ac may become the second source pattern bSp. The first source pattern aSp may be located between the first separation pattern aDP and the opening area insulating layer OSI, and the second source pattern bSp may be located between the second separation pattern bDP and the opening area insulating layer OSI.

[0064] The opening region insulating layer OSI may be formed between the first source pattern aSp and the second source pattern bSp, and a discharge contact DCC passing through the center of the opening region insulating layer OSI may be positioned. The discharge contact DCC may protrude into the lower structure LST by passing through the opening region insulating layer OSI, and the protruding portion may contact the peripheral line pMN of the lower structure LST.

[0065] The upper structure TST located on the source line SL may include first to third material layers MT1 to MT3, first and second slit structures 1SLT and 2SLT, a slit insulating layer SIS, first and second sub-support patterns 1SSP and 2SSP, first and second main support patterns aMSP and bMSP, and a contact CT.

[0066] The first material layer MT1 and the third material layer MT3 may be alternately stacked in the first region 1R and the second region 2R, and the first material layer MT1 and the second material layer MT2 may be alternately stacked in the open contact region OFC. A portion of the first material layer MT1 and the third material layer MT3 of the first region 1R and the second region 2R may extend into the open contact region OFC.

[0067] The first slit structure 1SLT may protrude into the source line SL by passing through the first material layer MT1 and the third material layer MT3 of the first region 1R, and the second slit structure 2SLT may protrude into the source line SL by passing through the first material layer MT1 and the third material layer MT3 of the second region 2R. The first slit structure 1SLT and the second slit structure 2SLT protruding into the source line SL may contact the source line SL. The first slit structure 1SLT and the second slit structure 2SLT may be formed of a conductive material or an insulating material. A slit insulating layer SIS may also be formed around the side surfaces of the first slit structure 1SLT and the second slit structure 2SLT. The slit insulating layer SIS may be an oxide layer. For example, the slit insulating layer SIS may be a silicon oxide layer.

[0068] The first main support pattern aMSP may be located between the second material layer MT2 and the third material layer MT3 in the open contact region OFC, and the second main support pattern bMSP may be located between the second material layer MT2 and the third material layer MT3 in the open contact region OFC. For example, the first main support pattern aMSP may contact the first source pattern aSp by passing through the first material layer MT1 to the third material layer MT3, and the second main support pattern bMSP may contact the second source pattern bSp by passing through the first material layer MT1 to the third material layer MT3. The first main support pattern aMSP and the second main support pattern bMSP may be formed of an insulating material.

[0069] The contact CT may contact the discharge contact DCC by passing through the first material layer MT1 and the second material layer MT2 of the open contact region OFC. The contact CT may be formed of a conductive material. Therefore, the contact CT, the discharge contact DCC, the peripheral line pMN, the peripheral contact pCT and the ground terminal GTN positioned along the central axis Ac may be electrically connected to each other.

[0070] FIG. 6A to FIG. 6O is a diagram illustrating a method of manufacturing a memory device according to an embodiment of the present disclosure.

[0071] Reference Fig. 6A The ground terminal GTN may be formed on a substrate SUB on which an open contact region OFC is defined. The open contact region OFC may be used for electrically connecting Figure 5 The region where the upper structure TST and the lower structure LST are located may be located between the first region 1R and the second region 2R. The ground terminal GTN may be formed by doping the substrate SUB with impurities, or may be formed by forming a groove in the substrate SUB and filling the groove with a conductive material. The ground terminal GTN may be connected to a terminal that provides a ground voltage.

[0072] A peripheral contact pCT, a peripheral wire pMN, and a peripheral insulating layer pIS may be formed on a substrate SUB. The peripheral contact pCT may be located on a ground terminal GTN, and the peripheral wire pMN may be located on the peripheral contact pCT. The peripheral contact pCT may have a width narrower than that of the ground terminal GTN, and the peripheral wire pMN may have a width wider than that of the peripheral contact pCT. The peripheral contact pCT and the peripheral wire pMN may be formed of a conductive material. The peripheral insulating layer pIS may be formed of an oxide layer covering the peripheral contact pCT and the peripheral wire pMN. Although not shown in the figure, the lower structure LST may also include Figure 1 The structure included in the peripheral circuit 180.

[0073] The first source layer SL1, the first buffer layer BF1, the sacrificial layer SC, the second buffer layer BF2, and the second source layer SL2 may be sequentially stacked on the lower structure LST. The first source layer SL1 and the second source layer SL2 may be formed of a conductive layer, and the first buffer layer BF1 and the second buffer layer BF2 may be formed of an insulating layer. For example, the first source layer SL1 and the second source layer SL2 may be formed of a conductive layer such as polysilicon, tungsten, or nickel, and the first buffer layer BF1 and the second buffer layer BF2 may be formed of an oxide layer such as a silicon oxide layer. The sacrificial layer SC may be formed of the same material as the first source layer SL1 and the second source layer SL2, or may be formed of a material having an etching selectivity different from that of the first buffer layer BF1 and the second buffer layer BF2. For example, the sacrificial layer SC may be formed of a material having an etching selectivity higher than that of the first buffer layer BF1 and the second buffer layer BF2 during a wet etching process. The sacrificial layer SC may have a thickness thinner than that of the first source layer SL1, and the second source layer SL2 may have a thickness thinner than that of the sacrificial layer SC. The first and second buffer layers BF1 and BF2 may have the same thickness or may have a thickness thinner than that of the second source layer SL2.

[0074] Reference Figure 6B , the first separation opening aOPd and the second separation opening bOPd may be formed in the boundary region between the opening contact region OFC and the first region 1R and the second region 2R, and an etching process for forming the central opening OPc in the opening contact region OFC may be performed. For example, the first separation opening aOPd exposing a portion of the peripheral insulating layer pIS may be formed by performing an etching process for removing a portion of the second source layer SL2, the second buffer layer BF2, the sacrificial layer SC, the first buffer layer BF1, and the first source layer SL1 located in the boundary region between the opening contact region OFC and the first region 1R. The second separation opening bOPd exposing a portion of the peripheral insulating layer pIS may be formed by performing an etching process for removing a portion of the second source layer SL2, the second buffer layer BF2, the sacrificial layer SC, the first buffer layer BF1, and the first source layer SL1 located in the boundary region between the opening contact region OFC and the second region 2R. The etching processes for forming the first separation opening aOPd and the second separation opening bOPd may be performed simultaneously. In the cross-sectional view cut along A1-A2, the first separation opening aOPd and the second separation opening bOPd are spaced apart from each other based on the central axis Ac. Figure 4 According to the described layout, the first separation opening aOPd and the second separation opening bOPd extend to each other between the region where the third subsidiary support patterns 3ASP are to be formed and the region where the main support patterns MSP are to be formed.

[0075] The central opening OPc may be formed by an etching process that removes a portion of the second source layer SL2, the second buffer layer BF2, the sacrificial layer SC, the first buffer layer BF1, and the first source layer SL1 located in the opening contact region OFC. The etching process for forming the central opening OPc may be performed simultaneously with the etching process for forming the first separation opening aOPd and the second separation opening bOPd, but due to the different widths between the central opening OPc and the first separation opening aOPd and the second separation opening bOPd, the two etching processes may be performed at different times to improve the reliability of the photolithography process. For example, assuming that the upper width of the central opening OPc is the first width 1W, the upper width of each of the first separation opening aOPd and the second separation opening bOPd may have a second width 2W that is narrower than the first width 1W. When there is a difference in the widths of openings adjacent to each other, since deformation may occur in the pattern during the photolithography process or dry etching process for forming the mask pattern, the etching process for forming the first separation opening aOPd and the second separation opening bOPd may be performed after the etching process for forming the central opening OPc, or the etching process for forming the first separation opening aOPd and the second separation opening bOPd may be performed after the etching process for forming the central opening OPc.

[0076] The first source layer SL1 and the second source layer SL2, the sacrificial layer SC, and the first buffer layer BF1 and the second buffer layer BF2 remaining between the central opening OPc and the first separation opening aOPd may become a first source pattern aSp, and the first source layer SL1 and the second source layer SL2, the sacrificial layer SC, and the first buffer layer BF1 and the second buffer layer BF2 remaining between the central opening OPc and the second separation opening bOPd may become a second source pattern bSp. The first source layer SL1 and the second source layer SL2, the sacrificial layer SC, and the first buffer layer BF1 and the second buffer layer BF2 remaining in the first region 1R may become a first preliminary pattern aLNp, and the first source layer SL1 and the second source layer SL2, the sacrificial layer SC, and the first buffer layer BF1 and the second buffer layer BF2 remaining in the second region 2R may become a second preliminary pattern bLNp.

[0077] Reference Figure 6C , can be filled with insulating material ISM Figure 6B The opening region insulating layer OSI and the first and second separation patterns aDP and bDP are formed by forming the first and second separation openings aOPd and bOPd and the central opening OPc. The insulating material ISM may be a silicon oxide layer.

[0078] Reference Fig.6D, a discharge contact DCC that contacts the peripheral line pMN by passing through the opening region insulating layer OSI can be formed. For example, a hole that exposes a portion of the peripheral line pMN can be formed by etching the central portion of the opening region insulating layer OSI to expose a portion of the peripheral insulating layer pIS and etching the exposed portion of the peripheral insulating layer pIS. A portion of the peripheral line pMN can be exposed through the lower surface of the hole, and a portion of the peripheral insulating layer pIS and the opening region insulating layer OSI can be exposed through the side surface of the hole. Subsequently, a discharge contact DCC can be formed by filling the inside of the hole with a conductive material. For example, the discharge contact DCC can be formed of a conductive material such as polysilicon, tungsten, or nickel.

[0079] Reference Fig. 6E , a preliminary stack structure pSTK may be formed on the second source layer SL2, the opening region insulating layer OSI, and the first and second separation patterns aDP and bDP. The preliminary stack structure pSTK may be formed by alternately stacking the first material layer MT1 and the second material layer MT2. For example, the first material layer MT1 may be formed on the second source layer SL2, the opening region insulating layer OSI, the first and second etching prevention patterns ESP1 and ESP2, and the discharge contact DCC, and the second material layer MT2 may be formed on the first material layer MT1. The first material layer MT1 may be formed again on the second material layer MT2. In this way, a preliminary stack structure pSTK including the first and second material layers MT1 and MT2 alternately stacked may be formed. The first material layer MT1 may be an oxide layer, and the second material layer MT2 may be a material having an etching selectivity different from that of the first material layer MT1. For example, the second material layer MT2 may be a nitride layer.

[0080] Reference Fig. 6F, a first sub-opening aOPs and a second sub-opening bOPs and a first main opening aOPm and a second main opening bOPm exposing a portion of the first preliminary pattern aLNp and the second preliminary pattern bLNp and a portion of the first source pattern aSp and the second source pattern bSp can be formed by etching a portion of the preliminary stack structure pSTK. Although not shown in the drawings, an additional opening can be formed between the first main opening aOPm and the second main opening bOPm. For example, at least one additional opening can be formed through the first material layer MT1 and the second material layer MT2 stacked on the discharge contact DCC. The first sub-opening aOPs and the second sub-opening bOPs can expose a portion of the first preliminary pattern aLNp and the second preliminary pattern bLNp by passing through the first material layer MT1 and the second material layer MT2 stacked in the first region 1R and the second region 2R. For example, the first sub-opening aOPs can expose a portion of the sacrificial layer SC of the first region 1R, and the second sub-opening bOPs can expose a portion of the sacrificial layer SC of the second region 2R. The first main opening aOPm and the second main opening bOPm may expose a portion of the first source pattern aSp and the second source pattern bSp by passing through the first material layer MT1 and the second material layer MT2 stacked in the opening contact region OFC. For example, the first main opening aOPm may expose a portion of the sacrificial layer SC of the first source pattern aSp, and the second main opening bOPm may expose a portion of the sacrificial layer SC of the second source pattern bSp. In the drawings, the depths of the first sub-opening aOPs, the first main opening aOPm, the second main opening bOPm, and the second sub-opening bOPs are shown to be the same, but the depths of these openings may be different from each other.

[0081] The etching process for forming the first sub-opening aOPs, the first main opening aOPm, the second main opening bOPm, and the second sub-opening bOPs may be performed as an anisotropic dry etching process. During the etching process, the first source pattern aSp and the second source pattern bSp and the first preliminary pattern aLNp and the second preliminary pattern bLNp may be used as an etching stop layer. For example, when a portion of the first source pattern aSp and the second source pattern bSp or the first preliminary pattern aLNp and the second preliminary pattern bLNp is exposed, the etching process for forming the first sub-opening aOPs, the first main opening aOPm, the second main opening bOPm, and the second sub-opening bOPs may be stopped. For example, when an element of the sacrificial layer SC is detected, the etching process for forming the first sub-opening aOPs, the first main opening aOPm, the second main opening bOPm, and the second sub-opening bOPs may be stopped.

[0082] During the etching process for forming the first sub-opening aOPs, the first main opening aOPm, the second main opening bOPm, and the second sub-opening bOPs, since the first and second source patterns aSp and the first and second preliminary patterns aLNp and bLNp can be used as etching stop layers, over-etching of the etching process can be prevented.

[0083] Reference Figure 6G , you can Fig. 6F The first opening aOPs, Fig. 6F The first main opening aOPm, Fig. 6F The second main opening bOPm and Fig. 6F The first and second subsidiary support patterns 1SSP and 2SSP as well as the first and second main support patterns aMSP and bMSP are formed in the second subsidiary openings bOPs. Figure 6G and Figure 3 , the first sub-support pattern 1SSP and the second sub-support pattern 2SSP may be spaced apart from each other in the XY plane, and the first main support pattern aMSP and the second main support pattern bMSP may extend from each other. The first sub-support pattern 1SSP and the second sub-support pattern 2SSP and the first main support pattern aMSP and the second main support pattern bMSP may be formed by an insulating layer. For example, the first sub-support pattern 1SSP and the second sub-support pattern 2SSP and the first main support pattern aMSP and the second main support pattern bMSP may be formed by a silicon oxide layer.

[0084] Reference Figure 6H , a first slit opening 1OPslt and a second slit opening 2OPslt may be formed in the first region 1R and the second region 2R of the preliminary stack structure pSTK. The first slit opening 1OPslt and the second slit opening 2OPslt may be regions that divide storage blocks. Therefore, the first slit opening 1OPslt and the second slit opening 2OPslt may pass through the preliminary stack structure pSTK and extend to a portion of the first preliminary pattern aLNp and the second preliminary pattern bLNp. For example, a portion of the sacrificial layer SC of the first preliminary pattern aLNp and the second preliminary pattern bLNp may be exposed through the lower surface of the first slit opening 1OPslt and the second slit opening 2OPslt, and the first material layer MT1 and the second material layer MT2 may be exposed through the side surfaces of the first slit opening 1OPslt and the second slit opening 2OPslt. The first slit opening 1OPslt may be formed in a region adjacent to the first sub-support pattern 1SSP in the first region 1R, and the second slit opening 2OPslt may be formed in a region adjacent to the second sub-support pattern 2SSP in the second region 2R.

[0085] Reference Fig.6I, an isotropic dry etching process or a wet etching process for removing the second material layer MT2 exposed through the first slit opening 1OPslt and the second slit opening 2OPslt may be performed. Because the first main support pattern aMSP and the second main support pattern bMSP have a layout of a line shape extending from each other (see Figure 3 ), so the second material layer MT2 between the first main support pattern aMSP and the second main support pattern bMSP is not exposed through the first main support pattern aMSP and the second main support pattern bMSP. Therefore, the second material layer MT2 between the first main support pattern aMSP and the second main support pattern bMSP can be retained. A first recessed portion REC1 can be formed between the first material layers MT1 from which the second material layer MT2 is removed. The first recessed portion REC1 refers to an empty space between the first material layers MT1.

[0086] Reference Figure 6J , a third material layer MT3 may be formed in the first recess REC1. The third material layer MT3 may be a conductive material. For example, the third material layer MT3 may be formed of a metal material such as tungsten (W), molybdenum (Mo), cobalt (Co) or nickel (Ni) or a semiconductor material such as silicon (Si) or polycrystalline silicon (Poly-Si). When the third material layer MT3 is formed, a stacked structure STK constructed of the first material layer MT1 and the third material layer MT3 may be formed.

[0087] Reference Figure 6K , a slit insulating layer SIS may be formed on the side surfaces of the first slit opening 1OPslt and the second slit opening 2OPslt. The slit insulating layer SIS may be an insulating layer. For example, the slit insulating layer SIS may be a silicon oxide layer. After forming the slit insulating layer SIS, the silicon oxide layer exposed through the lower surfaces of the first slit opening 1OPslt and the second slit opening 2OPslt may be removed. Figure 6J The sacrificial layer SC and the first buffer layer BF1 and the second buffer layer BF2. At this time, because the opening in the contact area OFC Figure 6J The sacrificial layer SC and the first and second buffer layers BF1 and BF2 are not exposed by the first and second separation patterns aDP and bDP, so the opening contact region OFC is Figure 6J The sacrificial layer SC and the first buffer layer BF1 and the second buffer layer BF2 can be retained. Figure 6J A second recess REC2 is formed between the sacrificial layer SC and the first and second source layers SL1 and SL2 of the first and second buffer layers BF1 and BF2. The second recess REC2 refers to an empty space between the first and second source layers SL1 and SL2.

[0088] Reference Figure 6L, a third source layer SL3 may be formed in the second recessed portion REC2. The third source layer SL3 may be a conductive material. For example, the third source layer SL3 may be formed of the same material as the first source layer SL1 and the second source layer SL2. The first to third source layers SL1 to SL3 that are in contact with each other in the first region 1R and the second region 2R may become source lines SL. For example, the first to third source layers SL1 to SL3 of the first region 1R may be first source lines aSL, and the first to third source layers SL1 to SL3 of the second region 2R may be second source lines bSL. Therefore, the first source line aSL and the first source pattern aSp may be separated from each other by the first separation pattern aDP, and the second source line bSL and the second source pattern bSp may be separated from each other by the second separation pattern bDP. When the third source layer SL3 is filled in the second recess REC2, since the third source layer SL3 can be formed in a portion of the lower portion and side surface of the first slit opening 1OPslt and the second slit opening 2OPslt, an etching process or a cleaning process can be further performed to remove the third source layer SL3 remaining in the first slit opening 1OPslt and the second slit opening 2OPslt.

[0089] Reference Figure 6M , you can Figure 6L The first slit structure 1SLT and the second slit structure 2SLT are formed in the first slit opening 1OPslt and the second slit opening 2OPslt. The first slit structure 1SLT may be formed in the first slit opening 1OPslt, and the second slit structure 2SLT may be formed in the second slit opening 2OPslt. The first slit structure 1SLT and the second slit structure 2SLT may be formed of an insulating material or a conductive material. When the first slit structure 1SLT and the second slit structure 2SLT are formed of a conductive material, the first slit structure 1SLT and the second slit structure 2SLT may become source contacts in contact with the source line SL. The source contact is a contact that transmits a source voltage to the source line SL. When the first slit structure 1SLT and the second slit structure 2SLT are formed of an insulating material, the source line SL may transmit a source voltage through a contact located in another area.

[0090] Reference Figure 6N, a discharge opening OPd exposing a portion of the discharge contact DCC can be formed by removing a portion of the first material layer MT1 and the second material layer MT2 between the first main support pattern aMSP and the second main support pattern bMSP. The etching process for forming the discharge opening OPd can be performed as an anisotropic dry etching process. The anisotropic dry etching process can be mainly performed in an RIE method or a method applying the RIE method. Plasma is used in the etching process of the RIE method or the method applying the RIE method. The positive ions generated by the plasma can move in a direction perpendicular to the etching target layer and collide with the etching target layer. Therefore, the binding force of the surface of the etching target layer may be weakened. The molecules of the portion of the etching target layer with weakened binding force can be discharged to the outside of the chamber together with the isotropically moving free radicals. As the depth of the discharge opening OPd increases, the number of positive ions remaining in the lower portion 61 of the discharge opening OPd may increase.

[0091] Reference Fig.6O , you can Figure 6N A contact CT is formed inside the discharge opening OPd. The contact CT may be formed of a conductive material. When the contact CT is formed, an upper structure TST including a first material layer MT1 to a third material layer MT3, a first slit structure 1SLT and a second slit structure 2SLT, a slit insulating layer SIS, a first secondary support pattern 1SSP and a second secondary support pattern 2SSP, a first main support pattern aMSP and a second main support pattern bMSP, and the contact CT may be formed. Figure 6N Positive ions in the discharge opening OPd may be discharged to the outside of the memory device through the discharge contact DCC, the peripheral line pMN, the peripheral contact pCT, and the ground terminal GTN.

[0092] Figure 7 is a diagram illustrating a memory card system 3000 to which the memory device of the present disclosure is applied.

[0093] Reference Figure 7 , the memory card system 3000 includes a controller 3100 , a memory device 3200 , and a connector 3300 .

[0094] The controller 3100 is connected to the memory device 3200. The controller 3100 is configured to access the memory device 3200. For example, the controller 3100 may be configured to control a programming operation, a read operation, or an erase operation of the memory device 3200, or to control a background operation. The controller 3100 is configured to provide an interface between the memory device 3200 and a host. The controller 3100 is configured to drive firmware for controlling the memory device 3200. For example, the controller 3100 may include components such as a random access memory (RAM), a processing unit, a host interface, a memory interface, and an error correction circuit.

[0095] The controller 3100 can communicate with an external device through the connector 3300. The controller 3100 can communicate with an external device (e.g., a host) according to a specific communication standard. For example, the controller 3100 is configured to communicate with an external device through at least one of the following various communication standards: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and NVMe. For example, the connector 3300 can be defined according to at least one of the above-mentioned various communication standards.

[0096] The memory device 3200 may include a plurality of memory cells and may be Figure 1 The memory devices 100 shown are designed identically.

[0097] The controller 3100 and the memory device 3200 may be integrated in one semiconductor device to construct a memory card. For example, the controller 3100 and the memory device 3200 may be integrated in one semiconductor device to construct a memory card such as a PC card (Personal Computer Memory Card International Association (PCMCIA)), a Compact Flash card (CF), a Smart Media Card (SM or SMC), a Memory Stick, a Multimedia Card (MMC, RS-MMC, Micro MMC or eMMC), an SD card (SD, Mini SD, Micro SD or SDHC), and a Universal Flash Storage (UFS) device.

[0098] Figure 8 is a diagram illustrating a solid state drive (SSD) system 4000 to which the memory device of the present disclosure is applied.

[0099] Reference Figure 8 , the SSD system 4000 includes a host 4100 and an SSD 4200. The SSD 4200 exchanges signals with the host 4100 through a signal connector 4001, and receives power through a power connector 4002. The SSD 4200 includes a controller 4210, a plurality of memory devices 4221 to 422n, an auxiliary power supply 4230, and a buffer memory 4240.

[0100] The controller 4210 may control the plurality of memory devices 4221 to 422n in response to a signal received from the host 4100. For example, the signal may be a signal based on an interface between the host 4100 and the SSD 4200. For example, the signal may be a signal defined according to at least one of interfaces such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, Universal Flash Storage (UFS), Wi-Fi, Bluetooth, and NVMe.

[0101] The plurality of memory devices 4221 to 422n may include a plurality of memory cells configured to store data. Each of the plurality of memory devices 4221 to 422n may be connected to Figure 1 The illustrated memory devices 100 are identically constructed. A plurality of memory devices 4221 to 422n may communicate with a controller 4210 through channels CH1 to CHn.

[0102] The auxiliary power supply 4230 is connected to the host 4100 through the power connector 4002. The auxiliary power supply 4230 may receive a power supply voltage from the host 4100 and be charged with the power supply voltage. When the power supply from the host 4100 is not smooth, the auxiliary power supply 4230 may provide the power supply voltage of the SSD 4200. For example, the auxiliary power supply 4230 may be located in the SSD 4200, or may be located outside the SSD 4200. For example, the auxiliary power supply 4230 may be located on the mainboard and provide auxiliary power to the SSD 4200.

[0103] The buffer memory 4240 operates as a buffer memory of the SSD 4200. For example, the buffer memory 4240 may temporarily store data received from the host 4100 or data received from the plurality of memory devices 4221 to 422n, or may temporarily store metadata (e.g., a mapping table) of the memory devices 4221 to 422n. The buffer memory 4240 may include a volatile memory such as DRAM, SDRAM, DDR SDRAM, and LPDDR SDRAM, or a nonvolatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0104] CROSS-REFERENCE TO RELATED APPLICATIONS

[0105] This application claims the priority of Korean Patent Application No. 10-2023-0133348 filed in the Korean Intellectual Property Office on October 6, 2023, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A memory device, the memory device comprising: Discharge contacts; a source pattern surrounding the periphery of the discharge contact and floating; a source line surrounding a periphery of the source pattern and to which a source voltage is applied; a separation pattern, the separation pattern electrically isolating the source pattern from the source line; a main support pattern, the main support pattern being located on the source pattern; A secondary support pattern, the secondary support pattern is located on the source line; as well as A contact piece is located on the discharge contact piece.

2. The memory device according to claim 1, further comprising: a peripheral wire in contact with a lower portion of the discharge contact member; a peripheral contact member contacting a lower portion of the peripheral wire; as well as A ground terminal contacts a lower portion of the peripheral contact.

3. The memory device according to claim 2, wherein: The contact, the discharge contact, the peripheral line, the peripheral contact, and the ground terminal are electrically connected to each other.

4. The memory device according to claim 2, wherein: The peripheral line, the peripheral contact, and the ground terminal are included in a lower structure, and the source line and the source pattern are located on the lower structure.

5. The memory device according to claim 1, further comprising: An opening region insulating layer is located between the source pattern and the discharge contact member.

6. The memory device according to claim 1, wherein: The source pattern comprises: a first source layer; a first buffer layer, the first buffer layer being located on the first source layer; a sacrificial layer, the sacrificial layer being located on the first buffer layer; a second buffer layer, the second buffer layer being located on the sacrificial layer; and A second source layer is located on the second buffer layer.

7. The memory device according to claim 6, wherein: The first source layer, the second source layer and the sacrificial layer include a conductive material, and The first buffer layer and the second buffer layer include insulating materials.

8. The memory device according to claim 1, wherein: The separation pattern includes an insulating material.

9. The memory device according to claim 1, wherein: The main support pattern and the subsidiary support pattern include an insulating material.

10. A memory device, the memory device comprising: An opening region insulating layer, the opening region insulating layer extending along a first direction; a discharge contact included in the opening region insulating layer; A source pattern, the source pattern surrounding the outer surface of the insulating layer in the opening area; a separation pattern surrounding an outer surface of the source pattern; as well as A source line surrounds an outer surface of the separation pattern.

11. The memory device according to claim 10, wherein: The source pattern is disposed around the opening region insulating layer along the first direction and a second direction perpendicular to the first direction, and the source pattern has a line shape.

12. The memory device according to claim 10, wherein: The separation pattern is disposed around the source pattern along the first and second directions, and the separation pattern has a line shape.

13. The memory device according to claim 10, wherein: The separation pattern includes an insulating material.

14. The memory device according to claim 10, wherein: The opening region insulating layer, the discharge contact, the source pattern, and the separation pattern are located in a connection region designated on one side of a memory block, and The source line is located in the connection region and a cell region adjacent to the connection region.

15. The memory device of claim 14, wherein: The source line extends from the connection region to the cell region.

16. The memory device according to claim 14, further comprising: A cell plug is located in the cell region.

17. The memory device according to claim 10, wherein: The source pattern is floated.

18. A method of manufacturing a memory device, the method comprising the steps of: stacking a source layer on the lower structure; separating the source electrode layer into a source electrode pattern and a preliminary pattern; forming a separation pattern between the source pattern and the preliminary pattern; forming a discharge contact in contact with the lower structure in a region spaced apart from the source pattern; forming a main support pattern located on the source pattern and a subsidiary support pattern located on the preliminary pattern; as well as The preliminary pattern is formed into a source line.

19. The method according to claim 18, wherein: The step of stacking the source layer includes the following steps: stacking a first source layer, a first buffer layer, a sacrificial layer, a second buffer layer, and a second source layer on the lower structure.

20. The method according to claim 18, wherein: The step of separating the source layer into the source pattern and the preliminary pattern includes performing an etching process for forming a separation opening for separating the source layer into the source pattern and the preliminary pattern.

21. The method according to claim 20, wherein: The step of forming the separation pattern includes the step of filling the separation openings with an insulating material.

22. The method according to claim 18, wherein: The main support pattern and the subsidiary support pattern are formed simultaneously.

23. The method according to claim 18, wherein: The step of forming the main support pattern and the subsidiary support pattern comprises the following steps: After forming the discharge contact, forming a preliminary stacked structure on the discharge contact, the source pattern, the separation pattern and the preliminary pattern; forming a main opening exposing a portion of the source pattern and a sub-opening exposing a portion of the preliminary pattern by etching a portion of the preliminary stack structure; and The main support pattern is formed in the main opening and the sub-support pattern is formed in the sub-opening by filling the main opening and the sub-opening with an insulating material.

24. The method according to claim 18, wherein: The step of forming the preliminary pattern into the source line comprises the following steps: removing the sacrificial layer included in the preliminary pattern; and The source line including the conductive material and the source layer is formed by filling the region where the sacrificial layer is removed with a conductive material.

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