A high-voltage-resistant field plate terminal planar gate silicon carbide VDMOS and its manufacturing method

Abstract

The present invention provides a high breakdown voltage field plate terminal planar gate silicon carbide VDMOS and a manufacturing method thereof. The method includes: depositing metal on the lower side of a silicon carbide substrate to form a drain metal layer; epitaxially growing on the upper side of the silicon carbide substrate to form a drift layer; forming a blocking layer, etching, and ion implanting to form a P-type region, a first N-type region, a second N-type region, a P-type well region, and an N-type source region; reforming the blocking layer, etching, and depositing to form a gate dielectric layer; reforming the blocking layer, etching, and depositing metal to form a gate metal layer; reforming the blocking layer, etching, and depositing metal to form a source metal layer; reforming the blocking layer, etching the blocking layer to form a through hole, and depositing to form an insulating dielectric layer; reforming the blocking layer, etching the blocking layer to form a through hole, and depositing metal to form a field plate metal layer; removing the blocking layer to complete the manufacturing, and improving the terminal breakdown voltage capability of the device without affecting the on-state characteristics of the device.

Description

Technical Field

[0001] The present invention relates to a high-voltage withstand field plate terminal planar gate silicon carbide VDMOS and a preparation method thereof. Background Art

[0002] Silicon carbide VDMOS is a typical representative of silicon carbide power devices and has wide applications in fields such as electric vehicles, aerospace, and power conversion. For silicon carbide power VDMOS, the performance requirements for the device vary in different fields, but generally, higher voltage withstand capabilities, lower on-resistance, faster switching speeds, higher reliability (including gate reliability, drain voltage shock reliability, short-circuit reliability, etc.), and lower body diode conduction losses are required. Moreover, on the basis that the device thickness meets the device voltage withstand, the problem of insufficient voltage withstand capability often occurs at the device terminal. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a high-voltage withstand field plate terminal planar gate silicon carbide VDMOS and a preparation method thereof, which can improve the terminal voltage withstand capability of the device without affecting the on-characteristics of the device by setting a field plate metal layer, a P-type region, a first N-type region, and a second N-type region.

[0004] In the first aspect, the present invention provides a preparation method of a high-voltage withstand field plate terminal planar gate silicon carbide VDMOS, including the following steps:

[0005] Step 1: Deposit metal on the lower side of the silicon carbide substrate to form a drain metal layer; epitaxially grow on the upper side of the silicon carbide substrate to form a drift layer;

[0006] Step 2: Form a blocking layer above the drift layer, etch the blocking layer to form a through hole, and perform ion implantation on the drift layer to form a P-type region;

[0007] Step 3: Remove the original blocking layer, re-form a blocking layer, etch the blocking layer to form a through hole, and perform ion implantation on the drift layer to form a first N-type region;

[0008] Step 4: Remove the original blocking layer, re-form a blocking layer, etch the blocking layer to form a through hole, and perform ion implantation on the drift layer to form a second N-type region;

[0009] Step 5: Remove the original blocking layer, re-form a blocking layer, etch the blocking layer to form a through hole, and perform ion implantation on the drift layer to form a P-type well region;

[0010] Step 6: Remove the original blocking layer, re-form a blocking layer, etch the blocking layer to form a through hole, and perform ion implantation on the P-type well region to form an N-type source region;

[0011] Step 7: Remove the original barrier layer, reform the barrier layer, etch the barrier layer to form a through hole, deposit, and form a gate dielectric layer;

[0012] Step 8: Remove the original barrier layer, reform the barrier layer, etch the barrier layer to form a through hole, deposit metal, and form a gate metal layer;

[0013] Step 9: Remove the original barrier layer, reform the barrier layer, etch the barrier layer to form a through hole, deposit metal, and form a source metal layer;

[0014] Step 10: Remove the original barrier layer, reform the barrier layer, etch the barrier layer to form a through hole, deposit, and form an insulating dielectric layer;

[0015] Step 11: Remove the original barrier layer, reform the barrier layer, etch the barrier layer to form a through hole, deposit metal, and form a field plate metal layer; remove the barrier layer to complete the preparation.

[0016] In a second aspect, the present invention provides a high-voltage withstand field plate terminal planar gate silicon carbide VDMOS, and the silicon carbide VDMOS is prepared by using the preparation method of a high-voltage withstand field plate terminal planar gate silicon carbide VDMOS described in the first aspect.

[0017] The advantages of the present invention are as follows:

[0018] First, the present invention constructs the structures of a P-type well region, a P-type region, a first N-type region, and a second N-type region. The doping concentrations of the P-type region and the first N-type region are low, and their electric field intensities are low. When the drain bears a high voltage, the electric field concentrated at the corner of the P-type well region diffuses to the left and right sides, gradually reducing the electric field intensity and forming a gradually changing electric field, avoiding breakdown caused by electric field concentration and improving the terminal voltage withstand ability;

[0019] Second, the present invention constructs a field plate metal layer. The field plate metal layer is connected to the source metal layer. When the drain bears a large voltage, the field plate metal layer is at a low voltage relative to the drain, and positive charges will be formed under the field plate metal layer, expanding the electric field at the edge of the P-type well region, thereby reducing the electric field intensity at the edge of the P-type well region and realizing an improvement in the terminal voltage withstand ability of the device;

[0020] Third, the present invention provides an insulating dielectric layer to improve the voltage withstand ability of the field plate metal layer, avoid the formation of a breakdown channel between the drain metal layer and the source metal layer in the second N-type region and the P-type region due to the drain voltage, and improve the reliability of the device structure. Description of the Drawings

[0021] The following further describes the present invention with reference to the accompanying drawings in conjunction with embodiments.

[0022] Figure 1 It is a schematic diagram of a high-voltage withstand field plate terminal planar gate silicon carbide VDMOS of the present invention.

[0023] Figure 2 Process cross-section of a high-voltage field plate terminal planar gate silicon carbide VDMOS according to the present invention Figure 1 。

[0024] Figure 3 Process cross-section of a high-voltage field plate terminal planar gate silicon carbide VDMOS according to the present invention Figure 2 。

[0025] Figure 4 Process cross-section of a high-voltage field plate terminal planar gate silicon carbide VDMOS according to the present invention Figure 3 。

[0026] Figure 5 Process cross-section of a high-voltage field plate terminal planar gate silicon carbide VDMOS according to the present invention Figure 4 。

[0027] Figure 6 Process cross-section of a high-voltage field plate terminal planar gate silicon carbide VDMOS according to the present invention Figure 5 。

[0028] Figure 7 Process cross-section of a high-voltage field plate terminal planar gate silicon carbide VDMOS according to the present invention Figure 6 。

[0029] Figure 8 Process cross-section of a high-voltage field plate terminal planar gate silicon carbide VDMOS according to the present invention Figure 7 。

[0030] Figure 9 Process cross-section of a high-voltage field plate terminal planar gate silicon carbide VDMOS according to the present invention Figure 8 。

[0031] Figure 10 Process cross-section of a high-voltage field plate terminal planar gate silicon carbide VDMOS according to the present invention Figure 9 。

[0032] Figure 11 Process cross-section of a high-voltage field plate terminal planar gate silicon carbide VDMOS according to the present invention Figure 10 。

[0033] Figure 12 Process cross-section of a high-voltage field plate terminal planar gate silicon carbide VDMOS according to the present invention Figure 10 I. Specific embodiments

[0034] To facilitate the understanding of this application, the following will provide a more comprehensive description of this application with reference to the relevant drawings. Embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of this application more thorough and comprehensive.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application belongs. The terms used in the specification of this application herein are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0036] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "in contact with", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or parts, these elements, components, regions, layers, doping types, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or part from another element, component, region, layer, doping type, or part. Thus, without departing from the teachings of the present invention, the first element, component, region, layer, doping type, or part discussed below may be referred to as the second element, component, region, layer, or part.

[0037] Spatial relationship terms such as "under", "below", "beneath", "underneath", "above", "over", etc. may be used herein to describe the relationship of one element or feature described in the figures to other elements or features. It should be understood that, in addition to the orientation depicted in the figures, spatial relationship terms also encompass different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as "under" or "beneath" or "underneath" another element or feature will be oriented "above" the other element or feature. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. Additionally, the device may also assume other orientations (such as, rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0038] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising", "including" or "having" and the like specify the presence of the stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the related listed items.

[0039] As Figures 1 to 12 shown, an embodiment of the present application provides a method for preparing a high-voltage withstand field plate terminal planar gate silicon carbide VDMOS, including the following steps:

[0040] Step 1: Deposit metal on the lower side of the silicon carbide substrate 101 to form a drain metal layer 112; epitaxially grow on the upper side of the silicon carbide substrate 101 to form a drift layer 102;

[0041] Step 2: Form a blocking layer 113 above the drift layer 102, etch the blocking layer 113 to form a through hole, and perform ion implantation on the drift layer 102 to form a P-type region 104;

[0042] Step 3: Remove the original blocking layer 113, reform the blocking layer 113, etch the blocking layer 113 to form a through hole, and perform ion implantation on the drift layer 102 to form a first N-type region 105;

[0043] Step 4: Remove the original blocking layer 113, reform the blocking layer 113, etch the blocking layer 113 to form a through hole, and perform ion implantation on the drift layer 102 to form a second N-type region 106;

[0044] Step 5: Remove the original blocking layer 113, reform the blocking layer 113, etch the blocking layer 113 to form a through hole, and perform ion implantation on the drift layer 102 to form a P-type well region 103;

[0045] Step 6: Remove the original blocking layer 113, reform the blocking layer 113, etch the blocking layer 113 to form a through hole, and perform ion implantation on the P-type well region 103 to form an N-type source region 1031;

[0046] Step 7: Remove the original blocking layer 113, reform the blocking layer 113, etch the blocking layer 113 to form a through hole, and deposit to form a gate dielectric layer 108;

[0047] Step 8: Remove the original blocking layer 113, reform the blocking layer 113, etch the blocking layer 113 to form a through hole, and deposit metal to form a gate metal layer 110;

[0048] Step 9: Remove the original barrier layer 113, reform the barrier layer 113, etch the barrier layer 113 to form a through hole, deposit metal, and form the source metal layer 111;

[0049] Step 10: Remove the original barrier layer 113, reform the barrier layer 113, etch the barrier layer 113 to form a through hole, deposit, and form the insulating dielectric layer 107;

[0050] Step 11: Remove the original barrier layer 113, reform the barrier layer 113, etch the barrier layer 113 to form a through hole, deposit metal, and form the field plate metal layer 109; Remove the barrier layer 113 to complete the preparation.

[0051] In this embodiment, preferably, the widths of the first N-type region 105, the P-type region 104, and the second N-type region 106 are all equal.

[0052] In this embodiment, preferably, the thickness of the field plate metal layer 109 is less than the thickness of the source metal layer 111.

[0053] In this embodiment, preferably, the doping concentration of the first N-type region 105 is less than the doping concentration of the drift layer 102.

[0054] In this embodiment, preferably, the doping concentration of the drift layer 102 is less than the doping concentration of the second N-type region 106.

[0055] As Figure 1 shown, the silicon carbide VDMOS obtained by the above manufacturing method includes:

[0056] Silicon carbide substrate 101;

[0057] Drift layer 102, the lower side of the drift layer 102 is connected to the upper side of the silicon carbide substrate 101; The drift layer 102 is provided with a convex portion 1021;

[0058] P-type well region 103, the lower side of the P-type well region 103 is connected to the upper side of the drift layer 102, and the inner side of the P-type well region 103 is connected to the outer side of the convex portion 1021; The P-type well region 103 is provided with an N-type source region 1031;

[0059] P-type region 104, the lower side of the P-type region 104 is connected to the upper side of the drift layer 102, and the inner side of the P-type region 104 is connected to the outer side of the P-type well region 103;

[0060] First N-type region 105, the lower side of the first N-type region 105 is connected to the upper side of the drift layer 102, and the inner side of the first N-type region 105 is connected to the outer side of the P-type region 104;

[0061] The second N-type region 106, the lower side surface of the second N-type region 106 is connected to the upper side surface of the drift layer 102, and the inner side surface of the second N-type region 106 is connected to the outer side surface of the first N-type region 105;

[0062] The insulating dielectric layer 107, the lower side surface of the insulating dielectric layer 107 is connected to the first N-type region 105, the second N-type region 106, and the P-type region 104;

[0063] The gate dielectric layer 108, the lower side surface of the gate dielectric layer 108 is connected to the upper side surface of the protrusion 1021, the upper side surface of the P-type well region 103, and the upper side surface of the N-type source region 1031;

[0064] The field plate metal layer 109, the lower side surface of the field plate metal layer 109 is connected to the upper side surface of the insulating dielectric layer 107;

[0065] The gate metal layer 110, the lower side surface of the gate metal layer 110 is connected to the gate dielectric layer 108;

[0066] The source metal layer 111 is respectively connected to the P-type well region 103, the N-type source region 1031, the P-type region 104, and the field plate metal layer 109;

[0067] And, the drain metal layer 112 is connected to the lower side surface of the silicon carbide substrate 101.

[0068] In another embodiment of the present invention, the doping concentration of the N-type silicon carbide substrate 101 is 2 - 8e18 cm -3 , the doping concentration of the N-type drift layer 102 is 6 - 10e16 cm -3 , the doping concentration of the P-type well region 103 is 6 - 10e17 cm -3 , the doping concentration of the P-type region 104 is 6 - 10e16 cm -3 , the doping concentration of the first N-type region 105 is 1 - 5e16 cm -3 , the doping concentration of the second N-type region 106 is 1 - 5e17 cm -3 , the materials of the insulating dielectric layer 107 and the gate dielectric layer 108 can be silicon dioxide, and the doping concentration of the N-type source region 1031 is 2 - 8e18 cm -3; The doping concentration of the N-type silicon carbide substrate 101 is to ensure a low-resistance ohmic contact with the drain metal layer 112 and reduce the overall on-resistance of the device; the doping concentration of the N-type drift layer 102 is a compromise between the reverse breakdown voltage and the on-resistance of the device; the P-type region 104, the first N-type region 105, and the second N-type region 106 are to form a P-type well region 103 - P-type region 104 - first N-type region 105 - second N-type region 106 structure at the terminal, realizing the transition from the P-type well region 103 to low doping. Thus, when the drain of the device withstands a high voltage, the electric field does not concentrate at the edge of the P-type well 103, achieving a gradual reduction in the electric field transition, thereby improving the reliability of the terminal; the insulating dielectric layer 107 and the field plate metal layer 109 are to form a P-type region 104 under the insulating dielectric layer 107 when a high voltage is applied to the drain of the device and the field plate metal layer 109 is at a low level relative to the drain, realizing the expansion of the positive charge region towards the edge based on the P-type well region 103 - P-type region 104 structure existing in the device structure itself; the field plate metal layer 109 is connected to the source metal layer 111. When the body diode of the device conducts a continuous current, the field plate metal layer 109 - insulating dielectric layer 107 structure of the device does not affect the characteristics of the body diode, thereby ensuring the body diode continuous current capacity of the device; the doping concentration of the N-type source region 1031 is to reduce the source contact resistance of the device and reduce the on-resistance of the device;

[0069] The thickness of the N-type silicon carbide substrate 101 of the device is 1 μm, which is to form a low-resistance ohmic contact with the drain metal layer 112 and reduce the on-resistance of the device; the thickness of the N-type drift layer 102 is 50 - 100 μm and is adjusted within the above range according to different requirements for the breakdown voltage characteristics of the device; the width of the P-type well region 103 of the device is 30% of the width of the drift layer 102, and the widths of the P-type region 104, the first N-type region 105, and the second N-type region 106 are all equal, each being 5% of the width of the drift layer 102. This is a compromise to ensure the low-resistance characteristics and the breakdown voltage terminal of the device, achieving both high breakdown voltage and low-resistance characteristics of the device; the thickness of the P-type well region 103 is 300 nm, the thickness of the N-type source region 1031 is 200 nm, and the thicknesses of the P-type region 104, the first N-type region 105, and the second N-type region 106 are all 500 nm, and the thickness of the insulating dielectric layer 107 is 200 nm. This is to ensure that when the drain withstands a large voltage, there will be no breakdown problem from the drain to the field plate metal;

[0070] In the present invention, a structure of a P-type well region 103 - P-type region 104 - first N-type region 105 - second N-type region 106 is constructed in the device. Due to the low doping concentration of the P-type region 104 and the first N-type region 105 structure, the electric field strength is low. Thus, when the device withstands a high voltage at the drain, the electric field concentrated at the corner of the P-type well 103 is diffused to the left and right sides, gradually reducing the electric field strength to form a gradually varying electric field, thereby avoiding breakdown caused by electric field concentration and improving the terminal breakdown voltage value; a field plate metal layer 109 is constructed. The field plate metal layer 109 is connected to the source metal layer 111. When the drain withstands a large voltage, the field plate metal layer 109 is at a low voltage relative to the drain, and positive charges will be formed under the field plate metal layer 109, thereby expanding the electric field at the edge of the P-type well region 103, thus reducing the electric field strength at the edge of the P-type well region 103 and realizing an improvement in the terminal breakdown voltage ability of the device; the thickness of the insulating dielectric layer 107 of the device is 200 nm, which is to improve the breakdown voltage ability of the field plate metal layer 109, avoid the formation of a breakdown channel between the drain metal layer 112 and the source metal layer 111 due to the drain voltage in the second N-type region 106 and the P-type region 104, and improve the reliability of the device structure.

[0071] Although the specific embodiments of the present invention have been described above, those skilled in the art of this technology should understand that the specific embodiments we described are illustrative rather than used to limit the scope of the present invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present invention should be covered by the scope protected by the claims of the present invention.

Claims

1. A preparation method of a high-voltage-resistant field plate terminal planar gate silicon carbide VDMOS, characterized in that: It includes the following steps: Step 1: Deposit metal on the lower side of the silicon carbide substrate to form a drain metal layer; epitaxially grow on the upper side of the silicon carbide substrate to form a drift layer; Step 2: Form a blocking layer above the drift layer, etch the blocking layer to form a through hole, and perform ion implantation on the drift layer to form a P-type region; Step 3: Remove the blocking layer in Step 2, reform the blocking layer, etch the blocking layer to form a through hole, and perform ion implantation on the drift layer to form a first N-type region; Step 4: Remove the blocking layer in Step 3, reform the blocking layer, etch the blocking layer to form a through hole, and perform ion implantation on the drift layer to form a second N-type region; Step 5: Remove the blocking layer in Step 4, reform the blocking layer, etch the blocking layer to form a through hole, and perform ion implantation on the drift layer to form a P-type well region; Step 6: Remove the blocking layer in Step 5, reform the blocking layer, etch the blocking layer to form a through hole, and perform ion implantation on the P-type well region to form an N-type source region; Step 7: Remove the blocking layer in Step 6, reform the blocking layer, etch the blocking layer to form a through hole, and deposit to form a gate dielectric layer; Step 8: Remove the blocking layer in Step 7, reform the blocking layer, etch the blocking layer to form a through hole, and deposit metal to form a gate metal layer; Step 9: Remove the blocking layer in Step 8, reform the blocking layer, etch the blocking layer to form a through hole, and deposit metal to form a source metal layer; Step 10: Remove the blocking layer in Step 9, reform the blocking layer, etch the blocking layer to form a through hole, and deposit to form an insulating dielectric layer; Step 11: Remove the blocking layer in Step 10, reform the blocking layer, etch the blocking layer to form a through hole, and deposit metal to form a field plate metal layer; remove the blocking layer to complete the preparation; The lower side of the P-type region is connected to the upper side of the drift layer, and the inner side of the P-type region is connected to the outer side of the P-type well region; the lower side of the first N-type region is connected to the upper side of the drift layer, and the inner side of the first N-type region is connected to the outer side of the P-type region; the lower side of the second N-type region is connected to the upper side of the drift layer, and the inner side of the second N-type region is connected to the outer side of the first N-type region.

2. The manufacturing method of a high breakdown voltage field plate terminal planar gate silicon carbide VDMOS as described in claim 1, wherein: The widths of the first N-type region, the P-type region, and the second N-type region are all equal.

3. The manufacturing method of a high breakdown voltage field plate terminal planar gate silicon carbide VDMOS according to claim 1, characterized in that: The thickness of the field plate metal layer is less than the thickness of the source metal layer.

4. The manufacturing method of a high breakdown voltage field plate terminal planar gate silicon carbide VDMOS according to claim 1, wherein: The doping concentration of the first N-type region is less than the doping concentration of the drift layer.

5. The manufacturing method of a high breakdown voltage field plate terminal planar gate silicon carbide VDMOS as claimed in claim 1, wherein: The doping concentration of the drift layer is less than the doping concentration of the second N-type region.

6. A high-voltage withstand field plate terminal planar gate silicon carbide VDMOS, characterized in that, The silicon carbide VDMOS is prepared by the preparation method described in any one of claims 1 to 5.

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