A low-resistance separated trench-gate silicon carbide VDMOS and its manufacturing method

Abstract

The present invention provides a low-resistance separated trench gate silicon carbide VDMOS and a preparation method thereof. The method includes: depositing metal on the lower side of a silicon carbide substrate to form a drain metal layer; epitaxially growing on the upper side of the silicon carbide substrate to form a drift layer; forming a blocking layer, etching, and ion implanting to form a P-type source region, a low-resistance region, a P-type well region, and an N-type source region; reforming the blocking layer, etching, and depositing to form a first insulating dielectric layer and a second insulating dielectric layer; reforming the blocking layer, etching, and depositing metal to form a first gate metal layer and a second gate metal layer respectively; reforming the blocking layer, etching, and depositing metal to form a first source metal layer; reforming the blocking layer, etching, and depositing metal to form a second source metal layer, removing the blocking layer to complete the preparation; reducing the drive loss and body diode loss of the device.

Description

Technical Field

[0001] The present invention relates to a low-resistance separated trench-gate silicon carbide VDMOS and a preparation method thereof. Background Art

[0002] Silicon carbide VDMOS is a typical representative of silicon carbide power devices and has wide applications in fields such as electric vehicles, aerospace, and power conversion. For silicon carbide power VDMOS, the requirements for device performance vary in different fields, but generally, higher breakdown voltage capabilities, lower on-resistances, faster switching speeds, higher reliabilities (including gate reliability, drain voltage shock reliability, short-circuit reliability, etc.), and lower body diode conduction losses are required. In view of the increasing demand for high-frequency applications of silicon carbide VDMOS in module power supplies and the increasing proportion of switching losses and body diode losses of VDMOS in device power consumption, a solution is urgently needed. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a low-resistance separated trench-gate silicon carbide VDMOS and a preparation method thereof, which construct a first gate metal layer, a second gate metal, and a Schottky body diode inside the device to reduce the driving loss and body diode loss of the device.

[0004] In a first aspect, the present invention provides a preparation method of a low-resistance separated trench-gate silicon carbide VDMOS, including the following steps:

[0005] Step 1: Deposit metal on the lower side of a silicon carbide substrate to form a drain metal layer; epitaxially grow on the upper side of the silicon carbide substrate to form a drift layer;

[0006] Step 2: Form a blocking layer above the drift layer, etch the blocking layer to form a through hole, and perform ion implantation on the drift layer to form a P-type source region;

[0007] Step 3: Remove the original blocking layer, re-form the blocking layer, etch the blocking layer to form a through hole, and perform ion implantation on the drift layer to form a low-resistance region;

[0008] Step 4: Remove the original blocking layer, re-form the blocking layer, etch the blocking layer to form a through hole, and perform ion implantation on the drift layer to form a P-type well region;

[0009] Step 5: Remove the original blocking layer, re-form the blocking layer, etch the blocking layer to form a through hole, and perform ion implantation on the P-type well region to form an N-type source region;

[0010] Step 6: Remove the original blocking layer, re-form the blocking layer, etch the blocking layer to form a through hole, and etch the low-resistance region to form a first groove and a second groove, and deposit to form a first insulating dielectric layer and a second insulating dielectric layer;

[0011] Step 7: Remove the original barrier layer, reform the barrier layer, etch the barrier layer to form a via hole, and etch the first insulating dielectric layer and the second insulating dielectric layer to form a first trench and a second trench, deposit metal, and form a first gate metal layer and a second gate metal layer respectively;

[0012] Step 8: Remove the original barrier layer, reform the barrier layer, etch the barrier layer to form a via hole, and etch the low-resistance region to form a third groove, deposit metal, and form a first source metal layer;

[0013] Step 9: Remove the original barrier layer, reform the barrier layer, etch the barrier layer to form a via hole, and etch the P-type source region and the N-type source region, deposit metal, form a second source metal layer, and remove the barrier layer to complete the preparation.

[0014] In a second aspect, the present invention provides a low-resistance separated trench gate silicon carbide VDMOS, which is prepared by using the preparation method of a low-resistance separated trench gate silicon carbide VDMOS described in the first aspect.

[0015] The advantages of the present invention are as follows:

[0016] First, by setting the first gate metal and the second gate metal layer, the gate structure size of the device is reduced, the gate-drain capacitance between the gate and the drain is reduced, thereby reducing the switching capacitance of the device and improving the switching speed of the device;

[0017] Second, a first source metal layer is constructed in the middle of the device, thereby constructing a Schottky diode inside the device, which can reduce the conduction loss of the body diode of the device. At the same time, under the condition of a lower source freewheeling current, the bipolar degradation effect caused by P-type carriers can be effectively suppressed;

[0018] Third, a heavily doped P-type source region is constructed outside the P-type well region of the device. The P-type source region has two functions. First, the P-type source region and the drift layer form a space charge region. Since the doping concentration of the P-type source region is high, the space charge region mainly diffuses into the drift layer, and a space charge region is formed on the side of the first gate metal layer and the second gate metal layer of the device close to the P-type well region, so as to improve the breakdown voltage of the device from the drain to the source and the gate; Second, it forms an ohmic contact with the second source metal layer to assist in freewheeling when the Schottky body diode freewheeling cannot meet the current demand, and improves the current capacity of the device;

[0019] Fourth, the low-resistance region is distributed directly below the first gate metal layer and the second gate metal layer, which can realize the electric field shielding from the gate to the drain of the device, thereby further reducing the gate-drain capacitance of the device and improving the switching speed of the device. Description of the Drawings

[0020] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0021] Figure 1 This is the schematic diagram of a low-resistance separated trench-gate silicon carbide VDMOS of the present invention.

[0022] Figure 2 This is the process cross-section of a low-resistance separated trench-gate silicon carbide VDMOS of the present invention Figure 1 。

[0023] Figure 3 This is the process cross-section of a low-resistance separated trench-gate silicon carbide VDMOS of the present invention Figure 2 。

[0024] Figure 4 This is the process cross-section of a low-resistance separated trench-gate silicon carbide VDMOS of the present invention Figure 3 。

[0025] Figure 5 This is the process cross-section of a low-resistance separated trench-gate silicon carbide VDMOS of the present invention Figure 4 。

[0026] Figure 6 This is the process cross-section of a low-resistance separated trench-gate silicon carbide VDMOS of the present invention Figure 5 。

[0027] Figure 7 This is the process cross-section of a low-resistance separated trench-gate silicon carbide VDMOS of the present invention Figure 6 。

[0028] Figure 8 This is the process cross-section of a low-resistance separated trench-gate silicon carbide VDMOS of the present invention Figure 7 。

[0029] Figure 9 This is the process cross-section of a low-resistance separated trench-gate silicon carbide VDMOS of the present invention Figure 8 。

[0030] Figure 10 This is the process cross-section of a low-resistance separated trench-gate silicon carbide VDMOS of the present invention Figure 9 。

[0031] Figure 11 This is the process cross-section of a low-resistance separated trench-gate silicon carbide VDMOS of the present invention Figure 10 。

[0032] Figure 12 This is the process cross-section of a low-resistance separated trench-gate silicon carbide VDMOS of the present invention Figure 10 One.

[0033] Figure 13Process cross-section of a low-resistance isolated trench-gate silicon carbide VDMOS according to the present invention Figure 10 II.

[0034] Figure 14 Process cross-section of a low-resistance isolated trench-gate silicon carbide VDMOS according to the present invention Figure 10 III. Specific embodiments

[0035] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided so that the disclosure of the present application is thorough and comprehensive.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application belongs. The terms used in the description of the present application herein are for the purpose of describing specific embodiments only and are not intended to limit the present application.

[0037] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "in contact with", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Thus, a first element, component, region, layer, doping type or part discussed below may be denoted as a second element, component, region, layer or part without departing from the teachings of the present invention.

[0038] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. can be used herein to describe the relationship of one element or feature described in the figure with other elements or features. It should be understood that, in addition to the orientations described in the figure, spatial relationship terms also include different orientations of the device during use and operation. For example, if the device in the drawing is flipped, an element or feature described as "under other elements" or "beneath it" or "under it" will be oriented "above" other elements or features. Thus, the exemplary terms "under" and "beneath" can include both upper and lower orientations. In addition, the device may also include additional orientations (such as rotating 90 degrees or other orientations), and the spatial descriptors used herein are accordingly interpreted.

[0039] As used herein, the singular forms of "a", "an", and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that terms such as "comprising" or "having" etc. specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the related listed items.

[0040] As Figures 1 to 14 shown, an embodiment of the present application provides a method for preparing a low-resistance separated trench gate silicon carbide VDMOS, including the following steps:

[0041] Step 1: Deposit metal on the lower side of the silicon carbide substrate 101 to form a drain metal layer 113; epitaxially grow on the upper side of the silicon carbide substrate 101 to form a drift layer 102;

[0042] Step 2: Form a blocking layer 114 above the drift layer 102, etch the blocking layer 114 to form a through hole, and perform ion implantation on the drift layer 102 to form a P-type source region 105;

[0043] Step 3: Remove the original blocking layer 114, reform the blocking layer 114, etch the blocking layer 114 to form a through hole, and perform ion implantation on the drift layer 102 to form a low-resistance region 106;

[0044] Step 4: Remove the original blocking layer 114, reform the blocking layer 114, etch the blocking layer 114 to form a through hole, and perform ion implantation on the drift layer 102 to form a P-type well region 103;

[0045] Step 5: Remove the original barrier layer 114, reform the barrier layer 114, etch the barrier layer 114 to form a via hole, and perform ion implantation into the P-type well region 103 to form an N-type source region 104;

[0046] Step 6: Remove the original barrier layer 114, reform the barrier layer 114, etch the barrier layer 114 to form a via hole, and etch the low-resistance region 106 to form a first groove 115 and a second groove 116, and deposit to form a first insulating dielectric layer 107 and a second insulating dielectric layer 108;

[0047] Step 7: Remove the original barrier layer 114, reform the barrier layer 114, etch the barrier layer 114 to form a via hole, and etch the first insulating dielectric layer 107 and the second insulating dielectric layer 108 to form a first trench 1071 and a second trench 1081, and deposit metal to form a first gate metal layer 109 and a second gate metal layer 110 respectively;

[0048] Step 8: Remove the original barrier layer 114, reform the barrier layer 114, etch the barrier layer 114 to form a via hole, and etch the low-resistance region 106 to form a third groove 117, and deposit metal to form a first source metal layer 111;

[0049] Step 9: Remove the original barrier layer 114, reform the barrier layer 114, etch the barrier layer 114 to form a via hole, and etch the P-type source region 105 and the N-type source region 104, deposit metal to form a second source metal layer 112, and remove the barrier layer 114 to complete the preparation.

[0050] In this embodiment, preferably, the silicon carbide substrate 101, the drift layer 102, and the low-resistance region 106 are all N-type.

[0051] In this embodiment, preferably, the doping concentration of the low-resistance region 106 is greater than that of the drift layer 102.

[0052] In this embodiment, preferably, the doping concentration of the P-type source region 105 is greater than that of the drift layer 102; the doping concentration of the P-type source region 105 is greater than that of the N-type source region 104; the doping concentration of the P-type source region 105 is greater than that of the P-type well region 103.

[0053] In this embodiment, preferably, the left side wall thickness of the first insulating dielectric layer 107 is less than the right side wall thickness.

[0054] In this embodiment, preferably, the left side wall thickness of the second insulating dielectric layer 108 is greater than the right side wall thickness.

[0055] As Figure 1 shown, the VDMOS obtained by the above manufacturing method includes:

[0056] Silicon carbide substrate 101;

[0057] Drift layer 102, the lower side of the drift layer 102 is connected to the upper side of the silicon carbide substrate 101, a protrusion 1021 is provided on the drift layer 102, and a groove 10211 is provided on the protrusion 1021;

[0058] P-type well region 103, the lower side of the P-type well region 103 is connected to the upper side of the protrusion 1021;

[0059] N-type source region 104, the lower side of the N-type source region 104 is connected to the upper side of the P-type well region 103;

[0060] P-type source region 105, the P-type source region 105 is connected to the upper side of the drift layer 102; the inner side of the P-type source region 105 is connected to the outer side of the protrusion 1021, the outer side of the P-type well region 103, and the outer side of the N-type source region 104;

[0061] Low-resistance region 106, the low-resistance region 106 is provided in the groove 10211;

[0062] First insulating dielectric layer 107, the lower part of the first insulating dielectric layer 107 is provided in the groove 10211, and the lower side of the first insulating dielectric layer 107 is connected to the upper side of the low-resistance region 106, one side of the first insulating dielectric layer 108 is connected to the inner side of the P-type well region 103 and the inner side of the N-type source region 104; a first trench 1071 is provided in the first insulating dielectric layer 107;

[0063] Second insulating dielectric layer 108, the lower part of the second insulating dielectric layer 108 is provided in the groove 10211, and the lower side of the second insulating dielectric layer 108 is connected to the upper side of the low-resistance region 106, one side of the second insulating dielectric layer 108 is connected to the inner side of the P-type well region 103 and the inner side of the N-type source region 104; a second trench 1081 is provided in the second insulating dielectric layer 108;

[0064] First gate metal layer 109, the first gate metal layer 109 is provided in the first trench 1071;

[0065] Second gate metal layer 110, the second gate metal layer 110 is provided in the second trench 1081;

[0066] First source metal layer 111, the lower part of the first source metal layer 111 is provided in the groove 10211, and the lower side of the first source metal layer 111 is connected to the upper side of the low-resistance region 106, and the side of the first source metal layer 111 is respectively connected to the other side of the first insulating dielectric layer 107 and the other side of the second insulating dielectric layer 108;

[0067] A second source metal layer 112, the second source metal layer 112 being connected to the P-type source region 105 and the N-type source region 104 respectively;

[0068] And a drain metal layer 113, the drain metal layer 113 being connected to the lower side surface of the silicon carbide substrate 101.

[0069] In another embodiment of the present invention, the doping concentration of the N-type silicon carbide substrate 101 is 2 - 8e18 cm -3 , the doping concentration of the N-type drift layer 102 is 6 - 10e16 cm -3 , the doping concentration of the N-type low-resistance region 106 is 6 - 10e17 cm -3 , the doping concentration of the P-type well region 103 is 6 - 10e16 cm -3 , the doping concentration of the P-type source region 105 is 1 - 5e19 cm -3 , the materials of the first insulating dielectric layer 107 and the second insulating dielectric layer 108 can be silicon dioxide, and the doping concentration of the N-type source region 104 is 2 - 8e18 cm -3 ;

[0070] The doping concentration of the N-type silicon carbide substrate 101 is to ensure a low-resistance ohmic contact with the drain metal layer 113 and reduce the overall on-resistance of the device; the doping concentration of the N-type drift layer 102 is a trade-off between the reverse breakdown voltage and the on-resistance of the device; the doping concentration of the P-type well region 103 is to achieve the breakdown voltage of the pn junction of the device when the drain of the device bears a high voltage; the doping concentration of the P-type source region 105 is to form a space charge region mainly diffusing towards the N-type drift layer 102 with the N-type drift layer 102, so as to achieve the protection of the P-type well 103, the first gate metal layer 109 and the second gate metal layer 110 of the device when the drain bears a large voltage; at the same time, the P-type source region 105 also needs to achieve an ohmic contact with the second source metal layer 112, so as to complete the supplement of the device current capacity under the condition of insufficient freewheeling of the parasitic Schottky substrate diode of the device and improve the device current capacity; the doping concentration of the N-type low-resistance region 106 is to form a Schottky contact with the first source metal 111, reduce the on-voltage drop of the body diode of the device and ensure the reverse breakdown voltage; the N-type low-resistance region 106 also needs to achieve the electric field shielding between the gate and the drain of the device, thereby reducing the gate-drain capacitance of the device and improving the switching speed of the device; the doping concentration of the N-type source region 104 is to reduce the source contact resistance of the device and reduce the on-resistance of the device;

[0071] The thickness of the N-type silicon carbide substrate 101 is 1 μm, which is for forming a low-resistance ohmic contact with the drain metal layer 113 to reduce the on-resistance of the device; the thickness of the N-type drift layer 102 is 50 - 100 μm and is adjusted within the above range according to different requirements for the breakdown voltage characteristics of the device; the thickness of the second source metal layer 112 is 300 nm, the thickness of the first source metal layer 111 is 700 nm, the thickness of the P-type source region 105 is 600 nm, and the width is 500 nm; the thickness of the N-type source region 104 is 100 nm, the thickness of the P-type well region 103 is 200 nm, the thickness of the N-type low-resistance region 106 is 200 nm, and the width is 3 μm, the bottom thickness of the first insulating dielectric layer is 100 nm, the width is 1 μm, the sidewall width on the side close to the P-type well region 103 is 50 nm, and the sidewall width on the side far from the P-type well region 103 is 100 nm, the thicknesses of the first gate metal layer 109 and the second gate metal layer 110 are both 600 nm, and the width is 850 nm;

[0072] In this embodiment, the first gate metal layer 109 and the second gate metal layer 110 are separately arranged, thereby reducing the gate structure size of the device, reducing the gate-drain capacitance between the gate and the drain of the device, thus reducing the switching capacitance of the device and improving the switching speed of the device; the N-type low-resistance region 106 of the device is located directly below the first gate metal layer 109 and the second gate metal layer 110, which can achieve the electric field shielding from the gate to the drain of the device, thereby further reducing the gate-drain capacitance of the device and improving the switching speed of the device.

[0073] The first source metal layer 111 is constructed, thereby constructing a Schottky diode inside the device to reduce the conduction loss of the body diode of the device. At the same time, under the condition of a lower source freewheeling current, the bipolar degradation effect caused by P-type carriers can be effectively suppressed. A heavily doped P-type source region 105 is constructed outside the P-type well region 103 of the device. The P-type source region 105 has two functions: the first is that the P-type source region 105 and the N-type drift layer 102 form a space charge region. Since the doping concentration of the P-type source region 105 is high, the space charge region mainly diffuses into the N-type drift layer 102, forming a space charge region on the side of the first gate metal layer 109 and the second gate metal layer 110 of the device close to the P-type well region 103, achieving the ability to improve the breakdown voltage from the drain to the source and the gate of the device. The second is to form an ohmic contact with the second source metal layer 112 to assist in freewheeling when the Schottky body diode freewheeling cannot meet the current demand, improving the current-carrying capacity of the device.

[0074] Although the specific embodiments of the present invention have been described above, those skilled in the art should understand that the specific embodiments we described are illustrative rather than used to limit the scope of the present invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present invention should all be covered by the scope protected by the claims of the present invention.

Claims

1. A preparation method of a low-resistance separated trench-gate silicon carbide VDMOS, characterized in that: It includes the following steps: Step 1: Deposit metal on the lower side of the silicon carbide substrate to form a drain metal layer; epitaxially grow on the upper side of the silicon carbide substrate to form a drift layer; Step 2: Form a blocking layer above the drift layer, etch the blocking layer to form a through hole, and perform ion implantation into the drift layer to form a P-type source region; Step 3: Remove the blocking layer in Step 2, reform the blocking layer, etch the blocking layer to form a through hole, and perform ion implantation into the drift layer to form a low-resistance region; Step 4: Remove the blocking layer in Step 3, reform the blocking layer, etch the blocking layer to form a through hole, and perform ion implantation into the drift layer to form a P-type well region; Step 5: Remove the blocking layer in Step 4, reform the blocking layer, etch the blocking layer to form a through hole, and perform ion implantation into the P-type well region to form an N-type source region; Step 6: Remove the blocking layer in Step 5, reform the blocking layer, etch the blocking layer to form a through hole, etch the low-resistance region to form a first groove and a second groove, and deposit to form a first insulating dielectric layer and a second insulating dielectric layer; Step 7: Remove the blocking layer in Step 6, reform the blocking layer, etch the blocking layer to form a through hole, etch the first insulating dielectric layer and the second insulating dielectric layer to form a first trench and a second trench, and deposit metal to form a first gate metal layer and a second gate metal layer respectively; Step 8: Remove the blocking layer in Step 7, reform the blocking layer, etch the blocking layer to form a through hole, etch the low-resistance region to form a third groove, and deposit metal to form a first source metal layer; Step 9: Remove the blocking layer in Step 8, reform the blocking layer, etch the blocking layer to form a through hole, etch the P-type source region and the N-type source region, deposit metal to form a second source metal layer, and remove the blocking layer to complete the preparation; The lower side of the drift layer is connected to the upper side of the silicon carbide substrate, there is a convex portion on the drift layer, and there is a groove on the convex portion; The lower side of the P-type well region is connected to the upper side of the convex portion; the lower side of the N-type source region is connected to the upper side of the P-type well region; The P-type source region is connected to the upper side of the drift layer; the inner side of the P-type source region is connected to the outer side of the convex portion, the outer side of the P-type well region, and the outer side of the N-type source region; The low-resistance region is arranged in the groove; The lower part of the first insulating dielectric layer is arranged in the groove, and the lower side of the first insulating dielectric layer is connected to the upper side of the low-resistance region, and one side of the first insulating dielectric layer is connected to the inner side of the P-type well region and the inner side of the N-type source region; there is a first trench in the first insulating dielectric layer; The lower part of the second insulating dielectric layer is arranged in the groove, and the lower side of the second insulating dielectric layer is connected to the upper side of the low-resistance region, and one side of the second insulating dielectric layer is connected to the inner side of the P-type well region and the inner side of the N-type source region; there is a second trench in the second insulating dielectric layer; The first gate metal layer is arranged in the first trench; The second gate metal layer is arranged in the second trench; The lower part of the first source metal layer is disposed in the groove, and the lower side surface of the first source metal layer is connected to the upper side surface of the low-resistance region. The side surfaces of the first source metal layer are respectively connected to the other side surface of the first insulating dielectric layer and the other side surface of the second insulating dielectric layer; The second source metal layer is respectively connected to the P-type source region and the N-type source region.

2. The manufacturing method of a low-resistance separated trench-gate silicon carbide VDMOS according to claim 1, characterized in that: The silicon carbide substrate, the drift layer, and the low-resistance region are all N-type.

3. The manufacturing method of a low-resistance separated trench-gate silicon carbide VDMOS according to claim 1, wherein: The doping concentration of the low-resistance region is greater than that of the drift layer.

4. The manufacturing method of a low-resistance separated trench gate silicon carbide VDMOS according to claim 1, wherein: The doping concentration of the P-type source region is greater than that of the drift layer; the doping concentration of the P-type source region is greater than that of the N-type source region; the doping concentration of the P-type source region is greater than that of the P-type well region.

5. The manufacturing method of a low-resistance separated trench-gate silicon carbide VDMOS according to claim 1, characterized in that: The thickness of the left side wall of the first insulating dielectric layer is less than that of the right side wall.

6. The manufacturing method of a low-resistance separated trench gate silicon carbide VDMOS as described in claim 1, wherein: The thickness of the left side wall of the second insulating dielectric layer is greater than that of the right side wall.

7. A low-resistance isolated trench-gate silicon carbide VDMOS, characterized in that, The silicon carbide VDMOS is obtained by the preparation method described in any one of claims 1 to 6.

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