Gallium nitride and gallium arsenide three-dimensional heterogeneous integrated radio frequency chip and preparation method thereof

Abstract

The invention discloses a gallium nitride and gallium arsenide three-dimensional heterogeneous integrated radio frequency chip and a preparation method thereof. The structure comprises a back metal, a substrate, a gallium nitride device epitaxial layer, a bonding dielectric layer, a gallium arsenide device epitaxial layer, a gallium nitride device electrode source electrode, a gallium nitride device electrode grid electrode, a gallium arsenide device electrode drain electrode, a gallium arsenide device electrode source electrode, a gallium arsenide device electrode grid electrode, a gallium arsenide device electrode drain electrode and a gallium nitride back through hole from bottom to top, the gallium arsenide back through hole, the front through hole, the gallium nitride outer surface electrode source electrode, the gallium nitride outer surface electrode drain electrode and the electrode on the upper surface of the gallium arsenide device epitaxial layer are interconnected according to needs to form an integrated circuit with a certain function. According to the invention, the electrodes of the gallium nitride and gallium arsenide radio frequency devices have extremely small space spacing, the loss of long-distance transmission signals under high frequency and the influence of parasitic parameters are reduced, the chip area and the chip volume are reduced, and the packaging cost is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices, in particular to a three-dimensional heterogeneous integrated radio frequency chip of gallium nitride and gallium arsenide and a preparation method thereof. Background Art

[0002] With the advent of the 5G era, communication systems have higher technical requirements such as reducing volume, increasing density, improving efficiency, reducing energy consumption, and reducing costs. In addition to continuing to improve indicators in terms of communication speed, capacity, latency, and spatial range, post-5G and 6G communication systems also need to solve important problems encountered in the current 5G communication system solutions, namely high cost and high power consumption. In the process of evolution from 4G to 5G and post-5G and 6G communication systems, communication systems need to process more and more frequency bands; in addition, with the widespread application of massive multiple-input multiple-output (MIMO) technology and carrier aggregation technology, communication base stations and terminal equipment need to integrate large-scale arrays consisting of multiple RF transceiver modules and antennas, resulting in a sharp increase in system cost and power consumption. Due to the significant decrease in the efficiency of RF front-end modules in high-frequency bands, the extension of communication carrier frequencies to millimeter wave bands has further aggravated the power consumption of base stations and terminal electronic equipment. High-density system integration can effectively reduce the high cost and high power consumption of 5G, post-5G, and 6G communication equipment.

[0003] As a third-generation semiconductor, GaN has excellent characteristics such as large bandgap, high electron mobility, and high electron saturation velocity. It has broad application potential in the fields of next-generation RF devices, power and electrical devices, etc. GaN-based devices have the advantages of high power and high efficiency at the transmitting end, while GaAs-based devices have the advantages of low noise and high gain at the receiving end. Therefore, if high-density micro-nano heterogeneous integration of GaN and GaAs microwave chips can be achieved, it will be of great significance to solving the problems of current communication systems. However, GaN and GaAs still have many difficulties in material compatibility, process compatibility, thermal compatibility and electromagnetic compatibility.

[0004] Based on this, it is urgent to propose a three-dimensional heterogeneous integrated radio frequency chip structure of gallium nitride and gallium arsenide and a preparation method thereof. Summary of the invention

[0005] In order to solve the above technical problems, the present invention provides a gallium nitride and gallium arsenide three-dimensional heterogeneous integrated radio frequency chip and a preparation method thereof.

[0006] To achieve the above object, the present invention is implemented according to the following technical solutions:

[0007] One of the purposes of the present invention is to provide a three-dimensional heterogeneous integrated radio frequency chip of gallium nitride and gallium arsenide, which includes, from bottom to top, a back metal, a substrate, a gallium nitride device epitaxial layer, a bonding dielectric layer, and a gallium arsenide device epitaxial layer;

[0008] The upper surface of the gallium nitride device epitaxial layer is provided with a gallium nitride device electrode source, a gallium nitride device electrode gate, and a gallium nitride device electrode drain;

[0009] A gallium arsenide device electrode source, a gallium arsenide device electrode gate, and a gallium arsenide device electrode drain are arranged on the upper surface of the gallium arsenide device epitaxial layer;

[0010] A GaN back via is arranged to pass through the substrate and the GaN device epitaxial layer from bottom to top, and the GaN back via is connected to the back metal and the GaN device electrode source;

[0011] A GaAs back via is arranged to pass through the substrate, the bonding dielectric layer and the GaAs device epitaxial layer from bottom to top, and the GaAs back via is connected to the back metal and the GaAs device electrode source;

[0012] A front through hole is arranged to pass through the bonding dielectric layer and the gallium arsenide device epitaxial layer from bottom to top, and the gallium nitride device electrode gate and the gallium nitride device electrode drain buried in the bonding dielectric layer are connected to the gallium nitride outer surface electrode source and the gallium nitride outer surface electrode drain on the upper surface of the gallium arsenide device epitaxial layer through metals deposited in the front through hole respectively; the gallium nitride outer surface electrode source, the gallium nitride outer surface electrode drain, the gallium arsenide device electrode source, the gallium arsenide device electrode gate and the gallium arsenide device electrode drain on the upper surface of the gallium arsenide device epitaxial layer are interconnected as needed to form an integrated circuit.

[0013] The gallium nitride device epitaxial material and gallium arsenide device epitaxial material of the structure of the present invention are stacked in the same direction in three-dimensional heterogeneous integration by wafer-level bonding. The three-dimensional integrated wafer is in a same direction bonding structure, and shares the substrate used for gallium nitride epitaxy. The gallium nitride radio frequency device and the gallium arsenide radio frequency device are interconnected with the grounding metal on the back of the substrate through the back through hole, and with the electrode on the upper surface of the wafer material through the front through hole. In this way, the electrodes of the gallium nitride and gallium arsenide radio frequency devices have extremely small spatial spacing, reducing the loss of long-distance transmission signals at high frequencies and the influence of parasitic parameters, and reducing the chip area and chip volume, reducing the packaging cost, and realizing a high-density, high-performance, and multi-functional gallium nitride and gallium arsenide heterogeneous integrated radio frequency chip.

[0014] Furthermore, the material of the substrate is one of silicon carbide, silicon, gallium nitride, aluminum nitride, and diamond, with a thickness of 30-500 μm; the material of the bonding dielectric layer is one of silicon oxide, silicon nitride, aluminum oxide, and aluminum nitride, with a thickness of 10 nm-5 μm.

[0015] Furthermore, the material of the epitaxial layer of the gallium nitride device is a compound formed by one or more of gallium nitride, aluminum nitride, and indium nitride; the epitaxial layer of the gallium nitride device comprises, from bottom to top, a nitride nucleation layer, a nitride transition layer, a nitride buffer layer, a nitride channel layer, and a nitride barrier layer; the material of the nitride nucleation layer is aluminum nitride with a thickness of 50-300nm; the material of the nitride transition layer is graded aluminum gallium nitride or aluminum nitride / aluminum gallium nitride superlattice , with a thickness of 500-1000nm; the material of the nitride buffer layer is gallium nitride, with a thickness of 100-1000nm; the material of the nitride channel layer is gallium nitride or indium gallium nitride or aluminum gallium nitride, with a thickness of 50-500nm; the material of the nitride barrier layer is aluminum gallium nitride or indium aluminum nitride, with a thickness of 5-30nm; a two-dimensional electron gas is formed between the nitride channel layer and the nitride barrier layer, which serves as a conductive channel of the gallium nitride radio frequency device;

[0016] The material of the epitaxial layer of the GaAs device is a compound composed of one or more of GaAs, InAs, Aluminum Arsenide, and InP; the epitaxial layer of the GaAs device includes, from bottom to top, an arsenide buffer layer, an arsenide channel layer, an arsenide isolation layer, an arsenide barrier layer, and an arsenide cap layer; the material of the arsenide buffer layer is GaAs with a thickness of 50-1000nm; the material of the arsenide channel layer is GaAs or InGaAs with a thickness of 50-300nm; the arsenide isolation layer is made of GaAs or InGaAs with a thickness of 50-300nm; the The material of the layer is aluminum gallium arsenic or indium aluminum arsenic or indium aluminum gallium arsenic or indium phosphide or indium gallium phosphide, with a thickness of 1-5nm; the material of the arsenide barrier layer is aluminum gallium arsenic or indium aluminum arsenic or indium aluminum gallium arsenic or indium aluminum gallium arsenic or indium gallium phosphide, with a thickness of 5-30nm; the material of the arsenide cap layer is aluminum gallium arsenic or indium aluminum arsenic or indium aluminum gallium arsenic or indium aluminum gallium arsenic or indium gallium phosphide, with a thickness of 2-10nm; a two-dimensional electron gas is formed between the arsenide channel layer and the arsenide isolation layer as a conductive channel of the gallium arsenide device.

[0017] Furthermore, the electrode gate of the gallium nitride device is a multi-layer metal material, the bottom layer is one of Ni, Ti, TiN, and TaN, and the second layer or the second layer above the second layer is one or more of Al, Au, Ti, Ta, Pt, TiN, TaN, W, and Cu;

[0018] The electrode source of the gallium nitride device is a multi-layer metal material, the bottom two layers from bottom to top are Ti and Al, or Ta and Al, or Mo and Al; the metals of other layers include one or more of Ti, Al, Ni, Au, Mo, Pt, and W;

[0019] The electrode drain of the gallium nitride device is a multi-layer metal material, the bottom two layers from bottom to top are Ti and Al, or Ta and Al, or Mo and Al; the metals of other layers include one or more of Ti, Al, Ni, Au, Mo, Pt, and W;

[0020] The electrode gate of the GaAs device is a multi-layer metal material, the bottom layer is one of Ti, Ta, Ni, TiN, and TaN, and the second layer or the second layer above the second layer is one or more of Al, Au, Ti, Ta, Pt, TiN, TaN, W, and Cu;

[0021] The electrode drain of the GaAs device is a multi-layer metal material, the bottom two layers from bottom to top are Ni and Ge, or Mo and Al; the metals of other layers include one or more of Ni and Au;

[0022] The electrode source of the GaAs device is a multi-layer metal material, wherein the bottom two layers from bottom to top are Ni and Ge, or Mo and Al; the metals of other layers include one or more of Ni and Au.

[0023] Furthermore, the back metal, the metal deposited in the front through hole and the metal material in the gallium nitride back through hole are all multilayer metal materials, and the multilayer metal material is one of Ni / Au, Ti / Au, Ni / Cu and Ti / Cu from bottom to top.

[0024] The second object of the present invention is to provide a method for preparing a three-dimensional heterogeneous integrated radio frequency chip of gallium nitride and gallium arsenide, comprising the following steps:

[0025] S1: epitaxially growing a GaN device epitaxial layer on a substrate to obtain an original GaN wafer;

[0026] S2: performing process preparation of gallium nitride devices on the original gallium nitride wafer obtained in step S1;

[0027] S3: Selecting a second substrate, epitaxially growing a GaAs device epitaxial layer, and obtaining an original GaAs wafer; the material of the second substrate is GaAs or silicon;

[0028] S4: bonding the transition carrier to the front side of the original GaAs wafer obtained in step S3 to obtain a first GaAs wafer;

[0029] S5: removing the second substrate of the first gallium arsenide wafer obtained in step S4 to obtain a second gallium arsenide wafer, wherein the back side of the gallium arsenide device epitaxial layer of the second gallium arsenide wafer is exposed to the outside;

[0030] S6: bonding the second gallium arsenide wafer obtained in step S5 to the original gallium nitride wafer obtained in step S2 and prepared by the gallium nitride device process to obtain a first heterogeneous integrated wafer, wherein the back side of the second gallium arsenide wafer is connected to the front side of the gallium nitride device epitaxial layer of the original gallium nitride wafer through a bonding dielectric layer;

[0031] S7: removing the transition carrier of the first heterogeneous integrated wafer obtained in step S5, exposing the front side of the epitaxial layer of the gallium arsenide device to the outside, and obtaining the gallium nitride and gallium arsenide three-dimensional heterogeneous integrated wafer proposed by the present invention;

[0032] S8: performing a process for preparing a gallium arsenide device on the three-dimensional heterogeneous integrated wafer obtained in step S6;

[0033] S9: etching the epitaxial layer and bonding dielectric layer of the GaAs device in some areas, making front through holes, depositing metal in the front through holes, and interconnecting the front electrodes of the three-dimensional heterogeneous integrated wafer;

[0034] S9: etching the substrate and the epitaxial layer of the gallium nitride device in a partial area to form a gallium nitride back via; etching the substrate, the epitaxial layer of the gallium nitride device, the bonding dielectric layer and the epitaxial layer of the gallium arsenide device in a partial area to form a gallium arsenide back via;

[0035] S10: Depositing back metal on the back side of the substrate and in the GaN back vias and GaAs back vias to produce a GaN and GaAs three-dimensional heterogeneous integrated RF chip.

[0036] Compared with the prior art, the present invention has the following beneficial effects:

[0037] 1) The present invention adopts a material structure combining gallium nitride and gallium arsenide, breaking through the performance limitations of single material devices and synergistically improving the power, efficiency and noise performance of the millimeter wave RF front end;

[0038] 2) The gallium nitride device and the gallium arsenide device of the present invention are stacked in the same direction in three-dimensional heterogeneous integration, with high integration density, short metal interconnection distance, small footprint, minimum space spacing, and the silicon carbide substrate of the gallium nitride wafer is helpful for heat dissipation of high-power devices;

[0039] 3) The three-dimensional heterogeneous integrated wafer of the present invention uses a substrate used for gallium nitride epitaxy, which has high thermal conductivity, improves the heat dissipation capacity of the heterogeneous integrated radio frequency new chip, and thus has better output power and efficiency;

[0040] 4) The present invention first completes the gallium nitride device process preparation and then performs wafer bonding, manufactures a three-dimensional heterogeneous integrated wafer and performs gallium arsenide process preparation. The gallium nitride device process technology selection is flexible and the process flow is highly compatible.

[0041] 5) The gallium nitride and gallium arsenide epitaxial material growth and device processing and preparation of the present invention are carried out using existing mature process technologies, with low cost and high solution feasibility. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 It is a schematic structural diagram of a gallium nitride and gallium arsenide three-dimensional heterogeneous integrated radio frequency chip provided in an embodiment of the present invention.

[0043] Figure 2 A schematic flow chart of a method for preparing a three-dimensional heterogeneously integrated radio frequency chip of gallium nitride and gallium arsenide provided in an embodiment of the present invention.

[0044] Figure 3 A schematic diagram of a device flow chart of a method for preparing a three-dimensional heterogeneous integrated radio frequency chip of gallium nitride and gallium arsenide provided in an embodiment of the present invention.

[0045] Description of reference numerals:

[0046] 1-back metal; 2-substrate; 3-gallium nitride device epitaxial layer; 4-bonding dielectric layer; 5-gallium nitride back via; 6-gallium arsenide back via; 61-gallium nitride device electrode source; 62-gallium nitride device electrode gate; 63-gallium nitride device electrode drain; 7-front via; 71-gallium arsenide device electrode source; 72-gallium arsenide device electrode gate; 73-gallium arsenide device electrode drain; 8-gallium arsenide device epitaxial layer; 621-gallium nitride outer surface electrode source; 631-gallium nitride outer surface electrode drain; 14-transition carrier. DETAILED DESCRIPTION

[0047] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with embodiments. The specific embodiments described herein are only used to explain the present invention and are not used to limit the invention.

[0048] like Figure 1As shown, this embodiment exemplarily shows a gallium nitride and gallium arsenide three-dimensional heterogeneous integrated radio frequency chip, which includes a back metal 1, a substrate 2, a gallium nitride device epitaxial layer 3, a bonding dielectric layer 4, and a gallium arsenide device epitaxial layer 8 from bottom to top; the upper surface of the gallium nitride device epitaxial layer 3 is provided with a gallium nitride device electrode source 61, a gallium nitride device electrode gate 62, and a gallium nitride device electrode drain 63; the upper surface of the gallium arsenide device epitaxial layer 8 is provided with a gallium arsenide device electrode source 71, a gallium arsenide device electrode gate 72, and a gallium arsenide device electrode drain 73; a gallium nitride back via 2 is provided to pass through the substrate 2 and the gallium nitride device epitaxial layer 3 from bottom to top, and a gallium nitride back via 5 connects the back metal 1 and the gallium nitride device electrode source 61; a gallium arsenide back via 6 is provided to pass through the substrate 2 and the bonding dielectric layer 3 from bottom to top. Layer 4 and GaAs device epitaxial layer 8, GaAs back via 6 connects back metal 1 and GaAs device electrode source 71; front via 7 is set to pass through bonding dielectric layer 4 and GaAs device epitaxial layer 8 from bottom to top to connect GaN device electrode gate 62 and GaN device electrode drain 63 buried in bonding dielectric layer 4 to GaN outer surface electrode source 621 and GaN outer surface electrode drain 631 on the upper surface of GaAs device epitaxial layer 8 respectively through metal deposited in front via 7; GaN outer surface electrode source 621, GaN outer surface electrode drain 631, GaAs device electrode source 71, GaAs device electrode gate 72 and GaAs device electrode drain 73 on the upper surface of GaAs device epitaxial layer 8 are interconnected as needed to form an integrated circuit.

[0049] The principle of this embodiment is: the epitaxial material of the gallium nitride device and the epitaxial material of the gallium arsenide device are bonded at the wafer level to achieve unidirectional stacked three-dimensional heterogeneous integration. The three-dimensional integrated wafer has a unidirectional bonding structure and shares the substrate used for gallium nitride epitaxy. The gallium nitride RF device and the gallium arsenide RF device are interconnected with the grounding metal on the back of the substrate through the back through hole and with the electrode on the upper surface of the wafer material through the front through hole. In this way, the electrodes of the gallium nitride and gallium arsenide RF devices have extremely small spatial spacing, reducing the loss of long-distance transmission signals at high frequencies and the influence of parasitic parameters, and reducing the chip area and chip volume, reducing the packaging cost, and realizing a high-density, high-performance, and multi-functional gallium nitride and gallium arsenide heterogeneous integrated RF chip.

[0050] In this embodiment, the material of the substrate 2 can be one of silicon carbide, silicon, gallium nitride, aluminum nitride, and diamond substrate, with a thickness of 30-500 μm. Preferably, the material of the substrate 2 is silicon carbide, with a thickness of 100 μm.

[0051] In this embodiment, the material of the bonding dielectric layer 4 can be one or more of silicon oxide, silicon nitride, aluminum oxide, and aluminum nitride, with a thickness of 10nm-5μm. Preferably, the material of the bonding dielectric layer 4 can be silicon oxide, with a thickness of 500nm.

[0052] In this embodiment, the epitaxial layer 3 of the gallium nitride device includes a nitride nucleation layer, a nitride transition layer, a nitride buffer layer, a nitride channel layer, and a nitride barrier layer. The material of the nitride nucleation layer is aluminum nitride with a thickness of 50-300nm; the material of the nitride transition layer is gradient aluminum gallium nitride, or aluminum nitride / aluminum gallium nitride superlattice, with a thickness of 500-1000nm; the material of the nitride buffer layer is gallium nitride with a thickness of 100-1000nm; the material of the nitride channel layer is gallium nitride, or indium gallium nitride, or aluminum gallium nitride, with a thickness of 50-500nm; the material of the nitride barrier layer is aluminum gallium nitride, or indium aluminum nitride, with a thickness of 5-30nm. A two-dimensional electron gas is formed between the nitride channel layer and the nitride barrier layer as a conductive channel of the gallium nitride radio frequency device. Preferably, the material of the nitride nucleation layer is aluminum nitride with a thickness of 200nm; the material of the nitride transition layer is gradient aluminum gallium nitride with a thickness of 8000nm; the material of the nitride buffer layer is gallium nitride with a thickness of 500nm; the material of the nitride channel layer is gallium nitride with a thickness of 200nm; and the material of the nitride barrier layer is aluminum gallium nitride with a thickness of 20nm.

[0053] In this embodiment, the material of the gallium arsenide device epitaxial layer 8 is a group III arsenide or group III phosphide material, which is a compound composed of one or more of gallium arsenide, indium arsenide, aluminum arsenide, and indium phosphide; the gallium arsenide device epitaxial layer 8 includes an arsenide buffer layer, an arsenide channel layer, an arsenide isolation layer, an arsenide barrier layer, and an arsenide cap layer. The material of the arsenide buffer layer is gallium arsenide with a thickness of 50-1000nm; the material of the arsenide channel layer is gallium arsenide, or indium gallium arsenide with a thickness of 1000nm. The thickness of the arsenide barrier layer is 50-300nm; the material of the arsenide isolation layer is aluminum gallium arsenide, or indium aluminum arsenic, or indium aluminum gallium arsenic, or indium phosphide, or indium gallium phosphide, with a thickness of 1-5nm; the material of the arsenide barrier layer is aluminum gallium arsenide, or indium aluminum arsenic, or indium aluminum gallium arsenic, or indium aluminum gallium arsenic, or indium gallium phosphide, with a thickness of 5-30nm; the material of the arsenide cap layer is aluminum gallium arsenide, or indium aluminum arsenic, or indium aluminum gallium arsenic, or indium aluminum gallium arsenic, or indium gallium phosphide, with a thickness of 2-10nm. A two-dimensional electron gas is formed between the arsenide channel layer and the arsenide isolation layer as a conductive channel of the gallium arsenide device. Preferably, the material of the arsenide buffer layer is gallium arsenide with a thickness of 500nm; the material of the arsenide channel layer is indium gallium arsenide with a thickness of 100nm; the material of the arsenide isolation layer is indium gallium phosphide with a thickness of 3nm; the material of the arsenide barrier layer is indium aluminum arsenic with a thickness of 20nm; the material of the arsenide cap layer is indium gallium phosphide with a thickness of 5nm.

[0054] In this embodiment, the bottom layer of the material of the GaN device electrode gate 62 is Ni, or Ti, or TiN, or TaN, and the second layer or the second layer above the second layer is one or more of Al, Au, Ti, Ta, Pt, TiN, TaN, W, and Cu. Preferably, the material of the GaN device electrode gate 62 is Ni and Au from bottom to top, with thicknesses of 50nm and 400nm respectively;

[0055] In this embodiment, the bottom two layers of the material of the gallium nitride device electrode source 61 are Ti, Al, or Ta, Al, or Mo, Al from bottom to top; the metals of other layers include one or more of Ti, Al, Ni, Au, Mo, Pt, and W. Preferably, the material of the gallium nitride device electrode source 83 is Ti, Al, Ni, and Au from bottom to top. The thicknesses are 20nm, 120nm, 40nm, and 50nm, respectively.

[0056] In this embodiment, the bottom two layers of the material of the GaN device electrode drain 61 are Ti, Al, or Ta, Al, or Mo, Al from bottom to top; the metals of other layers include one or more of Ti, Al, Ni, Au, Mo, Pt, and W. Preferably, the material of the GaN device electrode drain 63 is Ti, Al, Ni, and Au from bottom to top, with thicknesses of 20nm, 120nm, 40nm, and 50nm, respectively.

[0057] In this embodiment, the bottom layer of the material of the GaAs device electrode gate 72 is Ti, or Ta, or Ni, or TiN, or TaN, and the second layer or the second layer above the second layer is one or more of Al, Au, Ti, Ta, Pt, TiN, TaN, W, and Cu. Preferably, the material of the GaAs device electrode gate 72 is Ti, Pt, and Au from bottom to top, with a thickness of 50nm, 50nm, and 300nm.

[0058] In this embodiment, the bottom two layers of the material of the GaAs device electrode drain 71 are Ni, Ge, or Mo, Al from bottom to top, and the metals of other layers include one or more of Ni and Au. Preferably, the material of the GaAs device electrode drain 71 is Ni, Ge, Au, Ni, Au from bottom to top; the thickness is 5nm, 20nm, 100nm, 25nm, 100nm.

[0059] In this embodiment, the bottom two layers of the material of the GaAs device electrode source 73 are Ni, Ge, or Mo, Al from bottom to top, and the metals of other layers include one or more of Ni and Au. Preferably, the material of the GaAs device electrode source 73 is Ni, Ge, Au, Ni, Au from bottom to top, with a thickness of 5nm, 20nm, 100nm, 25nm, 100nm.

[0060] In this embodiment, the back metal, the metal deposited in the front through hole 7, and the metal material in the gallium nitride back through hole are all multilayer metal materials, and the multilayer metal material is one of Ni / Au, Ti / Au, Ni / Cu, and Ti / Cu from bottom to top. Preferably, the back metal 1, the metal deposited in the front through hole 7, and the metal material in the gallium nitride back through hole are Ti / Au, with a thickness of 100nm and 5μm.

[0061] Reference Figure 2 , Figure 3 When preparing the above-mentioned gallium nitride and gallium arsenide three-dimensional heterogeneous integrated radio frequency chip, the specific preparation process is as follows:

[0062] S1: epitaxially grow a GaN device epitaxial layer on a selected substrate to obtain an original GaN wafer;

[0063] S2: performing process preparation of gallium nitride devices on the original gallium nitride wafer obtained in step S1;

[0064] S3: Selecting a second substrate, epitaxially growing a GaAs device epitaxial layer, and obtaining an original GaAs wafer; the material of the second substrate may be GaAs or silicon;

[0065] S4: bonding the transition wafer to the front side of the original GaAs wafer obtained in step S3 to obtain a first GaAs wafer;

[0066] S5: removing the second substrate of the first gallium arsenide wafer obtained in step S3 to obtain a second gallium arsenide wafer, wherein the back side of the gallium arsenide device epitaxial layer of the second gallium arsenide wafer is exposed to the outside;

[0067] S6: bonding the second gallium arsenide wafer obtained in step S4 to the original gallium nitride wafer obtained in step S2 and prepared by the gallium nitride device process to obtain a first heterogeneous integrated wafer, wherein the back side of the second gallium arsenide wafer is connected to the front side of the gallium nitride device epitaxial layer of the original gallium nitride wafer through a bonding dielectric layer;

[0068] S6: removing the transition carrier of the first heterogeneous integrated wafer obtained in step S5, exposing the front side of the epitaxial layer of the gallium arsenide device to the outside, and obtaining the gallium nitride and gallium arsenide three-dimensional heterogeneous integrated wafer proposed by the present invention.

[0069] S7: performing a process for preparing a gallium arsenide device on the three-dimensional heterogeneous integrated wafer obtained in step S6;

[0070] S8: etching the epitaxial layer and bonding dielectric layer of the GaAs device in some areas, making front through holes, depositing metal in the front through holes, and interconnecting the front electrodes of the three-dimensional heterogeneous integrated wafer;

[0071] S9: etching the substrate and the epitaxial layer of the gallium nitride device in a partial area to form a gallium nitride back via; etching the substrate, the epitaxial layer of the gallium nitride device, the bonding dielectric layer and the epitaxial layer of the gallium arsenide device in a partial area to form a gallium arsenide back via;

[0072] S10: depositing back metal on the back side of the substrate and in the GaN back via and the GaAs back via.

[0073] At this point, the preparation of three-dimensional heterogeneous vertical integrated devices of gallium nitride devices and gallium arsenide devices has been completed.

[0074] The technical solution of the present invention is not limited to the above-mentioned specific embodiments. All technical variations made according to the technical solution of the present invention fall within the protection scope of the present invention.

Claims

1. A three-dimensional heterogeneous integrated radio frequency chip of gallium nitride and gallium arsenide, comprising, from bottom to top, a back metal (1), a substrate (2), a gallium nitride device epitaxial layer (3), a bonding dielectric layer (4), and a gallium arsenide device epitaxial layer (8); characterized in that: The upper surface of the gallium nitride device epitaxial layer (3) is provided with a gallium nitride device electrode source (61), a gallium nitride device electrode gate (62), and a gallium nitride device electrode drain (63); A gallium arsenide device electrode source (71), a gallium arsenide device electrode gate (72), and a gallium arsenide device electrode drain (73) are arranged on the upper surface of the gallium arsenide device epitaxial layer (8); A gallium nitride back via (5) is provided to pass through the substrate (2) and the gallium nitride device epitaxial layer (3) from bottom to top, and the gallium nitride back via (5) connects the back metal (1) and the gallium nitride device electrode source (61); A gallium arsenide back via (6) is provided to pass through the substrate (2), the bonding dielectric layer (4) and the gallium arsenide device epitaxial layer (8) from bottom to top, and the gallium arsenide back via (6) connects the back metal (1) and the gallium arsenide device electrode source (71); A front through hole (7) is provided to pass through the bonding dielectric layer (4) and the gallium arsenide device epitaxial layer (8) from bottom to top, and the gallium nitride device electrode gate (62) and the gallium nitride device electrode drain (63) buried in the bonding dielectric layer (4) are respectively connected to the gallium nitride outer surface electrode source (621) and the gallium nitride outer surface electrode drain (631) on the upper surface of the gallium arsenide device epitaxial layer (8) through metal deposited in the front through hole (7); the gallium nitride outer surface electrode source (621), the gallium nitride outer surface electrode drain (631), the gallium arsenide device electrode source (71), the gallium arsenide device electrode gate (72) and the gallium arsenide device electrode drain (73) on the upper surface of the gallium arsenide device epitaxial layer (8) are interconnected as needed to form an integrated circuit.

2. The gallium nitride and gallium arsenide three-dimensional heterogeneous integrated radio frequency chip according to claim 1, characterized in that: The material of the substrate (2) is one of silicon carbide, silicon, gallium nitride, aluminum nitride, and diamond, and has a thickness of 30-500 μm; the material of the bonding medium layer (4) is one of silicon oxide, silicon nitride, aluminum oxide, and aluminum nitride, and has a thickness of 10 nm-5 μm.

3. The gallium nitride and gallium arsenide three-dimensional heterogeneous integrated radio frequency chip according to claim 1, characterized in that: The material of the gallium nitride device epitaxial layer (3) is a compound formed by one or more of gallium nitride, aluminum nitride, and indium nitride; the gallium nitride device epitaxial layer (3) comprises, from bottom to top, a nitride nucleation layer, a nitride transition layer, a nitride buffer layer, a nitride channel layer, and a nitride barrier layer; the material of the nitride nucleation layer is aluminum nitride with a thickness of 50-300nm; the material of the nitride transition layer is graded aluminum gallium nitride or aluminum nitride / aluminum gallium nitride superlattice , with a thickness of 500-1000nm; the material of the nitride buffer layer is gallium nitride, with a thickness of 100-1000nm; the material of the nitride channel layer is gallium nitride or indium gallium nitride or aluminum gallium nitride, with a thickness of 50-500nm; the material of the nitride barrier layer is aluminum gallium nitride or indium aluminum nitride, with a thickness of 5-30nm; a two-dimensional electron gas is formed between the nitride channel layer and the nitride barrier layer, which serves as a conductive channel of the gallium nitride radio frequency device; The material of the gallium arsenide device epitaxial layer (8) is a compound composed of one or more of gallium arsenide, indium arsenide, aluminum arsenide, and indium phosphide; the gallium arsenide device epitaxial layer (8) comprises, from bottom to top, an arsenide buffer layer, an arsenide channel layer, an arsenide isolation layer, an arsenide barrier layer, and an arsenide cap layer; the material of the arsenide buffer layer is gallium arsenide, with a thickness of 50-1000nm; the material of the arsenide channel layer is gallium arsenide or indium gallium arsenide, with a thickness of 50-300nm; the The material of the material isolation layer is aluminum gallium arsenide or indium aluminum arsenic or indium aluminum gallium arsenic or indium phosphide or indium gallium phosphide, with a thickness of 1-5nm; the material of the arsenide barrier layer is aluminum gallium arsenic or indium aluminum arsenic or indium aluminum gallium arsenic or indium aluminum gallium arsenic or indium gallium phosphide, with a thickness of 5-30nm; the material of the arsenide cap layer is aluminum gallium arsenic or indium aluminum arsenic or indium aluminum gallium arsenic or indium aluminum gallium arsenic or indium gallium phosphide, with a thickness of 2-10nm; a two-dimensional electron gas is formed between the arsenide channel layer and the arsenide isolation layer as a conductive channel of the gallium arsenide device.

4. The gallium nitride and gallium arsenide three-dimensional heterogeneous integrated radio frequency chip according to claim 1, characterized in that: The electrode grid (62) of the gallium nitride device is a multi-layer metal material, the bottom layer is one of Ni, Ti, TiN, and TaN, and the second layer or the second layer above the second layer is one or more of Al, Au, Ti, Ta, Pt, TiN, TaN, W, and Cu; The gallium nitride device electrode source (61) is a multi-layer metal material, the bottom two layers from bottom to top are Ti and Al, or Ta and Al, or Mo and Al; the metals of other layers include one or more of Ti, Al, Ni, Au, Mo, Pt, and W; The gallium nitride device electrode drain (63) is a multi-layer metal material, the bottom two layers from bottom to top are Ti and Al, or Ta and Al, or Mo and Al; the metals of other layers include one or more of Ti, Al, Ni, Au, Mo, Pt, and W; The electrode grid (72) of the gallium arsenide device is a multi-layer metal material, the bottom layer is one of Ti, Ta, Ni, TiN, and TaN, and the second layer or the material above the second layer is one or more of Al, Au, Ti, Ta, Pt, TiN, TaN, W, and Cu; The GaAs device electrode drain (71) is a multi-layer metal material, the bottom two layers from bottom to top are Ni and Ge, or Mo and Al; the metals of other layers include one or more of Ni and Au; The gallium arsenide device electrode source (73) is a multi-layer metal material, the bottom two layers from bottom to top are Ni and Ge, or Mo and Al; the metals of other layers include one or more of Ni and Au.

5. The gallium nitride and gallium arsenide three-dimensional heterogeneous integrated radio frequency chip according to claim 1, characterized in that: The back metal (1), the metal deposited in the front through hole (7) and the metal material in the gallium nitride back through hole (5) are all multi-layer metal materials, and the multi-layer metal material is one of Ni / Au, Ti / Au, Ni / Cu and Ti / Cu from bottom to top.

6. A method for preparing a three-dimensional heterogeneous integrated radio frequency chip of gallium nitride and gallium arsenide as claimed in any one of claims 1 to 5, characterized in that: The following steps are involved: S1: epitaxially growing a gallium nitride device epitaxial layer (3) on a substrate (2) to obtain an original gallium nitride wafer; S2: performing process preparation of gallium nitride devices on the original gallium nitride wafer obtained in step S1; S3: selecting a second substrate, epitaxially growing a gallium arsenide device epitaxial layer (8), and obtaining an original gallium arsenide wafer; the material of the second substrate is gallium arsenide or silicon; S4: bonding the transition carrier (14) to the front side of the original gallium arsenide wafer obtained in step S3 to obtain a first gallium arsenide wafer; S5: removing the second substrate of the first gallium arsenide wafer obtained in step S4 to obtain a second gallium arsenide wafer, wherein the back side of the gallium arsenide device epitaxial layer (8) of the second gallium arsenide wafer is exposed to the outside; S6: bonding the second gallium arsenide wafer obtained in step S5 to the original gallium nitride wafer obtained in step S2 and prepared by the gallium nitride device process to obtain a first heterogeneous integrated wafer, wherein the back surface of the second gallium arsenide wafer is connected to the front surface of the gallium nitride device epitaxial layer (3) of the original gallium nitride wafer via a bonding dielectric layer (4); S7: removing the transition carrier (14) of the first heterogeneous integrated wafer obtained in step S5, exposing the front side of the gallium arsenide device epitaxial layer (8) to the outside, and obtaining the gallium nitride and gallium arsenide three-dimensional heterogeneous integrated wafer proposed by the present invention; S8: performing a process for preparing a gallium arsenide device on the three-dimensional heterogeneous integrated wafer obtained in step S6; S9: etching the gallium arsenide device epitaxial layer (8) and the bonding dielectric layer (4) in a partial area, making a front through hole (7), depositing metal in the front through hole (7), and interconnecting the front electrodes of the three-dimensional heterogeneous integrated wafer; S9: etching a portion of the substrate (2) and the gallium nitride device epitaxial layer (3) to form a gallium nitride back via (5); etching a portion of the substrate (2), the gallium nitride device epitaxial layer (3), the bonding dielectric layer (4) and the gallium arsenide device epitaxial layer (8) to form a gallium arsenide back via (6); S10: Depositing a back metal (1) on the back side of the substrate (2) and in the gallium nitride back via (5) and the gallium arsenide back via (6) to produce a gallium nitride and gallium arsenide three-dimensional heterogeneous integrated radio frequency chip.

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