Integrated circuit device and manufacturing method thereof

Abstract

In an integrated circuit device according to an embodiment and a method of manufacturing the same, in a structure including a backside power distribution network for a device region having an area reduced based on size reduction, a contact fusion bridge is formed on a source / drain contact, and thus, difficulty of a manufacturing process may be reduced and electrical characteristics may be enhanced.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0131943 filed on October 4, 2023, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The inventive concept relates to an integrated circuit device and a method of manufacturing the same, and more particularly, to an integrated circuit device including a back side power distribution network (BSPDN) and a method of manufacturing the same. Background Art

[0003] The progress of electronic technology has promoted the rapid shrinkage of integrated circuit devices. In highly shrunk integrated circuit devices, because high operating precision and fast operating speed are required, a wiring structure with a stable and / or optimized structure may be required in a relatively small area. For this reason, integrated circuit devices including a power distribution network on the back have been developed, but there may still be a need for improvement. Summary of the invention

[0004] The inventive concept provides an integrated circuit device having a structure for enhancing reliability of electrical connections in the integrated circuit device, the structure including a device region having an area reduced based on downsizing.

[0005] The embodiments of the inventive concept are not limited to the above, and other embodiments not explicitly described herein will be clearly understood by those of ordinary skill in the art from the following description.

[0006] An integrated circuit device according to an embodiment includes: a pair of fin-type active regions, the pair of fin-type active regions are arranged spaced apart from each other in a second horizontal direction intersecting the first horizontal direction to protrude from a back insulating structure in a vertical direction and extend longitudinally in the first horizontal direction; a device isolation layer on opposite sidewalls of the pair of fin-type active regions; a pair of source / drain regions on the pair of fin-type active regions; an interlayer insulating layer on the pair of source / drain regions and the device isolation layer; a through-hole power rail extending longitudinally in the first horizontal direction between the pair of fin-type active regions and extending through the interlayer insulating layer and the device isolation layer in a vertical direction; a pair of source / drain contacts arranged in the first horizontal direction. The invention relates to a power rail wiring, which extends in a horizontal direction to contact the pair of source / drain regions, and the through-hole power rail is located between the pair of source / drain contacts; a contact fusion bridge, which is on the through-hole power rail and the first source / drain contact of the pair of source / drain contacts and is electrically connected to the through-hole power rail and the first source / drain contact; a contact isolation insulating layer, which is on the through-hole power rail and the second source / drain contact of the pair of source / drain contacts; a through-hole structure, which is on the second source / drain contact; and a power rail wiring, which extends in a vertical direction through the back insulating structure and contacts the through-hole power rail, wherein the first source / drain contact and the contact fusion bridge are arranged as a single structure without a boundary surface therebetween.

[0007] An integrated circuit device according to an embodiment includes: an upper back-side insulating structure including a protruding portion and a lower back-side insulating structure on a lower surface of the upper back-side insulating structure opposite to the protruding portion; a pair of fin-type active regions on the protruding portion of the upper back-side insulating structure and extending longitudinally in a first horizontal direction; a device isolation layer on opposite sidewalls of each of the pair of fin-type active regions; a pair of nanosheet stacks disposed on a first portion of the pair of fin-type active regions; a gate electrode extending longitudinally on the pair of fin-type active regions to cross the pair of fin-type active regions and extending on the pair of nanosheet stacks; a pair of source / drain regions on a second portion of the pair of fin-type active regions; an interlayer insulating layer on the pair of source / drain regions and the device isolation layer; a through-hole power rail extending longitudinally in the first horizontal direction between the pair of fin-type active regions The invention relates to a device for manufacturing a power rail having a through hole and a power rail connected to the through hole. The device comprises a pair of source / drain contacts arranged to contact the pair of source / drain regions at intervals, a through hole power rail between the pair of source / drain contacts, a contact bridge on the through hole power rail and a first source / drain contact of the pair of source / drain contacts, a through hole structure on a second source / drain contact of the pair of source / drain contacts, and a power rail wiring extending in a vertical direction through an upper back side insulating structure and a lower back side insulating structure and contacting the through hole power rail, wherein an angle between a bottom surface of the contact bridge and a side wall is an acute angle, the bottom surface of the contact bridge is on an upper surface of the through hole power rail, and wherein an angle between a bottom surface of the through hole structure and a side wall is an obtuse angle, the bottom surface of the through hole structure is on an upper surface of the second source / drain contact.

[0008] A method for manufacturing an integrated circuit device according to an embodiment includes: forming a pair of fin-type active regions arranged spaced apart from each other in a second horizontal direction intersecting a first horizontal direction on a substrate to protrude in a vertical direction and extend longitudinally in the first horizontal direction; forming a device isolation layer on opposite sidewalls of each of the pair of fin-type active regions; forming a pair of source / drain regions on the pair of fin-type active regions; forming an interlayer insulating layer on the pair of source / drain regions and the device isolation layer; forming a through-hole power rail extending longitudinally along the first horizontal direction between the pair of fin-type active regions and extending through the interlayer insulating layer and the device isolation layer in the vertical direction; etching each of the pair of source / drain regions; and etching the through-hole power rail. a portion of each and a portion of the interlayer insulating layer therebetween to form a contact preliminary hole; forming a contact material layer in the contact preliminary hole and on the upper surface of the interlayer insulating layer; patterning the contact material layer to simultaneously form a pair of source / drain contacts spaced apart from each other in a second horizontal direction with a through-hole power rail located therebetween and a contact fusion bridge contacting at least a portion of the upper surface of the through-hole power rail; forming an upper insulating layer on the contact fusion bridge and the interlayer insulating layer; forming a through-hole structure extending through the upper insulating layer in a vertical direction; removing the substrate to form a back-side insulating structure in the region where the substrate is removed; and forming a power rail wiring extending through the back-side insulating structure in a vertical direction and contacting the through-hole power rail. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a diagram showing a plan layout of a unit block of an integrated circuit device according to an embodiment;

[0011] Figure 2 is a plan layout diagram showing an integrated circuit device according to an embodiment;

[0012] Figure 3 is along Figure 2 A cross-sectional view taken along line AA';

[0013] Figure 4 is along Figure 2 A cross-sectional view taken along line BB';

[0014] Figure 5 is along Figure 2 A cross-sectional view taken along line CC';

[0015] Figure 6 yes Figure 3 An enlarged cross-sectional view of a region DD;

[0016] Figure 7 and Figure 8is a cross-sectional view showing an integrated circuit device according to another embodiment;

[0017] Fig. 9 is a flow chart showing a method for manufacturing an integrated circuit device according to an embodiment;

[0018] Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 , Fig.16 , Fig.17 , Fig.18 , Fig.19 , Fig. 20 , Fig.21 , Fig. 22 , Fig.23 and Fig.24 is a diagram showing a method of manufacturing an integrated circuit device in a process sequence according to an embodiment;

[0019] Fig.25 and Fig.26 is a cross-sectional view corresponding to an active pattern of an integrated circuit device according to an embodiment; and

[0020] Fig. 27 is a block diagram illustrating a system including an integrated circuit device according to an embodiment. DETAILED DESCRIPTION

[0021] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. The terms "first", "second", etc. may be used herein only to distinguish one component, layer, direction, etc. from another component, layer, direction, etc. When used herein, the terms "include", "comprise", "contain", "have", and / or "contain" specify the presence of stated elements, but do not exclude the presence of other elements. The term "and / or" includes any and all combinations of one or more of the items listed in association. The term "connection" may be used herein to refer to physical connections and / or electrical connections. When a component or layer is referred to herein as "directly" on ... or "directly in contact ..." or "directly connected ...", there is no intermediate component or layer. Similarly, when components are "directly" adjacent to each other, there may be no intermediate component.

[0022] Figure 1 is a diagram showing a planar layout of a unit block 12 of an integrated circuit device 10 according to an embodiment.

[0023] Reference Figure 1 , the cell block 12 of the integrated circuit device 10 may include a plurality of logic cells LC including circuit patterns for configuring various circuits.

[0024] The plurality of logic cells LC may be arranged in a matrix form along a first horizontal direction (eg, an X direction) and a second horizontal direction (eg, a Y direction) in the cell block 12 .

[0025] The plurality of logic cells LC may include a circuit pattern having a layout designed based on a placement and routing (PnR) technology so as to perform at least one logic function. The plurality of logic cells LC may have functions of performing various logic functions. In some embodiments, each of the plurality of logic cells LC may include a plurality of standard cells. In some embodiments, at least some of the plurality of logic cells LC may perform the same logic function. In other embodiments, at least some of the plurality of logic cells LC may perform different logic functions.

[0026] The plurality of logic cells LC may include various logic cells, each of which includes a plurality of circuit elements. For example, each of the plurality of logic cells LC may be configured to implement AND, NAND, OR, NOR, XOR, XNOR, INV, ADD, BUF, DLY, FIL, MUX (MXT / MXIT), OR / AND / INVERTER (OAI), AND / OR (AO), AND / OR / INVERTER (AOI), D flip-flop, reset flip-flop, master-slave flip-flop, latch, or a combination thereof, but is not limited thereto.

[0027] In the cell block 12, at least some of the plurality of logic cells LC configuring a row R1, R2, R3, R4, R5, or R6 may have the same width in the first horizontal direction (X direction). In addition, at least some of the plurality of logic cells LC configuring a row R1, R2, R3, R4, R5, or R6 may have the same height. However, the inventive concept is not limited to the illustration, and at least some of the plurality of logic cells LC configuring a row R1, R2, R3, R4, R5, or R6 may have different widths and heights.

[0028] The area of ​​each of the plurality of logic cells LC included in the cell block 12 of the integrated circuit device 10 may be defined by a cell boundary CBD. A cell boundary contact portion CBC where the cell boundaries CBD contact each other may be disposed between two adjacent logic cells LC in the first horizontal direction (X direction) or the second horizontal direction (Y direction) among the plurality of logic cells LC.

[0029] In some embodiments, two logic cells LC adjacent to each other in the width direction among the plurality of logic cells LC configuring a row R1, R2, R3, R4, R5, or R6 may contact each other at the cell boundary contact portion CBC without a spacing distance. In other embodiments, two logic cells LC adjacent to each other in the width direction among the plurality of logic cells LC configuring a row R1, R2, R3, R4, R5, or R6 may be spaced apart from each other by a spacing distance.

[0030] In some embodiments, two logic cells LC adjacent to each other among a plurality of logic cells LC configuring a row R1, R2, R3, R4, R5, or R6 may perform the same function. In this case, the two logic cells LC adjacent to each other may have the same structure. In other embodiments, two logic cells LC adjacent to each other among a plurality of logic cells LC configuring a row R1, R2, R3, R4, R5, or R6 may perform different functions.

[0031] In some embodiments, one logic cell LC selected from a plurality of logic cells LC included in the cell block 12 of the integrated circuit device 10 and another logic cell LC adjacent to the selected logic cell LC in the second horizontal direction (Y direction) may have a symmetrical structure with respect to a cell boundary contact portion CBC therebetween. For example, the reference logic cell LC_R of the third row R3 and the lower logic cell LC_L of the second row R2 may have a symmetrical structure with respect to the cell boundary contact portion CBC therebetween. In addition, the reference logic cell LC_R of the third row R3 and the upper logic cell LC_H of the fourth row R4 may have a symmetrical structure with respect to the cell boundary contact portion CBC therebetween.

[0032] The drawing shows the cell block 12 including six rows R1 to R6 , but this may be merely an embodiment, and the cell block 12 may include various numbers of rows selected according to circumstances, and one row may include various numbers of logic cells selected according to circumstances.

[0033] One line selected from a plurality of ground lines VSS and a plurality of power lines VDD may be arranged between two adjacent rows of a plurality of rows R1 to R6, wherein each row includes a plurality of logic cells LC arranged in a row and extending longitudinally in a first horizontal direction (X direction). The plurality of ground lines VSS and the plurality of power lines VDD may each extend in the first horizontal direction (X direction), and may be alternately arranged and spaced apart from each other in a second horizontal direction (Y direction). Therefore, each of the plurality of ground lines VSS and the plurality of power lines VDD may be arranged to overlap with a cell boundary CBD of the corresponding logic cell LC in the first horizontal direction (X direction). When viewed along a line extending in a particular direction or in a plane perpendicular to the particular direction, components or layers described as "overlapping" in a particular direction may be at least partially shielded from each other.

[0034] Figure 2 is a plan layout diagram showing an integrated circuit device 10 according to an embodiment. Figure 2 Shows Figure 1 The floor plan layout of some components in area EX. Figure 3 is along Figure 2 A cross-sectional view taken along line AA'. Figure 4 is along Figure 2 A cross-sectional view taken along line BB'. Figure 5 is along Figure 2 A cross-sectional view taken along line CC'. Figure 6 yes Figure 3 An enlarged cross-sectional view of region DD.

[0035] Reference Figures 2 to 6 , the integrated circuit device 10 may include a pair of fin-type active areas FA adjacent to each other in the second horizontal direction (Y direction) with a through-hole power rail 130 therebetween.

[0036] The integrated circuit device 10 according to the embodiment may include a pair of fin-type active areas FA protruding from the back insulating structures 210 and 220 described below, respectively. The pair of fin-type active areas FA may be elongated or longitudinally extended along a first horizontal direction (X direction) on the back insulating structures 210 and 220, and may be spaced apart from each other in a second horizontal direction (Y direction) perpendicular to the first horizontal direction (X direction) to extend in parallel. A pair of fin-type active areas FA is shown in the drawings, but this may be only an embodiment, and the integrated circuit device 10 may include various numbers of fin-type active areas FA selected according to circumstances.

[0037] The device isolation layer 103 may be disposed to cover at least a portion of each of two (eg, opposite) sidewalls of each of the pair of fin-type active regions FA. The device isolation layer 103 may include an insulating material, and may include silicon oxide, for example, but is not limited thereto.

[0038] A pair of source / drain regions SD may be disposed in a pair of fin-type active regions FA. That is, a pair of source / drain regions SD may be formed in a region where a pair of fin-type active regions FA are partially etched. In some embodiments, a pair of source / drain regions SD may each be a raised source / drain region. Therefore, relative to the backside insulating structures 210, 220, the upper end of a pair of source / drain regions SD may be higher than the upper end of a pair of fin-type active regions FA. It will be understood that spatially related terms such as "above", "up", "below", "below", "below", "above", etc. may be represented by reference numerals and refer to the accompanying drawings, except where otherwise specified. It will be understood that in addition to the orientations shown in the drawings, spatially related terms are also intended to include different orientations of the device in use or operation. For example, if the device in the drawings is flipped, the elements described as "below" or "below" other elements or features will be oriented "above" other elements or features.

[0039] The interlayer insulating layer 110 may be disposed on the pair of source / drain regions SD and the device isolation layer 103. In addition, the interlayer insulating layer 110 may be formed to contact an outer sidewall of each of a plurality of gate structures 120 described below. The interlayer insulating layer 110 may include an insulating material, and may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-k dielectric material.

[0040] The plurality of gate structures 120 may extend longitudinally in the second horizontal direction (Y direction) on the pair of fin-type active areas FA. The nanosheet stack NS may be disposed at an upper portion of each of the pair of fin-type active areas FA in a region where the pair of fin-type active areas FA intersect with the plurality of gate structures 120. The nanosheet stack NS may be disposed at a position spaced apart from each of the pair of fin-type active areas FA in a vertical direction (e.g., Z direction).

[0041] As used herein, the term "nanosheet" may refer to a conductive structure comprising a cross section that is substantially perpendicular to the direction of current flow. A nanosheet will be understood to include nanowires.

[0042] The plurality of gate structures 120 may be spaced apart from each other in a first horizontal direction (X direction) and may extend in a second horizontal direction (Y direction). In addition, the plurality of gate structures 120 may be disposed on a pair of fin-type active regions FA and the device isolation layer 103. Each of the plurality of gate structures 120 may include a gate spacer 121, a gate dielectric layer 123, a gate electrode 125, and a gate capping layer 127.

[0043] The gate spacer 121 may include, for example, silicon nitride. The gate spacer 121 may be formed by a process such as a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process.

[0044] The gate dielectric layer 123 may be disposed between the gate electrode 125 and the fin-type active area FA. In addition, the gate dielectric layer 123 may be disposed between the gate electrode 125 and the nanosheet stack NS. In addition, the gate dielectric layer 123 may be disposed between the gate electrode 125 and the interlayer insulating layer 110. In some embodiments, the gate dielectric layer 123 may extend in a second horizontal direction (Y direction) along the contour of the fin-type active area FA protruding upward from the device isolation layer 103. In addition, the gate dielectric layer 123 may be disposed to surround the nanosheet stack NS. The terms "surrounding" or "covering" or "filling" as used herein may not require completely surrounding or covering or filling the described element or layer, but may, for example, mean partially surrounding or covering or filling the described element or layer, for example, always having a gap or other space.

[0045] In some embodiments, the gate dielectric layer 123 and the gate electrode 125 may be formed by a replacement metal gate process or a gate-last process. The gate dielectric layer 123 may include a high-k dielectric material having a dielectric constant higher than that of silicon oxide. For example, the gate dielectric layer 123 may include HfO, ZrO, LaO, AlO, or TaO.

[0046] The gate electrode 125 may have a single-layer structure or a multi-layer structure in which two or more layers are stacked. In some embodiments, the gate electrode 125 may include a work function adjustment layer and a central electrode layer. The work function adjustment layer may perform a function of adjusting the work function, and the central electrode layer may fill a space formed by the work function adjustment layer. The work function adjustment layer may include, for example, at least one of TiN, WN, TiAl, TiAlN, TaN, TiC, TaC, TaCN, TaSiN, and combinations thereof. In addition, the central electrode layer may include, for example, at least one of tungsten (W), aluminum (Al), cobalt (Co), titanium (Ti), tantalum (Ta), polycrystalline silicon (poly-Si), SiGe, and a metal alloy.

[0047] The gate capping layer 127 may be disposed on the gate electrode 125. In some embodiments, the gate capping layer 127 may be a self-aligned hard mask pattern, but is not limited thereto. The gate capping layer 127 may include, for example, silicon nitride.

[0048] The via power rail 130 may extend in the vertical direction (Z direction) between the pair of fin-type active areas FA. The via power rail 130 may pass through the interlayer insulating layer 110 and the device isolation layer 103 in the vertical direction (Z direction). The via power rail 130 may include, for example, molybdenum (Mo), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), manganese (Mn), titanium (Ti), tantalum (Ta), aluminum (Al), combinations thereof, or alloys thereof, but is not limited thereto.

[0049] Both (eg, opposite) sidewalls of the via power rail 130 may be surrounded by a rail insulating layer 132. The rail insulating layer 132 may include silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof.

[0050] A pair of source / drain contacts CA may be disposed on the pair of source / drain regions SD. In addition, the pair of source / drain contacts CA may contact the pair of source / drain regions SD and may be arranged spaced apart from each other in the second horizontal direction (Y direction) with the through-hole power rail 130 therebetween. In addition, each of the pair of source / drain contacts CA may be spaced apart from the gate electrode 125 in the first horizontal direction (X direction).

[0051] The pair of source / drain contacts CA may include, for example, Mo, Cu, W, Co, Ru, Mn, Ti, Ta, Al, a combination thereof, or an alloy thereof, but is not limited thereto.

[0052] In the integrated circuit device 10 according to the embodiment, a pair of source / drain contacts CA may include a first source / drain contact CA1 and a second source / drain contact CA2 having different shapes, which will be described in detail below.

[0053] The contact fusion bridge CM may be disposed on and electrically connected to the first source / drain contact CA1 of a pair of source / drain contacts CA and the through-hole power rail 130. That is, the first source / drain contact CA1 and the contact fusion bridge CM may be configured as an integral structure or a single member, wherein no boundary surface or interface is formed between them. In other words, in some embodiments, the first source / drain contact CA1 and the contact fusion bridge CM may be integral with each other, which may also be referred to as a single structure without an interface therebetween.

[0054] As described below, this can be characterized based on the following manufacturing process: wherein the first source / drain contact CA1 and the contact fusion bridge CM are formed from the same material layer by a one-time etching process. Therefore, in the integrated circuit device 100, the contact fusion bridge CM can include the same material as the above pair of source / drain contacts CA.

[0055] The inner sidewall of the first source / drain contact CA1 may be set to contact the track insulation layer 132. When viewed in a cross-sectional view, the contact fusion bridge CM may have a trapezoidal shape, and the bottom surface of the contact fusion bridge CM may be set to contact the upper surface of the through-hole power rail 130 and the upper surface of the track insulation layer 132. Based on such a structure, the first source / drain contact CA1 and the through-hole power rail 130 may not contact each other at the same level, and may be electrically connected to each other through the contact fusion bridge CM. As used herein, elements at the same "level" or contacts therebetween may refer to a distance relative to the upper surface or lower surface of the structure shown.

[0056] In addition, the bottom surface of the contact fusion bridge CM may be disposed to be spaced apart from the upper surface of the gate electrode 125 in the vertical direction (Z direction). This may be characterized based on the gate capping layer 127 disposed on the upper surface of the gate electrode 125. In addition, when viewed in a plan view, the contact fusion bridge CM may be formed not to overlap with the pair of nanosheet stacks NS.

[0057] The contact isolation insulating layer 140 may be disposed between the second source / drain contact CA2 of the pair of source / drain contacts CA and the through-hole power rail 130. The contact isolation insulating layer 140 may be disposed between the pair of source / drain contacts CA adjacent to each other in the second horizontal direction (Y direction), and may electrically disconnect or isolate the pair of source / drain contacts CA from each other. Each contact isolation insulating layer 140 disposed between two adjacent gate electrodes 125 among the plurality of gate electrodes 125 may be disposed between the pair of source / drain contacts CA.

[0058] A portion of the sidewall of the via power rail 130 may be in contact with the contact isolation insulating layer 140, and an inner sidewall of the second source / drain contact CA2 may be disposed in contact with the contact isolation insulating layer 140. In addition, the upper surface of the via power rail 130, the upper surface of the rail insulating layer 132, the upper surface of the contact isolation insulating layer 140, and the upper surface of the second source / drain contact CA2 may configure a coplanar surface. When viewed in a cross-sectional view, the contact isolation insulating layer 140 and the contact fusion bridge CM may be disposed spaced apart from each other in the second horizontal direction (Y direction).

[0059] The upper insulating layer 150 may be formed to cover both (e.g., opposite) sidewalls of the contact fusion bridge CM, and an upper surface of each of the via power rail 130, the rail insulating layer 132, the contact isolation insulating layer 140, a pair of source / drain contacts CA, the contact fusion bridge CM, and the interlayer insulating layer 110. The upper insulating layer 150 may include, for example, silicon oxide, silicon nitride, an ultra-low-k material having an ultra-low dielectric constant K, or a combination thereof.

[0060] The through-hole structure 160 may pass through the upper insulating layer 150 and may contact the upper surface of the second source / drain contact CA2. That is, the through-hole structure 160 may be disposed on the second source / drain contact CA2. Therefore, the source / drain region SD may be electrically connected to the through-hole structure 160 through the second source / drain contact CA2. The through-hole structure 160 may include, for example, Mo, Cu, W, Co, Ru, Mn, Ti, Ta, Al, a combination thereof, or an alloy thereof, but is not limited thereto.

[0061] In the integrated circuit device 10 according to the embodiment, the angle between the bottom surface and the side wall of the contact fusion bridge CM may be an acute angle, the angle between the bottom surface and the side wall of the through-hole structure 160 may be an obtuse angle, and the angle between the bottom surface and the outer side wall of each of a pair of source / drain contacts CA may be an obtuse angle. As used herein, the outer side wall may be opposite to the inner side wall of a pair of source / drain contacts CA, wherein the inner side walls may face each other. In other words, the horizontal width CMW1 of the bottom surface of the contact fusion bridge CM may be greater than the horizontal width CMW2 of the upper surface of the contact fusion bridge CM, and the horizontal width 160W1 of the bottom surface of the through-hole structure 160 may be less than the horizontal width 160W2 of the upper surface of the through-hole structure 160. As described below, this may be characterized based on the following manufacturing process: wherein the first source / drain contact CA1 and the contact fusion bridge CM are formed by a one-time or same etching process, but the embodiments of the inventive concept are not limited thereto.

[0062] The back side insulating structures 210 and 220 may be disposed under the pair of fin type active areas FA. The back side insulating structures 210 and 220 may include an upper back side insulating structure 210 having a protruding portion and a lower back side insulating structure 220 disposed on a lower surface of the upper back side insulating structure 210 .

[0063] In some embodiments, the upper back insulating structure 210 and the lower back insulating structure 220 may include different insulating materials. Each of the upper back insulating structure 210 and the lower back insulating structure 220 may include, for example, a different material selected from silicon oxide, silicon nitride, silicon carbide, and a low-k dielectric material. The low-k dielectric material may include fluorine-doped silicon oxide, organic silicate glass, carbon-doped oxide, porous silicon oxide, porous organic silicate glass, spin-on organic polymer dielectrics, spin-on silicon-based polymer dielectrics, or a combination thereof.

[0064] The power rail wiring 230 may pass through the back side insulation structures 210 and 220 in the vertical direction (Z direction) and may contact the through-hole power rail 130. In some embodiments, the power rail wiring 230 may be configured or may be configured to provide Figure 1. The power rail wiring 230 may include a metal wiring layer and a conductive barrier layer surrounding the metal wiring layer. Here, the metal wiring layer may include, for example, Mo, W, Co, Ru, Mn, Ti, Ta, Al, Cu, a combination thereof, or an alloy thereof. The conductive barrier layer may include, for example, Ti, Ta, W, TiN, TaN, WN, WCN, TiSiN, TaSiN, WSiN, or a combination thereof.

[0065] Advances in electronic technology have led to rapid shrinkage of integrated circuit devices. In highly shrunk integrated circuit devices, because of the need for operating precision and fast operating speed, it may be necessary to provide a wiring structure with a stable and optimized structure in a relatively small area. For this reason, an integrated circuit device 10 including a back side power distribution network (BSPDN) is being developed.

[0066] Generally, in the manufacturing process of the integrated circuit device 10 including the BSPDN, a process of removing a portion of the rail insulating layer 132 disposed at the sidewall of the via power rail 130 may be performed to facilitate electrical connection between the via power rail 130 and the source / drain contact CA. However, in the process of forming the via power rail 130 and the source / drain contact CA, it may be difficult to remove only a portion of the rail insulating layer 132 disposed therebetween without affecting the manufacturing process of other elements. Therefore, problems caused by process errors may occur.

[0067] In order to solve such a problem, in the integrated circuit device 10 according to the embodiment, the contact fusion bridge CM may be provided on the source / drain contact CA as a whole (i.e., as an integral structure or a single member), and a process of removing only a portion of the rail insulating layer 132 may not be performed, thereby reducing the difficulty and / or complexity of the manufacturing process. That is, based on the rail insulating layer 132, the source / drain contact CA and the through-hole power rail 130 may not contact each other at the same level, and, for example, at the top or upper surface of the through-hole power rail 130 (rather than at the side surface or sidewall thereof), may be electrically connected to each other through the contact fusion bridge CM.

[0068] As a result, in the integrated circuit device 10 according to the embodiment, in the structure including the BSPDN for the device region having an area reduced based on the downsizing, a partial etching process of the rail insulating layer 132, whose difficulty level of the manufacturing process may be high, can be omitted and can be replaced by a process of forming the contact fusion bridge CM, and therefore, the difficulty level and / or complexity of the manufacturing process can be reduced and the electrical characteristics can be enhanced.

[0069] Figure 7 and Figure 8 is a cross-sectional view showing an integrated circuit device according to another embodiment.

[0070] Most of the components and materials used to configure the integrated circuit devices 20 and 30 described below may be similar to those described herein. Figures 2 to 6 Therefore, for the sake of convenience, the following will mainly describe the differences from the above-mentioned integrated circuit device 10.

[0071] Reference Figure 7 According to another embodiment, the integrated circuit device 20 may include a pair of source / drain contacts CA including a contact fusion bridge CM2 and a via structure 160 .

[0072] In the integrated circuit device 20 according to another embodiment, the contact fusion bridge CM2 may be disposed on the through-hole power rail 130 and the first source / drain contact CA1 of the pair of source / drain contacts CA. That is, the first source / drain contact CA1 and the contact fusion bridge CM2 may be configured as an integral or single structure, wherein no boundary surface or interface is formed therebetween. That is, in some embodiments, there may be no interface between the first source / drain contact CA1 and the contact fusion bridge CM.

[0073] In the integrated circuit device 20 according to another embodiment, the via structure 160 may pass through the upper insulating layer 150 and may contact the upper surface of the second source / drain contact CA2. That is, the via structure 160 may be disposed on the second source / drain contact CA2. Therefore, the source / drain region SD may be electrically connected to the via structure 160 through the second source / drain contact CA2.

[0074] In the integrated circuit device 20 according to another embodiment, the thickness CM2T of the contact fusion bridge CM2 in the vertical direction (Z direction) may be substantially equal to the thickness 160T of the via structure 160 in the vertical direction (Z direction). In other words, the level of the bottom surface of the contact fusion bridge CM2 may be substantially the same as or coplanar with the level of the bottom surface of the via structure 160, and the level of the top surface of the contact fusion bridge CM2 may be substantially the same as or coplanar with the level of the top surface of the via structure 160.

[0075] Reference Figure 8 , the integrated circuit device 30 according to another embodiment may include a pair of source / drain contacts CA including a contact bridge CM3 and a via structure 160 .

[0076] In an integrated circuit device 30 according to another embodiment, the contact bridge CM3 may be disposed on the through-hole power rail 130 and the first source / drain contact CA1 of the pair of source / drain contacts CA. That is, the first source / drain contact CA1 and the contact bridge CM3 may be configured to form different structures of a boundary surface or interface therebetween. This may be characterized based on the following manufacturing process: wherein the first source / drain contact CA1 and the contact bridge CM3 are formed from different material layers by different etching processes. Therefore, in the integrated circuit device 30, the contact bridge CM3 may include a material different from that of the pair of source / drain contacts CA, but is not limited thereto.

[0077] In the integrated circuit device 30 according to another embodiment, the inner sidewall of the first source / drain contact CA1 may be provided to contact the track insulating layer 132. When viewed in a cross-sectional view, the contact bridge CM3 may have a trapezoidal shape, and the bottom surface of the contact bridge CM3 may be provided to contact the upper surface of the first source / drain contact CA1, the upper surface of the via power rail 130, and the upper surface of the track insulating layer 132. Based on such a structure, the first source / drain contact CA1 and the via power rail 130 may not directly contact each other at the same level, but may be electrically connected to each other through the contact bridge CM3.

[0078] Fig. 9 is a flowchart illustrating a method of manufacturing an integrated circuit device according to an embodiment.

[0079] In some embodiments, a particular process sequence may be performed differently than described or in a different order than described, where some embodiments may be implemented differently. For example, two processes described consecutively or sequentially may be performed substantially simultaneously, or may be performed in a reverse order than described.

[0080] Reference Fig. 9 , the method S10 of manufacturing an integrated circuit device according to the embodiment may include first to ninth operations S110 to S190 .

[0081] The manufacturing method S10 of the integrated circuit device according to the embodiment may include: a first operation S110 of forming a pair of fin-type active regions protruding on the substrate; a second operation S120 of forming a pair of source / drain regions on the pair of fin-type active regions; a third operation S130 of forming a through-hole power rail between the pair of fin-type active regions; a fourth operation S140 of etching a portion of each of the pair of source / drain regions to form a contact preliminary hole; a fifth operation S150 of forming a contact material layer filling the contact preliminary hole (e.g., filling the entirety thereof); a sixth operation S160 of patterning the contact material layer to simultaneously form a pair of source / drain contacts having a through-hole power rail therebetween and a contact fusion bridge contacting the upper surface of the through-hole power rail; a seventh operation S170 of forming an upper insulating layer on or covering the contact fusion bridge and a through-hole structure passing through the upper insulating layer; an eighth operation S180 of removing the substrate and forming a back-side insulating structure in the region where the substrate is removed; and a ninth operation S190 of forming a power rail wiring passing through the back-side insulating structure and contacting the through-hole power rail.

[0082] Reference will be made to the following description Figures 10 to 24 Technical features and / or structural features generated by each of the first to ninth operations S110 to S190 are described in detail.

[0083] Figures 10 to 24 is a diagram illustrating a method of manufacturing an integrated circuit device in process order according to an embodiment.

[0084] Reference Fig.10 , a nanosheet stack NS (see Figure 4 ) and the fin type active area FA can be formed by etching a partial area of ​​the substrate 101.

[0085] The substrate 101 may be a wafer including silicon (Si). In some embodiments, the substrate 101 may be a wafer including a semiconductor element such as Ge or a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). In addition, the substrate 101 may have a silicon-on-insulator (SOI) structure. In addition, the substrate 101 may include a conductive region, and, for example, may include a well doped with impurities or a structure doped with impurities.

[0086] An insulating layer on or covering the fin-type active area FA may be formed on the substrate 101, and then the device isolation layer 103 may be formed by etching the insulating layer. In this case, the fin-type active area FA may protrude upward from the upper surface of the device isolation layer 103 and may be formed to be exposed. The term "exposed" may be used to describe the relationship between elements and / or certain intermediate processes in the process of manufacturing a complete semiconductor device, but may not necessarily require that a specific region, layer, structure, or other element be exposed in the context of a complete device.

[0087] By using a replacement metal gate process, a gate dielectric layer 123 (see FIG. 1 ) may be sequentially formed on the nanosheet stack NS and the fin-type active area FA of the substrate 101. Figure 4 ), the gate electrode 125 (see Figure 4 ) and a plurality of gate structures 120 of a gate capping layer 127 (see Figure 4 ). These processes may be based on conventional techniques, and therefore, detailed descriptions thereof are omitted.

[0088] The source / drain regions SD may be formed on the fin type active region FA exposed at both sides (eg, opposite sides) of each of the plurality of gate structures 120 through an epitaxial growth process.

[0089] The interlayer insulating layer 110 may be formed to cover the source / drain region SD and the device isolation layer 103. The interlayer insulating layer 110 may include, for example, an insulating material such as silicon oxide. An upper insulating layer 150 may be formed on an upper surface of the interlayer insulating layer 110 and an upper surface of each of the plurality of gate structures 120.

[0090] A through-hole power rail 130 extending in the vertical direction (Z direction) may be formed between a pair of fin-type active regions FA. The through-hole power rail 130 may pass through the interlayer insulating layer 110 and the device isolation layer 103 in the vertical direction (Z direction). In addition, a rail insulating layer 132 may be formed at both (e.g., opposite) sidewalls of the through-hole power rail 130. The rail insulating layer 132 may include silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof.

[0091] Reference Fig.11 , a contact isolation hole 140H may be formed between the via power rail 130 and one source / drain region SD of the pair of source / drain regions SD.

[0092] According to circumstances, the contact isolation hole 140H may be formed in the vertical direction (Z direction) by etching a portion of the rail insulating layer 132 and a portion of the interlayer insulating layer 110. The process of forming the contact isolation hole 140H may be a dry etching process.

[0093] Reference Fig.12, can be achieved by making the contact isolation hole 140H (see Fig.11 ) is filled with insulating material to form a contact isolation insulating layer 140.

[0094] In order to form the contact isolation insulating layer 140, a filling contact isolation hole 140H (see Fig.11 ) and covers the upper surface of the interlayer insulating layer 110, the surface of the resulting material may be planarized, and a portion of the insulating material layer may be removed so that only the contact isolation hole 140H is filled with the insulating material layer (see Fig.11 ) remains, thereby exposing the upper surface of the interlayer insulating layer 110 again.

[0095] A chemical mechanical polishing (CMP) process or an etch-back process may be used for planarization, but the inventive concept is not limited thereto. In some embodiments, the insulating material layer may include silicon nitride, silicon oxynitride, silicon oxycarbide, or a combination thereof. In other embodiments, the insulating material layer may include an air gap or void therein.

[0096] In some embodiments, the contact isolation insulating layer 140 may be formed by contacting the source / drain contacts CA described below (see Fig.16 ) is formed before, but is not limited thereto. That is, in other embodiments, the source / drain contact CA may be formed first (see Fig.16 ), and then, a contact isolation insulating layer 140 may be formed.

[0097] Reference Fig.13 By etching a portion of the interlayer insulating layer 110 and a portion of the pair of source / drain regions SD, a contact preliminary hole CAH exposing the pair of source / drain regions SD may be formed between two adjacent gate structures 120 of the plurality of gate structures 120 .

[0098] When performing the etching process for forming the contact preliminary hole CAH, at least a portion of the pair of source / drain regions SD exposed through the contact preliminary hole CAH may be consumed or otherwise removed. The lowest surface of the inner surface of the contact preliminary hole CAH may be disposed between the pair of source / drain regions SD exposed at the inner surface of the contact preliminary hole CAH.

[0099] In the process of forming the contact preliminary hole CAH, the contact isolation insulating layer 140 may not be etched and may remain. That is, the etching process of forming the contact preliminary hole CAH may be a process in which the etching selectivity of or corresponding to the interlayer insulating layer 110 is different from the etching selectivity of or corresponding to the contact isolation insulating layer 140.

[0100] Reference Fig.14, can completely fill the contact preliminary hole CAH (see Fig.13 ), and a contact material layer CAL may be formed to cover an upper surface of the interlayer insulating layer 110.

[0101] The contact material layer CAL may be formed to contact the pair of source / drain regions SD. The contact material layer CAL may pass through the interlayer insulating layer 110 in a vertical direction (Z direction) and may contact the source / drain regions SD.

[0102] The contact material layer CAL may include, for example, Mo, Cu, W, Co, Ru, Mn, Ti, Ta, Al, combinations thereof, or alloys thereof, but is not limited thereto.

[0103] Reference Fig.15 , a portion of the upper portion of the contact material layer CAL may be removed by performing a polishing process on the upper surface of the contact material layer CAL.

[0104] The polishing process may be performed as a CMP process or an etch-back process. Due to the polishing process, the height of the upper surface of the contact material layer CAL may be reduced, and thus the thickness may be reduced. In some embodiments, the polishing process may be performed on the contact material layer CAL so that the upper surface of the interlayer insulating layer 110 is exposed.

[0105] The mask pattern MP may be formed on the contact material layer CAL. The mask pattern MP may be formed by an argon fluoride (ArF) photolithography process or an extreme ultraviolet (EUV) photolithography process. In some embodiments, the mask pattern MP may be a photoresist pattern or a hard mask pattern, but is not limited thereto.

[0106] Reference Fig.16 , can be achieved by using the mask pattern MP (see Fig.15 ) as an etching mask to etch the contact material layer CAL (see Fig.15 ), therefore, a pair of source / drain contacts CA may be formed on a pair of source / drain regions SD.

[0107] The contact fusion bridge CM may be disposed on the first source / drain contact CA1 of the pair of source / drain contacts CA and the through-hole power rail 130. Based on such a manufacturing process, the first source / drain contact CA1 and the contact fusion bridge CM may be configured as an integral or single structure, wherein no boundary surface or interface is formed between them. In addition, the contact isolation insulating layer 140 may be disposed between the second source / drain contact CA2 of the pair of source / drain contacts CA and the through-hole power rail 130.

[0108] In other words, a pair of source / drain contacts CA may be formed by a damascene process, and at the same time, the contact fusion bridge CM may be formed by an anisotropic etching process. The anisotropic etching process may be, for example, a plasma etching process. Accordingly, the angle between the bottom surface and the sidewall of the contact fusion bridge CM may be an acute angle, and the angle between the bottom surface and the outer sidewall of each of the pair of source / drain contacts CA may be an obtuse angle.

[0109] Reference Fig.17 The upper insulating layer 150 may be formed to cover two (e.g., opposite) sidewalls of the contact fusion bridge CM and the upper surface of each of the through-hole power rail 130, the rail insulating layer 132, the contact isolation insulating layer 140, a pair of source / drain contacts CA, the contact fusion bridge CM, and the interlayer insulating layer 110.

[0110] The upper insulating layer 150 may include, for example, silicon oxide, silicon nitride, an ultra low-k (ULK) material having an ultra low-k dielectric constant, or a combination thereof.

[0111] Reference Fig.18 , a through preliminary hole 160H exposing a portion of an upper surface of the second source / drain contact CA2 may be formed through the upper insulating layer 150 .

[0112] The through-hole preliminary hole 160H may be formed in the vertical direction (Z direction) by etching a portion of the upper insulating layer 150. The process of forming the through-hole preliminary hole 160H may be a dry etching process.

[0113] Reference Fig.19 , can be made by making the initial hole 160H in the through hole (see Fig.19 ) is filled with conductive material to form a through-hole structure 160.

[0114] To form the via structure 160, a filling via preliminary hole 160H may be first formed (see Fig.19 ) and covers the upper surface of the upper insulating layer 150, the surface of the resulting material may be planarized, and a portion of the conductive material layer may be removed so that only the through hole preliminary hole 160H (see Fig.19 ) remains, thereby exposing the upper surface of the upper insulating layer 150 again.

[0115] A CMP process or an etch-back process may be used for planarization, but the inventive concept is not limited thereto. In some embodiments, the conductive material layer may include, for example, Mo, Cu, W, Co, Ru, Mn, Ti, Ta, Al, combinations thereof, or alloys thereof, but is not limited thereto.

[0116] Reference Fig. 20 , a backside removal process of removing a portion of the substrate 101 may be performed.

[0117] The backside removal process for reducing the thickness of the substrate 101 may include a process of alternately performing a grinding process and a wet etching process to expose the bottom surface of the via power rail 130 and the bottom surface of the rail insulation layer 132. Therefore, after removing a portion of the substrate 101, the backside surface of the substrate 101 may be closer to the device isolation layer 103.

[0118] Reference Fig.21 , the lower portion of each of the pair of fin-type active regions FA and the entire substrate 101 (see Fig. 20 ), and an upper back-side insulating structure 210 including a protruding portion may be formed in the region formed by the removal.

[0119] As described above, the entire substrate 101 (see Fig. 20 ) to obtain a bulk reduction structure. The upper back side insulating structure 210 may include, for example, a material selected from silicon oxide, silicon nitride, silicon carbide, and a low-k dielectric material.

[0120] Reference Fig. 22 , a lower back-side insulating structure 220 may be formed on a lower surface of the upper back-side insulating structure 210 .

[0121] The lower back side insulating structure 220 may include, for example, a material selected from silicon oxide, silicon nitride, silicon carbide, and a low-k dielectric material. In some embodiments, the upper back side insulating structure 210 and the lower back side insulating structure 220 may include different insulating materials.

[0122] The upper back side insulating structure 210 and the lower back side insulating structure 220 may be referred to as back side insulating structures 210 and 220. Therefore, the back side insulating structures 210 and 220 may be disposed under a pair of fin type active regions FA.

[0123] Reference Fig.23 , a power rail preliminary hole 230H may be formed passing through the back side insulating structures 210 and 220 in the vertical direction (Z direction).

[0124] Forming the power rail preliminary hole 230H may include a process of etching a portion of each of the back side insulating structures 210 and 220 from a back side surface of each of the back side insulating structures 210 and 220 to expose a bottom surface of the via power rail 130 and a bottom surface and lower sidewall of the rail insulating layer 132 .

[0125] Reference Fig.24 , can be made by making a preliminary hole 230H in the power rail (see Fig.23 ) is filled with conductive material to form power rail wiring 230.

[0126] To form the power rail wiring 230, a filling power rail preliminary hole 230H may be formed first (see Fig.23 ) and covers the bottom surface of the lower back insulating structure 220, the surface of the resulting material may be planarized, and a portion of the conductive material layer may be removed so that only the power rail preliminary hole 230H (see Fig.23 ) is retained, thereby exposing the bottom surface of the lower back-side insulating structure 220 again.

[0127] Subsequently, as circumstances dictate, a backside wiring structure (not shown) may be formed below the power rail wiring 230 and the lower backside insulating structure 220 , thereby manufacturing the integrated circuit device 10 according to the embodiment.

[0128] As mentioned above, the above reference Figures 10 to 24 The method of manufacturing the integrated circuit device 10 is described, but it will be understood that the above referenced method can be manufactured by implementing various changes or modifications to the above description within the scope of the inventive concept. Figure 7 and Figure 8 Integrated circuit devices 20 and 30 are described.

[0129] Fig.25 and Fig.26 is a cross-sectional view corresponding to an active pattern of an integrated circuit device according to an embodiment.

[0130] Most of the components and materials used to configure the integrated circuit devices 40 and 50 described below may be similar to those described herein. Figures 2 to 6 Therefore, for the sake of convenience, the following will mainly describe the differences from the above-mentioned integrated circuit device 10.

[0131] Reference Fig.25 In the integrated circuit device 40 , when the fin active area FA having a fin shape extends in the first horizontal direction (X direction), a transistor configured by the fin active area FA and the gate electrode 125 may be referred to as a fin field effect transistor (FinFET).

[0132] Reference Fig.26 In the integrated circuit device 50, the fin type active area FA may include a plurality of nanosheet stacks NS that are spaced apart from each other in a vertical direction (Z direction) and extend in a first horizontal direction (X direction), and a transistor configured by the plurality of nanosheet stacks NS and the gate electrode 125 may include a multi-bridge channel FET (MBCFET).

[0133] Although not shown, the nanosheet for the p-type transistor and the nanosheet for the n-type transistor may be separated from each other by a dielectric wall, and thus the integrated circuit device 50 may include a ForkFET having a structure in which the n-type transistor is closer to the p-type transistor.

[0134] Furthermore, the integrated circuit device 50 may include a vertical FET (VFET) having a structure in which source / drain regions are spaced apart from each other in a vertical direction (Z direction), a channel region is provided between the source / drain regions, and a gate electrode surrounds the channel region.

[0135] Furthermore, the integrated circuit device 50 may include complementary FETs (CFETs), negative FETs (NCFETs), and carbon nanotube FETs (CNTs), or may include bipolar junction transistors and other three-dimensional (3D) transistors.

[0136] Fig. 27 is a block diagram illustrating a system 1000 including an integrated circuit device according to an embodiment.

[0137] Reference Fig. 27 , the system 1000 may include a controller 1010 , an input / output (I / O) device 1020 , a storage device 1030 , an interface 1040 , and a bus 1050 .

[0138] System 1000 may be a mobile system, or may be a system for sending or receiving information. In some embodiments, the mobile system may be a portable computer, a web tablet computer, a mobile phone, a digital music player, or a memory card.

[0139] The controller 1010 may be configured to control an execution program in the system 1000 , and may be configured with a microprocessor, a digital signal processor, a microcontroller, or a device similar thereto.

[0140] The I / O device 1020 may be used to input or output data of the system 1000. The system 1000 may be connected to an external device (e.g., a personal computer or a network) by using the I / O device 1020, and may exchange data with the external device. The I / O device 1020 may be, for example, a touch screen, a touch pad, a keyboard, or a display.

[0141] The memory device 1030 may store data used for the operation of the controller 1010, or may store data obtained through the processing of the controller 1010. The memory device 1030 may include one of the integrated circuit devices 10, 20, 30, 40, and 50 according to the above-described embodiments.

[0142] The interface 1040 may be a data transmission path between the system 1000 and an external device. The controller 1010 , the I / O device 1020 , the storage device 1030 , and the interface 1040 may communicate with each other through the bus 1050 .

[0143] In the above, exemplary embodiments have been described in the drawings and the specification. The embodiments have been described by using the terms described herein, but this is only used to describe the inventive concept and is not used to limit the meaning or scope of the inventive concept defined in the appended claims. Therefore, the scope of the inventive concept can be limited based on the scope of the appended claims.

[0144] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the scope of the appended claims.

Claims

1. An integrated circuit device comprising: a pair of fin-type active regions spaced apart from each other in a second horizontal direction intersecting the first horizontal direction, wherein the pair of fin-type active regions protrude from the back insulating structure in a vertical direction perpendicular to the first horizontal direction and extend longitudinally in the first horizontal direction; a device isolation layer on opposite side walls of each of the pair of fin-type active regions; a pair of source / drain regions on the pair of fin-type active regions; an interlayer insulating layer on the pair of source / drain regions and the device isolation layer; a through-hole power rail extending longitudinally in the first horizontal direction between the pair of fin-type active regions and extending through the interlayer insulating layer and the device isolation layer in the vertical direction; a pair of source / drain contacts arranged in the second horizontal direction to contact the pair of source / drain regions, the through-hole power rail being located between the pair of source / drain contacts; a contact fusion bridge on and electrically connected to the through-hole power rail and a first source / drain contact of the pair of source / drain contacts; a contact isolation insulating layer on the through hole power rail and a second source / drain contact of the pair of source / drain contacts; a through-hole structure on the second source / drain contact; and a power rail wiring extending in the vertical direction through the back side insulating structure and contacting the through hole power rail, The first source / drain contact and the contact fusion bridge have a single structure without a boundary surface therebetween.

2. The integrated circuit device according to claim 1, wherein: The angle between the bottom surface of the contact fusion bridge and the side wall is an acute angle, and the bottom surface of the contact fusion bridge is on the upper surface of the through-hole power rail, wherein the angle between the bottom surface and the side wall of the through-hole structure is an obtuse angle, and the bottom surface of the through-hole structure is on the upper surface of the second source / drain contact, and The angle between the bottom surface of each of the pair of source / drain contacts and the outer sidewall is an obtuse angle, and the bottom surface of each of the pair of source / drain contacts is on the corresponding upper surfaces of the pair of source / drain regions.

3. The integrated circuit device according to claim 2, further comprising: rail insulating layer, on opposite side walls of the through hole power rail, The inner sidewall of the first source / drain contact facing the second source / drain contact contacts the rail insulating layer.

4. The integrated circuit device according to claim 3, wherein: An upper surface of the through-hole power rail, an upper surface of the rail insulation layer, and an upper surface of the second source / drain contact are coplanar.

5. The integrated circuit device according to claim 4, wherein: In cross-sectional view, the contact fusion bridge has a trapezoidal shape, and A bottom surface of the contact fusing bridge contacts an upper surface of the through-hole power rail and an upper surface of the rail insulating layer.

6. The integrated circuit device according to claim 1, wherein: A portion of a sidewall of the through-hole power rail contacts the contact isolation insulating layer, and The inner sidewall of the second source / drain contact facing the first source / drain contact contacts contacts the contact isolation insulating layer.

7. The integrated circuit device according to claim 6, wherein: The contact isolation insulating layer and the contact fusing bridge are spaced apart from each other in the second horizontal direction.

8. The integrated circuit device according to claim 1, wherein: The first source / drain contact and the via power rail do not directly contact each other at respective sidewalls, but are electrically connected to each other through the contact fusion bridge at an upper surface of the via power rail.

9. The integrated circuit device according to claim 1, further comprising: a gate electrode extending longitudinally in the second horizontal direction on the pair of fin-type active regions; as well as a gate capping layer, on the gate electrode, Wherein, a bottom surface of the contact fusion bridge is spaced apart from an upper surface of the gate electrode in the vertical direction.

10. The integrated circuit device according to claim 9, further comprising a pair of nanosheet stacks between the pair of fin-type active regions and the gate electrode, in, In a plan view, the contact fusion bridge does not overlap with the pair of nanosheet stacks.

11. An integrated circuit device comprising: an upper back insulating structure including a protruding portion and a lower back insulating structure on a lower surface of the upper back insulating structure opposite to the protruding portion; a pair of fin-type active regions on the protruding portion of the upper backside insulating structure and extending longitudinally in a first horizontal direction; a device isolation layer on opposite side walls of each of the pair of fin-type active regions; a pair of nanosheet stacks on a first portion of the pair of fin-type active regions; a gate electrode extending longitudinally on the pair of fin-type active regions to cross the pair of fin-type active regions and extending on the pair of nanosheet stacks; a pair of source / drain regions on the second portions of the pair of fin-type active regions; an interlayer insulating layer on the pair of source / drain regions and the device isolation layer; a through-hole power rail extending longitudinally in the first horizontal direction between the pair of fin-type active areas and extending through the interlayer insulating layer and the device isolation layer in a vertical direction perpendicular to the first horizontal direction; a pair of source / drain contacts spaced apart from each other to contact the pair of source / drain regions, the through-hole power rail being located between the pair of source / drain contacts; a contact bridge over the through-hole power rail and a first source / drain contact of the pair of source / drain contacts; a through-hole structure on a second source / drain contact of the pair of source / drain contacts; as well as a power rail wiring extending in the vertical direction through the upper back side insulating structure and the lower back side insulating structure and contacting the through hole power rail, wherein the angle between the bottom surface and the side wall of the contact bridge is an acute angle, the bottom surface of the contact bridge is on the upper surface of the through-hole power rail, and wherein the angle between the bottom surface and the side wall of the through-hole structure is an obtuse angle, the bottom surface of the through-hole structure is on the upper surface of the second source / drain contact.

12. The integrated circuit device according to claim 11, wherein: The first source / drain contact and the contact bridge have a single structure without a boundary surface therebetween.

13. The integrated circuit device according to claim 11, wherein: The first source / drain contact and the contact bridge include different structures with an interface therebetween.

14. The integrated circuit device according to claim 11, wherein: The thickness of the contact bridge in the vertical direction is smaller than the thickness of the through-hole structure in the vertical direction.

15. The integrated circuit device according to claim 11, wherein: The thickness of the contact bridge in the vertical direction is substantially equal to the thickness of the through-hole structure in the vertical direction.

16. A method of manufacturing an integrated circuit device, the method comprising: forming a pair of fin-type active regions spaced apart from each other in a second horizontal direction intersecting the first horizontal direction on a substrate, wherein the pair of fin-type active regions protrude in a vertical direction perpendicular to the first horizontal direction and extend longitudinally in the first horizontal direction; forming a device isolation layer on opposite sidewalls of each of the pair of fin-type active regions; forming a pair of source / drain regions on the pair of fin-type active regions; forming an interlayer insulating layer on the pair of source / drain regions and the device isolation layer; forming a through-hole power rail extending longitudinally in the first horizontal direction between the pair of fin-type active regions and extending through the interlayer insulating layer and the device isolation layer in the vertical direction; etching a portion of each of the pair of source / drain regions and a portion of the interlayer insulating layer between the pair of source / drain regions to form a contact preliminary hole; forming a contact material layer in the preliminary contact hole and on the upper surface of the interlayer insulating layer; patterning the contact material layer to simultaneously form a pair of source / drain contacts spaced apart from each other in the second horizontal direction and a contact fusion bridge contacting at least a portion of an upper surface of the via power rail, wherein the via power rail is between the pair of source / drain contacts; forming an upper insulating layer on the contact fusion bridge and the interlayer insulating layer; forming a through hole structure extending through the upper insulating layer in the vertical direction; removing the substrate to form a back side insulating structure in a region where the substrate is removed; as well as A power rail wiring is formed that extends through the back side insulation structure in the vertical direction and contacts the through-hole power rail.

17. The method according to claim 16, wherein: The first source / drain contact of the pair of source / drain contacts and the contact fusion bridge have a single structure without a boundary surface therebetween.

18. The method according to claim 17, wherein: In the operation of forming the through-hole power rail, forming a rail insulating layer on opposite sidewalls of the through hole power rail, and Inner sidewalls of the first source / drain contacts are formed to contact the rail insulating layer.

19. The method according to claim 18, wherein: The first source / drain contact and the via power rail do not directly contact each other at respective sidewalls, but are electrically connected to each other through the contact fusion bridge at an upper surface of the via power rail.

20. The method according to claim 16, wherein: The angle between the bottom surface of the contact fusion bridge and the side wall is an acute angle, and the bottom surface of the contact fusion bridge is on the upper surface of the through-hole power rail, The angle between the bottom surface and the side wall of the through hole structure is an obtuse angle, and the bottom surface of the through hole structure is on the upper surface of the second source / drain contact in the pair of source / drain contacts, and The angle between the bottom surface of each of the pair of source / drain contacts and the outer sidewall is an obtuse angle, and the bottom surface of each of the pair of source / drain contacts is on the corresponding upper surfaces of the pair of source / drain regions.

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