Inverter structure and inverter manufacturing method
By forming an insulating layer, an active layer and a metal layer on the first MOS tube of the inverter, a second MOS tube is formed, and connected through through holes to form a vertically stacked inverter structure, the problem of excessive inverter area is solved, and area saving and performance decoupling is achieved.
Patent Information
- Application Number
- CN202411801805.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-09
- Publication Date
- 2025-04-08
AI Technical Summary
In the prior art, the inverter occupies a large area, and it is difficult to effectively reduce the area by reducing the channel size or gap.
By forming an insulating layer, an active layer and a metal layer on the first MOS tube, a second MOS tube is formed, and the first MOS tube is connected to the drain terminal of the second MOS tube through a through hole to form a vertically stacked inverter structure.
A significant savings in inverter area are achieved while avoiding the impact on other chip devices. The performance design is not limited by the performance requirements of other devices.
Smart Images
Figure CN119789520A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to an inverter structure and a method for manufacturing the inverter. Background Art
[0002] Inverters are essential in most logic, radio frequency and storage circuits. As the size of integrated circuits continues to shrink, reducing the area occupied by inverters is one of the effective ways to improve chip area utilization and enhance chip competitiveness.
[0003] In order to reduce the area occupied by the inverter, it is usually achieved by reducing the channel size or reducing the gap between devices. However, due to the limitations of process capabilities and equipment capabilities, it is becoming increasingly difficult to achieve.
[0004] Therefore, how to effectively reduce the area of the inverter has become a technical problem that needs to be solved urgently in the industry. Summary of the invention
[0005] The present invention provides an inverter structure and an inverter manufacturing method to solve the problem of large occupied area of the inverter in the prior art.
[0006] According to a first aspect of the present invention, there is provided an inverter structure, comprising:
[0007] substrate;
[0008] A first MOS transistor, located on the substrate, the first MOS transistor comprising a first source region, a first drain region and a gate structure; wherein the gate structure comprises a gate oxide layer and a polysilicon layer sequentially located on the substrate;
[0009] an insulating layer, located on the substrate and covering the first source region, the first drain region and the gate structure;
[0010] An active layer, located on a first preset area of the insulating layer;
[0011] a metal layer, located on the active layer and respectively located on both sides of the gate structure to form a second source region and a second drain region; wherein the second source region, the second drain region, the active layer, the insulating layer and the polysilicon layer constitute a second MOS transistor; and the first MOS transistor and the second MOS transistor have opposite conductivity types;
[0012] The metal interconnection layer includes a dielectric layer located on the substrate and a plurality of through holes located in the dielectric layer, wherein the through holes include a first through hole and a second through hole; wherein the second through holes are respectively used to lead out the first source region, the polysilicon layer and the second source region, and the first through hole is used to jointly lead out the first drain region and the second drain region.
[0013] Optionally, the first MOS tube is a PMOS tube, and the second MOS tube is an NMOS tube.
[0014] Optionally, the material of the active layer includes hydrogenated amorphous silicon or indium gallium zinc oxide, and the thickness of the active layer is 5 nanometers to 100 nanometers.
[0015] Optionally, it further includes: an ohmic contact layer, wherein the ohmic contact layer is located between the metal layer and the active layer, and the ohmic contact layer is located on both sides of the gate structure.
[0016] Optionally, the ohmic contact layer is a highly doped N-type hydrogenated amorphous silicon film, and the thickness of the ohmic contact layer is 5 nanometers to 100 nanometers.
[0017] Optionally, the material of the metal layer is titanium, and the thickness of the metal layer is 10 nanometers to 1000 nanometers.
[0018] Optionally, the material of the insulating layer includes silicon nitride, silicon dioxide, or silicon carbonitride, and the thickness of the insulating layer is 20 nanometers to 500 nanometers.
[0019] According to a second aspect of the present invention, a method for manufacturing an inverter is provided, the method comprising:
[0020] Providing a substrate; wherein a first MOS transistor is formed on the substrate, and the first MOS transistor includes a first source region, a first drain region and a gate structure; wherein the gate structure includes a gate oxide layer and a polysilicon layer sequentially formed on the substrate;
[0021] Depositing an insulating layer on the substrate, wherein the insulating layer covers the first source region, the first drain region and the gate structure;
[0022] Depositing an active layer on a first preset area of the insulating layer, wherein the first preset area corresponds to the first MOS transistor;
[0023] Depositing a metal layer on a second preset area of the active layer, wherein the metal layer exposes the active layer corresponding to the gate structure and is located on both sides of the gate structure to serve as a second source region and a second drain region; the second source region, the second drain region, the active layer, the insulating layer and the polysilicon layer constitute a second MOS transistor;
[0024] A metal interconnection layer is formed on the substrate; the metal interconnection layer includes a dielectric layer formed on the substrate and a plurality of through holes formed in the dielectric layer, the through holes include a first through hole and a second through hole; the second through holes are respectively used to lead out the first source region, the polysilicon layer and the second source region, and the first through hole is used to jointly lead out the first drain region and the second drain region.
[0025] Optionally, depositing an active layer on the first preset area of the insulating layer includes:
[0026] Depositing an active material layer on the substrate; wherein the active material layer covers the insulating layer;
[0027] The active material layer is etched using the first patterned mask layer as a mask to form an active layer located on the first preset area.
[0028] Optionally, depositing a metal layer on the active layer comprises:
[0029] Depositing a metal material layer on the substrate; wherein the metal material layer covers the active layer;
[0030] The metal material layer is etched using the second patterned mask layer as a mask to form a metal layer that exposes the active layer corresponding to the gate structure and is located on both sides of the gate structure. The metal layers on both sides of the gate structure form a second source region and a second drain region respectively.
[0031] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:
[0032] In the inverter structure provided in the first aspect of the embodiment of the present invention, an insulating layer, an active layer, a second source region, and a second drain region are formed above the first MOS tube, and the second MOS tube is formed by the second source region, the second drain region, the active layer, the insulating layer, and the polysilicon layer in the gate structure of the first MOS tube, so that the first MOS tube and the second MOS tube are stacked in the vertical direction, and then the drain terminals of the first MOS tube and the second MOS tube are connected through a through hole to form an inverter. Since the first MOS tube and the second MOS tube constituting the inverter are stacked in the vertical direction, the area occupied by the inverter is greatly saved compared with the traditional inverter with a planar structure.
[0033] Furthermore, by stacking, decoupling between the inverter and other chip devices can be achieved, so that the inverter can reduce the area occupied by the inverter without affecting other devices included in the chip, and its performance design will not be limited by the performance requirements of other devices included in the chip.
[0034] Furthermore, the inverter structure also includes an ohmic contact layer, which is deposited between the active layer and the metal layer, so that a better electrical connection is formed between the active layer and the metal layer, which can effectively improve the electrical performance of the device.
[0035] In the method for manufacturing an inverter provided in the second aspect of the embodiment of the present invention, a second MOS tube is manufactured on the first MOS tube by using a deposition process, and the drain terminals of the first MOS tube and the second MOS tube are connected through a through hole to form a stacked inverter structure, thereby greatly saving the area occupied by the inverter compared to a traditional planar structure inverter. BRIEF DESCRIPTION OF THE DRAWINGS
[0036] Figure 1 is a cross-sectional view of an inverter structure provided by an embodiment of the present invention Figure 1 ;
[0037] Figure 2 is a cross-sectional view of an inverter structure provided by an embodiment of the present invention Figure 2 ;
[0038] Figure 3 A schematic flow chart of a method for manufacturing an inverter provided in one embodiment of the present invention;
[0039] Figure 4a-4e is based on Figure 3 The device cross-sectional structure schematic diagram corresponding to the inverter manufacturing method at different process stages is shown.
[0040] Reference numerals:
[0041] 1- substrate;
[0042] 2-Shallow trench isolation structure;
[0043] 3-First source region;
[0044] 4-first drain region;
[0045] 5-gate oxide layer;
[0046] 6-polysilicon layer;
[0047] 7- insulation layer;
[0048] 8- Active layer;
[0049] 9-Ohmic contact layer;
[0050] 10- second drain region;
[0051] 11- Second source area;
[0052] 12- dielectric layer;
[0053] 13-first through hole;
[0054] 14- Second through hole. DETAILED DESCRIPTION
[0055] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the embodiments in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present invention. The terms "first", "second", "third", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.
[0056] As described in the background technology, the existing inverter is usually a planar structure, that is, N-type MOS tubes and P-type MOS tubes are formed in different regions of the substrate to form an inverter, so an inverter requires at least two different types of MOS tubes, and it is also necessary to consider whether the key dimensions of the two MOS tubes and the distance between them can ensure that the inverter can work normally. Based on this, the substrate area occupied by the inverter is large, which reduces the competitiveness of chip products. And there is no effective solution in the prior art for reducing the area of the inverter.
[0057] In view of this, the present invention creatively proposes an inverter structure, which includes: a substrate, a first MOS transistor, an insulating layer, an active layer, a metal layer and a metal interconnection layer; wherein the first MOS transistor is located on the substrate, the first MOS transistor includes a first source region, a first drain region and a gate structure, the gate structure includes a gate oxide layer and a polysilicon layer sequentially located on the substrate; the insulating layer is located on the substrate and covers the first source region, the first drain region and the gate structure; the active layer is located on a first preset area of the insulating layer, the first preset area corresponds to the first MOS transistor; The metal layer is located on the active layer to form a second source region and a second drain region; wherein the second source region, the second drain region, the active layer, the insulating layer and the polysilicon layer constitute a second MOS tube, and the first MOS tube and the second MOS tube have opposite conductivity types; the metal interconnection layer includes a dielectric layer located on the substrate and a plurality of through holes located in the dielectric layer, and the through holes include a first through hole and a second through hole; wherein the second through hole is used to lead out the first source region, the polysilicon layer and the second source region respectively, and the first through hole is used to lead out the first drain region and the second drain region together.
[0058] The inverter structure provided by the present invention forms an insulating layer, an active layer and a metal layer on the first MOS tube in sequence, so that the second source region and the second drain region formed by the polysilicon layer, the insulating layer, the active layer and the metal layer in the first MOS tube constitute the second MOS tube, and the drain ends of the first MOS tube and the second MOS tube are connected through a through hole, thereby forming a three-dimensional inverter structure in which the first MOS tube and the second MOS tube are stacked in a vertical direction, so that compared with a traditional inverter with a planar structure, the inverter structure greatly saves the area occupied by the inverter.
[0059] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0060] in, Figure 1 is a cross-sectional view of an inverter structure provided by an embodiment of the present invention Figure 1 .
[0061] Please refer to Figure 1 In one embodiment of the present invention, an inverter structure is provided, comprising:
[0062] Substrate 1.
[0063] The first MOS transistor is located on the substrate 1 , and includes a first source region 3 , a first drain region 4 and a gate structure; wherein the gate structure includes a gate oxide layer 5 and a polysilicon layer 6 which are sequentially located on the substrate 1 .
[0064] The insulating layer 7 is located on the substrate 1 and covers the first source region 3 , the first drain region 4 and the gate structure.
[0065] Specifically, the insulating layer 7 covers the first source region 3 , the first drain region 4 and the top surface of the gate structure, and covers the sidewalls of the gate structure.
[0066] In one embodiment, a shallow trench isolation structure 2 is usually formed around the first MOS transistor to isolate it from other devices; in this case, the insulating layer 7 can cover the shallow trench isolation structure 2 .
[0067] The active layer 8 is located on a first preset region of the insulating layer 7. The first preset region is a region opposite to the first MOS transistor and is slightly smaller than the region of the first MOS transistor.
[0068] Specifically, the active layer 8 covers the insulating layer 7 located on the gate structure, and covers a portion of the insulating layer 7 located on the first source region 3 and a portion of the insulating layer 7 located on the first drain region 4 .
[0069] In this embodiment, Figure 1 As shown, a portion of the first source region 3 and a portion of the first drain region 4 away from the gate structure are not covered with the active layer 8. Those skilled in the art can understand that the area on the first source region 3 and the first drain region 4 that is not covered with the active layer 8 is used for subsequent extraction of the first source region 3 and the first drain region 4. Therefore, the area on the first source region 3 and the first drain region 4 that is not covered with the active layer 8 can be determined according to actual process requirements and the size of the extraction through hole, and the present application does not impose any limitation on this.
[0070] The metal layer is located on the active layer 8 and is respectively located on both sides of the gate structure to form a second source region 11 and a second drain region 10; wherein the second source region 11, the second drain region 10, the active layer 8, the insulating layer 7 and the polysilicon layer 6 constitute a second MOS tube; and the first MOS tube and the second MOS tube have opposite conductivity types.
[0071] Specifically, combined Figure 1 The metal layer covers the sidewalls and part of the top surface of the active layer 8, that is, part of the top surface of the active layer 8 is not covered by the metal layer, and the exposed top surface of the active layer 8 corresponds to the gate structure of the first MOS tube.
[0072] In a specific embodiment, the metal layer also covers a portion of the upper surface of the insulating layer 7 that is not covered by the active layer 8. Figure 1 The metal layer also covers a portion of the insulating layer 7 on the first source region 3 and the first drain region 4 that is close to the gate structure and is not covered by the active layer 8 .
[0073] In one embodiment, the first source region 3 and the second source region 11 are located on one side of the gate structure, and the first drain region 4 and the second drain region 10 are located on the other side of the gate structure.
[0074] The metal interconnection layer includes a dielectric layer 12 formed on the substrate 1 and a plurality of through holes formed in the dielectric layer 12 , wherein the through holes include a first through hole 13 and a second through hole 14 .
[0075] In this embodiment, there are a plurality of second through holes 14, which are respectively used to lead out the first source region 3, the polysilicon layer 6 and the second source region 11. The first through hole 13 is used to lead out the first drain region 4 and the second drain region 10 together.
[0076] In this embodiment, the first drain region 4 and the second drain region 10 are led out together through the first through hole 13, so that the first drain region 4 and the second drain region 10 are electrically connected, so that the first MOS transistor and the second MOS transistor form an inverter.
[0077] In this embodiment, the first through hole 13 needs to lead out both the first drain region 4 and the second drain region 10, so the size of the first through hole 13 is larger than the size of the second through hole 14. Specifically, the present application does not impose any specific restrictions on the sizes of the first through hole and the second through hole, as long as they can meet the actual processing requirements.
[0078] In one embodiment, the material of the shallow trench isolation structure 2 may be, for example, silicon dioxide, which is used to isolate the inverter structure from other devices on the substrate 1 to avoid leakage, breakdown and other problems caused by mutual influence between devices.
[0079] In this embodiment, the substrate 1 may be a silicon substrate, or a substrate of other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium, and the present invention does not impose any limitation on this.
[0080] In this embodiment, the insulating layer 7 can serve as the gate dielectric layer of the second MOS transistor, and is used to isolate the polysilicon layer 6 from the second source region 11 and the second drain region 10, thereby preventing current from flowing from the polysilicon layer 6 to the second source region 11 and the second drain region 10 of the second MOS transistor.
[0081] As an example, the material of the insulating layer 7 can be any one of silicon nitride, silicon dioxide, and silicon carbonitride, and the thickness of the insulating layer 7 can be 20 nanometers to 500 nanometers. Of course, those skilled in the art should be aware that there are many options for the material and thickness of the insulating layer 7, and the present invention is not limited thereto.
[0082] The active layer 8 is used to form a carrier transmission channel between the second source region 11 and the second drain region 10 .
[0083] It should be noted that the threshold voltage of the second MOS tube needs to match the threshold voltage of the first MOS tube. The threshold voltage of the second MOS tube can be adjusted by adjusting the thickness of the active layer 8, for example. The thicker the active layer 8 is, the lower the threshold voltage of the second MOS tube is. As an example, the thickness of the active layer 8 is 5 nanometers to 100 nanometers. Of course, those skilled in the art can realize that there are many ways to adjust the threshold voltage of the second MOS tube, and the technicians can choose according to the actual situation, and the present invention does not limit this.
[0084] As an example, the material of the metal layer is titanium, and the thickness of the metal layer is 10 nanometers to 1000 nanometers. Of course, those skilled in the art should be aware that there are many options for the material and thickness of the metal layer, and the present invention is not limited thereto.
[0085] in, Figure 2 is a cross-sectional view of an inverter structure provided by an embodiment of the present invention Figure 2 .
[0086] In this embodiment, please refer to Figure 2 The inverter structure also includes an ohmic contact layer 9, which is located between the metal layer and the active layer 8, and the ohmic contact layer 9 is located on both sides of the gate structure; wherein the ohmic contact layer 9 can form a better electrical connection between the metal layer and the active layer 8, which can effectively improve the electrical performance of the device.
[0087] As an example, the thickness of the ohmic contact layer 9 is 50 nanometers to 100 nanometers.
[0088] It should be noted that, according to the different conductivity types of the second MOS tube, the selection of the materials of the active layer 8 and the ohmic contact layer 9 will also change accordingly. For example, if the second MOS tube is a PMOS tube, the material of the active layer 8 can be carbon nanotubes or metal oxides, and the material of the ohmic contact layer 9 can be highly doped P-type polysilicon; if the second MOS tube is an NMOS tube, the material of the active layer 8 can be hydrogenated amorphous silicon or indium gallium zinc oxide amorphous silicon or metal oxides, and the material of the ohmic contact layer 9 can be highly doped N-type hydrogenated amorphous silicon film. Therefore, the materials of the active layer 8 and the ohmic contact layer 9 can be selected according to actual conditions.
[0089] In this embodiment, the material of the through hole can be a variety of metals and alloys, such as tungsten, copper, and titanium.
[0090] As an example, the material of the dielectric layer 12 is silicon dioxide. Of course, those skilled in the art should be aware that there are many other options for the material of the dielectric layer 12, and the present invention is not limited thereto.
[0091] In summary, by sequentially forming an insulating layer, an active layer and a metal layer on the first MOS tube, the second source region and the second drain region formed by the polysilicon layer, the insulating layer, the active layer and the metal layer in the first MOS tube constitute the second MOS tube, and the drain terminals of the first MOS tube and the second MOS tube are connected through a through hole, thereby forming a three-dimensional inverter structure in which the first MOS tube and the second MOS tube are stacked in a vertical direction, so that compared with a traditional inverter with a planar structure, the inverter structure greatly saves the area occupied by the inverter.
[0092] Furthermore, by stacking, decoupling between the inverter and other chip devices can be achieved, that is, the inverter can reduce the area it occupies without affecting other devices included in the chip, and its performance design will not be limited by the performance requirements of other devices included in the chip.
[0093] Please continue to refer to Figure 3 , Figure 4a-4e ;in, Figure 3 A schematic flow chart of a method for manufacturing an inverter provided in one embodiment of the present invention; Figure 4a-4e is based on Figure 3 The device cross-sectional structure schematic diagram corresponding to the inverter manufacturing method at different process stages is shown.
[0094] like Figure 3 Combination Figure 4a-4e As shown, an embodiment of the present invention further provides a method for manufacturing an inverter, which is used to prepare the above inverter structure, and the method includes:
[0095] S1: providing a substrate 1; wherein a first MOS transistor is formed on the substrate 1, and a shallow trench isolation structure 2 is formed around the first MOS transistor, the first MOS transistor comprises a first source region 3, a first drain region 4 and a gate structure; wherein the gate structure comprises a gate oxide layer 5 and a polysilicon layer 6 sequentially formed on the substrate 1; Figure 4a shown.
[0096] S2: depositing an insulating layer 7 on the substrate 1, wherein the insulating layer 7 covers the first source region 3, the first drain region 4 and the gate structure; Figure 4b shown.
[0097] As an example, the insulating layer 7 also covers the shallow trench isolation structure 2. Of course, it should be appreciated that in other embodiments, the insulating layer 7 may not cover the shallow trench isolation structure 2, and the present invention is not limited to this.
[0098] S3: depositing an active layer 8 on a first predetermined area of the insulating layer 7; Figure 4c shown.
[0099] Among them, the first preset area can be understood as an area opposite to the first MOS tube and slightly smaller than the area of the first MOS tube; the active layer 8 is deposited on the insulating layer 7 corresponding to the gate structure, the insulating layer 7 corresponding to a part of the first source region 3, and the insulating layer 7 corresponding to a part of the first drain region 4, and the active layer 8 is not covered on the part of the first source region 3 and the part of the first drain region 4 away from the gate structure.
[0100] As an implementation, S3 may include:
[0101] S31: depositing an active material layer on the substrate 1; wherein the active material layer covers the insulating layer 7;
[0102] S32: using the first patterned mask layer as a mask, etching the active material layer to form an active layer 8 located on the first preset area.
[0103] As a specific implementation, S32 includes:
[0104] S321: spin coating a first photoresist layer on the active material layer;
[0105] S322: using a photomask to expose and develop the first photoresist layer to achieve first patterning of the first photoresist layer, thereby forming a first patterned photoresist layer;
[0106] S323: using the first patterned photoresist layer as a mask, etching the active material layer to retain the active layer 8 on the first preset area.
[0107] In this embodiment, after step S323 is completed, the following step may further include: removing the remaining first patterned photoresist layer.
[0108] In addition, it should be appreciated that the above example uses the material of the first patterned mask layer as photoresist. In actual applications, the patterned mask layer may also be made of other materials and may also be formed in other ways, and the present invention is not limited thereto.
[0109] Preferably, after completing S3, the method may further include: depositing an ohmic contact layer on the active layer 8, wherein the ohmic contact layer is located on both sides of the gate structure.
[0110] As an implementation mode, after step S31, an ohmic contact material layer is deposited on the active material layer; then, the active material layer and the ohmic contact material layer are etched with a first patterned mask layer to form an active layer 8 and an ohmic contact layer located on the first preset area.
[0111] As an example, the insulating layer 7 , the active layer 8 and the ohmic contact layer 9 are deposited by chemical vapor deposition.
[0112] S4: depositing a metal layer on the active layer 8 to form a metal layer that exposes the active layer 8 corresponding to the gate structure and is located on both sides of the gate structure to serve as a second source region 11 and a second drain region 10; wherein the second source region 11, the second drain region 10, the active layer 8, the insulating layer 7 and the polysilicon layer 6 constitute a second MOS transistor; wherein the first source region 3 and the second source region 11 are located on one side of the gate structure, and the first drain region 4 and the second drain region 10 are located on the other side of the gate structure; Figure 4d shown.
[0113] As an implementation, S4 may include:
[0114] S41: depositing a metal material layer on the substrate 1; wherein the metal material layer covers the active layer 8;
[0115] S42: using the second patterned mask layer as a mask, etching the metal material layer to form a metal layer that exposes the active layer 8 corresponding to the gate structure and is located on both sides of the gate structure, wherein the metal layers on both sides of the gate structure respectively form a second source region 11 and a second drain region 10.
[0116] As a specific implementation, S42 includes:
[0117] S421: Spin-coating a second photoresist layer on the metal material layer;
[0118] S422: using a photomask to expose and develop the second photoresist layer to achieve second patterning of the second photoresist layer, thereby forming a second patterned photoresist layer;
[0119] S423: using the second patterned photoresist layer as a mask, etching the metal material layer to form a metal layer that exposes the active layer corresponding to the gate structure and is located on both sides of the gate structure.
[0120] In this embodiment, after step S423 is completed, the following step may further include: removing the remaining second patterned photoresist layer.
[0121] In addition, it should be appreciated that the above example uses the material of the second patterned mask layer as photoresist. In actual applications, the patterned mask layer may also be made of other materials and may also be formed in other ways, and the present invention is not limited thereto.
[0122] As an example, the metal layer is deposited by physical vapor deposition.
[0123] The insulating layer 7 can serve as an etching stop layer to protect the underlying structure from being damaged when etching the active layer 8 and the metal layer, and can also serve as an etching stop point to avoid over-etching.
[0124] S5: forming a metal interconnection layer on the substrate 1; the metal interconnection layer comprises a dielectric layer 12 formed on the substrate 1 and a plurality of through holes formed in the dielectric layer 12, the through holes comprising a first through hole 13 and a second through hole 14; wherein the second through hole 14 is used to lead out the first source region 3, the polysilicon layer 6 and the second source region 11 respectively, and the first through hole 13 is used to lead out the first drain region 4 and the second drain region 10 together, so that the first drain region 4 and the second drain region 10 are electrically connected, so that the first MOS transistor and the second MOS transistor form an inverter; Figure 4e shown.
[0125] In summary, the method for manufacturing an inverter provided by the present invention manufactures a second MOS tube on a first MOS tube by thin film deposition to form a three-dimensional inverter structure, so that the area of the manufactured inverter is greatly reduced compared with the area of the inverter with a planar structure in the prior art.
[0126] Furthermore, since the second MOS tube is made by a thin film deposition process, its performance is related to the deposited insulating layer, the active layer and the metal layer, so that its own performance can be changed by adjusting the materials, thickness, etc. of the insulating layer, the active layer and the metal layer. Therefore, the performance design of the second MOS tube is no longer limited by the performance requirements of other chip devices, thereby achieving decoupling between the inverter and other chip devices.
[0127] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.
Claims
1. An inverter structure, characterized in that: include: substrate; A first MOS transistor, located on the substrate, the first MOS transistor comprising a first source region, a first drain region and a gate structure; wherein the gate structure comprises a gate oxide layer and a polysilicon layer sequentially located on the substrate; an insulating layer, located on the substrate and covering the first source region, the first drain region and the gate structure; An active layer, located on a first preset area of the insulating layer, wherein the first preset area corresponds to the first MOS transistor; a metal layer, located on the active layer and respectively located on both sides of the gate structure to form a second source region and a second drain region; wherein the second source region, the second drain region, the active layer, the insulating layer and the polysilicon layer constitute a second MOS transistor; and the first MOS transistor and the second MOS transistor have opposite conductivity types; The metal interconnection layer includes a dielectric layer located on the substrate and a plurality of through holes located in the dielectric layer, wherein the through holes include a first through hole and a second through hole; wherein the second through holes are respectively used to lead out the first source region, the polysilicon layer and the second source region, and the first through hole is used to jointly lead out the first drain region and the second drain region.
2. The inverter structure according to claim 1, characterized in that: The first MOS tube is a PMOS tube, and the second MOS tube is an NMOS tube.
3. The inverter structure according to claim 1, characterized in that: The material of the active layer includes hydrogenated amorphous silicon or indium gallium zinc oxide, and the thickness of the active layer is 5 nanometers to 100 nanometers.
4. The inverter structure according to claim 1, characterized in that: Also includes: An ohmic contact layer is located between the metal layer and the active layer, and the ohmic contact layer is located at both sides of the gate structure.
5. The inverter structure according to claim 4, characterized in that: The ohmic contact layer is a highly doped N-type hydrogenated amorphous silicon film, and the thickness of the ohmic contact layer is 5 nanometers to 100 nanometers.
6. The inverter structure according to claim 1, characterized in that: The material of the metal layer is titanium, and the thickness of the metal layer is 10 nanometers to 1000 nanometers.
7. The inverter structure according to claim 1, characterized in that: The material of the insulating layer includes silicon nitride, silicon dioxide, and silicon carbonitride, and the thickness of the insulating layer is 20 nanometers to 500 nanometers.
8. A method for manufacturing an inverter, characterized in that: The method comprises: Providing a substrate; wherein a first MOS transistor is formed on the substrate, and the first MOS transistor includes a first source region, a first drain region and a gate structure; wherein the gate structure includes a gate oxide layer and a polysilicon layer sequentially formed on the substrate; Depositing an insulating layer on the substrate, wherein the insulating layer covers the first source region, the first drain region and the gate structure; Depositing an active layer on a first preset area of the insulating layer, wherein the first preset area corresponds to the first MOS transistor; Depositing a metal layer on the active layer, wherein the metal layer exposes the active layer corresponding to the gate structure and is located on both sides of the gate structure to serve as a second source region and a second drain region; the second source region, the second drain region, the active layer, the insulating layer and the polysilicon layer constitute a second MOS transistor; A metal interconnection layer is formed on the substrate; the metal interconnection layer includes a dielectric layer formed on the substrate and a plurality of through holes formed in the dielectric layer, the through holes include a first through hole and a second through hole; the second through holes are respectively used to lead out the first source region, the polysilicon layer and the second source region, and the first through hole is used to jointly lead out the first drain region and the second drain region.
9. The method for manufacturing an inverter according to claim 8, characterized in that: Depositing an active layer on a first predetermined area of the insulating layer comprises: Depositing an active material layer on the substrate, wherein the active material layer covers the insulating layer; The active material layer is etched using the first patterned mask layer as a mask to form an active layer located on the first preset area.
10. The method for manufacturing an inverter according to claim 8, characterized in that: Depositing a metal layer on the active layer, comprising: Depositing a metal material layer on the substrate, wherein the metal material layer covers the active layer; The metal material layer is etched using the second patterned mask layer as a mask to form a metal layer that exposes the active layer corresponding to the gate structure and is located on both sides of the gate structure. The metal layers on both sides of the gate structure form a second source region and a second drain region respectively.