A method for improving the depth uniformity of deep grooves on the back side

Abstract

The present invention discloses a method for improving the depth uniformity of deep grooves on the back side, specifically, by pre-preparing a first layer on the intersection area of ​​the substrate surface provided with a photosensitive area, and then etching the intersection area and the non-intersection area having the first layer simultaneously, thereby offsetting the difference in groove depth caused by different opening sizes in the intersection area and the non-intersection area, and finally obtaining a deep groove with better depth uniformity in each groove area.

Description

Technical Field

[0001] The present invention relates to the field of image sensors, and in particular to a method for improving the depth uniformity of back deep grooves. Background Art

[0002] CMOS (Complementary Metal-Oxide-Semiconductor) image sensors have the advantages of simple process, easy integration with other devices, small size, light weight, low power consumption, and low cost. Therefore, with the development of technology, CMOS image sensors are increasingly replacing CCD (Charge-coupled Device) image sensors in various electronic products. At present, CMOS image sensors have been widely used in static digital cameras, camera phones, digital video cameras, medical cameras (such as gastroscopes), automotive cameras, etc. CMOS image sensors can be divided into FSI (Front Side Illumination) and BSI (Back Side Illumination).

[0003] However, as the pixel size of image sensors becomes smaller and smaller, the crosstalk between adjacent photosensitive areas becomes more and more serious. Crosstalk will lead to more white pixels and reduce the sensitivity of image sensors. The industry usually adopts DTI (deep trench isolation) structure to reduce crosstalk.

[0004] like Figure 1 As shown, the DTI structure generally includes a deep trench and an isolation material filled in the trench. The deep trench is generally several microns deep and has a high aspect ratio. Therefore, the polymer produced in the process of etching to form the deep trench is difficult to be extracted from the trench. The etching load effect makes the polymer in the trench area with a large characteristic size easier to be extracted than the polymer in the trench area with a small characteristic size. This results in the trench depth formed in the trench area with a small characteristic size being smaller than the trench depth in the trench area with a large characteristic size. In the image sensor chip, the deep trench isolation structure extends laterally around multiple pixel units, and the deep trench isolation structure includes a first trench extending along a first direction and a second trench extending along a second direction. There are multiple intersection areas between the multiple first trenches and the multiple second trenches, and the characteristic size of the intersection area is larger than the characteristic size of the non-intersection area, so that the etching depth of the intersection area is greater than the etching depth of the non-intersection area. Therefore, a method for improving the uniformity of the deep trench depth on the back side is urgently needed to improve the performance of the CMOS image sensor. Summary of the invention

[0005] To achieve the above object, the present invention provides a method for improving the depth uniformity of deep grooves on the back side, which specifically includes the following steps: A substrate is provided. Before etching the substrate, a first layer is arranged in at least a part of the deep groove. The substrate and the first layer are simultaneously etched to form a deep groove extending laterally and longitudinally and having an intersection area, wherein the first layer covers the intersection area so that the depth difference ratio of each area of ​​the deep groove is not greater than 5%.

[0006] Furthermore, the method for forming the first layer includes forming a patterned first mask layer on the substrate, the patterned first mask layer exposing the intersection area, etching the substrate to form a first groove, removing the first mask layer, spin coating a fluid material on the substrate to form the first layer, and forming a patterned second mask layer on the first layer, the patterned second mask layer at least exposing the deep groove area.

[0007] Furthermore, the method for forming the first layer may also include forming a photoresist layer on the substrate, exposing and developing the photoresist layer, retaining the photoresist layer in the intersection area, and forming a patterned second mask layer on the substrate, wherein the patterned second mask layer at least exposes the deep groove area.

[0008] Furthermore, the method for forming the first layer may also include forming a dielectric layer on the substrate, patterning the dielectric layer so that the patterned dielectric layer basically covers the intersection area, forming a patterned second mask layer on the dielectric layer, the patterned second mask layer at least exposes the deep trench area, and simultaneously etching away the dielectric layer and part of the silicon in the non-intersection area.

[0009] Furthermore, the fluid material is BARC and / or SOC.

[0010] Furthermore, the photoresist layer is a negative photoresist.

[0011] Furthermore, the material of the second mask layer is one or more of a photoresist material and BRAC.

[0012] Furthermore, the material of the dielectric layer is one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0013] Compared with the prior art, the technical solution of the present invention has the following beneficial effects: the present invention forms a first layer which is relatively difficult to etch in advance in the intersection area of ​​the deep groove to be formed on the surface of the substrate provided with a photosensitive area, and then etches the intersection area and the non-intersection area having the first layer at the same time, thereby offsetting the difference in groove depth caused by the different opening sizes in the intersection area and the non-intersection area, and finally obtaining deep grooves with better depth uniformity in each area, or further obtaining deep grooves with shallower depth in the intersection area. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The accompanying drawings of the present invention constitute a part of this specification and are used to further understand the present invention. The drawings illustrate embodiments of the present invention and together with the description are used to explain the principle of the present invention.

[0015] Figure 1 This is a schematic diagram of the process flow of Example 1; Figure 2 This is a schematic diagram of the process flow of Example 2; Figure 3 This is a schematic diagram of the process flow of Example 3; Figure 4 This is a schematic diagram of the mask used in the present invention. DETAILED DESCRIPTION

[0016] The following detailed descriptions are all illustrative and are intended to provide further explanation of the present invention. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs.

[0017] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit exemplary embodiments according to the present invention.

[0018] The present invention provides a method for optimizing the uniformity of deep trench etching depth to reduce the influence of etching on the structure below the trench.

[0019] The following is explained based on some examples. It should be noted that, for the convenience of description, some embodiments of the present application may use spatial relative terms such as "above", "below", "top", "below", etc. to describe the relationship between an element or component and another (or other) elements or components as shown in the various figures of the embodiments. It should be understood that in addition to the orientations described in the drawings, the spatial relative terms are also intended to include different orientations of the device in use or operation. For example, if the device in the drawings is turned over, the elements or components described as being "below" or "below" other elements or components will subsequently be positioned as being "above" or "above" other elements or components. The terms "first", "second", etc. below are used to distinguish between similar elements and are not necessarily used to describe a specific order or time sequence. It is to be understood that these terms used in this way are interchangeable where appropriate. Example

[0020] As a preferred embodiment, a method for optimizing the uniformity of deep trench etching depth provided by the present invention comprises the following steps: Combine the following Figure 1 The detailed steps of the technical solution of embodiment 1 of the present invention are introduced in detail.

[0021] like Figure 1 As shown, a substrate 100 is provided, wherein the substrate 100 has a first surface and a second surface, wherein the second surface has a connection layer 200 connected to a carrier wafer 300, and in some embodiments, the connection layer 200 includes a metal interconnect layer and a dielectric layer. A patterned photoresist layer 400 is sequentially formed on the first surface of the substrate 100, wherein the patterning needs to expose the substrate in the deep trench intersection area to be formed subsequently, and then the substrate is etched on the photoresist layer 400 to a certain thickness. The photoresist layer 400 is removed, and then a fluid material is spin-coated on the substrate to form a dielectric layer 500. In this embodiment, the fluid material uses BARC (silicon bottom anti-reflective coating) or SOC (spin-on-carbon). In some other embodiments, a mixture of SOC and SHB (silicon-containing anti-reflective coating) can also be used. Then, a patterned photoresist layer 600 is formed on the dielectric layer 500. The patterning here requires that the substrate in the intersection area and the non-intersection area of ​​the deep trench to be formed subsequently are exposed. Then, a first etching is performed to remove a part of the thickness of the first layer 500, and then a second etching is performed to synchronously etch the dielectric layer 500 and the substrate in the intersection area and the substrate in the non-intersection area, and finally, the deep trench 700 in the intersection area and the deep trench 800 in the non-intersection area have a depth difference of no more than 5% in absolute value. Example

[0022] The present invention also provides a method for improving the uniformity of deep trench etching depth, comprising the following steps: refer to Figure 2 , providing a substrate 100, the substrate 100 having a first surface and a second surface, the second surface having a connection layer 200 connected to a carrier wafer 300, in some embodiments, the connection layer 200 includes a metal interconnection layer and a dielectric layer. A photoresist layer 400 using a negative photoresist is sequentially formed on the first surface of the substrate 100, and then patterned, wherein the patterning needs to expose the substrate outside the deep groove intersection area to be formed subsequently, and then a patterned photoresist layer 600 is formed on the substrate 100, wherein the patterning here needs to expose the substrate in the deep groove intersection area and the non-intersection area to be formed subsequently, and then etched, wherein the photoresist layer 400 and the substrate in the intersection area and the substrate in the non-intersection area are etched synchronously, and finally the absolute value of the depth difference between the deep trench 700 in the intersection area and the deep trench 800 in the non-intersection area is formed to be no greater than 5%. Example

[0023] Combine the following Figure 3 Another embodiment of the present application is briefly described.

[0024] like Figure 3As shown, a substrate 100 is provided. The substrate 100 has a first surface and a second surface. The second surface has a connection layer 200 connected to a carrier wafer 300. In some embodiments, the connection layer 200 includes a metal interconnection layer and a dielectric layer. A dielectric layer 500 is sequentially formed on the first surface of the substrate 100. In this embodiment, the material of the dielectric layer is one or more of silicon nitride, silicon oxide, and silicon oxynitride. Then, a patterned photoresist layer 400 is prepared on the dielectric layer 500, wherein the patterning only needs to cover the intersection area of ​​the deep grooves to be formed subsequently, and in some other embodiments, it can also cover part of the non-intersection area. In this embodiment, the patterned photoresist layer 400 is used as a mask layer to etch the dielectric layer, retaining the dielectric layer in the intersection area, and then a patterned photoresist layer 600 is formed on the substrate 100. The patterning here needs to expose the substrate in the intersection area and non-intersection area of ​​the deep grooves to be formed subsequently, and then the substrate is etched. Here, the first etching is used to remove the dielectric layer 500 in the intersection area and part of the substrate in the non-intersection area, and then the second etching is used to synchronously etch the substrate in the intersection area and non-intersection area, and finally the deep trench 700 in the intersection area and the deep trench 800 in the non-intersection area are formed, and the absolute value of the depth difference is not greater than 5%.

[0025] like Figure 4 As shown, 12A is a mask pattern that only covers the deep trench intersection area, 11B is a mask pattern that exposes the deep trench intersection area and non-intersection area, 13A is a mask pattern that only exposes the deep trench intersection area, and 14A is a mask pattern that covers the deep trench intersection area and partially covers the non-intersection area. In the above three embodiments and some other embodiments, the following can be used: Figure 4 The mask shown is used to pattern the dielectric layer and the photoresist layer.

[0026] In addition, the present invention also provides an image sensor having a deep trench array with uniform depth prepared by the method involved in any of the aforementioned embodiments.

[0027] The basic concepts have been described above. Obviously, for those skilled in the art, the above detailed disclosure is only for example and does not constitute a limitation of the present invention. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements and corrections to the present invention. Such modifications, improvements and corrections are suggested in the present invention, so such modifications, improvements and corrections still belong to the spirit and scope of the exemplary embodiments of the present invention.

[0028] It should be understood that the embodiments described in the present invention are only used to illustrate the principles of the embodiments of the present invention. Other variations may also fall within the scope of the present invention. Therefore, as examples and not limitations, alternative configurations of the embodiments of the present invention may be considered consistent with the teachings of the present invention. Accordingly, the embodiments of the present invention are not limited to the embodiments explicitly introduced and described in the present invention.

Claims

1. A method for improving the depth uniformity of deep grooves on the back side, characterized in that: providing a substrate, Before etching the substrate, a first layer is provided in at least a portion of the deep trench. The substrate and the first layer are simultaneously etched to form deep trenches extending laterally and longitudinally and having an intersection region, wherein the first layer covers the intersection region, The depth difference ratio of each area of ​​the deep groove is no more than 5%.

2. The method according to claim 1, characterized in that: The method for forming the first layer comprises: forming a patterned first mask layer on the substrate, wherein the patterned first mask layer has a cross region, etching the substrate to form a first trench, removing the first mask layer, Spin coating a fluid material on the substrate to form the first layer, A patterned second mask layer is formed on the first layer, wherein the patterned second mask layer at least exposes the deep trench region.

3. The method according to claim 1, characterized in that The method for forming the first layer comprises: forming a photoresist layer on the substrate, exposing and developing the photoresist layer, and retaining the photoresist layer in the intersection area, A patterned second mask layer is formed on the substrate, wherein the patterned second mask layer at least exposes the deep trench region.

4. The method according to claim 1, characterized in that The method for forming the first layer comprises: forming a dielectric layer as the first layer on the substrate, and patterning the dielectric layer so that the patterned dielectric layer substantially covers the intersection area, forming a patterned second mask layer on the dielectric layer, wherein the patterned second mask layer at least exposes the deep trench region, The dielectric layer and a portion of silicon in the non-intersection region are removed by simultaneous etching.

5. The method according to claim 2, characterized in that: The flowable material is BARC and / or SOC.

6. The method according to claim 3, characterized in that The photoresist layer is a negative photoresist.

7. The method according to claim 2 or 3, characterized in that: The material of the second mask layer is one or more of a photoresist material and a BARC material.

8. The method according to claim 4, characterized in that The material of the dielectric layer is one or more of silicon oxide, silicon nitride, and silicon oxynitride.

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