Verification method and system in artificial neural network array

Abstract

Numerous examples of a verification circuit and associated methods in an artificial neural network are disclosed. In one example, a system includes: a vector-matrix multiplication array including a plurality of non-volatile memory cells arranged in rows and columns, the non-volatile memory cells being capable of respectively storing one of N possible levels corresponding to one of N possible currents; and a plurality of output blocks to receive current from respective columns of the vector-matrix multiplication array and to generate a voltage during a verify operation of the vector-matrix multiplication and to generate a digital output during a read operation of the vector-matrix multiplication.

Description

[0001] Priority declaration

[0002] This application claims priority to U.S. patent application No. 18 / 080,545, filed on December 13, 2022, entitled “Verification Method and System in Artificial Neural Network Array,” and U.S. provisional patent application No. 63 / 409,142, filed on September 22, 2022, entitled “Verification Method and System in Artificial Neural Network Array.” Technical Field

[0003] Many examples of verification circuits and associated methods in artificial neural networks are disclosed. Background Art

[0004] Artificial neural networks simulate biological neural networks (the central nervous system of animals, especially the brain), and are used to estimate or approximate functions that may depend on a large number of inputs and are usually unknown. Artificial neural networks typically consist of layers of interconnected "neurons" that exchange messages with each other.

[0005] FIG1 illustrates an artificial neural network, where circles represent inputs or layers of neurons. Connections (called synapses) are represented by arrows and have numerical weights that can be tuned based on experience. This allows the neural network to adapt to the input and be able to learn. Typically, a neural network includes multiple layers of inputs. There are typically one or more intermediate layers of neurons, and an output layer of neurons that provide the output of the neural network. Neurons at each level make decisions based on data received from the synapses, either individually or collectively.

[0006] One of the main challenges in developing artificial neural networks for high-performance information processing is the lack of adequate hardware technology. In fact, practical neural networks rely on a large number of synapses to achieve high connectivity between neurons, i.e. very high computational parallelism. In principle, this complexity can be achieved by digital supercomputers or clusters of dedicated graphics processing units. However, these approaches, in addition to their high cost, are also mediocre in energy efficiency compared to biological networks, which consume much less energy mainly due to the low-precision analog calculations they perform. CMOS analog circuits have been used for artificial neural networks, but given the large number of neurons and synapses, the synapses of most CMOS implementations are too large.

[0007] Applicant previously disclosed an artificial (simulated) neural network using one or more non-volatile memory arrays as synapses in U.S. Patent Application Publication 2017 / 0337466A1, which is incorporated herein by reference. The non-volatile memory array operates as an analog neural memory and includes non-volatile memory cells arranged in rows and columns. The neural network includes a first plurality of synapses configured to receive a first plurality of inputs and generate a first plurality of outputs therefrom, and a first plurality of neurons configured to receive a first plurality of outputs. The first plurality of synapses includes a plurality of memory cells, wherein each of the memory cells includes: a source region and a drain region spaced apart formed in a semiconductor substrate, wherein a channel region extends between the source region and the drain region; a floating gate disposed above a first portion of the channel region and insulated from the first portion; and a non-floating gate disposed above a second portion of the channel region and insulated from the second portion. Each of the plurality of memory cells stores a weight value corresponding to a plurality of electrons on the floating gate. The plurality of memory cells multiply the first plurality of inputs by the stored weight values ​​to generate a first plurality of outputs.

[0008] Non-volatile memory cell

[0009] Nonvolatile memory is well known. For example, U.S. Pat. No. 5,029,130 ​​(“the '130 patent”), which is incorporated herein by reference, discloses an array of split-gate nonvolatile memory cells, which is a type of flash memory cell. Such a memory cell 210 is shown in FIG. 2 . Each memory cell 210 includes a source region 14 and a drain region 16 formed in a semiconductor substrate 12 with a channel region 18 therebetween. A floating gate 20 is formed over and insulated from (and controls the conductivity of) a first portion of the channel region 18, and is formed over a portion of the source region 14. A word line terminal 22 (which is typically coupled to a word line) has a first portion disposed over and insulated from (and controls the conductivity of) a second portion of the channel region 18, and a second portion extending upward and located over the floating gate 20. The floating gate 20 and the word line terminal 22 are insulated from the substrate 12 by a gate oxide. A bit line 24 is coupled to the drain region 16.

[0010] Memory cell 210 is erased (where electrons are removed from the floating gate) by placing a high positive voltage on word line terminal 22, which causes the electrons on floating gate 20 to tunnel through the intervening insulator via Fowler-Nordheim (FN) tunneling from floating gate 20 to word line terminal 22.

[0011] The memory cell 210 is programmed by source side injection (SSI) with hot electrons (where electrons are placed on the floating gate) by placing a positive voltage on the word line terminal 22 and a positive voltage on the source region 14. The electron flow will flow from the drain region 16 to the source region 14. When the electrons reach the gap between the word line terminal 22 and the floating gate 20, the electrons will accelerate and become hot. Due to the electrostatic attraction from the floating gate 20, some of the heated electrons will be injected through the gate oxide onto the floating gate 20.

[0012] The memory cell 210 is read by placing a positive read voltage on the drain region 16 and the word line terminal 22 (which turns on the portion of the channel region 18 below the word line terminal). If the floating gate 20 is positively charged (i.e., the electrons are erased), the portion of the channel region 18 below the floating gate 20 is also turned on, and current will flow through the channel region 18, which is sensed as an erased state or a "1" state. If the floating gate 20 is negatively charged (i.e., programmed by electrons), the portion of the channel region below the floating gate 20 is mostly or completely turned off, and current will not (or very little) flow through the channel region 18, which is sensed as a programmed state or a "0" state.

[0013] Table 1 depicts typical voltage and current ranges that may be applied to the terminals of the memory cell 210 for performing read operations, erase operations, and program operations:

[0014] Table 1: Operation of the flash memory unit 210 of FIG. 2

[0015] WL BL SL Read 2V-3V 0.6V-2V 0V Erase About 11V-13V 0V 0V programming 1V-2V 10.5μA-3μA 9V-10V

[0016] Other split gate memory cell configurations are known as other types of flash memory cells. For example, FIG. 3 depicts a four-gate memory cell 310, which includes a source region 14, a drain region 16, a floating gate 20 above a first portion of a channel region 18, a select gate 22 (typically coupled to a word line WL) above a second portion of the channel region 18, a control gate 28 above the floating gate 20, and an erase gate 30 above the source region 14. This configuration is described in U.S. Pat. No. 6,747,310, which is incorporated herein by reference for all purposes. Here, except for the floating gate 20, all gates are non-floating gates, meaning that they are electrically connected or capable of being electrically connected to a voltage source. Programming is performed by heated electrons from the channel region 18 that inject themselves into the floating gate 20. Erasing is performed by electrons tunneling from the floating gate 20 to the erase gate 30.

[0017] Table 2 depicts typical voltage and current ranges that may be applied to the terminals of the memory cell 310 for performing read operations, erase operations, and program operations:

[0018] Table 2: Operation of the flash memory unit 310 of FIG. 3

[0019] WL / SG BL CG EG SL Read 1.0V-2V 0.6V-2V 0V-2.6V 0V-2.6V 0V Erase -0.5V / 0V 0V 0V / -8V 8V-12V 0V programming 1V 0.1μA-1μA 8V-11V 4.5V-9V 4.5V-5V

[0020] FIG4 depicts a tri-gate memory cell 410, which is another type of flash memory cell. Memory cell 410 is the same as memory cell 310 of FIG3, except that memory cell 410 does not have a separate control gate. Erase operations (thus erasing by using an erase gate) and read operations are similar to the operations of FIG3, except that no control gate bias is applied. Program operations are also completed without a control gate bias, and therefore, a higher voltage is applied on the source line during a programming operation to compensate for the lack of a control gate bias.

[0021] Table 3 depicts typical voltage and current ranges that may be applied to the terminals of the memory cell 410 for performing read operations, erase operations, and program operations:

[0022] Table 3: Operation of the flash memory unit 410 of FIG. 4

[0023] WL / SG BL EG SL Read 0.7V-2.2V 0.6V-2V 0V-2.6V 0V Erase -0.5V / 0V 0V 11.5V 0V programming 1V 0.2μA-3μA 4.5V 7V-9V

[0024] FIG5 depicts a stacked gate memory cell 510, which is another type of flash memory cell. Memory cell 510 is similar to memory cell 210 of FIG2, except that floating gate 20 extends over the entire channel region 18, and control gate 22 (which here will be coupled to the word line) extends over floating gate 20, separated by an insulating layer (not shown). Erasing is performed by FN tunneling of electrons from the FG to the substrate, programming is performed by channel hot electron (CHE) injection at the region between channel 18 and drain region 16, by electron flow from source region 14 toward drain region 16, and a read operation similar to memory cell 210 with a higher control gate voltage.

[0025] Table 4 depicts typical voltage ranges that may be applied to the terminals of the memory cell 510 and the substrate 12 for performing read operations, erase operations, and program operations:

[0026] Table 4: Operation of the flash memory unit 510 of FIG. 5

[0027] CG BL SL Substrate Read 2V-5V 0.6-2V 0V 0V Erase -8V to -10V / 0V FLT FLT 8-10V / 15-20V programming 8V-12V 3-5V 0V 0V

[0028] The methods and devices described herein can be applied to other non-volatile memory technologies, such as but not limited to FINFET split-gate flash memory or stacked-gate flash memory, NAND flash memory, SONOS (silicon-oxide-nitride-oxide-silicon, charge trapped in nitride), MONOS (metal-oxide-nitride-oxide-silicon, metal charge trapped in nitride), ReRAM (resistive RAM), PCM (phase change memory), MRAM (magnetic RAM), FeRAM (ferroelectric RAM), CT (charge trapping) memory, CN (carbon tube) memory, OTP (two-level or multi-level one-time programmable) and CeRAM (correlated electron RAM), etc.

[0029] In order to utilize a memory array comprising one of the above-described types of non-volatile memory cells in an artificial neural network, two modifications are made. First, the circuitry is configured so that each memory cell can be individually programmed, erased, and read without adversely affecting the memory states of other memory cells in the array, as further explained below. Second, continuous (analog) programming of the memory cells is provided.

[0030] Specifically, the memory state (i.e., the charge on the floating gate) of each memory cell in the array can be changed from a fully erased state to a fully programmed state, and vice versa, independently and continuously with minimal disturbance to other memory cells. This means that the cell storage device is actually analog, or at least can store one of many discrete values ​​(such as 16 or 64 different values), which allows very precise and individual tuning of all the memory cells in the memory array, and makes the memory array ideal for storing and fine tuning the synaptic weights of a neural network.

[0031] Neural Network Using Non-Volatile Memory Cell Array

[0032] Figure 6 The present example conceptually illustrates a non-limiting example of a neural network utilizing a non-volatile memory array. This example uses a non-volatile memory array neural network for a facial recognition application, but any other suitable application may also be implemented using a neural network based on a non-volatile memory array.

[0033] For this example, S0 is the input layer, which is a 32x32 pixel RGB image with 5 bits of precision (i.e., three 32x32 pixel arrays, one for each color R, G, and B, with 5 bits of precision per pixel). Synapse CB1 from input layer S0 to layer C1 applies different sets of weights in some cases and shared weights in other cases, and scans the input image with a 3x3 pixel overlapping filter (kernel), shifting the filter by 1 pixel (or more than 1 pixel as the model dictates). Specifically, the values ​​of 9 pixels in the 3x3 portion of the image (i.e., called the filter or kernel) are provided to synapse CB1, where these 9 input values ​​are multiplied by the appropriate weights, and after summing the outputs of the multiplications, a single output value is determined and provided by the first synapse of CB1 for generating a pixel of one of the feature maps of layer C1. The 3x3 filter is then shifted right by one pixel within the input layer S0 (i.e., a column of three pixels on the right is added, and a column of three pixels on the left is released), whereby the 9 pixel values ​​in this newly positioned filter are provided to the synapse CB1, where they are multiplied by the same weights and a second single output value is determined by the associated synapse. This process continues until the 3x3 filter has scanned all three colors and all bits (precision values) over the entire 32x32 pixel image of the input layer S0. The process is then repeated using different sets of weights to generate different feature maps for layer C1 until all feature maps for layer C1 are calculated.

[0034] At layer C1, in this example, there are 16 feature maps, each with 30x30 pixels. Each pixel is a new feature pixel extracted from the product of the input and the kernel, so each feature map is a two-dimensional array, so in this example, layer C1 consists of a two-dimensional array of 16 layers (remember that the layers and arrays referred to in this article are logical relationships, not necessarily physical relationships, that is, arrays do not have to be oriented to physical two-dimensional arrays). Each of the 16 feature maps in layer C1 is generated by one of sixteen different sets of synaptic weights applied to the filter scan. The C1 feature maps can all relate to different aspects of the same image features, such as boundary identification. For example, a first map (generated using a first set of weights, shared for all scans used to generate the first map) can identify circular edges, a second map (generated using a second set of weights different from the first set of weights) can identify rectangular edges, or the aspect ratio of certain features, and so on.

[0035] Before passing from layer C1 to layer S1, an activation function P1 (pooling) is applied, which pools the values ​​from consecutive non-overlapping 2x2 regions in each feature map. The purpose of the pooling function P1 is to average neighboring positions (or a max function can also be used) to, for example, reduce the dependency of edge positions and reduce the data size before entering the next stage. At layer S1, there are 16 15x15 feature maps (i.e., sixteen different arrays, each with 15x15 pixels). The synapse CB2 from layer S1 to layer C2 scans the map in layer S1 using a 4x4 filter, where the filter is shifted by 1 pixel. At layer C2, there are 22 12x12 feature maps. Before passing from layer C2 to layer S2, an activation function P2 (pooling) is applied, which pools the values ​​from consecutive non-overlapping 2x2 regions in each feature map. At layer S2, there are 22 6x6 feature maps. An activation function (pooling) is applied to the synapse CB3 from layer S2 to layer C3, where each neuron in layer C3 is connected to each map in layer S2 via a corresponding synapse of CB3. At layer C3, there are 64 neurons. Synapse CB4 from layer C3 to output layer S3 completely connects C3 to S3, i.e., each neuron in layer C3 is connected to each neuron in layer S3. The output at S3 includes 10 neurons, where the highest output neuron determines the class. For example, the output may indicate recognition or classification of the content of the original image.

[0036] The synapses at each layer are implemented using an array or a portion of an array of non-volatile memory cells.

[0037] Figure 7 A block diagram of an array that can be used for this purpose is shown in FIG. 3. The vector-matrix multiplication (VMM) array 32 includes non-volatile memory cells and serves as a synapse between one layer and the next (such as Figure 6 CB1, CB2, CB3 and CB4 in FIG. 3 ). Specifically, the VMM array 32 includes a nonvolatile memory cell array 33, an erase gate and word line gate decoder 34, a control gate decoder 35, a bit line decoder 36 and a source line decoder 37, which decode the corresponding inputs of the nonvolatile memory cell array 33. The input to the VMM array 32 may come from the erase gate and word line gate decoder 34 or from the control gate decoder 35. In this example, the source line decoder 37 also decodes the output of the nonvolatile memory cell array 33. Alternatively, the bit line decoder 36 may decode the output of the nonvolatile memory cell array 33.

[0038] The non-volatile memory cell array 33 serves two purposes. First, it stores weights to be used by the VMM array 32. Second, the non-volatile memory cell array 33 effectively multiplies the input with the weights stored in the non-volatile memory cell array 33 and each output line (source line or bit line) adds them to produce an output, which will serve as the input of the next layer or the input of the final layer. By performing multiplication and addition functions, the non-volatile memory cell array 33 eliminates the need for separate multiplication and addition logic circuits, and is also power efficient due to its in-situ memory calculations.

[0039] The output of the non-volatile memory cell array 33 is provided to a differential summer (such as a summing operational amplifier or a summing current mirror) 38, which sums the output of the non-volatile memory cell array 33 to create a single value for the convolution. The differential summer 38 is arranged to perform the summing of positive and negative weights.

[0040] The summed output value of the difference summer 38 is then provided to the activation function block 39, which modifies the output. The activation function block 39 may provide a sigmoid, tanh, or ReLU function. The modified output value of the activation function block 39 becomes the next layer (e.g., Figure 6 The elements of the feature map of layer C1 in the image are then applied to the next synapse to produce the next feature map layer or the final layer. Thus, in this example, the non-volatile memory cell array 33 constitutes a plurality of synapses (which receive their inputs from an existing neuron layer or from an input layer such as an image database), and the summing operational amplifier 38 and the activation function block 39 constitute a plurality of neurons.

[0041] Figure 7 The inputs to the VMM array 32 (WLx, EGx, CGx, and optionally BLx and SLx) may be analog levels, binary levels, or digital bits (in which case a DAC is provided to convert the digital bits to the appropriate input analog levels), and the outputs may be analog levels, binary levels, or digital bits (in which case an output ADC is provided to convert the output analog levels to digital bits).

[0042] Figure 8 1 is a block diagram depicting the use of multiple layers of VMM arrays 32, labeled here as VMM arrays 32a, 32b, 32c, 32d, and 32e. Figure 8As shown, the input (denoted as Inputx) is converted from digital to analog by a digital-to-analog converter 31 and provided to an input VMM array 32a. The converted analog input may be a voltage or a current. The first level of input D / A conversion may be accomplished by using a function or LUT (lookup table) that maps the input Inputx to the appropriate analog level of the matrix multiplier of the input VMM array 32a. The input conversion may also be accomplished by an analog-to-analog (A / A) converter to convert an external analog input into a mapped analog input to the input VMM array 32a.

[0043] The output generated by the input VMM array 32a is provided as input to the next VMM array (hidden level 1) 32b, which in turn generates outputs provided as input to the next VMM array (hidden level 2) 32c, and so on. The layers of the VMM array 32 serve as different layers of synapses and neurons of a convolutional neural network (CNN). Each VMM array 32a, 32b, 32c, 32d, and 32e can be an independent physical non-volatile memory array, or multiple VMM arrays can utilize different portions of the same non-volatile memory array, or multiple VMM arrays can utilize overlapping portions of the same physical non-volatile memory array. Figure 8 The example shown includes five layers (32a, 32b, 32c, 32d, 32e): one input layer (32a), two hidden layers (32b, 32c) and two fully connected layers (32d, 32e). One of ordinary skill in the art will appreciate that this is merely an example and that, on the contrary, the system may include more than two hidden layers and more than two fully connected layers.

[0044] Vector-Matrix Multiplication (VMM) Array

[0045] Fig. 9 A neuron VMM array 900 is depicted, which is particularly suitable for use with memory cells 310 as shown in FIG3 and used as synapses and components of neurons between an input layer and the next layer. The VMM array 900 includes a memory array 901 of nonvolatile memory cells and a reference array 902 of nonvolatile reference memory cells (at the top of the array). Alternatively, another reference array may be placed at the bottom.

[0046] In the VMM array 900, control gate lines (such as control gate line 903) extend in the vertical direction (so reference array 902 is orthogonal to control gate line 903 in the row direction), and erase gate lines (such as erase gate line 904) extend in the horizontal direction. Here, the inputs to the VMM array 900 are set on the control gate lines (CG0, CG1, CG2, CG3), and the outputs of the VMM array 900 appear on the source lines (SL0, SL1). In one example, only even rows are used, and in another example, only odd rows are used. The current placed on each source line (SL0, SL1, respectively) performs a summing function of all currents from the memory cells connected to that particular source line.

[0047] As described herein for neural networks, non-volatile memory cells of VMM array 900 (ie, memory cells 310 of VMM array 900 ) may be configured to operate in a sub-threshold region.

[0048] The nonvolatile reference memory cell and the nonvolatile memory cell described herein are biased in weak inversion (subthreshold region):

[0049] Ids=Io*e (Vg-Vth) / nVt =w*Io*e (Vg) / nVt ,

[0050] where w = e (-Vth) / nVt

[0051] Where Ids is the drain to source current; Vg is the gate voltage on the memory cell; Vth is the threshold voltage of the memory cell; Vt is the thermal voltage = k*T / q, where k is the Boltzmann constant, T is the temperature in Kelvin, and q is the electron charge; n is the slope factor = 1+(Cdep / Cox), where Cdep = the capacitance of the depletion layer, and Cox is the capacitance of the gate oxide layer; Io is the memory cell current at a gate voltage equal to the threshold voltage, and Io is related to (Wt / L)*u*Cox*(n-1)*Vt 2 is proportional to , where u is the carrier mobility, and Wt and L are the width and length of the memory cell, respectively.

[0052] For an I to V logarithmic converter that uses a memory cell (such as a reference memory cell or a peripheral memory cell) or a transistor to convert the input current into an input voltage:

[0053] Vg=n*Vt*log[Ids / wp*Io]

[0054] Wherein, wp is w of a reference memory cell or a peripheral memory cell.

[0055] For a memory array used as a vector matrix multiplier VMM array with current input, the output current is:

[0056] Iout=wa*Io*e (Vg) / nVt ,Right now

[0057] Iout=(wa / wp)*Iin=W*Iin

[0058] W=e (Vthp-Vtha) / nVt

[0059] Here, wa = w for each memory cell in the memory array.

[0060] Vthp is the effective threshold voltage of the peripheral memory cells, and Vtha is the effective threshold voltage of the main (data) memory cells. Note that the threshold voltage of the transistor is a function of the substrate bulk bias voltage, and the substrate bulk bias voltage, denoted as Vsb, can be modulated to compensate for various conditions at this temperature. The threshold voltage Vth can be expressed as:

[0061]

[0062] where Vth0 is the threshold voltage with zero substrate bias, is the surface potential, and γ is the bulk effect parameter.

[0063] The word line or control gate may be used as the input of the memory cell for the input voltage.

[0064] Alternatively, the flash memory cells of the VMM array described herein may be configured to operate in the linear region:

[0065] Ids=β*(Vgs-Vth)*Vds;β=u*Cox*Wt / L

[0066] W=αα(Vgs-Vth)

[0067] This means that the weight W in the linear region is proportional to (Vgs-Vth)

[0068] The word line or control gate or bit line or source line can be used as the input of the memory cell operating in the linear region. The bit line or source line can be used as the output of the memory cell.

[0069] For an IV linear converter, a memory cell (such as a reference memory cell or a peripheral memory cell) or a transistor operating in a linear region may be used to linearly convert an input / output current into an input / output voltage.

[0070] Alternatively, the memory cells of the VMM array described herein may be configured to operate in the saturation region:

[0071] Ids=1 / 2*β*(Vgs-Vth) 2 ; β=u*Cox*Wt / L

[0072] Wα(Vgs-Vth) 2 , which means weight W and (Vgs-Vth) 2 Proportional

[0073] The word line, control gate, or erase gate can be used as the input of the memory cell operating in the saturation region. The bit line or source line can be used as the output of the output neuron.

[0074] Alternatively, the memory cells of the VMM array described herein may be used for all regions or combinations thereof (subthreshold, linear or saturation regions) of each layer or multiple layers of a neural network.

[0075] U.S. Patent No. 10,748,630 describes Figure 7 Other examples of VMM arrays 32 of , which are incorporated herein by reference. As described herein, source lines or bit lines can be used as neuron outputs (current summing outputs).

[0076] Fig.10 A neuron VMM array 1000 is depicted, which is particularly suitable for the memory cell 210 shown in FIG. 2 and serves as a synapse between an input layer and a next layer. The VMM array 1000 includes a memory array 1003 of nonvolatile memory cells, a reference array 1001 of a first nonvolatile reference memory cell, and a reference array 1002 of a second nonvolatile reference memory cell. The reference arrays 1001 and 1002 arranged in the column direction of the array are used to convert the current input flowing into the terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs WL0, WL1, WL2, and WL3. In practice, the first nonvolatile reference memory cell and the second nonvolatile reference memory cell are diode-connected through a multiplexer 1014 (only partially depicted), in which the current input flows. The reference cells are tuned (e.g., programmed) to a target reference level. The target reference level is provided by a reference microarray matrix (not shown).

[0077] The memory array 1003 serves two purposes. First, it stores the weights that the VMM array 1000 will use on its corresponding memory cells. Second, the memory array 1003 effectively multiplies the inputs (i.e., the current inputs provided in the terminals BLR0, BLR1, BLR2, and BLR3, which the reference arrays 1001 and 1002 convert into input voltages to supply to the word lines WL0, WL1, WL2, and WL3) by the weights stored in the memory array 1003, and then adds all the results (memory cell currents) to produce an output on the corresponding bit lines (BL0-BLN), which will be the input to the next layer or the input to the final layer. By performing multiplication and addition functions, the memory array 1003 eliminates the need for separate multiplication logic circuits and addition logic circuits, and is also highly power-efficient. Here, the voltage inputs are provided on the word lines WL0, WL1, WL2, and WL3, and the outputs appear on the corresponding bit lines BL0-BLN during the read (inference) operation. The current placed on each of the bit lines BL0-BLN performs a summing function of the currents from all of the nonvolatile memory cells connected to that particular bit line.

[0078] Table 5 depicts operating voltages and currents for the VMM array 1000. The columns in the table indicate the voltages placed on the word line for a selected cell, the word line for an unselected cell, the bit line for a selected cell, the bit line for an unselected cell, the source line for a selected cell, and the source line for an unselected cell. The rows indicate read, erase, and program operations.

[0079] Table 5: Fig.10 Operation of VMM Array 1000 :

[0080] WL WL-Not selected BL BL-Not selected SL SL-Not selected Read 1V-3.5V -0.5V / 0V 0.6-2V(Ineuron) 0.6V-2V / 0V 0V 0V Erase About 5V-13V 0V 0V 0V 0V 0V programming 1V-2V -0.5V / 0V 0.1-3uA Vinh~2.5V 4V-10V 0V-1V / FLT

[0081] Fig.11 A neuron VMM array 1100 is depicted, which is particularly suitable for use with the memory cell 210 shown in FIG. 2 and serves as a synapse and component of a neuron between an input layer and a next layer. The VMM array 1100 includes a memory array 1103 of nonvolatile memory cells, a reference array 1101 of a first nonvolatile reference memory cell, and a reference array 1102 of a second nonvolatile reference memory cell. The reference arrays 1101 and 1102 extend in the row direction of the VMM array 1100. The VMM array is similar to the VMM 1000, except that in the VMM array 1100, the word lines extend in the vertical direction. Here, the inputs are provided on the word lines (WLA0, WLB0, WLA1, WLB2, WLA2, WLB2, WLA3, WLB3), and the outputs appear on the source lines (SL0, SL1) during a read operation. The current placed on each source line performs a summing function of all currents from the memory cells connected to that particular source line.

[0082] Table 6 depicts operating voltages and currents for the VMM array 1100. The columns in the table indicate the voltages placed on the word line for a selected cell, the word line for an unselected cell, the bit line for a selected cell, the bit line for an unselected cell, the source line for a selected cell, and the source line for an unselected cell. The rows indicate read, erase, and program operations.

[0083] Table 6: Fig.11 Operation of the VMM array 1100

[0084]

[0085] Fig.12 A neuron VMM array 1200 is depicted, which is particularly suitable for use with the memory cell 310 shown in FIG. 3 and is used as a synapse and component of a neuron between an input layer and a next layer. The VMM array 1200 includes a memory array 1203 of nonvolatile memory cells, a reference array 1201 of a first nonvolatile reference memory cell, and a reference array 1202 of a second nonvolatile reference memory cell. The reference arrays 1201 and 1202 are used to convert current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs CG0, CG1, CG2, and CG3. In practice, the first nonvolatile reference memory cell and the second nonvolatile reference memory cell are diode-connected through a multiplexer 1212 (only partially shown), wherein the current input flows into them through BLR0, BLR1, BLR2, and BLR3. Multiplexers 1212 each include a respective multiplexer 1205 and cascode transistor 1204 to ensure a constant voltage on a bit line (such as BLR0) of each of the first and second nonvolatile reference memory cells during a read operation. The reference cells are tuned to a target reference level.

[0086] The memory array 1203 serves two purposes. First, it stores weights to be used by the VMM array 1200. Second, the memory array 1203 effectively multiplies the inputs (current inputs provided to terminals BLR0, BLR1, BLR2, and BLR3, which are converted by reference arrays 1201 and 1202 into input voltages to be provided to the control gates (CG0, CG1, CG2, and CG3)) by the weights stored in the memory array, and then adds all the results (cell currents) to produce an output, which appears in BL0-BLN and will be the input to the next layer or the input to the final layer. By performing multiplication and addition functions, the memory array eliminates the need for separate multiplication and addition logic circuits and is also highly power efficient. Here, the inputs are provided on the control gate lines (CG0, CG1, CG2, and CG3), and the outputs appear on the bit lines (BL0-BLN) during a read operation. The current placed on each bit line performs a summing function of all currents from the memory cells connected to that particular bit line.

[0087] The VMM array 1200 implements unidirectional tuning of the non-volatile memory cells in the memory array 1203. That is, each non-volatile memory cell is erased and then partially programmed until the desired charge on the floating gate is reached. If too much charge is placed on the floating gate (causing an erroneous value to be stored in the cell), the cell is erased and the sequence of partial programming operations restarts. As shown, two rows sharing the same erase gate (such as EG0 or EG1) are erased together (which is called a page erase), and thereafter, each cell is partially programmed until the desired charge on the floating gate is reached.

[0088] Table 7 depicts operating voltages and currents for the VMM array 1200. The columns in the table indicate the voltages placed on the word line for a selected cell, the word line for an unselected cell, the bit line for a selected cell, the bit line for an unselected cell, the control gate for a selected cell, the control gate for an unselected cell in the same sector as the selected cell, the control gate for an unselected cell in a different sector than the selected cell, the erase gate for a selected cell, the erase gate for an unselected cell, the source line for a selected cell, and the source line for an unselected cell. The rows indicate read, erase, and program operations.

[0089] Table 7: Fig.12 Operation of the VMM array 1200

[0090]

[0091] Fig.13A neuron VMM array 1300 is depicted that is particularly suitable for use with memory cells 310 as shown in FIG. 3 and serves as a synapse and component of a neuron between an input layer and a next layer. The VMM array 1300 includes a memory array 1303 of nonvolatile memory cells, a reference array 1301 of a first nonvolatile reference memory cell, and a reference array 1302 of a second nonvolatile reference memory cell. The EG lines EGR0, EG0, EG1, and EGR1 extend vertically, while the CG lines CG0, CG1, CG2, and CG3 and the SL lines WL0, WL1, WL2, and WL3 extend horizontally. The VMM array 1300 is similar to the VMM array 1400, except that the VMM array 1300 implements bidirectional tuning, where each individual cell can be fully erased, partially programmed, and partially erased as needed to achieve a desired amount of charge on the floating gate due to the use of separate EG lines. As shown, reference arrays 1301 and 1302 convert input currents in terminals BLR0, BLR1, BLR2, and BLR3 into control gate voltages CG0, CG1, CG2, and CG3 to be applied to the memory cells in the row direction (through the action of diode-connected reference cells via multiplexer 1314). The current outputs (neurons) are in bit lines BL0-BLN, where each bit line sums all currents from the non-volatile memory cells connected to that particular bit line.

[0092] Table 8 depicts operating voltages and currents for the VMM array 1300. The columns in the table indicate the voltages placed on the word line for a selected cell, the word line for an unselected cell, the bit line for a selected cell, the bit line for an unselected cell, the control gate for a selected cell, the control gate for an unselected cell in the same sector as the selected cell, the control gate for an unselected cell in a different sector than the selected cell, the erase gate for a selected cell, the erase gate for an unselected cell, the source line for a selected cell, and the source line for an unselected cell. The rows indicate read, erase, and program operations.

[0093] Table 8: Fig.13 Operation of the VMM array 1300

[0094]

[0095] Fig. 22 A neuron VMM array 2200 is depicted, which is particularly suitable for the memory unit 210 shown in FIG. 2 and is used as a synapse and component of neurons between the input layer and the next layer. In the VMM array 2200, inputs INPUT0, . . . , INPUT N On bit lines BL0, BL NThe signals are received on the source lines SL0, SL1, SL2 and SL3, and outputs OUTPUT1, OUTPUT2, OUTPUT3 and OUTPUT4 are generated on the source lines SL0, SL1, SL2 and SL3, respectively.

[0096] Fig.23 A neuron VMM array 2300 is depicted that is particularly suitable for use with memory cells 210 as shown in FIG. 2 and used as synapses and components of neurons between an input layer and the next layer. In this example, inputs INPUT0, INPUT1, INPUT2, and INPUT3 are received on source lines SL0, SL1, SL2, and SL3, respectively, and outputs OUTPUT0, ..., OUTPUT N On the bit lines BL0, BL N Generate on.

[0097] Fig.24 A neuron VMM array 2400 is depicted, which is particularly suitable for use with the memory unit 210 shown in FIG. 2 and is used as a synapse and component of neurons between an input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M On word lines WL0, ......, WL M is received and output OUTPUT0, ......, OUTPUT N On the bit lines BL0, BL N Generate on.

[0098] Fig.25 A neuron VMM array 2500 is depicted, which is particularly suitable for use with the memory unit 310 shown in FIG. 3 and is used as a synapse and component of neurons between an input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M On word lines WL0, ......, WL M is received and output OUTPUT0, ......, OUTPUT N On the bit lines BL0, BL N Generate on.

[0099] Fig.26 A neuron VMM array 2600 is depicted, which is particularly suitable for use with the memory unit 410 shown in FIG. 4 and is used as a synapse and component of neurons between an input layer and the next layer. In this example, inputs INPUT0, ..., INPUT n On the vertical control gate lines CG0, CG NThe signals are received on the source lines SL0 and SL1, and outputs OUTPUT1 and OUTPUT2 are generated on the source lines SL0 and SL1.

[0100] Fig. 27 Depicted is a neuron VMM array 2700 that is particularly suitable for use with memory cells 410 as shown in FIG. 4 and used as synapses and components of neurons between an input layer and the next layer. In this example, inputs INPUT0, . . . , INPUT N are received at the gates of bit line control gates 2701-1, 2701-2, ..., 2701-(N-1), and 2701-N, which are respectively coupled to bit lines BL0, ..., BL N Example outputs OUTPUT1 and OUTPUT2 are generated on source lines SL0 and SL1.

[0101] Fig.28 A neuron VMM array 2800 is depicted, which is particularly suitable for use with memory cells 310 as shown in FIG. 3, memory cells 510 as shown in FIG. 5, and memory cells 510 as shown in FIG. Figure 7 The memory unit 710 shown in FIG. 1 is used as a synapse and a component of a neuron between an input layer and a next layer. In this example, inputs INPUT0, . . . , INPUT M On word lines WL0, . . . , WL M is received and output OUTPUT0, ......, OUTPUT N On bit lines BL0, BL N Generate on.

[0102] Fig.29 A neuron VMM array 2900 is depicted, which is particularly suitable for use with memory cells 310 as shown in FIG. 3, memory cells 510 as shown in FIG. 5, and memory cells 510 as shown in FIG. Figure 7 The memory unit 710 shown in FIG. 1 is used as a synapse and a component of a neuron between an input layer and a next layer. In this example, inputs INPUT0, . . . , INPUT M On the control gate lines CG0, CG M OUTPUT0, OUTPUT1, OUTPUT2, OUTPUT3, OUTPUT4 N On the vertical source lines SL0, SL N Each source line SL i The source line coupled to all memory cells in column i.

[0103] Fig.30A neuron VMM array 3000 is depicted, which is particularly suitable for use with memory cells 310 as shown in FIG. 3, memory cells 510 as shown in FIG. 5, and memory cells 510 as shown in FIG. Figure 7 The memory unit 710 shown in FIG. 1 is used as a synapse and a component of a neuron between an input layer and a next layer. In this example, inputs INPUT0, . . . , INPUT M On the control gate lines CG0, CG M OUTPUT0, OUTPUT1, OUTPUT2, OUTPUT3, OUTPUT4 N On the vertical bit lines BL0, BL N On generation, each bit line BL i The bit line coupled to all memory cells in column i.

[0104] Long Short-Term Memory

[0105] Prior art includes a concept called long short-term memory (LSTM). LSTM cells are commonly used in neural networks. LSTM allows a neural network to remember information for a predetermined arbitrary time interval and use the information in subsequent operations. A conventional LSTM cell includes a cell, an input gate, an output gate, and a forget gate. The three gates regulate the flow of information into and out of the cell and the time interval at which information is remembered in the LSTM. VMMs are particularly useful in LSTM cells.

[0106] FIG. 14 depicts an example LSTM 1400. The LSTM 1400 in this example includes units 1401, 1402, 1403, and 1404. Unit 1401 receives an input vector x0 and generates an output vector h0 and a unit state vector c0. Unit 1402 receives an input vector x1, an output vector (hidden state) h0 from unit 1401, and a unit state c0 from unit 1401, and generates an output vector h1 and a unit state vector c1. Unit 1403 receives an input vector x2, an output vector (hidden state) h1 from unit 1402, and a unit state c1 from unit 1402, and generates an output vector h2 and a unit state vector c2. Unit 1404 receives an input vector x3, an output vector (hidden state) h2 from unit 1403, and a unit state c2 from unit 1403, and generates an output vector h3. Additional units may be used, and an LSTM with four units is merely an example.

[0107] Figure 15 depicts an example implementation of an LSTM cell 1500 that may be used for cells 1401, 1402, 1403, and 1404 in Figure 14. LSTM cell 1500 receives an input vector x(t), a cell state vector c(t-1) from a previous cell, and an output vector h(t-1) from a previous cell, and generates a cell state vector c(t) and an output vector h(t).

[0108] LSTM cell 1500 includes sigmoid function devices 1501, 1502, and 1503, each of which applies a number between 0 and 1 to control how much of each component in the input vector is allowed to pass through to the output vector. LSTM cell 1500 also includes tanh devices 1504 and 1505 for applying a hyperbolic tangent function to the input vector, multiplier devices 1506, 1507, and 1508 for multiplying two vectors together, and an addition device 1509 for adding two vectors together. The output vector h(t) can be provided to the next LSTM cell in the system, or it can be accessed for other purposes.

[0109] Fig.16 LSTM cell 1600 is depicted, which is an example of a specific implementation of LSTM cell 1500. For the convenience of the reader, the same numbering as LSTM cell 1500 is used in LSTM cell 1600. Sigmoid function devices 1501, 1502 and 1503 and tanh device 1504 each include multiple VMM arrays 1601 and activation function blocks 1602. Therefore, it can be seen that VMM arrays are particularly useful in LSTM cells used in certain neural network systems. Multiplier devices 1506, 1507 and 1508 and addition device 1509 are implemented digitally or in analog. Activation function block 1602 can be implemented digitally or in analog.

[0110] An alternative form of LSTM cell 1600 (and another example of a specific implementation of LSTM cell 1500) is Fig.17 In Fig.17, the sigmoid function devices 1501, 1502 and 1503 and the tanh device 1504 share the same physical hardware (VMM array 1701 and activation function block 1702) in a time-division multiplexing manner. The LSTM unit 1700 also includes a multiplier device 1703 for multiplying two vectors together, an addition device 1708 for adding two vectors together, a tanh device 1505 (which includes an activation function block 1702), a register 1707 for storing the value i(t) when the value i(t) is output from the sigmoid function block 1702, a register 1704 for storing the value f(t)*c(t-1) when the value is output from the multiplier device 1703 through the multiplexer 1710, a register 1705 for storing the value i(t)*u(t) when the value is output from the multiplier device 1703 through the multiplexer 1710, and a register 1706 for storing the value o(t)*c~(t) when the value is output from the multiplier device 1703 through the multiplexer 1710, and a multiplexer 1709.

[0111] LSTM cell 1600 includes multiple sets of VMM arrays 1601 and corresponding activation function blocks 1602, while LSTM cell 1700 includes only one set of VMM arrays 1701 and activation function blocks 1702, which are used to represent multiple layers in the example of LSTM cell 1700. LSTM cell 1700 will require less space than LSTM 1600 because LSTM cell 1700 only requires 1 / 4 of its space for VMM and activation function blocks compared to LSTM cell 1600.

[0112] It is also understood that the LSTM cell will typically include multiple VMM arrays, each of which requires functionality provided by certain circuit blocks outside the VMM array (such as summers and activation function blocks and high voltage generation blocks). Providing a separate circuit block for each VMM array would require a large amount of space within the semiconductor device and would be inefficient to a certain extent. Therefore, the examples described below reduce the circuitry required outside the VMM array itself.

[0113] Gate Controlled Recursive Unit

[0114] The simulated VMM implementation can be used for a Gated Recurrent Unit (GRU) system. GRU is a gate mechanism in a recurrent neural network. GRU is similar to LSTM, except that a GRU cell generally contains fewer components than an LSTM cell.

[0115] FIG. 18 depicts an example GRU 1800. The GRU 1800 in this example includes units 1801, 1802, 1803, and 1804. Unit 1801 receives an input vector x0 and generates an output vector h0. Unit 1802 receives an input vector x1, an output vector h0 from unit 1801, and generates an output vector h1. Unit 1803 receives an input vector x2 and an output vector (hidden state) h1 from unit 1802 and generates an output vector h2. Unit 1804 receives an input vector x3 and an output vector (hidden state) h2 from unit 1803 and generates an output vector h3. Additional units may be used, and a GRU with four units is merely an example.

[0116] FIG. 19 depicts an example implementation of a GRU cell 1900 that may be used for cells 1801, 1802, 1803, and 1804 of FIG. 18. GRU cell 1900 receives an input vector x(t) and an output vector h(t-1) from a previous GRU cell, and generates an output vector h(t). GRU cell 1900 includes sigmoid function devices 1901 and 1902, each of which applies a number between 0 and 1 to components from the output vector h(t-1) and the input vector x(t). GRU cell 1900 also includes a tanh device 1903 for applying a hyperbolic tangent function to the input vector, a plurality of multiplier devices 1904, 1905, and 1906 for multiplying two vectors together, an addition device 1907 for adding two vectors together, and a complement device 1908 for subtracting the input from 1 to generate an output.

[0117] Fig. 20 A GRU unit 2000 is depicted, which is an example of a specific implementation of the GRU unit 1900. For the convenience of the reader, the same numbering is used in the GRU unit 2000 as in the GRU unit 1900. Fig. 20 As can be seen in FIG. 1 , sigmoid function devices 1901 and 1902 and tanh device 1903 each include multiple VMM arrays 2001 and activation function blocks 2002. Therefore, it can be seen that the VMM array is particularly useful in the GRU unit used in some neural network systems. Multiplier devices 1904, 1905 and 1906, addition device 1907 and complementary device 1908 are implemented in digital or analog form. Activation function block 2002 can be implemented in digital or analog form.

[0118] An alternative form of GRU unit 2000 (and another example of a specific implementation of GRU unit 1900) is Fig.21 In Fig.21In , the GRU unit 2100 utilizes a VMM array 2101 and an activation function block 2102 which, when configured as a sigmoid function, applies a number between 0 and 1 to control how much of each component in the input vector is allowed to pass through to the output vector. Fig.21 , the sigmoid function devices 1901 and 1902 and the tanh device 1903 share the same physical hardware (VMM array 2101 and activation function block 2102) in a time-division multiplexing manner. The GRU unit 2100 also includes a multiplier device 2103 for multiplying two vectors together, an addition device 2105 for adding two vectors together, a complementary device 2109 for subtracting an input from 1 to generate an output, a multiplexer 2104, a register 2106 for holding the value h(t-1)*r(t) when it is output from the multiplier device 2103 through the multiplexer 2104, a register 2107 for holding the value h(t-1)*z(t) when it is output from the multiplier device 2103 through the multiplexer 2104, and a register 2108 for holding the value h^(t)*(1-z(t)) when it is output from the multiplier device 2103 through the multiplexer 2104.

[0119] The GRU unit 2000 includes multiple sets of VMM arrays 2001 and activation function blocks 2002, while the GRU unit 2100 includes only one set of VMM arrays 2101 and activation function blocks 2102, which are used to represent multiple layers in the example of the GRU unit 2100. The GRU unit 2100 will require less space than the GRU unit 2000 because the GRU unit 2100 only requires 1 / 3 of its space for the VMM and activation function blocks compared to the GRU unit 2000.

[0120] It will also be appreciated that a GRU system will typically include multiple VMM arrays, each of which requires functionality provided by certain circuit blocks outside the VMM array (such as summers and activation function blocks and high voltage generation blocks). Providing a separate circuit block for each VMM array would require a significant amount of space within the semiconductor device and would be somewhat inefficient. Therefore, the examples described below reduce the circuitry required outside the VMM array itself.

[0121] The inputs to the VMM array can be analog levels, binary levels, pulses, time-modulated pulses, or digital bits (in which case a DAC is required to convert the digital bits to the appropriate input analog levels), and the outputs can be analog levels, binary levels, timed pulses, pulses, or digital bits (in which case an output ADC is required to convert the output analog levels to digital bits).

[0122] In general, for each memory cell in the VMM array, each weight W can be implemented by a single memory cell or by a differential cell or by two hybrid memory cells (average of 2 cells). In the case of a differential cell, two memory cells are required to implement the weight W as a differential weight (W=W+-W-). In two hybrid memory cells, two memory cells are required to implement the weight W as the average of the two cells.

[0123] Fig.31 A VMM system 3100 is depicted. In some examples, the weights W stored in the VMM array are stored as a differential pair W+ (positive weight) and W- (negative weight), where W=(W+)-(W-). In the VMM system 3100, half of the bit lines are designated as W+ lines, i.e., bit lines connected to memory cells that will store positive weights W+, and the other half of the bit lines are designated as W- lines, i.e., bit lines connected to memory cells that implement negative weights W-. The W- lines are interspersed between the W+ lines in an alternating manner. The subtraction operation is performed by a summing circuit (such as summing circuits 3101 and 3102), which receives current from the W+ line and the W- line. The output of the W+ line and the output of the W- are combined together to effectively give W=W+-W- for each (W+, W-) cell pair of all (W+, W-) line pairs. Although described above with respect to W- lines interspersed between W+ lines in an alternating manner, in other examples, the W+ lines and W- lines may be arbitrarily located anywhere in the array.

[0124] Fig.32 Another example is depicted. In VMM system 3210 , positive weights W+ are implemented in a first array 3211 , and negative weights W− are implemented in a second array 3212 , which is separate from the first array, and the resulting weights are appropriately combined together by summing circuit 3213 .

[0125] Fig.33A VMM system 3300 is depicted, in which the weights W stored in the VMM array are stored as a differential pair W+ (positive weight) and W- (negative weight), where W=(W+)-(W-). The VMM system 3300 includes an array 3301 and an array 3302. Half of the bit lines in each of the arrays 3301 and 3302 are designated as W+ lines, i.e., bit lines connected to memory cells that will store positive weights W+, and the other half of the bit lines in each of the arrays 3301 and 3302 are designated as W- lines, i.e., bit lines connected to memory cells that implement negative weights W-. The W- lines are interspersed between the W+ lines in an alternating manner. The subtraction operation is performed by a summing circuit (such as summing circuits 3303, 3304, 3305, and 3306), which receives current from the W+ lines and the W- lines. The outputs of the W+ lines and the outputs of the W- lines from each array 3301, 3302 are combined together to effectively give W=W+-W- for each (W+, W-) cell pair for all (W+, W-) line pairs. In addition, the W values ​​from each array 3301 and 3302 can be further combined by summing circuits 3307 and 3308 so that each W value is the result of subtracting the W value from array 3301 from the W value from array 3302, which means that the final result from summing circuits 3307 and 3308 is a difference of two difference values.

[0126] Each nonvolatile memory cell used in an analog neural memory system is erased and programmed to hold a very specific and precise amount of charge (i.e., number of electrons) in the floating gate. For example, each floating gate should hold one of N different values, where N is the number of different weights that can be indicated by each cell. Examples of N include 16, 32, 64, 128, and 256.

[0127] It is important to be able to accurately verify a programming operation after it has been performed. Summary of the invention

[0128] Many examples of verification circuits and associated methods in artificial neural networks are disclosed. BRIEF DESCRIPTION OF THE DRAWINGS

[0129] FIG. 1 is a diagram illustrating an example of an artificial neural network.

[0130] FIG. 2 depicts a prior art split-gate flash memory cell.

[0131] FIG. 3 depicts another prior art split gate flash memory cell.

[0132] FIG. 4 depicts another prior art split gate flash memory cell.

[0133] FIG. 5 depicts another prior art split gate flash memory cell.

[0134] Figure 6 Schematic diagram illustrating different levels of an exemplary artificial neural network utilizing one or more non-volatile memory arrays.

[0135] Figure 7 FIG. 1 is a block diagram illustrating a VMM system.

[0136] Figure 8 is a block diagram illustrating an example artificial neural network utilizing one or more VMM systems.

[0137] Fig. 9 Another example of a VMM system is depicted.

[0138] Fig.10 Another example of a VMM system is depicted.

[0139] Fig.11 Another example of a VMM system is depicted.

[0140] Fig.12 Another example of a VMM system is depicted.

[0141] Fig.13 Another example of a VMM system is depicted.

[0142] FIG. 14 depicts a prior art long short term memory system.

[0143] FIG. 15 depicts an example cell for use in a long short term memory system.

[0144] Fig.16 An example implementation of the unit of FIG. 15 is depicted.

[0145] Fig.17 Another example implementation of the unit of FIG. 15 is depicted.

[0146] FIG. 18 depicts a prior art gate-controlled recursive cell system.

[0147] FIG. 19 depicts an example cell for use in a gate-controlled recursive cell system.

[0148] Fig. 20 An example implementation of the unit of FIG. 19 is depicted.

[0149] Fig.21 Another example implementation of the unit of FIG. 19 is depicted.

[0150] Fig. 22 Another example of a VMM system is depicted.

[0151] Fig.23 Another example of a VMM system is depicted.

[0152] Fig.24 Another example of a VMM system is depicted.

[0153] Fig.25 Another example of a VMM system is depicted.

[0154] Fig.26 Another example of a VMM system is depicted.

[0155] Fig. 27 Another example of a VMM system is depicted.

[0156] Fig.28 Another example of a VMM system is depicted.

[0157] Fig.29 Another example of a VMM system is depicted.

[0158] Fig.30 Another example of a VMM system is depicted.

[0159] Fig.31 Another example of a VMM system is depicted.

[0160] Fig.32 Another example of a VMM system is depicted.

[0161] Fig.33 Another example of a VMM system is depicted.

[0162] Fig.34 Another example of a VMM system is depicted.

[0163] Fig.35A and Fig.35B The corresponding programming method is described.

[0164] Fig.36 Describes the search and execution methods.

[0165] Fig.37 Describes the precise programming method.

[0166] Fig.38 Describes the precise programming method.

[0167] Fig.39 An adaptive calibration method is depicted.

[0168] Fig.40 The calibration circuit is depicted.

[0169] Fig.41 An adaptive calibration method is depicted.

[0170] Fig.42 Depicted is the absolute calibration method.

[0171] Fig.43 A VMM system including verification circuitry is depicted.

[0172] Fig.44A An example verification circuit is depicted.

[0173] Fig.44B An example comparator circuit with offset compensation is depicted.

[0174] Fig.45 A reference voltage generator is depicted.

[0175] Fig.46 Physical arrays including reference arrays are depicted.

[0176] Fig.47 Physical arrays including reference arrays are depicted.

[0177] Fig.48 Depicted are a physical array comprising a VMM array and another physical array comprising a reference array.

[0178] Fig.49 A reference array comprising a plurality of reference sub-arrays is depicted.

[0179] Fig.50 A reference array comprising a plurality of reference sub-arrays is depicted. DETAILED DESCRIPTION

[0180] VMM system architecture

[0181] Fig.34 Depicted is a block diagram of a VMM system 3400. The VMM system 3400 includes a VMM array 3401, a row decoder 3402, a high voltage decoder 3403, a column decoder 3404, a bit line driver 3405, an input circuit 3406, an output circuit 3407, a control logic component 3408, and a bias generator 3409. The VMM system 3400 also includes a high voltage generation block 3410, which includes a charge pump 3411, a charge pump regulator 3412, and a high voltage level generator 3413. The VMM system 3400 also includes a (programming / erasing or weight adjustment) algorithm controller 3414, an analog circuit 3415, a control engine 3416 (which may include special functions such as arithmetic functions, activation functions, embedded microcontroller logic, but is not limited to such), a test control logic unit 3417, and a static random access memory (SRAM) block 3418 to store intermediate data such as for input circuits (e.g., activation data) or output circuits (neuron output data) or data for programming (such as data for an entire row or multiple rows).

[0182] The input circuit 3406 may include various circuits such as a DAC (digital-to-analog converter), a DPC (digital-to-pulse converter, digital-to-time modulated pulse converter), an AAC (analog-to-analog converter, such as a current-to-voltage converter, a logarithmic converter), a PAC (pulse-to-analog level converter), or any other type of converter. The input circuit 3406 may implement one or more of normalization, linear or nonlinear up / down scaling functions, or arithmetic functions. The input circuit 3406 may implement a temperature compensation function for the input level. The input circuit 3406 may implement an activation function such as a ReLU or a sigmoid. The input circuit 3406 may store digital activation data to be applied as an input signal or combined with an input signal during a programming or read operation. The digital activation data may be stored in a register. The input circuit 3406 may include circuits for driving array terminals, such as CG, WL, EG, and SL lines, which may include sample-and-hold circuits and buffers. The DAC may be used to convert the digital activation data into an analog input voltage to be applied to the array.

[0183] Output circuit 3407 may include circuits such as ITV (current-to-voltage circuit), ADC (analog-to-digital converter, which is used to convert neuron analog output into digital bits), AAC (analog-to-analog converter, such as current-to-voltage converter, logarithmic converter), APC (analog-to-pulse converter, analog-to-time modulated pulse converter) or any other type of converter. Output circuit 3407 can convert the array output into activation data. Output circuit 3407 can implement an activation function, such as a rectified linear activation function (ReLU) or sigmoid. Output circuit 3407 can implement one or more of statistical normalization, regularization, up / down scaling / gain function, statistical rounding, or arithmetic functions (e.g., addition, subtraction, division, multiplication, shift, logarithm) for the neuron output. Output circuit 3407 can implement a temperature compensation function for the neuron output or array output (such as bit line output) to keep the power consumption of the array approximately constant over a temperature range or to improve the accuracy of the array (neuron) output, such as by keeping the IV slope approximately the same over a temperature range. The output circuit 3407 may include a register for storing output data.

[0184] Fig.35AA programming method 3500 is depicted. First, the method starts (step 3501), which typically occurs in response to receiving a program command. Next, a bulk programming operation programs all cells to a "0" state (step 3502). Then, a soft erase operation erases all cells to a weak erase level so that each cell will consume, for example, approximately 1 μA-5 μA of current during a read operation (step 3503). This is in contrast to a deep erase level, in which each cell will consume, for example, approximately 20 μA-30 μA of current during a read operation. Then, a hard programming operation is performed on all unselected cells to a very deep programming state to add electrons to the floating gate of the cell (step 3504), thereby ensuring that those cells are truly "off," meaning that those cells will consume a negligible amount of current during a read operation.

[0185] A coarse programming operation is then performed to program the selected cells to a level closer to the target, such as 2X-100X the target. A coarse programming operation is performed on the selected cells (step 3505), followed by a fine programming operation (step 3506) to program the precise value desired for each selected cell.

[0186] The coarse programming operation (3505) may consist of multiple coarse verification / programming cycles. In each coarse verification / programming cycle, a verification operation is performed to verify whether the cell output meets the coarse target; if not, a programming operation is performed again on the cell. The verification / programming cycle is repeated until the cell output of all target cells meets the coarse target.

[0187] The precise programming operation (3506) may consist of multiple precise verification / program verification / programming cycles. In each precise verification / programming cycle, a verification operation is performed to verify whether the cell output meets the precise target; if not, a programming operation is performed again on the cell. The verification / programming cycle is repeated until the cell output of all target cells meets the precise target.

[0188] Fig.35B Another programming method 3510 is depicted that is similar to programming method 3500. However, instead of Fig.35A After the method starts (step 3501), all cells are erased to the "1" state using an erase operation (step 3512). Then, all cells are programmed to a weakly programmed state (level) using a soft programming operation (step 3513), so that each cell will consume, for example, about 3μA-5μA of current during a read operation. Afterwards, a hard programming operation is performed on all unselected cells to a very deep programmed state (step 3504), followed by Fig.35A Rough and fine programming (3505-3506) is performed as in. Fig.35B A variation of the example would remove the soft programming method (step 3513).

[0189] Fig.36 A first example of a coarse programming operation 3505 is depicted, which is a search and execution method 3600. First, a lookup table search is performed to determine a coarse target current value (I ) for a selected cell based on the value intended to be stored in the selected cell. CT )(Step 3601). For example, the table is created by silicon characterization or wafer test calibration. Assume that the selected cell can be programmed to store one of N possible values ​​(e.g., 128, 64, 32 without limitation). Each of the N values ​​will correspond to a different expected current value (I D In one example, the lookup table may contain M possible current values ​​to be used as a rough target current value I for the selected cell during the search and execution of method 3600. CT , where M is an integer less than N. For example, if N is 8, then M can be 4, which means that there are 8 possible values ​​that the selected cell can store, and one of the 4 rough target current values ​​will be selected as the rough target for the search and execution method 3600. That is, the search and execution method 3600 (which, as indicated above, is an example of the coarse programming method 3505) is intended to quickly program the selected cell to a value that is somewhat close to the desired value (I D ) value (I CT ), then the precision programming method 3506 aims to program the selected cell more precisely to the desired value (I D ).

[0190] For a simple example of N=8 and M=4, examples of cell values, desired current values, and rough target current values ​​are depicted in Tables 9 and 10:

[0191] Table 9: Example of N expected current values ​​when N = 8

[0192] <![CDATA[ The value stored in the selected cell ]]> <![CDATA[ Expected current value (I D ) ]]> 000 100pA 001 200pA 010 300pA 011 400pA 100 500pA 101 600pA 110 700pA 111 800pA

[0193] Table 10: Example of M target current values ​​when M = 4

[0194] <![CDATA[ Rough target current value (I CT ) ]]> <![CDATA[ Associated cell value ]]> <![CDATA[800pA+ I CTOFFSET1 ]]> 000，001 <![CDATA[1600pA+ I CTOFFSET2 ]]> 010，011 <![CDATA[2400pA+ I CTOFFSET3 ]]> 100，101 <![CDATA[3200pA+ I CTOFFSET4 ]]> 110，111

[0195] Offset value I CTOFFSETx Used to prevent the desired current value from being exceeded during coarse adjustment.

[0196] Once the rough target current value I is selected CT, the selected cell is programmed by applying a voltage v0 to the appropriate terminal of the selected cell based on the cell architecture type of the selected cell (e.g., memory cell 210, 310, 410, or 510) (step 3602). If the selected cell is a memory cell 310 of the type in FIG. 3, then a voltage v0 will be applied to the control gate terminal 28 and the voltage will be programmed according to the rough target current value I CT , v0 can be 5V-7V. The value of V0 can be optionally obtained from the stored value of v0 and the rough target current value I CT The voltage is determined in the voltage lookup table.

[0197] Next, by applying a voltage v i =v i-1 +v increment to program the selected cell, where i starts at 1 and increments each time the step is repeated, and where v increment is a small fine voltage that will result in a degree of programming appropriate for the desired granularity of change (step 3603). Thus, the first time step 3603 is performed, i=1, and v1 will be v0+v increment Then, a verify operation occurs (step 3604), in which a read operation is performed on the selected cell and the current consumed by the selected cell (I cell ) and the rough target threshold I CT For comparison. If I cell Less than or equal to I CT (which is here the first threshold), then the search and execution method 3600 is complete and the precise programming method 3506 can begin. cell Not less than or equal to I CT , then i is incremented and step 3603 is repeated.

[0198] Therefore, at the moment when the coarse programming method 3505 ends and the fine programming method 3506 begins, the voltage v i will be the final voltage used to program the selected cell, and the selected cell will store the value corresponding to the rough target current I CT The associated value, where I cell >=I CT The precise programming method 3506 programs the selected cell to a level where it consumes current I during the read operation. D To the extent that (plus or minus an acceptable amount of deviation, such as + / - 30% or less, e.g., + / - 50 pA), the current is the expected current value associated with the value intended to be stored in the selected cell.

[0199] Fig.37Depicted are examples of different voltage progressions that may be applied to the control gates of selected memory cells during a coarse programming operation 3505 and / or a fine programming operation 3506. It consists of multiple verify / program cycles.

[0200] In the first method, increasing voltages are applied to the control gate in a progressive manner to program the selected memory cell. The starting point is v i , which during the fine programming operation 3506 will be the final voltage applied during the coarse programming method 3505. The increment v p1 Add to v1, then use the voltage v1+v p1 The selected cell (indicated by the second pulse from the left in progressive 3701) is programmed. p1 is less than v increment (the voltage increment used during the coarse programming method 3505). After each programming voltage is applied, a verify operation is performed (similar to step 3404), in which it is determined whether Icell is less than or equal to I PT1 (which is the first precise target current value and is the second threshold here), where I PT1 =I D +I PT1OFFSET , where I PT1OFFSET is the offset value added to prevent programming overshoot. If not, another increment v p1 is added to the previously applied programming voltage and the process is repeated. cell Less than or equal to I PT1 Optionally, if I PT1 Equal to I D or approximately equal to I with sufficient accuracy D (ie, plus or minus an acceptable amount of deviation), the selected memory cell has been successfully programmed.

[0201] If I PT1 Not close enough to I D , that is, it is not approximately equal to I with sufficient accuracy D , further programming of smaller granularity occurs. Here, step 3702 is now used. The starting point for step 3702 is the final voltage used for programming under step 3701. Increment V p2 (It is less than v p1 ) is added to the voltage, and the combined voltage is applied to program the selected memory cell. After each programming voltage is applied, a verification operation (similar to step 3404) is performed, in which I cell Is it less than or equal to I PT2 (which is the second precise target current value and is the third threshold value here), where I PT2 =ID+IPT2OFFSET , where I PT2OFFSET is the offset value added to prevent programming overshoot. If not, another increment v p2 is added to the previously applied programming voltage and the process is repeated. cell Less than or equal to I PT2 (plus or minus an acceptable amount of deviation), then that portion of the programming sequence stops. Here, it is assumed that I PT2 Equal to I D or close enough to I D , so that programming can stop because the target value has been achieved with sufficient accuracy. It will be appreciated by one of ordinary skill in the art that additional progression can be applied by using smaller and smaller programming increments. For example, in Fig.38 In , three progressions (3801, 3802, and 3803) are applied instead of just two.

[0202] The second method is Fig.37 The progressive 3703 and Fig.38 Instead of increasing the voltage applied during programming of the selected memory cell, the same voltage is applied for the duration of the increasing period. That is, the additional time increment t p1 added to the programming pulses so that each pulse applied is longer than the previously applied pulse by t p1 After each programming pulse is applied, a verify operation is performed that is the same as that previously described for progression 3701. Optionally, additional progressions may be applied where the additional time increments added to the programming pulses are of shorter duration than the previously used progression. Although only one time progression is shown, one of ordinary skill in the art will appreciate that any number of different time progressions may be applied.

[0203] Additional details of three examples of coarse programming method 3505 will now be provided.

[0204] Fig.39 Another example of a coarse programming method 3505 is depicted, which is an adaptive calibration method 3900. The adaptive calibration method starts (step 3901). The cell is programmed with a default starting value v0 (step 3902). Unlike in the search and execute method 3600, here v0 is not derived from a lookup table, but can be a relatively small initial value. The control gate voltage of the cell is measured at a first current value IR1 (e.g., 100 nA) and a second current value IR2 (e.g., 10 nA), and a subthreshold slope is determined based on these measurements (e.g., 360 mV / dec) and stored (step 3903).

[0205] Determine the new programming voltage v iThe first time this step is performed, i=1, and v1 is determined based on the stored subthreshold slope value and the current target and offset values ​​using a subthreshold formula, such as the following:

[0206] Vi=V i-1 +V increment ,

[0207] Where V increment Proportional to the slope Vg

[0208] Vg=n*Vt*log[Ids / wa*Io]

[0209] Here, wa is the w of the memory cell, and Ids is the current target value plus the offset value.

[0210] If the stored slope value is relatively steep, a relatively small current offset value may be used. If the stored slope value is relatively flat, a relatively high current offset value may be used. Thus, determining the slope information allows the selection of a current offset value that is customized for the particular cell under consideration. This will ultimately make the programming process shorter. As this step is repeated, i is incremented and v is incremented. i =v i-1 +v increment Then use v i Programming. increment Can be stored from v increment The value of is determined from the lookup table with the target current value.

[0211] Next, a verify operation occurs, in which a read operation is performed on the selected cell and the current consumed by the selected cell (I cell ) and the rough target threshold I CT Compare (step 3905). If I cell Less than or equal to I CT , where I CT Set to =I D +I CTOFFSET , where I CTOFFSET is the offset value added to prevent programming overshoot, then the adaptive calibration method 3900 is complete and the precise programming operation 3506 can begin. cell Not less than or equal to I CT , then repeat steps 3904-3905, and i is incremented. Then, the precise programming method 3506 is started, where the voltage v i is the final voltage used to program the selected cell.

[0212] Fig.40Depicted are aspects of an adaptive calibration operation 3900. During step 3903, current source 4001 applies current values ​​IR1 and IR2 to a selected cell (here memory cell 4002), and then measures the voltage at the control gate of memory cell 4002 (CGR1 for IR1 and CGR2 for IR2). The slope is determined as (CGR2-CGR1) / dec of the current, which is the slope of VCG versus LOG(I).

[0213] Fig.41 Another example of a coarse programming operation 3505 is depicted, which is an adaptive calibration method 4100. The adaptive calibration method starts (step 4101). The cell is programmed with a default starting value v0 (step 4102). V0 is derived from a lookup table, such as created based on silicon characteristics, whose values ​​are offset so as not to exceed the target programming value.

[0214] In the next step 4103, an IV slope parameter is created for predicting the next programming voltage, and the first control gate read voltage V CGR1 is applied to the selected cell and the resulting cell current IR1 is measured. Then, the second control gate read voltage V CGR2 is applied to the selected cell and the resulting cell current IR2 is measured. The slope is determined based on these measurements and is stored, for example, according to the equation in the subthreshold region (a cell operating in subthreshold):

[0215] Slope = (V CGR1 -V CGR2 ) / (LOG(IR1)-LOG(IR2))

[0216] (Step 4103). CGR1 and V CGR2 Examples of the values ​​of are, for example, 1.5 V and 1.3 V, respectively.

[0217] Determining the slope information allows the selection of a V tailored to the particular cell in question. increment This will ultimately make the programming process shorter.

[0218] When step 4104 is repeated, i is incremented and the new desired programming voltage V is determined based on the stored slope value and the current target and offset values ​​using the following equation: i :

[0219] V i =V i-1 +V increment ,

[0220] For i-1, V increment =α*slope*(LOG(IR1)-LOG(I CT )), where ICT is the target current, and α is a predetermined constant <1 (programmed offset value) to prevent overshoot, for example, 0.9. i It is VSLP or VCGP, that is, the source line programming voltage or the control gate programming voltage.

[0221] The cell is then programmed using Vi (step 4104).

[0222] Next, a verify operation occurs, in which a read operation is performed on the selected cell and the current consumed by the selected cell (I cell ) and I CT Compare (step 4106). If I cell Less than or equal to I CT (which is the rough target threshold here), where I CT Set to =I D +I CTOFFSET , where I CTOFFSET If i is an offset value added to prevent programming overshoot, the process proceeds to step 4107. If not, the process returns to step 4104 and i is incremented.

[0223] In step 4107, I cell and less than I CT Threshold CT2 The purpose of this is to see whether overshoot has occurred. That is, although the goal is to make I cell below ICT, but if it is much below ICT, overshoot has occurred and the stored value may actually correspond to an erroneous value. cell Not less than or equal to I CT2 , then overshoot has not occurred and the adaptive calibration method 4100 has been completed, at which point the process proceeds to the precise programming operation 3506. cell Less than or equal to I CT2 , then an overshoot has occurred. The selected cell is then erased (step 4108), and the programming process restarts at step 4102, where i is reset to 0. Optionally, if step 4108 is performed more than a predetermined number of times, the selected cell may be considered a bad cell that should not be used.

[0224] The fine programming operation 3506 may consist of multiple verify and program (V / P) cycles, where the programming voltage is incremented by a constant fine voltage with a fixed pulse width, or where the programming voltage is fixed and the programming pulse width is varied.

[0225] Optionally, the step of determining whether the current through the selected non-volatile memory cell during a read or verify operation is less than or equal to a coarse target threshold can be performed by applying a fixed bias to the terminals of the non-volatile memory cell; measuring and digitizing the current consumed by the selected non-volatile memory cell to generate digital output bits; and comparing the digital output bits to digital bits representing a first threshold current.

[0226] Optionally, the step of determining whether the current through the selected non-volatile memory cell during a read or verify operation is less than or equal to a coarse target threshold can be performed by applying a fixed bias to the terminals of the non-volatile memory cell; measuring and digitizing the current consumed by the selected non-volatile memory cell to generate digital output bits; and comparing the digital output bits to digital bits representing a first threshold current.

[0227] Optionally, the step of determining whether the current through the selected non-volatile memory cell during a read or verify operation is less than or equal to a coarse target threshold can be performed by applying an input to a terminal of the non-volatile memory cell; modulating the current consumed by the selected non-volatile memory cell with an output pulse to generate a modulated output; digitizing the modulated output to generate digital output bits; and comparing the digital output bits to digital bits representing a first threshold current.

[0228] Fig.42 A third example of a coarse programming operation 3505 is depicted, which is an absolute calibration method 4200. The absolute calibration method starts (step 4201). The cell is programmed with a default starting value v0 (step 4202). At a current value I target The control gate voltage (VCGRx) of the cell is measured and stored (step 4203). Based on the stored control gate voltage and the current target value and offset value I offset +I target To determine a new desired voltage v1 (step 4204). For example, the new desired voltage v1 can be calculated as follows: v1 = V0 + (VCGBIAS - stored VCGR), where VCGBIAS is the default read control gate voltage at the maximum target current, for example, equal to about 1.5V, and the stored VCGR is the read control gate voltage measured in step 4203.

[0229] Then use v i Program the cell. When i=1, use the voltage v1 from step 4204. When i>1, use the voltage v i =v i-1 +v increment .v increment Can be stored from vincrement Next, a verification operation is performed, in which a read operation is performed on the selected cell, and the current consumed by the selected cell (I cell) with I CT Compare (step 4206). If I cell Less than or equal to I CT (which is the threshold here), then the absolute calibration method 4200 is complete and the precise programming method 3506 can begin. cell Not less than or equal to I CT , then steps 4205-4206 are repeated, and i is incremented.

[0230] A single weight verification method can be used to verify whether a cell has achieved a weight target due to a programming operation. A memory cell is selected for a verification operation and then the weight target is determined by the following reference. Figure 43 to Figure 49 Describes a verification mechanism to verify the output of a memory cell.

[0231] A differential weight verification method may be used to determine whether a differential cell (formed by two cells, where the stored value is the difference of the values ​​stored in the two cells) has achieved a weight target as a result of a programming operation. Two cells associated with a differential weight are selected for a verification operation. Then, the differential weight is determined by the following reference. Figure 43 to Figure 49 The verification mechanism described is used to verify the output difference between units. For example, if unit 1 stores a w+ value and unit 2 stores a w- value, then w=w+-w- is the differential weight. Unit 1 and unit 2 are two units to be selected for the verification operation to determine whether the weight w has achieved the target. Alternatively, the w- value of unit 2 is verified first, and then the differential weight w is verified. Alternatively, the w+ value of unit 1 is verified first, and then the differential weight w is verified. Alternatively, the w+ value of unit 1 and the w- value of unit 2 are verified in the first operation, and then the differential weight w is verified in the second operation.

[0232] Fig.43 A VMM system 4300 is depicted. A current-to-voltage converter and analog-to-digital converter block 4301 receives current from a VMM array 3401, typically from a bit line or source line in the VMM array 3401, and provides an output to a verification circuit 4302. The current-to-voltage converter and analog-to-digital converter block 4301 and the verification circuit 4302 together are output blocks coupled to the VMM array 3401 to generate a voltage during a verification operation of the VMM array 3401 and to generate a digital output during a read operation of the VMM array 3401. Each current-to-voltage converter in block 4301 converts a current into a voltage. The analog-to-digital converters in block 4301 are reconfigured (such as described below with reference to Fig.44AThe described manner) is to be used during a verification operation (also referred to as a read-verify operation). During the verification operation, a reference array 4304 is used to generate all N possible current targets (e.g., 32 values ​​ranging from 3nA-96nA in increments of 3nA). Each of the N possible current targets corresponds to one of the N weight targets in the corresponding reference memory cell stored in the reference array 4304. Alternatively, a master reference current generator 4305 is used to generate all N current targets. The reference current from the reference array 4304 or the master reference current generator 4305 is provided to a reference voltage generator 4303, which includes a voltage DAC, and the reference current is converted into a reference voltage using the voltage DAC, wherein there are N possible voltages corresponding to the N possible values. For example, for a 5-bit cell, there are 32 reference voltages corresponding to 32 current targets. An appropriate one of the N voltage values ​​is selected for comparison by the verification circuit 4302 against the voltage provided by the corresponding current-voltage converter 4301. This comparison is a verification operation performed by verification circuit 4302. Thus, the weights can be verified after they are programmed into VMM array 3401. In this method, verification is accomplished by comparing the output voltage from the memory cell with a reference voltage from voltage reference generator 4303.

[0233] Alternatively, a reference current digital-to-analog converter (IDAC) is used to directly verify the cell current without using a current-to-voltage converter, which means that the cell current is compared with a reference current. Under this method, the delay and variation will usually be large due to the settling time of low current (e.g., a few nA) circuits.

[0234] Fig.44A A neuron output ITV+ADC+verification circuit 4488 is depicted, which includes a current-to-voltage converter (ITV) 4401, a successive approximation register (SAR) analog-to-digital converter (ADC) 4402, and a verification circuit 4403. The verification circuit 4403 includes a comparator 4404 (which is also used to generate a digital output during a read operation or a read neuron operation), a reference voltage selection circuit 4406, and a verification register 4405. The verification register 4405 is a data output register of the SAR ADC 4402, which is used here to perform a verification function, but can also be used to generate a digital output during a read operation or a read neuron operation. The current-to-voltage converter 4401 and the SAR analog-to-digital converter 4402 are Fig.43 An example of a specific implementation of the current-to-voltage converter and the analog-to-digital converter 4301 in FIG. 4 and verifying that the circuit 4403 is Fig.43 An example of a specific implementation of the verification circuit 4302 in FIG.

[0235] The current-to-voltage converter 4401 and the SAR analog-to-digital converter 4301 may be used during a read operation or a neural read operation. However, the current-to-voltage converter 4401 and the SAR analog-to-digital converter 4301 may also be used during a verification operation in which a weight (intended to be one possible weight value among N possible weight values) that has been programmed into a non-volatile memory cell in a VMM array is verified.

[0236] The current-to-voltage converter 4401 receives current from the VMM array from a single selected cell and converts the current into a voltage. The current-to-voltage conversion may be accomplished by a plurality of resistors ITV (RITV) 4490R or a plurality of capacitors ITV (CITV) 4490C. One of the N possible reference voltages is provided to the verification circuit 4403 via a verification register 4405 and a verification reference voltage selection circuit 4406. The verification register may be, for example, an 8-bit register that is used to select a voltage reference level from 256 voltage reference levels in the verification reference voltage selection circuit 4406. The verification reference voltage that is an input (via a verification reference voltage line) to the verification reference voltage selection circuit 4406 is determined by, for example, a Fig.45 The global verification reference voltage generator in 4401 is provided. The comparator 4404 then compares the voltage from the current-to-voltage converter 4401 with one of the N possible reference voltages to indicate whether the cell is storing the correct value. The capacitor and SAR logic in the SAR ADC 4402 are not used during the verification operation. In one example, the control circuit closes the switch S1A in the SARADC 4402 to provide the positive output Vinp of the ITV 4401 directly to the non-inverting input of the comparator 4404, and opens the switch (unnamed) and closes the switch (unnamed) to provide the output of the verification reference voltage selection circuit 4406 to the inverting input of the comparator 4404.

[0237] ITV+ADC+verification circuit 4488 can be used for single weight verification operation as well as differential weight verification operation. For single weight verification operation, only one input from one unit is required. The output voltage of ITV 4401 is proportional to the value of the unit current and is verified relative to the reference voltage level provided by the verification reference voltage selection circuit 4406. For differential weight verification operation, two inputs from two units are two inputs to ITV+ADC+verification circuit 4488, and the output voltage of ITV 4401 (such as Vinp) is proportional to the difference of the two unit currents and is verified relative to the reference voltage level provided by the verification reference voltage selection circuit 4406.

[0238] The total offset compensation of the ITV+ADC+verification circuit 4488 can be fine-tuned by using the offset trim of the comparator 4404. This offset can be further fine-tuned by trimming the resistor 4490R or capacitor 4490C of the 4401 ITV circuit.

[0239] In another example, the overall gain compensation of the ITV+ADC+verification circuit 4488 may be fine tuned by fine tuning the resistor 4490R or the capacitor 4490C of the 4401 ITV circuit.

[0240] An alternative method of offset compensation can be performed in the time domain by using an ITV 4401 with a capacitor 4490C. An output voltage is generated by the ITV 4401 using a variable width pulse with an integrated reference current input for implementing the capacitor 4490C. A comparator 4404 compares the output voltage from the ITV 4401 to the reference voltage. The parameters of the variable width pulse are stored, such as by a counter (not shown) in the digital domain or by a table (not shown) storing the analog voltage in the analog domain of each ITV (the analog voltage is converted from the variable pulse input). The controller (not shown) uses this information to enable the ITV for verification operation using an enable signal.

[0241] Fig.44B A comparator and offset circuit 4490 is depicted, which may be used in place of Fig.44A The comparator 4404 in the circuit 4490 is used to add the additional functionality of offset compensation. The comparator and offset circuit 4490 includes a comparator 4491 that compares the inputs VINP and VINN (which may be the same as Fig.44A ) to generate the output COMPOUT and its complement COMPOUTB. The calibration circuit 4492 can be adjusted to provide the offset voltage VON to the comparator 4491, and the calibration circuit 4493 can be adjusted to provide the offset voltage VOP to the comparator 4492.

[0242] Fig.45 A reference voltage generator 4500 is depicted. The reference voltage generator 4500 is an example implementation of the reference voltage generator 4303. In one example, a reference array 4304 (not shown) provides a maximum current from a reference cell, where the current represents the highest possible weight (of N possible weights) that can be stored in a non-volatile memory cell. The provided maximum current from the reference cell is converted by a current-to-voltage converter 4501 into a high verification reference voltage, which can be accomplished using a resistor current-to-voltage converter (RITV) 4511 or a capacitor current-to-voltage converter (CITV) 4510.

[0243] This voltage is then used to generate, for example, 32 verification reference voltages for a 5-bit cell, such as through a resistor string 4504, which includes N-1 resistors in series here. In another example, the reference array provides a reference current that is converted into a reference voltage, such as a reference current that can be a mid-range value that is appropriately converted into all N reference voltages (e.g., through a current ratio mirror, through a trimmed resistor value, or through a capacitor value that is trimmed via an ITV circuit). The ITV 4501 shown in the figure uses a differential operational amplifier. The ITV is a replica of the subcircuit ITV4301 in the VMM system 4300, and is also shown as the ITV 4401 in the ITV+ADC+verification circuit 4488. The differential operational amplifier (opamp) is a replica of the local differential op amp 4480 in Figure 44, so that the N global references can track the local voltage from the ITV 4301 through PVT (process, power source, or temperature) changes. Alternatively, the ITV 4501 can be based on a single-ended operational amplifier. Resistors 4511x and capacitors 4510x are trimmable to adjust the range and compensate for mismatch or offset variations. Resistor string 4504 is trimmable to adjust the range VN to V1, shift the range VN to V1 up / down, or adjust the local value VN to V1.

[0244] In another example, a constant current bias (such as from an IDAC) is used instead of a reference current from a reference array.

[0245] Current bias or reference current from a reference array is adjustable to achieve a target value. They also compensate for PVT (process, power source or temperature) variations.

[0246] The total global offset and mismatch compensation of the ITV+ADC+verification circuit 4488 can be fine-tuned by using the offset and mismatch trim of the reference generator 4500. This can be done by adjusting the current bias 4512 or trimming resistors 4511a and 4511b, capacitors 4510a and 4510b, or resistor string 4504.

[0247] Buffer 4502 is used to buffer a high verification reference voltage (e.g., which represents the 32nd level (L31) of the 32 reference voltage levels (L0-L31) for a 5-bit cell) to drive resistor string 4504 at one end of resistor string 4504. In another example, buffer 4503 is provided to buffer a low verification reference voltage VREF2, which corresponds to the 1st level (L0) of the 32 levels (L0-L31) for a 5-bit cell, and provides the voltage to one end of resistor string 4504. For example, the high verification reference voltage may be 900mV and the low verification reference voltage may be 300mV. Voltage ladder (resistor string) 4504 generates N voltages ranging from V0 to VN, which represent N possible values ​​that can be stored in the VMM array. These reference voltages are then used by verification circuit 4403 in FIG. 44. In another example, the input voltage and / or output voltage of the buffers 4502 and 4503 are trimmed to adjust the range and calibrate any offsets, such as buffer offsets. Alternatively, the ITV 4501 can directly drive the resistor string 4504 to provide 32 reference levels (L0-L31).

[0248] In one example, K verification reference voltage lines may be used to provide N different voltages. For example, for a 5-bit cell, 32 verification reference voltage lines are required to feed the verification reference voltage selection circuit 4406, while for a 6-bit cell, 64 verification reference voltage lines are required. The 32 reference voltage lines may each be used twice to provide 64 verification reference voltages by time-division multiplexing their use, such that the 32 lines provide a first set of 32 voltages during a first verification period and a second set of 32 voltages during a second verification period. This method may be extended by providing 128 voltages for a 7-bit cell using four verification periods or providing 256 voltages or more for an 8-bit cell using eight verification periods, but is not limited thereto.

[0249] In one example, bias voltages (such as CG bias and EG bias) at the input of the array used to verify operation are generated from a reference array such that these biases adapt over temperature to make the array current as constant as possible.

[0250] Figures 46 to 50 Describes the Fig.43 An example of a reference array of reference array 4304 in FIG.

[0251] Fig.46 A physical array 4600 is depicted. The physical array 4600 includes an array of non-volatile memory cells. The non-volatile memory cells may optionally include stacked gate flash memory cells or split gate flash memory cells. The physical array 4600 is divided into two types of arrays, namely, the VMM array 3401 (e.g., Fig.34In one example, the VMM array 3401 and the reference array 4304 share the same bit lines. In another example, the VMM array 3401 and the reference array 4304 use separate sets of bit lines, where the two sets of bit lines are disconnected.

[0252] Fig.47 A physical array 4700 is depicted that is divided into two arrays, namely, the VMM array 3401 and the reference array 4304. In one example, the VMM array 3401 and the reference array 4304 share one or more sets of horizontal lines, such as word lines, control gate lines, and erase lines. In another example, the VMM array 3401 and the reference array 4304 do not share any sets of horizontal lines.

[0253] Fig.48 An example is depicted in which reference array 4304 and VMM array 3401 are located in separate physical arrays. For example, there may be a substrate separation or active diffusion separation between the two arrays. Physical array 4801 includes VMM array 3401, and physical array 4802 includes reference array 4304. VMM array 3401 and reference array 4304 do not share any bit lines, word lines, control gate lines, or erase lines.

[0254] Fig.49 An example of a reference array 4304 is depicted. Here, the reference array 4304 includes a plurality of reference sub-arrays, such as sub-reference arrays 4901-0, 4901-1, ..., 4901-(n-1), and 4901-n. Thus, the reference array 4304 includes n+1 different reference sub-arrays. Different reference sub-arrays may have different characteristics that cause the corresponding reference array to be characterized by a different IV curve than the other reference sub-arrays. For example, the size of the corresponding reference sub-array may vary in one or more of the following aspects: (1) the width of the control gate line of the transistor of the corresponding reference array; (2) the width of the word line of the transistor of the corresponding reference array; (3) the width of the floating gate of the transistor of the corresponding reference array; (4) the total width of the non-volatile memory cells in the corresponding reference array; (5) the shallow trench isolation (STI) spacing within the corresponding reference array; or (6) other characteristics. In addition, the reference sub-arrays may vary in one or more device implant conditions or doping characteristics (such as, but not limited to, well implant conditions, source implant conditions, and drain implant conditions).

[0255] Fig.50Another example of a reference array 4304 is depicted. Here, the reference array 4303 includes a plurality of reference subarrays, such as reference subarrays 5001-0, 5001-1, ..., 5001-(n-1), and 5001-n, and 5001-0, 5002-1, ..., 5002-(n-1), and 5002-n. Therefore, the reference array 4304 includes 2*(n+1) different reference subarrays, which means that Fig.49 Twice as much. Fig.50 In (such as Fig.49 Different reference sub-arrays in the array may have different characteristics that cause the corresponding reference sub-array to be characterized by an IV curve different from other reference arrays. For example, the size of the corresponding reference sub-array may vary in one or more of the following aspects: control gate width, word line width, floating gate width, total width of non-volatile memory cells in the array, STI spacing, and device implantation conditions, but are not limited thereto.

[0256] It should be noted that, as used herein, the terms "above" and "on" both inclusively include "directly on" (no intervening materials, elements, or spaces are provided in between) and "indirectly on" (intervening materials, elements, or spaces are provided in between). Similarly, the term "adjacent" includes "directly adjacent" (no intervening materials, elements, or spaces are provided in between) and "indirectly adjacent" (intervening materials, elements, or spaces are provided in between), "mounted to" includes "directly mounted to" (no intervening materials, elements, or spaces are provided in between) and "indirectly mounted to" (intervening materials, elements, or spaces are provided in between), and "electrically coupled to" includes "directly electrically coupled to" (no intervening materials or elements electrically connecting the elements together) and "indirectly electrically coupled to" (intervening materials or elements electrically connecting the elements together). For example, forming an element "above" a substrate may include directly forming the element on the substrate without intervening materials / elements in between, and indirectly forming the element on the substrate with one or more intervening materials / elements in between.

Claims

1. A system, comprising: a vector-matrix multiplication array comprising a plurality of non-volatile memory cells arranged in rows and columns, the non-volatile memory cells each capable of storing one of N possible levels corresponding to one of N possible currents; and A plurality of output blocks are configured to receive current from corresponding columns of the vector-matrix multiplication array and to generate voltages during a verify operation of the vector-matrix multiplication and to generate digital outputs during a read operation of the vector-matrix multiplication array. 2 . The system of claim 1 , wherein the plurality of output blocks convert current from columns of the array into voltage using a plurality of resistors or a plurality of capacitors.

3. The system according to claim 1, comprising: A reference voltage generator is used to generate one of the N voltages during the verification operation.

4. The system according to claim 3, comprising: A verification circuit is configured to compare a voltage from the reference voltage generator with a voltage from one of the plurality of output blocks.

5. The system of claim 4, wherein the verification circuit generates a digital output indicative of a result of the comparison.

6. The system of claim 3, wherein the reference voltage generator generates the one of the N voltages in response to a current received from a reference array.

7. The system of claim 3, wherein the reference voltage generator generates the one of the N voltages in response to a current received from a main reference current generator.

8. The system of claim 3, wherein the reference voltage generator comprises: a current-to-voltage converter, the current-to-voltage converter being configured to convert a maximum current among the N possible currents into a maximum voltage; and A resistor string is used to generate N voltages ranging from the maximum voltage to a minimum voltage.

9. The system of claim 8, wherein the resistor string comprises (N-1) resistors connected in series.

10. The system of claim 8, comprising a first buffer for providing the maximum voltage to a first end of the resistor string.

11. The system of claim 10, comprising a second buffer for providing the minimum voltage to a second end of the resistor string.

12. A system, comprising: a current-to-voltage converter for converting current from the vector-matrix array into a voltage; a successive approximation register analog-to-digital converter for receiving the voltage from the current-to-voltage converter and generating a digital output during a read operation; and A verification circuit is configured to receive the voltage from the current-to-voltage converter and compare the voltage to a reference voltage during a verification operation.

13. The system of claim 12, wherein the reference voltage is provided by a reference voltage generator, the reference voltage generator comprising: a current-to-voltage converter for converting a maximum current among the N possible currents into a maximum voltage; and A resistor string is used to generate N voltages ranging from the maximum voltage to a minimum voltage.

14. The system of claim 13, wherein the resistor string comprises (N-1) resistors connected in series.

15. The system of claim 13, comprising a first buffer for providing the maximum voltage to a first end of the resistor string.

16. The system of claim 15, comprising a second buffer for providing the minimum voltage to a second end of the resistor string.

17. A system, comprising: a vector-matrix multiplication array comprising a plurality of non-volatile memory cells arranged in rows and columns, the non-volatile memory cells each capable of storing one of N possible voltages corresponding to one of N possible currents; and A plurality of current-to-voltage converters and a plurality of verification circuits for receiving current from columns of the array and generating voltages during verification operations of the vector-matrix multiplication array and generating digital outputs during read operations of the vector-matrix multiplication array.

18. The system according to claim 17, comprising: A reference voltage generator is provided for generating one of N voltages during the verification operation of the vector-matrix multiplication array.

19. The system according to claim 18, comprising: A comparator is configured to compare a voltage from the reference voltage generator with a voltage from one of the plurality of current-to-voltage converters.

20. The system of claim 19, wherein the comparator performs offset calibration.

21. The system of claim 20, wherein the offset calibration is performed in the time domain.

22. The system of claim 17, wherein the current-to-voltage converter converts current from a column of the array into a voltage using a plurality of resistors or a plurality of capacitors.

23. A system, comprising: a vector-matrix multiplication array comprising a plurality of non-volatile memory cells arranged in rows and columns, the non-volatile memory cells each capable of storing one of N possible levels corresponding to one of N possible currents; and A plurality of output blocks are provided for receiving differential currents from columns of the vector-matrix multiplication array and generating voltages during a verify operation of the vector-matrix multiplication array.

24. The system of claim 23, further comprising: A verification circuit is used to generate an output.

25. The system according to claim 23, wherein the plurality of output blocks include corresponding current-voltage converters for converting the current of the columns of the array from the vector-matrix multiplication array into voltage using a plurality of resistors or a plurality of capacitors, respectively.

26. The system according to claim 25, wherein the plurality of output blocks include corresponding analog-to-digital converters for converting the voltage from the current-voltage converter into a digital output, and wherein the verification operation utilizes the digital output.

27. A method, the method comprising: receiving a differential current according to the formula w=(w+)-(w-), where (w+) is received from the first column of the vector-matrix multiplication array and (w-) is received from the second column of the vector-matrix multiplication array; and verifying the differential current with respect to a reference current.

28. A system, the system comprising: a vector-matrix multiplication array including a plurality of non-volatile memory cells arranged in rows and columns, the non-volatile memory cells each being capable of storing one of N possible levels corresponding to one of N possible currents; and a plurality of reference voltage generators for generating K reference voltages on K reference voltage lines, where K<N, and wherein the K reference voltage lines verify N possible currents in a time-division multiplexing manner.

29. The system according to claim 28, the system comprising: a plurality of current-voltage converters for receiving current from the columns of the array of the vector-matrix multiplication array and generating a voltage during a verification operation of the vector-matrix multiplication array.

30. The system according to claim 29, wherein the current-voltage converter uses a plurality of resistors or a plurality of capacitors to convert the current of the columns of the array from the vector-matrix multiplication array into voltage.

31. The system according to claim 28, the system comprising: a verification circuit for generating a comparison output.

32. The system according to claim 28, the system comprising: an analog-to-digital converter for generating a comparison output.

Images