Techniques for hybrid digital / analog processors for quantum computers

Abstract

Techniques for a hybrid digital / analog processor for a quantum computer are disclosed. In an illustrative embodiment, a hybrid digital / analog processor may be capable of processing digital instructions as well as analog instructions. The digital instruction may be, for example, read from or write to a memory or register, perform an arithmetic operation, perform a branch, etc. The analog instructions may be used, for example, to provide an analog voltage to a particular electrode of a qubit, to provide an analog pulse to a qubit, to measure reflection of an analog signal from a qubit, etc. Integration of analog operations in a hybrid digital / analog processor may improve performance by, for example, reducing latency and reducing power usage.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of and priority to U.S. Patent Application No. 17 / 954,131, filed on September 27, 2022, entitled “TECHNOLOGIES FOR HYBRID DIGITAL / ANALOG PROCESSORS FOR A QUANTUM COMPUTER.” The disclosure of the foregoing application is considered part of the disclosure of the present application and is incorporated herein by reference in its entirety. Background Art

[0003] Quantum computers demonstrate computing capabilities that are unattainable with classical computing. One of the many challenges in quantum computing is high-speed, low-latency communication with a large number of qubits. Methods such as finite state machines can manage relatively small numbers of qubits, but are not feasible for large numbers of qubits. The circuitry used to manage qubits should be close to the qubits to reduce latency. However, the circuitry is close to the qubits in, for example, a dilution refrigerator. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1A-1F Various views of an example quantum dot device are shown according to one embodiment.

[0005] Figure 2 is a simplified block diagram of at least one embodiment of a quantum computing device.

[0006] Figure 3 yes Figure 2 A simplified block diagram of at least one embodiment of a portion of a quantum computing device.

[0007] Figure 4 is a simplified block diagram of at least one embodiment of a hybrid digital / analog processor for the quantum computing device of FIG. 1 .

[0008] Figure 5 is a simplified block diagram of at least one embodiment of a multi-core hybrid digital / analog processor for the quantum computing device of FIG. 1 .

[0009] Figure 6 It has multiple hybrid digital / analog processors Figure 2 A simplified block diagram of at least one embodiment of a portion of a quantum computing device.

[0010] Figure 7 It can be done by Figure 2 A simplified block diagram of at least one embodiment of an environment for establishing a quantum computing device.

[0011] Figure 8 is used in Figure 4 A simplified flow chart of at least one embodiment of a method of executing a program on a hybrid digital / analog processor.

[0012] Fig. 9 is used by Figure 2 A simplified flow chart of at least one embodiment of a method of executing a program on a quantum computing device.

[0013] Fig.10 is a top view of a wafer and die according to any of the embodiments disclosed herein.

[0014] Fig.11 is a cross-sectional side view of an integrated circuit according to any of the embodiments disclosed herein.

[0015] Figures 12A-12D is a perspective view of example planar, gate-all-around, and stacked gate-all-around transistors.

[0016] Fig.13 is a cross-sectional side view of an integrated circuit device assembly according to any of the embodiments disclosed herein.

[0017] Fig.14 is a block diagram of an example electrical device according to any of the embodiments disclosed herein. DETAILED DESCRIPTION

[0018] Aspects of the present disclosure include a quantum computing device with a hybrid digital / analog processor. In an illustrative embodiment, the hybrid digital / analog processor is located in a dilution refrigerator near the quantum bits of the quantum computing device. In use, a processor in the quantum computing device sends instructions to the hybrid digital / analog processor. The processor can send digital instructions as well as analog instructions. Digital instructions can include, for example, reading memory and writing memory, arithmetic operations, conditional branches, reading and writing registers, etc. Analog instructions can include instructions for generating or reading analog pulses, which are sent to and received from quantum bits. Compared with using a digital processor with a separate analog signal processing circuit, a hybrid digital / analog processor can be able to coordinate operations on quantum bits with lower latency, lower power, and better synchronization.

[0019] In the following description, specific details are set forth, but embodiments of the technology described herein may be practiced without these specific details. Well-known circuits, structures, and techniques are not shown in detail to avoid obscuring the understanding of this specification. Phrases such as "embodiment", "various embodiments", "some embodiments", etc. may include features, structures, or characteristics, but not every embodiment must include the particular feature, structure, or characteristic.

[0020] In the following description, for the purpose of explanation, many specific details are set forth in order to provide a thorough understanding thereof. However, it is apparent that novel embodiments can be practiced without these specific details. In other examples, well-known structures and devices are shown in block diagram form to facilitate their description. It is intended to cover all modifications, equivalents, and alternatives within the scope of the claims.

[0021] Some embodiments may have some, all, or none of the features described for other embodiments. "First", "second", "third", etc. describe common objects and indicate different instances of the same object being referenced. Such adjectives do not mean that the object described in this way must be in a given sequence in time, space, order, or in any other way. "Connection" can indicate that an element is in direct physical or electrical contact, and "coupling" can indicate that an element cooperates or interacts, but these elements may or may not be in direct physical or electrical contact. In addition, the terms "including", "comprising", "having", etc. used in embodiments of the present disclosure are synonymous. The terms modified by the word "substantially" include arrangements, orientations, spacings, or positions that are slightly different from the meaning of the unmodified term. For example, substrate assembly features (e.g., through width) described as having substantially listed dimensions can vary within a few percent of the listed dimensions.

[0022] As used herein, the phrase "communicatively coupled" refers to the ability of a component to send or receive signals to or from another component. The signal can be any type of signal, for example, an input signal, an output signal, or a power signal. A component can send or receive signals to or from another component to which it is communicatively coupled via a wired or wireless communication medium (e.g., conductive traces, conductive contacts, air). Examples of communicatively coupled components include integrated circuit dies in the same package that communicate via an embedded bridge in a package substrate and an integrated circuit component attached to a printed circuit board, wherein the integrated circuit component sends or receives signals to or from other integrated circuit components or electronic devices attached to the printed circuit board.

[0023] It should be understood that in the examples further shown and described below, the drawings may not be drawn to scale and may not include all possible layers and / or circuit components. In addition, it should be understood that although certain drawings show transistor designs including source / drain regions, electrodes, etc. with orthogonal (e.g., vertical) boundaries, the embodiments herein may implement such boundaries in a substantially orthogonal manner (e.g., within + / - 5 degrees or + / - 10 degrees of orthogonality) due to manufacturing methods used to manufacture such devices or for other reasons.

[0024] As used herein, in the context of a first layer or component being located on a second layer or component, the phrase "located on..." refers to the first layer or component being physically attached to the second layer or component directly (with no layers or components between the first layer or component and the second layer or component) or being physically attached to the second layer or component using one or more intermediate layers or components.

[0025] As used herein, the term "adjacent" refers to layers or components that are in physical contact with each other. That is, there are no layers or components between the adjacent layers or components. For example, layer X adjacent to layer Y refers to a layer that is in physical contact with layer Y.

[0026] As used herein, the terms "upper" / "lower" or "above" / "below" may refer to the relative position of an object (e.g., a surface described above), particularly in view of the relative positions of the examples shown in the accompanying drawings, rather than the absolute position of the object. For example, an upper surface of a device may be on a side of the device opposite the lower surface of an object, and the upper surface may generally face upward only when viewed in a particular manner. As another example, a first object above a second object may be on or near the "upper" surface of the second object, rather than near the "lower" surface of the objects, and the first object may actually be above the second object only when the two objects are viewed in a particular manner.

[0027] Reference is made to the accompanying drawings, which are not necessarily drawn to scale, in which similar or identical numerals may be used to represent the same or similar parts in different drawings. The use of similar or identical numerals in different drawings does not mean that all drawings including similar or identical numerals constitute a single or identical embodiment. The same reference numerals with different letter suffixes may represent different instances of similar components. The drawings generally illustrate various embodiments discussed in this document by way of example and not limitation.

[0028] Quantum computers use quantum mechanical phenomena (e.g., superposition and entanglement) to perform calculations, simulations, or other functions. In contrast to digital computers that store data in one of two definite states (0 or 1), quantum computing uses quantum bits (qubits), which can be in a superposition of states. Quantum bits can be implemented using physically distinguishable quantum states of elementary particles (e.g., electrons and photons). For example, the polarization of photons can be used, where the two states are vertical polarization and horizontal polarization. Similarly, the spin of an electron may have distinguishable states such as "up spin" and "down spin." A quantum bit in a quantum mechanical system can be in a superposition of two states at the same time, which is a unique and fundamental feature of quantum computing.

[0029] The algorithms executed by quantum computing systems contain quantum logic operations performed on qubits. In some cases, the results of the algorithms are not deterministic. Quantum algorithms can be repeated many times in order to determine the statistical distribution of the results or to have a high probability of finding the correct answer. In some cases, classical algorithms can be used to check whether the quantum computer has determined the correct result.

[0030] A variety of different technologies have been used to implement qubits, which can manipulate and read quantum states. These include, but are not limited to (spin-based and space-based) quantum dot devices, trapped-ion devices, superconducting quantum computers, optical lattices, nuclear magnetic resonance computers, solid-state NMR Kane quantum devices, electron quantum computers on helium, cavity quantum electrodynamics (CQED) devices, molecular magnet computers, and fullerene-based ESR quantum computers, to name a few. Therefore, although quantum dot devices are described below in conjunction with specific embodiments of the present invention, the basic principles of the present invention can be used in conjunction with any type of quantum computer (including but not limited to those listed above). The embodiments of the present invention described herein do not necessarily require a specific physical implementation for qubits.

[0031] Quantum dots are small semiconductor particles, typically a few nanometers in size. Due to their small size, quantum dots operate according to the rules of quantum mechanics and thus have optical and electronic properties that differ from those of macroscopic entities. Quantum dots are sometimes referred to as "artificial atoms", which refers to the fact that quantum dots are single objects with discrete, bound electronic states, just as is the case with atoms or molecules.

[0032] Figure 1A-1F are various views of a quantum dot device 100 that may be used with the embodiments of the present invention described below. Figure 1A is a top view of a portion of a quantum dot device 100 with some material removed such that first gate line 102, second gate line 104, and third gate line 106 are visible. Although many of the figures and descriptions herein may refer to a particular set of wire-OR gates as "barrier" or "quantum dot" wire-OR gates, respectively, this is for ease of discussion only, and in other embodiments, the roles of "barrier" and "quantum dot" wires and gates may be swapped (e.g., barrier gates may alternatively be used as quantum dot gates, and vice versa). Figure 1B-Figure 1F yes Figure 1A A side cross-sectional view of a quantum dot device 100; in particular, Figure 1B is through Figure 1A A view of section BB, Figure 1C is through Figure 1A A view of section CC, Figure 1D is through Figure 1A A view of the cross section DD, Figure 1E is through Figure 1A A view of a cross section EE, and Figure 1F is through Figure 1A A cross-sectional view of FF.

[0033] The quantum dot device 100 of FIG1 can be operated in any of a variety of ways. For example, in some embodiments, an electrical signal such as a voltage, current, radio frequency (RF), and / or microwave signal can be provided to one or more of the first gate line 102, the second gate line 104, and / or the third gate line 106 to form a quantum dot (e.g., a quantum dot based on electron spin or a quantum dot based on hole spin) in a quantum well stack 146 under a third gate 166 of the third gate line 106. The electrical signal provided to the third gate line 106 can control the potential of the quantum well under the third gate 166 of the third gate line 106, and the electrical signal provided to the first gate line 102 (and / or the second gate line 104) can control the potential energy barrier between adjacent quantum wells under the first gate 162 of the first gate line 102 (and / or the second gate 164 of the second gate line 104). Quantum interactions between quantum dots in different quantum wells in the quantum well stack 146 (eg, under different quantum dot gates) can be controlled in part by the potential energy barrier provided by the barrier potential applied between these quantum dots (eg, through an intervening barrier gate).

[0034] Typically, the quantum dot device 100 disclosed herein may also include a magnetic field source (not shown) that can be used to create an energy difference in the state of a typically degenerate quantum dot (e.g., a spin state of a quantum dot based on electron spin), and the state of the quantum dot (e.g., spin state) can be manipulated by applying electromagnetic energy to a gate line to generate a quantum bit capable of computation. The magnetic field source can be one or more magnetic lines of force. Thus, the quantum dot device 100 disclosed herein can manipulate the position, quantity, and quantum state (e.g., spin) of the quantum dots in the quantum well stack 146 by controlled application of electromagnetic energy.

[0035] In the quantum dot device 100 of FIG. 1 , a gate dielectric 114 may be disposed on a quantum well stack 146. The quantum well stack 146 may include at least one quantum well layer (not shown in FIG. 1 ) in which quantum dots may be localized during operation of the quantum dot device 100. The gate dielectric 114 may be any suitable material, for example, a high-k material. A plurality of parallel first gate lines 102 may be disposed on the gate dielectric 114, and a spacer material 118 may be disposed on the sides of the first gate lines 102. In some embodiments, a patterned hard mask 110 may be disposed on the first gate lines 102 (wherein the pattern corresponds to the pattern of the first gate lines 102), and the spacer material 118 may extend upward along the sides of the hard mask 110, as shown. Each of the first gate lines 102 may be a first gate 162. Different ones of the first gate lines 102 may be electrically controlled in any desired combination (eg, each first gate line 102 may be electrically controlled individually, or some or all of the first gate lines 102 may be shorted together in one or more groups, as desired).

[0036] A plurality of parallel second gate lines 104 may be disposed above and between the first gate lines 102. As shown in FIG1 , the second gate lines 104 may be arranged perpendicular to the first gate lines 102. The second gate lines 104 may extend above the hard mask 110 and may include a second gate 164 extending downward toward the quantum well stack 146 and contacting the gate dielectric 114 between adjacent first gate lines 102 in the first gate lines 102, as shown in FIG1 . Figure 1DAs shown. In some embodiments, the second gate 164 may fill the area between adjacent first gate lines 102 / spacer material 118 structures in the first gate line 102 / spacer material 118 structure; in other embodiments, an insulating material (not shown) may be present between the first gate line 102 / spacer material 118 structure and the adjacent second gate 164. In some embodiments, the spacer material 118 may be disposed on the side of the second gate line 104; in other embodiments, the spacer material 118 may not be disposed on the side of the second gate line 104. In some embodiments, the hard mask 115 may be disposed above the second gate line 104. Multiple second gates 164 in the second gates 164 of the second gate lines 104 are electrically continuous (due to the shared conductive material of the second gate lines 104 above the hard mask 110). Different second gate lines 104 in the second gate lines 104 may be electrically controlled in any desired combination (for example, each second gate line 104 may be electrically controlled individually, or some or all of the second gate lines 104 may be shorted together in one or more groups as desired). The first gate lines 102 and the second gate lines 104 may together form a grid, as depicted in FIG. 1 .

[0037] A plurality of parallel third gate lines 106 may be disposed above and between the first gate lines 102 and the second gate lines 104. As shown in FIG. 1 , the third gate lines 106 may be arranged diagonally with the first gate lines 102 and diagonally with the second gate lines 104. In particular, the third gate lines 106 may be arranged diagonally above openings in a grid formed by the first gate lines 102 and the second gate lines 104. The third gate lines 106 may include a third gate 166 extending downwardly to the gate dielectric 114 in the openings in the grid formed by the first gate lines 102 and the second gate lines 104; thus, each third gate 166 may be bounded by two different first gate lines 102 and two different second gate lines 104. In some embodiments, the third gates 166 may be defined by the insulating material 128; in other embodiments, the third gates 166 may fill the openings in the grid (e.g., contacting the spacer material 118 disposed on the sides of the adjacent first gate lines 102 and second gate lines 104, not shown). Additional insulating material 117 may be disposed on and / or around the third gate lines 106. Multiple third gates 166 in the third gates 166 of the third gate lines 106 are electrically continuous (due to the shared conductive material of the third gate lines 106 above the first gate lines 102 and the second gate lines 104). Different ones of the third gate lines 106 may be electrically controlled in any desired combination (e.g., each third gate line 106 may be electrically controlled individually, or some or all of the third gate lines 106 may be shorted together in one or more groups as desired).

[0038] Although Figure 1A-1F A specific number of first gate lines 102, second gate lines 104, and third gate lines 106 are shown, but this is for illustration purposes only, and any number of first gate lines 102, second gate lines 104, and third gate lines 106 may be included in the quantum dot device 100. Other examples of arrangements of the first gate lines 102, second gate lines 104, and third gate lines 106 are possible. Electrical interconnects (e.g., vias and conductive lines) may contact the first gate lines 102, second gate lines 104, and third gate lines 106 in any desired manner.

[0039] Not shown in FIG. 1 is an accumulation region that can be electrically coupled to a quantum well layer (e.g., laterally proximate to a quantum well layer) of the quantum well stack 146. The accumulation region can be separated from the gate line by a thin layer of intervening dielectric material. The accumulation region can be a region where carriers accumulate (e.g., due to doping, or due to the presence of a large electrode that pulls carriers into the quantum well layer) and can be used as a reservoir for carriers that can be selectively pulled into a region of the quantum well layer below the third gate 166 (e.g., by controlling the voltage on the quantum dot gate, the first gate 162, and the second gate 164) to form a carrier-based quantum dot (e.g., an electron or hole quantum dot that includes a single charge carrier, multiple charge carriers, or no charge carriers). In other embodiments, the quantum dot device 100 may not include a lateral accumulation region, but may include doped layers within the quantum well stack 146. These doped layers can provide carriers for the quantum well layer. In any of the embodiments of the quantum dot device 100 disclosed herein, any combination of accumulation regions (eg, doped or undoped) or doped layers in the quantum well stack 146 may be used.

[0040] Reference now Figure 2 , showing a simplified block diagram of a quantum computing device 200. In some embodiments, the quantum computing device 200 may include the Figure 1A-1F The quantum dot device 100 described. The quantum computing device 200 may be embodied as or included in any type of computing device. For example, the quantum computing device 200 may include or otherwise be included in, but is not limited to, a server computer, an embedded computing system, a system on a chip (SoC), a multiprocessor system, a processor-based system, a consumer electronic device, a desktop computer, a laptop computer, a network device, a networked computer, a distributed computing system, and / or any other computing device. The illustrative quantum computing device 200 includes a processor 202, a memory 204, an input / output (I / O) subsystem 206, a quantum / classical interface circuit system 208, and a quantum processor 210. In some embodiments, one or more of the illustrative components of the quantum computing device 200 may be incorporated into another component or otherwise form a part of another component. For example, in some embodiments, the memory 204 or a portion thereof may be incorporated into the processor 202. In some embodiments, the quantum computing device 200 may be embodied as described below with respect to Fig.14 The electrical device 1400 is described, or may include any suitable components of the electrical device 1400.

[0041] In some embodiments, the quantum computing device 200 may be located in a data center with other computing devices, such as an enterprise data center (e.g., a data center owned and operated by a company and typically located on the company's premises), a hosting service data center (e.g., a data center managed by a third party on behalf of a company), a co-location data center (e.g., a data center in which the data center infrastructure is provided by a data center host, and the company provides and manages its own data center components (servers, etc.)), a cloud data center (e.g., a data center operated by a cloud service provider that hosts company applications and data), and an edge data center (e.g., a data center that typically has a smaller footprint than other data center types and is located near the geographic area it serves), a micro data center, etc. In some embodiments, the quantum computing device 200 may receive work over a network (e.g., the Internet) to be executed on the quantum processor 210. The quantum computing device 200 may perform the work on the quantum processor 210 and send the results back to the requesting device.

[0042] Processor 202 may be embodied as any type of processor capable of performing the functions described herein. For example, processor 202 may be embodied as a single-core or multi-core processor, a single-socket or multi-socket processor, a digital signal processor, a graphics processor, a neural network computing engine, an image processor, a microcontroller, or other processor or processing / control circuit. Processor 202 may include multiple processor cores. In some embodiments, processor 202 supports quantum extensions to the existing ISA of processor / core 202, thereby allowing instructions to interact with quantum / classical interface circuit system 208 and quantum processor 210.

[0043] Memory 204 may be embodied as any type of volatile or non-volatile memory or data storage device capable of performing the functions described herein. In operation, memory 204 may store various data and software used during operation of quantum computing device 200, such as operating systems, applications, programs, libraries, and drivers. Memory 204 is communicatively coupled to processor 202 via I / O subsystem 206, which may be embodied as a circuit system and / or component for facilitating input / output operations with processor 202, memory 204, and other components of quantum computing device 200. For example, I / O subsystem 206 may be embodied as or otherwise include a memory controller hub, an input / output control hub, a firmware device, a communication link (e.g., a point-to-point link, a bus link, a wire, a cable, an optical guide, a printed circuit board trace, etc.), and / or other components and subsystems for facilitating input / output operations. I / O subsystem 206 may use any suitable connector, interconnect, bus, protocol, etc. (e.g., SoC structure, USB2, USB3, USB4, The I / O subsystem 206 may be a processor 202, a memory 204, a memory 205, a memory 206, a memory 207, a memory 208, a memory 209, a memory 210, a memory 211, a memory 212, a memory 213, a memory 214, a memory 215, a memory 216, a memory 217, a memory 218, a memory 219, a memory 220, a memory 221, a memory 222, a memory 224, a memory 225, a memory 226, a memory 227, a memory 228, a memory 229, a memory 230, a memory 231, a memory 232, a memory 233, a memory 234, a memory 235, a memory 236, a memory 237, a memory 23

[0044] The quantum / classical interface circuit system 208 is configured to interface with both the classical components (e.g., the processor 202 and the memory 204) of the quantum computing device 200 and the quantum processor 210. The quantum / classical interface circuit system 208 may include various analog or digital circuit systems, such as analog-to-digital converters, digital-to-analog converters, high-gain amplifiers, low-noise amplifiers, cryogenic amplifiers, field programmable gate arrays (FPGAs), classical processors, application-specific integrated circuits (ASICs), signal conditioning circuit systems, etc. In some embodiments, some or all of the quantum / classical interface circuit system 208 may be inside a refrigerator (e.g., a dilution refrigerator, a magnetic refrigerator, a helium-4 and / or helium-3 refrigerator, etc.). Some or all of the components of the quantum / classical interface circuit system 208 may be at any suitable temperature, such as 10 millikelvin, 100 millikelvin, 4 kelvin, 20 kelvin, 77 kelvin, room temperature or higher, or any temperature therebetween.

[0045] The quantum processor 210 is configured to operate on one or more qubits. The qubits may be any suitable type of qubit, for example, Figure 1A-1F In other embodiments, the qubits may be, for example, charge qubits, transmon qubits, microwave qubits, superconducting qubits, or any other suitable type of qubit. Quantum processor 210 may include any suitable number of physical or logical qubits, for example, 1-10 6 In the illustrative embodiment, some or all of quantum processor 210 are in a refrigerator such as a dilution refrigerator. In particular, in the illustrative embodiment, the qubits are maintained at a temperature of about 10 millikelvin. In other embodiments, the qubits may be maintained at any suitable temperature, for example, 1-100 millikelvin or higher, depending on the temperature sensitivity of the particular qubits used.

[0046] Quantum processor 210 may be able to control various qubits in various ways, for example, by performing two-qubit gates, three-qubit gates, error correction operations, converting states from one type of qubit to another type of qubit, measuring some, any, or all of the qubits, initializing some, any, or all of the qubits, and the like.

[0047] The quantum computing device 200 may include Figure 2 Additional components not shown, such as one or more data storage devices, a network interface controller, one or more peripheral devices, etc.

[0048] Reference now Figure 3 In one embodiment, some or all of the quantum processor 210 and the quantum / classical interface circuit system 208 may be in a cryogenic refrigerator 300. The quantum / classical interface circuit system 208 includes a hybrid digital / analog processor 302 that may be interfaced with a companion chip 308. The hybrid digital / analog processor 302 may also be referred to as an auxiliary processor, a slave processor, or simply a processor. The hybrid digital / analog processor 302 may be connected to the companion chip 308 via one or more wires 310. The wires 310 may be embodied as one or more cables, buses, twisted pairs, etc.

[0049] In an illustrative embodiment, the hybrid digital / analog processor 302 can be in a first stage 316 of a cryogenic refrigerator 300, and the companion chip 308 and the quantum processor 210 can be in a second stage 318 of the cryogenic refrigerator 300. In an illustrative embodiment, the first stage 316 is maintained at a temperature of about 4 Kelvin, and the second stage 318 is maintained at a temperature of about 20 milliKelvin. In other embodiments, the first stage 316 can be maintained at, for example, 1-77 Kelvin, and the second stage 318 can be maintained at, for example, 10-100 milliKelvin. In some embodiments, Figure 3 The various components can be in Figure 3 The stages shown are different stages, and / or the cryocooler 300 may include additional stages, for example, one or more stages at a higher or lower temperature than the first stage 316 and / or the second stage 318. The cryocooler 300 may be any suitable refrigerator with active or passive cooling, for example, a dilution refrigerator, a magnetic refrigerator, a helium-4 and / or helium-3 refrigerator, etc.

[0050] In use, and as follows about Figure 4-Figure 6As described in more detail, hybrid digital / analog processor 302 receives instructions from another component of quantum computing device 200 (e.g., from processor 202 or memory 204). Instructions can be digital instructions, such as reading from or writing to memory, reading from or writing to registers, conditional branches, etc. Instructions can also be analog instructions, such as instructions for generating or receiving analog pulses, setting analog voltages for qubits, setting digital voltages for multiplexers that select qubits, etc. Hybrid digital / analog processor 302 can send digital signals and / or analog signals to and receive digital signals and / or analog signals from companion chip 308. Signals for multiple qubits can be sent from hybrid digital / analog processor 302 to companion chip 308 on wire 310, and companion chip 308 can demultiplex signals from hybrid digital / analog processor 302, for example, by using frequency multiplexing, time multiplexing, etc. Therefore, hybrid digital / analog processor 302 can send analog signals to and receive analog signals from a relatively large number of qubits through a relatively small number of wires 310. For example, the hybrid digital / analog processor 302 may control 2-100 qubits for each wire 310 that carries analog signals to and from the hybrid digital / analog processor 302. Additionally or alternatively, in some embodiments, the hybrid digital / analog processor 302 may send and receive analog and / or digital signals directly to and from the quantum processor 210, without necessarily going through the companion chip 308.

[0051] Reference now Figure 4 In one embodiment, the hybrid digital / analog processor 302 includes a processor core 402, a memory 404, an input / output (I / O) 406, an interconnect 408, and a debug access port (DAP) 410. The processor core 402 includes an instruction management circuit system 412, a digital execution circuit system 414, and an analog execution circuit system 416. In an illustrative embodiment, the hybrid digital / analog processor 302 is based on a von Neumann architecture. In an illustrative embodiment, the hybrid digital / analog processor 302 is embodied as an integrated circuit package having one or more semiconductor dies, one or more circuit boards having interconnect layers, etc. The hybrid digital / analog processor 302 may be embodied as a system on a chip. The hybrid digital / analog processor 302 may employ an architecture having any suitable number of bits, for example, a 32-bit architecture or a 64-bit architecture. The instruction set of the hybrid digital / analog processor 302 includes both digital instructions and analog instructions, and may be an extension or modification of an existing instruction set (e.g., x86), or may be a different instruction set.

[0052] Memory 404 may be embodied as any suitable type or amount of memory, such as, for example, one or more levels of SRAM cache. I / O 406 allows digital input to and digital output from hybrid digital / analog processor 302. Interconnect 408 allows communication between various components of hybrid digital / analog processor 302. DAP 410 allows debugging of operations on hybrid digital / analog processor 302.

[0053] Instruction management circuit system 412 includes acquisition / streaming module 418, decoding module 422 and dispatch module 424. Acquisition / streaming module 418 acquires or streams the next instruction or instruction set. Acquisition / streaming module 418 can receive instructions from on-processor memory 404 or from another component of quantum computing device 200 (e.g., processor 202 or memory 204). Decoding module 422 is configured to decode the instruction and determine what the instruction is, and specifically, determine whether the instruction should be executed by digital execution circuit system 414 or analog execution circuit system 416. Dispatch module 424 sends the instruction to digital execution circuit system 414 or analog execution circuit system 416 as appropriate.

[0054] Digital execution circuit system 414 is used to execute digital instructions. Digital instructions can be, for example, reading from or writing to memory (e.g., memory 404 or memory 204), reading from or writing to registers (e.g., registers in core 402), conditional branches, etc. Digital instructions can be arithmetic operations that can be performed by arithmetic logic unit (ALU) 426. For instructions that transfer data to one or more memories, address generation unit (AGU) 428 can be used to calculate addresses for accessing main memory 204. In some cases, digital instructions can be used to write parameters to registers, which are used to generate analog pulses as part of executing analog instructions.

[0055] The analog execution circuit system 416 is used to execute the analog instructions. The analog execution circuit system includes one or more signal processing blocks (SPBs) 430. SPB 430 may also be referred to as a digital signal processor (DSP) 430. In an illustrative embodiment, each SPB 430 may use wires 310 to send signals to or receive signals from the supporting chip 308 and the quantum processor. The signal sent to the supporting chip 308 may be, for example, an analog pulse for performing an operation on a qubit, an analog voltage for controlling the DC voltage applied to the qubit, a digital voltage for selecting a qubit by multiplexing, etc. The signal received from the supporting chip 308 may be, for example, a reflection of a signal sent to the qubit indicating the state of the qubit. In some embodiments, each SPB 430 may send or receive signals for several (e.g., 2-1002) qubits. SPB 430 may use multiplexing (e.g., frequency multiplexing and / or time multiplexing) to send or receive signals for more than one qubit on a single wire 310 or a group of wires 310. The analog instructions can be used, for example, to generate or measure analog pulses. In some embodiments, the instructions can cause the SPB 430 to first generate analog pulses that are sent to the quantum bits on the quantum processor, and then measure the reflected or returned signals. In some embodiments, the parameters of the pulses can be loaded into registers using digital instructions before executing the analog instructions. For example, in one embodiment, the digital instructions can load the values ​​of the frequency of the pulse, the amplitude of the pulse, the phase of the pulse, the envelope of the pulse, etc. into the registers. The analog instructions can then instruct the SPB 430 to generate pulses based on the parameters stored in the registers. In an illustrative embodiment, the SPB 430 can directly access the analog input channels and analog output channels of the hybrid digital / analog processor 302.

[0056] SPB 430 can generate voltage or pulses with any suitable wavelength, bandwidth, envelope (e.g., square wave or Gaussian), amplitude, etc. SPB 430 can generate square voltage pulses with a duration of, for example, 1 nanosecond to 100 microseconds. SPB 430 can generate microwave pulses with a duration of, for example, 1-100 nanoseconds. Microwave pulses can be modulated at a carrier frequency of, for example, 11-20 gigahertz, with a bandwidth of, for example, 1-100 megahertz. To measure the state of a qubit, SPB 430 can generate one or more pulses with a center frequency of 50-1000 MHz and a bandwidth of 2-20 MHz. The SPB 430 or a different SPB that generates the pulses can measure the reflection of such a signal from the qubit and infer the state of the qubit based on the reflection.

[0057] It should be appreciated that the timing of analog signals is critical. Therefore, in some embodiments, some or all of the hybrid digital / analog processors 302 may operate in a timing-aware mode or real-time mode, ensuring that signals sent to the quantum processor 210 are sent at the appropriate time.

[0058] In an illustrative embodiment, analog execution circuitry 416 may not operate at the same clock rate as other components of processor core 402 (e.g., digital execution circuitry 414). For example, analog execution circuitry 416 may operate in a different clock domain and / or may operate at a different clock rate. In some embodiments, portions of analog execution circuitry 416 may be powered off to reduce power usage.

[0059] In an illustrative embodiment, the processor core 402 of the hybrid digital / analog processor 302 may be able to control several qubits, for example, 2-1000 qubits. To this end, the processor core 402 may include several SPBs 430, for example, 2-10. SPBs 430 may perform operations on qubits at a relatively low rate, for example, one operation per qubit per 20 nanoseconds. However, if the processor core 402 controls, for example, 100 qubits, the processor core 402 consumes one operation per 0.2 nanoseconds or at a rate of 5 gigahertz. In order to provide enough instructions to the processor core 402, the front end of the hybrid digital / analog processor may be relatively wide. For example, the hybrid digital / analog processor may receive, for example, 5-20 instructions per clock cycle.

[0060] It should be appreciated that the integration of SPB 430 into processor core 402 can provide several advantages. Since SPB 430 is integrated into the same die or package as other components of processor core 402, the delay between digital execution circuit system 414 and analog execution circuit system 416 is reduced. For example, data handover from digital and analog backends can occur within a few clock cycles, or in less than one nanosecond. Additionally, digital execution circuit system 414 and analog execution circuit system 416 can share memory 404 and registers, thereby further reducing the delay required for copying data and reducing the power used in memory storage. Any digital circuit system required to manage SPB 430 can be integrated with other digital circuit systems in processor core 402, thereby reducing components in SPB 430. Since the front end for both digital instructions and analog instructions is the same, the compiler can optimize the program at compile time to run more efficiently on the hybrid digital / analog processor 302. Feedback (eg, conditional readout, error correction readout, etc.) from the quantum processor 210 may be used to feed forward to further operations on the quantum processor 210 with low latency, thereby improving the performance of algorithms executed on the quantum processor 210 .

[0061] It should be appreciated that the description of the hybrid digital / analog processor 302 is simplified and that the hybrid digital / analog processor 302 may include additional components or circuitry commonly found in processors. For example, the hybrid digital / analog processor 302 may include a memory management unit (MMU), may use techniques such as pipelining, may execute instructions out of order, etc.

[0062] Reference now Figure 5 In some embodiments, a single processor core 402 may have difficulty performing all of the desired functions of a hybrid digital / analog processor 302. For example, a hybrid digital / analog processor 302 may manage a large number of qubits (e.g., 100-1000 qubits), and a single processor core 402 may not be able to add more SPBs 430 without suffering a performance penalty. In such embodiments, a hybrid digital / analog processor 302 may include more than one processor core 402, such as Figure 5 The hybrid digital / analog processor 302 may include any suitable number of processor cores 402 , for example, 1-20. The multi-core hybrid digital / analog processor 302 may include a core synchronization matrix 502 to synchronize timing between the various processor cores 402 and, in particular, between the various SPBs 430 .

[0063] Reference now Figure 6In some embodiments, a single hybrid digital / analog processor 302 may have difficulty controlling the desired number of qubits of a quantum processor 210, even for a hybrid digital / analog processor 302 having multiple cores 402. For example, a hybrid digital / analog processor 302 may manage a large number of qubits (e.g., 1,000-10,000 qubits), and a single hybrid digital / analog processor 302 may not be able to add more processor cores 402 without suffering performance losses or lower yields. In such embodiments, the quantum / classical interface circuit system 208 may include more than one hybrid digital / analog processor 302, such as Figure 6 As shown. The quantum / classical interface circuit system 208 can include any suitable number of hybrid digital / analog processors 302, for example, 1-20. The core synchronization matrix 502 in each hybrid digital / analog processor 302 can synchronize between the hybrid digital / analog processors and between the processor cores 402. In the illustrative embodiment, each hybrid digital / analog processor 302 has a corresponding companion chip 308, and various companion chips 308 are connected to different qubits on the same quantum processor 210.

[0064] Reference now Figure 7In an illustrative embodiment, the quantum computing device 200 establishes an environment 700 during operation. The illustrative environment 700 includes a compiler 702, an instruction scheduler 704, and a synchronizer 706. The various modules of the environment 700 may be embodied as hardware, software, firmware, or a combination thereof. For example, the various modules, logic, and other components of the environment 700 may form part of or otherwise be established by the processor 202, memory 204, data storage device, or other hardware component of the quantum computing device 200. Therefore, in some embodiments, one or more of the modules of the environment 700 may be embodied as a collection of circuit systems or electrical devices (e.g., compiler circuit system 702, instruction scheduler circuit system 704, synchronizer circuit system 706, etc.). It should be appreciated that in such an embodiment, one or more of the circuits (e.g., compiler circuit system 702, instruction scheduler circuit system 704, synchronizer circuit system 706, etc.) may form part of one or more of the processor 202, memory 204, data storage device, and / or other components of the quantum computing device 200. For example, in some embodiments, some or all of the modules may be embodied as a processor 202, a memory 204, and / or a data storage device storing instructions to be executed by the processor 202. Additionally, in some embodiments, one or more of the illustrative modules may form part of another module and / or one or more of the illustrative modules may be independent of each other. Furthermore, in some embodiments, one or more of the modules of the environment 700 may be embodied as a virtualized hardware component or simulation architecture, which may be established and maintained by the processor 202 or other components of the quantum computing device 200. It should be appreciated that some of the functions of one or more of the modules of the environment 700 may require hardware implementation, in which case embodiments of the modules implementing such functions will be at least partially embodied as hardware.

[0065] Compiler 702 (which may be embodied as hardware, firmware, software, virtualized hardware, emulation architecture, and / or combinations thereof as discussed above) is configured to compile programs to be executed by processor 202, hybrid digital / analog processor 302, and quantum processor 210. In an illustrative embodiment, compiler 702 may optimize compiled code based on the capabilities of hybrid digital / analog processor 302. The optimization may reduce or eliminate idle time of hybrid digital / analog processor 302, core 402, SPB 430, etc.

[0066] The instruction scheduler 704 (which may be embodied as hardware, firmware, software, virtualized hardware, simulation architecture, and / or combinations thereof as discussed above) is configured to schedule instructions on one or more hybrid digital / analog processors 302. The instructions may be digital instructions or analog instructions. The instructions may be used, for example, to initialize some or all of the qubits in the quantum processor 210, perform one or more operations on the qubits, and read values ​​from one or more of the qubits. The instruction scheduler 704 may coordinate the scheduling of operations on different SPBs 430, on different cores 402, and on different hybrid digital / analog processors 302. The instruction scheduler 704 may have various options for channel assignment within a given hybrid digital / analog processor 302 and across various hybrid digital / analog processors 302.

[0067] The instruction scheduler 704 is configured to receive feedback data from the hybrid digital / analog processor 302, for example, readout data from the qubits of the quantum processor 210. Since computing power and cooling capabilities may be limited on the hybrid digital / analog processor 302, a portion of the algorithm for controlling the qubits of the quantum processor 210 may be executed on the processor 202, especially when latency is not critical. The instruction scheduler 704 may determine what operation should be performed on the quantum processor 210 based on the measurement of the qubits, and the instruction scheduler 704 may send instructions and / or data to the hybrid digital / analog processor 302 based on the measurement of the qubits.

[0068] The synchronizer 706 may manage synchronization between the various cores 402 , the SPB 430 , etc. of the one or more hybrid digital / analog processors 302 . The synchronizer 706 may communicate with the various core synchronization matrices 502 of the hybrid digital / analog processors 302 .

[0069] Reference now Figure 8 , in one embodiment, a flow chart of a method 800 for executing instructions of a hybrid digital / analog processor 302 is shown. The method 800 begins at block 802, where the hybrid digital / analog processor 302 receives instructions. The hybrid digital / analog processor 302 may receive instructions from, for example, the processor 202, the memory 204, the memory 404, etc.

[0070] In block 804, hybrid digital / analog processor 302 determines whether the instruction is a digital instruction or an analog instruction. Hybrid digital / analog processor 302 may check the decoded microcode in the instruction to determine whether the instruction is a digital instruction or an analog instruction. For example, instructions with a specific microcode may be assigned to digital execution circuit system 414, and instructions with a specific microcode may be assigned to analog execution circuit system 416.

[0071] In block 806, if the instruction is a digital instruction, the method 800 proceeds to block 808, where the instruction is passed to the digital execution circuitry 414, and the digital execution circuitry 414 executes the instruction. The instruction may be, for example, a read or write memory operation, a read or write register operation, an arithmetic operation, a conditional branch, etc. The method 800 then jumps to block 816, where the hybrid digital / analog processor 302 is synchronized between cores 402, and in some embodiments, the hybrid digital / analog processor 302 is synchronized with other hybrid digital / analog processors 302. The method 800 then loops back to block 802 to receive another instruction.

[0072] Referring back to block 806, if the instruction is not a digital instruction, the method 800 jumps to block 810, where the instruction is passed to the analog execution circuit system 416, and the analog execution circuit system 416 executes the instruction. In block 812, the analog execution circuit system 416 can generate an analog signal, for example, a radio frequency pulse. The analog execution circuit system 416 can use the values ​​stored in the registers (e.g., registers indicating amplitude, frequency, envelope, etc.) to generate the analog signal. In block 814, the analog execution circuit system 416 can measure the analog signal, for example, the reflection of the RF signal sent to the qubit. In some embodiments, generating the analog signal and measuring the reflection can be performed as a single instruction. Then, the method 800 proceeds to block 816 to synchronize with other cores 402 and / or synchronize with other hybrid digital / analog processors 302.

[0073] It should be appreciated that the method 800 illustrates a simplified flow of the hybrid digital / analog processor 302 and that in some embodiments, the flow of the hybrid digital / analog processor 302 may include additional steps, may execute steps out of order, etc. For example, in some embodiments, the hybrid digital / analog processor 302 may use pipelining and / or may execute certain instructions out of order.

[0074] Reference now Fig. 9, in one embodiment, a flow chart of a method 900 for executing a program on a quantum processor 210 is shown. The method 900 may be performed by components of the quantum computing device 200 (e.g., the processor 202, the memory 204, the compiler 702, the instruction scheduler 704, the synchronizer 706, etc.). The method 900 begins at block 902, in which the quantum computing device 200 compiles a program to be executed by the processor 202, the hybrid digital / analog processor 302, and the quantum processor 210. In an illustrative embodiment, the compiler may optimize the compiled code based on the capabilities of the hybrid digital / analog processor 302. The optimization may reduce or eliminate idle time of the hybrid digital / analog processor 302, the core 402, the SPB 430, etc.

[0075] In block 906, processor 202 sends one or more instructions to one or more hybrid digital / analog processors 302. The instructions may be digital instructions or analog instructions. The instructions may be used, for example, to initialize some or all of the qubits in quantum processor 210, perform one or more operations on the qubits, and read values ​​from one or more of the qubits. Processor 202 may coordinate the scheduling of operations on different SPBs 430, on different cores 402, and on different hybrid digital / analog processors 302. Processor 202 may have various options for channel assignment within a given hybrid digital / analog processor 302 and across various hybrid digital / analog processors 302.

[0076] In block 908, if the processor 202 has not received data (e.g., measurement data of one or more qubits) from the hybrid digital / analog processor 302, the method 900 loops back to block 908 to continue waiting for a result from the hybrid digital / analog processor 302. If the processor 202 does receive data from the hybrid digital / analog processor 302, the method 900 proceeds to block 910.

[0077] In block 910, the processor 202 determines what instructions to send to the hybrid digital / analog processor 302. Because computing power and cooling capabilities may be limited on the hybrid digital / analog processor 302, a portion of the algorithm for controlling the qubits of the quantum processor 210 may be executed on the processor 202, especially where latency is not critical. The processor 202 may determine what operations should be performed on the quantum processor 210 based on the measurements of the qubits, and the processor 202 may send instructions and / or data to the hybrid digital / analog processor 302 based on the measurements of the qubits. In block 912, the processor 202 sends the instructions and / or data to the hybrid digital / analog processor 302.

[0078] In block 914, the processor 202 may manage synchronization between the various cores 402 of the one or more hybrid digital / analog processors 302. The method 900 then loops back to block 908 to wait for more data to be received from the hybrid digital / analog processor 302.

[0079] Fig.10 1 is a top view of a wafer 1000 and die 1002 that may be included in any of the processors disclosed herein (e.g., any suitable die as a die of processor 202, hybrid digital / analog processor 302, or quantum processor 210). Wafer 1000 may be comprised of semiconductor material and may include one or more die 1002 having integrated circuit structures formed on a surface of wafer 1000. Individual die 1002 may be repeating units of an integrated circuit product including any suitable integrated circuit. After fabrication of the semiconductor product is complete, wafer 1000 may undergo a singulation process in which die 1002 are separated from one another to provide individual “chips” of an integrated circuit product. Die 1002 may be any of the dies of a processor disclosed herein (e.g., processor 202, hybrid digital / analog processor 302, or quantum processor 210). Die 1002 may include one or more transistors (e.g., transistors discussed below). Fig.11 Some of the transistors 1140 of the present invention), supporting circuit systems for routing electrical signals to the transistors, passive components (e.g., signal traces, resistors, capacitors, or inductors), and / or any other integrated circuit components. In some embodiments, wafer 1000 or die 1002 may include memory devices (e.g., random access memory (RAM) devices, such as static RAM (SRAM) devices, magnetic RAM (MRAM) devices, resistive RAM (RRAM) devices, conductive bridge RAM (CBRAM) devices, etc.), logic devices (e.g., AND gates, OR gates, NAND gates, or NOR gates), or any other suitable circuit elements. Multiple of these devices may be combined on a single die 1002. For example, a memory array formed by multiple memory devices may be formed on a die that is connected to a processor unit (e.g., Fig.14 The processor unit 1402) or other logic on the same die 1002, wherein the other logic is configured to store information in a memory device or execute instructions stored in a memory array. Various processors (e.g., processor 202, hybrid digital / analog processor 302, or quantum processor 210) in the processors disclosed herein can be manufactured using die-to-wafer assembly technology, in which some dies are attached to a wafer 1000 including other dies, and the wafer 1000 is subsequently singulated.

[0080] Fig.111 is a cross-sectional side view of an integrated circuit device 1100 that may be included in any of the processors disclosed herein (e.g., processor 202, hybrid digital / analog processor 302, or quantum processor 210). One or more of the integrated circuit devices 1100 may be included in one or more dies 1002 ( Fig.10 ). The integrated circuit device 1100 may be formed on a die substrate 1102 (eg, Fig.10 1000) and may be included in a die (e.g., Fig.10 The die substrate 1102 may be a semiconductor substrate composed of a semiconductor material system including, for example, an n-type or p-type material system (or a combination of the two). The die substrate 1102 may include, for example, a crystalline substrate formed using bulk silicon or a silicon-on-insulator (SOI) substructure. In some embodiments, the die substrate 1102 may be formed using an alternative material that may or may not be combined with silicon, including but not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Other materials classified as Group II-VI, Group III-V, or Group IV may also be used to form the die substrate 1102. Although several examples of materials that may form the die substrate 1102 are described herein, any material that may serve as the basis for the integrated circuit device 1100 may be used. The die substrate 1102 may be a singulated die (e.g., Fig.10 of a die 1002) or a wafer (e.g., Fig.10 portion of wafer 1000).

[0081] The integrated circuit device 1100 may include one or more device layers 1104 disposed on a die substrate 1102. The device layer 1104 may include features of one or more transistors 1140 (e.g., metal oxide semiconductor field effect transistors (MOSFETs)) formed on the die substrate 1102. The transistor 1140 may include, for example, one or more source and / or drain (S / D) regions 1120, a gate 1122 for controlling current flow between the S / D regions 1120, and one or more S / D contacts 1124 for routing electrical signals to / from the S / D regions 1120. The transistor 1140 may include additional features not depicted for clarity, such as device isolation regions, gate contacts, etc. The transistor 1140 is not limited to Fig.11 The types and configurations depicted in the drawings and may include various other types and configurations, such as planar transistors, non-planar transistors, or a combination of both. Non-planar transistors may include FinFET transistors, such as dual-gate transistors or tri-gate transistors, and wrap-around or all-around gate transistors, such as nanoribbon transistors, nanosheet transistors, or nanowire transistors.

[0082] Figures 12A-12D is a simplified perspective view of example planar, FinFET, gate-all-around, and stacked gate-all-around transistors. Figures 12A-12D The transistor is shown formed on a substrate 1216 having a surface 1208. Isolation regions 1214 separate the source and drain regions of the transistor from other transistors and from a body region 1218 of the substrate 1216.

[0083] Fig. 12A is a perspective view of an example planar transistor 1200 including a gate 1202 that controls current flow between a source region 1204 and a drain region 1206. The transistor 1200 is planar because the source region 1204 and the drain region 1206 are planar relative to a substrate surface 1208.

[0084] Fig. 12B is a perspective view of an example FinFET transistor 1220 including a gate 1222 that controls current flow between a source region 1224 and a drain region 1226. Transistor 1220 is non-planar because source region 1224 and drain region 1226 include a "fin" that extends upward from substrate surface 1228. Because gate 1222 surrounds three sides of the semiconductor fin extending from source region 1224 to drain region 1226, transistor 1220 can be considered a tri-gate transistor. Fig. 12B One S / D fin is shown extending through the gate 1222 , but multiple S / D fins may extend through the gate of the FinFET transistor.

[0085] Fig. 12C is a perspective view of a gate-all-around (GAA) transistor 1240 including a gate 1242 that controls current flow between a source region 1244 and a drain region 1246. The transistor 1240 is non-planar because the source region 1244 and the drain region 1246 are elevated from the substrate surface 1228.

[0086] Fig.12D 12 is a perspective view of a GAA transistor 1260 including a gate 1262 that controls current flow between multiple elevated source regions 1264 and multiple elevated drain regions 1266. Transistor 1260 is a stacked GAA transistor because the gate controls current flow between multiple elevated S / D regions stacked on top of each other. Transistor 1240 and transistor 1260 are considered to be all-around gate transistors because the gate surrounds all sides of the semiconductor portion extending from the source region to the drain region. Depending on the width of the semiconductor portion extending through the gate (e.g., width 1248 for transistor 1240 and width 1268 for transistor 1260, respectively), transistor 1240 and transistor 1260 may alternatively be referred to as nanowire transistors, nanosheet transistors, or nanoribbon transistors.

[0087] Back to Fig.11 , transistor 1140 may include a gate 1122 formed of at least two layers (gate dielectric and gate electrode). The gate dielectric may include one layer or a stack of layers. One or more layers may include silicon oxide, silicon dioxide, silicon carbide and / or high-k dielectric material.

[0088] High-k dielectric materials may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in gate dielectrics include, but are not limited to, hafnium oxide, hafnium oxide of silicon, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium oxide of silicon, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, titanium strontium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, when high-k materials are used, an annealing process may be performed on the gate dielectric to improve the quality of the gate dielectric.

[0089] The gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor 1140 is a p-type metal oxide semiconductor (PMOS) transistor or an n-type metal oxide semiconductor (NMOS) transistor. In some implementations, the gate electrode may be composed of a stack of two or more metal layers, one or more of which are work function metal layers and at least one of which is a fill metal layer. Other metal layers may be included for other purposes, such as barrier layers.

[0090] For PMOS transistors, metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to NMOS transistors (e.g., for work function adjustment). For NMOS transistors, metals that can be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to PMOS transistors (e.g., for work function adjustment).

[0091] In some embodiments, when observing the cross section of the transistor 1140 along the source-channel-drain direction, the gate electrode may be composed of a U-shaped structure including a bottom portion substantially parallel to the surface of the die substrate 1102 and two sidewall portions substantially perpendicular to the top surface of the die substrate 1102. In other embodiments, at least one of the metal layers forming the gate electrode may be only a planar layer substantially parallel to the top surface of the die substrate 1102 and does not include a sidewall portion substantially perpendicular to the top surface of the die substrate 1102. In other embodiments, the gate electrode may be composed of a combination of a U-shaped structure and a planar non-U-shaped structure. For example, the gate electrode may be composed of one or more U-shaped metal layers formed on top of one or more planar non-U-shaped layers.

[0092] In some embodiments, a pair of sidewall spacers may be formed on opposite sides of the gate stack to support the gate stack. The sidewall spacers may be formed of materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and typically include deposition and etching process steps. In some embodiments, multiple pairs of spacers may be used; for example, two, three, or four pairs of sidewall spacers may be formed on opposite sides of the gate stack.

[0093] The S / D region 1120 may be formed within the die substrate 1102 adjacent to the gate 1122 of each transistor 1140. For example, the S / D region 1120 may be formed using an implantation / diffusion process or an etching / deposition process. In the implantation / diffusion process, dopants such as boron, aluminum, antimony, phosphorus, or arsenic may be ion-implanted into the die substrate 1102 to form the S / D region 1120. An annealing process to activate the dopant and further diffuse the dopant into the die substrate 1102 may be performed after the ion implantation process. In the etching / deposition process, the die substrate 1102 may first be etched to form a groove at the location of the S / D region 1120. An epitaxial deposition process may then be performed to fill the groove with a material for fabricating the S / D region 1120. In some implementations, the S / D region 1120 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be in-situ doped with a dopant such as boron, arsenic, or phosphorus. In some embodiments, one or more alternative semiconductor materials such as germanium or III-V materials or alloys may be used to form S / D region 1120. In further embodiments, S / D region 1120 may be formed using one or more layers of metals and / or metal alloys.

[0094] Electrical signals such as power and / or input / output (I / O) signals may be provided through one or more interconnect layers (in the Fig.111100) to and / or from devices (e.g., transistors 1140) of device layer 1104. For example, conductive features (e.g., gates 1122 and S / D contacts 1124) of device layer 1104 can be electrically coupled to interconnect structures 1128 of interconnect layers 1106-1110. One or more interconnect layers 1106-1110 can form a metallization stack (also referred to as an "ILD stack") 1119 of integrated circuit device 1100.

[0095] Interconnect structures 1128 may be arranged within interconnect layers 1106-1110 to route electrical signals according to various designs; in particular, the arrangement is not limited to Fig.11 The specific configuration of the interconnect structure 1128 is depicted in FIG. Fig.11 A particular number of interconnect layers 1106 - 1110 are depicted in FIG. 1 , but embodiments of the present disclosure include integrated circuit devices having more or fewer interconnect layers than depicted.

[0096] In some embodiments, the interconnect structure 1128 may include wires 1128a and / or vias 1128b filled with a conductive material such as a metal. The wires 1128a may be arranged to route electrical signals in the direction of a plane substantially parallel to the surface of the die substrate 1102 on which the device layer 1104 is formed. For example, the wires 1128a may route electrical signals in the direction of entering and exiting a page and / or in the direction of crossing a page. The vias 1128b may be arranged to route electrical signals in the direction of a plane substantially perpendicular to the surface of the die substrate 1102 on which the device layer 1104 is formed. In some embodiments, the vias 1128b may electrically couple the wires 1128a of different interconnect layers 1106-1110 together.

[0097] The interconnect layers 1106-1110 may include a dielectric material 1126 disposed between interconnect structures 1128, such as Fig.11 As shown. In some embodiments, the dielectric material 1126 disposed between the interconnect structures 1128 in different interconnect layers in the interconnect layers 1106-1110 can have different compositions; in other embodiments, the composition of the dielectric material 1126 between different interconnect layers 1106-1110 can be the same. The device layer 1104 can also include a dielectric material 1126 disposed between the transistor 1140 and the bottom layer of the metallization stack. The dielectric material 1126 included in the device layer 1104 can have a different composition than the dielectric material 1126 included in the interconnect layers 1106-1110; in other embodiments, the composition of the dielectric material 1126 in the device layer 1104 can be the same as the dielectric material 1126 included in any of the interconnect layers 1106-1110.

[0098] A first interconnect layer 1106 (referred to as metal 1 or "M1") can be formed directly on the device layer 1104. In some embodiments, the first interconnect layer 1106 can include lines 1128a and / or vias 1128b, as shown. The lines 1128a of the first interconnect layer 1106 can be coupled to contacts (e.g., S / D contacts 1124) of the device layer 1104. The vias 1128b of the first interconnect layer 1106 can be coupled to the lines 1128a of the second interconnect layer 1108.

[0099] A second interconnect layer 1108 (referred to as metal 2 or "M2") may be formed directly on the first interconnect layer 1106. In some embodiments, the second interconnect layer 1108 may include vias 1128b to couple the wires 1128 of the second interconnect layer 1108 with the wires 1128a of the third interconnect layer 1110. Although the wires 1128a and vias 1128b are structurally depicted with wires within respective interconnect layers for clarity, in some embodiments, the wires 1128a and vias 1128b may be structurally and / or materially continuous (e.g., filled simultaneously during a dual damascene process).

[0100] A third interconnect layer 1110 (referred to as Metal 3 or "M3") (and additional interconnect layers as needed) may be formed successively on the second interconnect layer 1108 according to similar techniques and configurations as described in connection with the second interconnect layer 1108 or the first interconnect layer 1106. In some embodiments, interconnect layers that are "higher" (i.e., farther from the device layer 1104) in the metallization stack 1119 in the integrated circuit device 1100 may be thicker than interconnect layers lower in the metallization stack 1119, wherein the lines 1128a and vias 1128b in the higher interconnect layers are thicker than the lines and vias in the lower interconnect layers.

[0101] The integrated circuit device 1100 may include a solder resist material 1134 (eg, polyimide or similar material) formed on the interconnect layers 1106-1110 and one or more conductive contacts 1136. Fig.11 , the conductive contact 1136 is shown as taking the form of a bonding pad. The conductive contact 1136 can be electrically coupled to the interconnect structure 1128 and configured to route the electrical signal of the transistor 1140 to an external device. For example, a solder bond can be formed on one or more of the conductive contacts 1136 to mechanically and / or electrically couple the integrated circuit die including the integrated circuit device 1100 to another component (e.g., a printed circuit board). The integrated circuit device 1100 may include additional or alternative structures to route electrical signals from the interconnect layers 1106-1110; for example, the conductive contacts 1136 may include other similar features (e.g., posts) that route electrical signals to external components.

[0102] In some embodiments where the integrated circuit device 1100 is a double-sided die, the integrated circuit device 1100 may include another metallization stack (not shown) on the opposite side of the device layer 1104. The metallization stack may include a plurality of interconnect layers as discussed above with reference to the interconnect layers 1106-1110 to provide conductive paths (e.g., including conductive lines and vias) between the device layer 1104 and additional conductive contacts (not shown) on the side of the integrated circuit device 1100 opposite the conductive contacts 1136.

[0103] In other embodiments where the integrated circuit device 1100 is a double-sided die, the integrated circuit device 1100 may include one or more through silicon vias (TSVs) through the die substrate 1102; these TSVs may contact the device layer 1104 and may provide a conductive path between the device layer 1104 and additional conductive contacts (not shown) on the side of the integrated circuit device 1100 opposite the conductive contacts 1136. In some embodiments, the TSVs extending through the substrate may be used to route power and ground signals from the conductive contacts on the side of the integrated circuit device 1100 opposite the conductive contacts 1136 to the transistor 1140 and any other components integrated into the die 1100, and the metallization stack 1119 may be used to route I / O signals from the conductive contacts 1136 to the transistor 1140 and any other components integrated into the die 1100.

[0104] Multiple integrated circuit devices 1100 can be stacked with one or more TSVs in each stacked device, thereby providing a connection between one device in the device and any of the other devices in the stack. For example, one or more high bandwidth memory (HBM) integrated circuit dies can be stacked on top of a substrate integrated circuit die, and the TSVs in the HBM die can provide a connection between each HBM and the substrate integrated circuit die. The conductive contact portion can provide additional connections between adjacent integrated circuit dies in the stack. In some embodiments, the conductive contact portion can be a fine pitch solder bump (microbump).

[0105] Fig.131 is a cross-sectional side view of an integrated circuit device assembly 1300 that may include any of the processors disclosed herein (e.g., processor 202, hybrid digital / analog processor 302, or quantum processor 210). In some embodiments, integrated circuit device assembly 1300 may be processor 202, hybrid digital / analog processor 302, or quantum processor 210. Integrated circuit device assembly 1300 includes a plurality of components disposed on a circuit board 1302 (which may be a motherboard, system board, mainboard, etc.). Integrated circuit device assembly 1300 includes components disposed on a first side 1340 of circuit board 1302 and an opposing second side 1342 of circuit board 1302; generally, components may be disposed on one or both of sides 1340 and 1342. Any of the integrated circuit components discussed below with reference to integrated circuit device assembly 1300 may take the form of any suitable embodiment in an embodiment of a processor disclosed herein (e.g., processor 202, hybrid digital / analog processor 302, or quantum processor 210).

[0106] In some embodiments, circuit board 1302 may be a printed circuit board (PCB) that includes multiple metal (or interconnect) layers separated from each other by dielectric material layers and interconnected by conductive vias. Each metal layer includes conductive traces. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals between components coupled to circuit board 1302 (optionally in combination with other metal layers). In other embodiments, circuit board 1302 may be a non-PCB substrate. Fig.13 The illustrated integrated circuit device assembly 1300 includes a package-on-interposer structure 1336 coupled to a first side 1340 of a circuit board 1302 via a coupling component 1316. The coupling component 1316 can electrically and mechanically couple the package-on-interposer structure 1336 to the circuit board 1302 and can include solder balls (e.g., Fig.13 as shown), pins (e.g., as part of a pin grid array (PGA)), contacts (e.g., as part of a land grid array (LGA)), male and female portions of a socket, an adhesive, a bottom fill material, and / or any other suitable electrical and / or mechanical coupling structures.

[0107] The package-on-interposer structure 1336 may include an integrated circuit component 1320 coupled to the interposer 1304 via a coupling component 1318. The coupling component 1318 may take any suitable form for the application, such as the forms discussed above with reference to the coupling component 1316. Fig.13A single integrated circuit component 1320 is shown in FIG. 1 , but multiple integrated circuit components may be coupled to interposer 1304 ; indeed, additional interposers may be coupled to interposer 1304 . Interposer 1304 may provide an intermediate substrate for bridging circuit board 1302 and integrated circuit component 1320 .

[0108] Integrated circuit assembly 1320 may be a device including one or more integrated circuit dies (eg, Fig.10 The tube core 1002, Fig.11 The integrated circuit device 1100 of the present invention is a packaged or unpackaged integrated circuit product of an integrated circuit device 1100) and / or one or more other suitable components. The packaged integrated circuit component includes one or more integrated circuit dies mounted on a packaging substrate, wherein the integrated circuit die and the packaging substrate are encapsulated in a housing material such as metal, plastic, glass, or ceramic. In one example of an unpackaged integrated circuit component 1320, a single monolithic integrated circuit die includes solder bumps attached to contacts on the die. The solder bumps allow the die to be directly attached to the interposer 1304. The integrated circuit component 1320 may include one or more computing system components, such as one or more processor units (e.g., system on chip (SoC), processor core, graphics processor unit (GPU), accelerator, chipset processor), I / O controller, memory, or network interface controller. In some embodiments, the integrated circuit component 1320 may include one or more additional active or passive devices, such as capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices.

[0109] In embodiments where the integrated circuit assembly 1320 includes multiple integrated circuit dies, the dies of the integrated circuit assembly 1320 may be of the same type (a homogeneous multi-die integrated circuit assembly) or of two or more different types (a heterogeneous multi-die integrated circuit assembly). A multi-die integrated circuit assembly may be referred to as a multi-chip package (MCP) or a multi-chip module (MCM).

[0110] In addition to including one or more processor units, the integrated circuit assembly 1320 may also include additional components, such as embedded DRAM, stacked high bandwidth memory (HBM), shared cache memory, input / output (I / O) controller, or memory controller. Any of these additional components may be located on the same integrated circuit die as the processor unit, or on one or more integrated circuit dies separate from the integrated circuit die that includes the processor unit. These separate integrated circuit dies may be referred to as "chiplets." In embodiments in which the integrated circuit assembly includes multiple integrated circuit dies, the interconnections between the dies may be provided by a packaging substrate, one or more silicon interposers, one or more silicon bridges embedded in the packaging substrate (e.g., It is provided by an embedded multi-die interconnect bridge (EMIB)) or a combination thereof.

[0111] Typically, interposer 1304 can extend connections to a wider pitch, or reroute connections to different connections. For example, interposer 1304 can couple integrated circuit component 1320 to a set of ball grid array (BGA) conductive contacts of coupling component 1316 to couple to circuit board 1302. Fig.13 In the illustrated embodiment, integrated circuit component 1320 and circuit board 1302 are attached to opposite sides of interposer 1304; in other embodiments, integrated circuit component 1320 and circuit board 1302 may be attached to the same side of interposer 1304. In some embodiments, three or more components may be interconnected through interposer 1304.

[0112] In some embodiments, the interposer 1304 may be formed as a PCB, including multiple metal layers separated from each other by dielectric material layers and interconnected by conductive vias. In some embodiments, the interposer 1304 may be formed of epoxy, glass fiber reinforced epoxy, epoxy with inorganic fillers, ceramic materials, or polymer materials such as polyimide. In some embodiments, the interposer 1304 may be formed of alternative rigid or flexible materials, which may include the same materials used in semiconductor substrates described above, for example, silicon, germanium, and other III-V and IV materials. The interposer 1304 may include metal interconnects 1308 and vias 1310, including but not limited to through-vias 1310-1 (extending from the first side 1350 of the interposer 1304 to the second side 1354 of the interposer 1304), blind vias 1310-2 (extending from the first side 1350 or the second side 1354 of the interposer 1304 to the internal metal layers), and buried vias 1310-3 (connecting the internal metal layers).

[0113] In some embodiments, interposer 1304 may include a silicon interposer. Through silicon vias (TSVs) extending through the silicon interposer may connect connections on a first side of the silicon interposer to an opposite second side of the silicon interposer. In some embodiments, interposer 1304 including a silicon interposer may also include one or more routing layers to route connections on a first side of interposer 1304 to an opposite second side of interposer 1304.

[0114] The interposer 1304 may also include embedded devices 1314, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices may also be formed on the interposer 1304, such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and micro-electromechanical systems (MEMS) devices. The package structure 1336 on the interposer may take the form of any of the package structures on the interposer known in the art. In an embodiment where the interposer is a non-printed circuit board.

[0115] Integrated circuit device assembly 1300 may include integrated circuit component 1324 coupled to first side 1340 of circuit board 1302 via coupling component 1322. Coupling component 1322 may take the form of any of the embodiments discussed above with reference to coupling component 1316, and integrated circuit component 1324 may take the form of any of the embodiments discussed above with reference to integrated circuit component 1320.

[0116] Fig.13 The illustrated integrated circuit device assembly 1300 includes a package-on-package structure 1334 coupled to a second side 1342 of a circuit board 1302 via a coupling component 1328. The package-on-package structure 1334 may include an integrated circuit component 1326 and an integrated circuit component 1332 coupled together via a coupling component 1330 such that the integrated circuit component 1326 is disposed between the circuit board 1302 and the integrated circuit component 1332. The coupling component 1328 and the coupling component 1330 may take the form of any of the embodiments of the coupling component 1316 discussed above, and the integrated circuit component 1326 and the integrated circuit component 1332 may take the form of any of the embodiments of the integrated circuit component 1320 discussed above. The package-on-package structure 1334 may be configured according to any of the package-on-package structures known in the art.

[0117] Fig.141 is a block diagram of an example electrical device 1400 that may include one or more of the processors disclosed herein (e.g., processor 202, hybrid digital / analog processor 302, or quantum processor 210). For example, any suitable component of the components of the electrical device 1400 may include one or more of the integrated circuit device assembly 1300, integrated circuit assembly 1320, integrated circuit device 1100, or integrated circuit die 1002 disclosed herein, and may be arranged in any of the processors disclosed herein (e.g., processor 202, hybrid digital / analog processor 302, or quantum processor 210). Multiple components in Fig.14 1400, but any one or more of these components may be omitted or duplicated as appropriate for the application. In some embodiments, some or all of the components included in the electrical device 1400 may be attached to one or more motherboards, mainboards, or system boards. In some embodiments, one or more of these components are manufactured onto a single system-on-chip (SoC) die.

[0118] Additionally, in various embodiments, the electrical device 1400 may not include Fig.14 1400 may include one or more of the components shown, but the electrical device 1400 may include interface circuitry for coupling to one or more of the components. For example, the electrical device 1400 may not include the display device 1406, but may include display device interface circuitry (e.g., connector and driver circuitry) to which the display device 1406 may be coupled. In another set of examples, the electrical device 1400 may not include the audio input device 1424 or the audio output device 1408, but may include audio input device interface circuitry or audio output device interface circuitry (e.g., connector and support circuitry) to which the audio input device 1424 or the audio output device 1408 may be coupled.

[0119] The electrical device 1400 may include one or more processor units 1402 (e.g., one or more processor units). As used herein, the term "processor unit," "processing unit," or "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory to convert the electronic data into other electronic data that can be stored in registers and / or memory. The processor unit 1402 may include one or more digital signal processors (DSPs), application specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), general purpose GPUs (GPGPUs), accelerated processing units (APUs), field programmable gate arrays (FPGAs), neural network processing units (NPUs), data processor units (DPUs), accelerators (e.g., graphics accelerators, compression accelerators, artificial intelligence accelerators), controller cryptographic processors (specialized processors that execute cryptographic algorithms in hardware), server processors, controllers, or any other suitable type of processor unit. Therefore, a processor unit may be referred to as an XPU (or xPU).

[0120] The electrical device 1400 may include a memory 1404, which may itself include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM), static random access memory (SRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory, chalcogenide-based phase change non-voltage memory), solid-state memory, and / or a hard disk drive. In some embodiments, the memory 1404 may include memory located on the same integrated circuit die as the processor unit 1402. The memory may be used as a cache memory (e.g., level 1 (L1), level 2 (L2), level 3 (L3), level 4 (L4), last level cache (LLC)), and may include embedded dynamic random access memory (eDRAM) or spin-transfer torque magnetic random access memory (STT-MRAM).

[0121] In some embodiments, the electrical device 1400 may include one or more processor units 1402 that are heterogeneous or asymmetric with another processor unit 1402 in the electrical device 1400. There may be various differences between the processing units 1402 in the system in terms of a range of quality metrics including architectural, microarchitectural, thermal, power consumption characteristics, etc. These differences may effectively manifest themselves as asymmetry and heterogeneity between the processor units 1402 in the electrical device 1400.

[0122] In some embodiments, the electrical device 1400 may include a communication component 1412 (e.g., one or more communication components). For example, the communication component 1412 may manage wireless communications to transmit data to and from the electrical device 1400. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., which may transmit data through a non-solid medium using modulated electromagnetic radiation. The term "wireless" does not imply that the associated devices do not contain any wires, although in some embodiments the devices may not contain wires.

[0123] The communication component 1412 can implement any of a plurality of wireless standards or protocols, including but not limited to Institute of Electrical and Electronics Engineers (IEEE) standards, including Wi-Fi (IEEE 802.11 series), IEEE 802.16 standards (e.g., IEEE 802.16-2005 amendments), Long Term Evolution (LTE) projects, and any amendments, updates, and / or revisions (e.g., Advanced LTE projects, Ultra Mobile Broadband (UMB) projects (also known as "3GPP2"), etc.). IEEE 802.16-compatible broadband wireless access (BWA) networks are commonly referred to as WiMAX (the abbreviation stands for Worldwide Interoperability for Microwave Access) networks, which is a certification mark for products that pass IEEE 802.16 standard conformance and interoperability testing. The communication component 1412 can operate according to a Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication component 1412 can operate according to Enhanced Data GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication component 1412 can operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution Data Optimized (EV-DO) and its derivatives, and any other wireless protocol designated as 3G, 4G, 5G and higher. In other embodiments, the communication component 1412 can operate according to other wireless protocols. The electrical device 1400 may include an antenna 1422 for facilitating wireless communications and / or receiving other wireless communications (e.g., AM or FM radio transmissions).

[0124] In some embodiments, the communication component 1412 can manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., IEEE 802.3 Ethernet standard). As described above, the communication component 1412 can include multiple communication components. For example, the first communication component 1412 can be dedicated to shorter-range wireless communications (e.g., Wi-Fi or Bluetooth), and the second communication component 1412 can be dedicated to longer-range wireless communications (e.g., Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or other). In some embodiments, the first communication component 1412 can be dedicated to wireless communications, and the second communication component 1412 can be dedicated to wired communications.

[0125] The electrical device 1400 may include a battery / power circuitry 1414. The battery / power circuitry 1414 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuitry for coupling components of the electrical device 1400 to an energy source separate from the electrical device 1400 (e.g., AC line power).

[0126] The electrical device 1400 may include a display device 1406 (or corresponding interface circuitry, as described above). The display device 1406 may include one or more embedded or wired or wirelessly connected external visual indicators, such as a head-up display, a computer monitor, a projector, a touch screen display, a liquid crystal display (LCD), a light emitting diode display, or a flat panel display.

[0127] Electrical device 1400 may include audio output device 1408 (or corresponding interface circuitry, as described above). Audio output device 1408 may include any embedded or wired or wirelessly connected external device that generates an audible indicator, such as a speaker, a headset, or earphones.

[0128] The electrical device 1400 may include an audio input device 1418 (or corresponding interface circuitry, as described above). The audio input device 1418 may include any embedded or wired or wirelessly connected external device that generates a signal representing sound, such as a microphone, a microphone array, or a digital musical instrument (e.g., a musical instrument with a musical instrument digital interface (MIDI) output). The electrical device 1400 may include a global navigation satellite system (GNSS) device 1418 (or corresponding interface circuitry, as described above), such as a global positioning system (GPS) device. The GNSS device 1418 may communicate with a satellite-based system and may determine the geographic location of the electrical device 1400 based on information received from one or more GNSS satellites, as is known in the art.

[0129] Electrical device 1400 may include other output devices 1410 (or corresponding interface circuitry, as described above). Examples of other output devices 1410 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

[0130] The electrical device 1400 may include another input device 1120 (or corresponding interface circuitry, as described above). Examples of other input devices 1420 may include an accelerometer, a gyroscope, a compass, an image capture device (e.g., a monoscopic or stereo camera), a trackball, a trackpad, a touchpad, a keyboard, a cursor control device (e.g., a mouse), a stylus, a touch screen, a proximity sensor, a microphone, a barcode reader, a quick response (QR) code reader, an electrocardiogram (ECG) sensor, a PPG (photoplethysmogram) sensor, a galvanic skin response sensor, any other sensor, or a radio frequency identification (RFID) reader.

[0131] The electrical device 1400 may have any desired form factor, such as a handheld or mobile electrical device (e.g., a cellular phone, a smart phone, a mobile Internet device, a music player, a tablet computer, a laptop computer, a two-in-one convertible computer, a portable all-in-one computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra-mobile personal computer, a portable game console, etc.), a desktop electrical device, a server, a rack-level computing solution (e.g., a blade, tray or cradle computing system), a workstation or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a fixed game console, a smart TV, a vehicle control unit, a digital camera, a digital video recorder, a wearable electrical device, or an embedded computing system (e.g., a computing system that is part of a vehicle, a smart home appliance, a consumer electronic product or device, a manufacturing device). In some embodiments, the electrical device 1400 may be any other electronic device that processes data. In some embodiments, the electrical device 1400 may include multiple discrete physical components. Given the range of devices that the electrical device 1400 may represent in various embodiments, in some embodiments, the electrical device 1400 may be referred to as a computing device or a computing system.

[0132] Example

[0133] Illustrative examples of the technology disclosed herein are provided below. Embodiments of the technology may include any one or more of the examples described below and any combination of the examples described below.

[0134] Example 1 includes a device, including: a processor, the processor including a processor core, the processor core including: an instruction management circuit system, a digital instruction execution circuit system and an analog instruction execution circuit system, the instruction management circuit system is used to: receive multiple instructions; determine whether each instruction in the multiple instructions is a digital instruction or an analog instruction; in response to determining that the corresponding instructions are digital instructions, send each digital instruction in the multiple instructions to the digital instruction execution circuit system; and in response to determining that the corresponding instructions are analog instructions, send each analog instruction in the multiple instructions to the analog instruction execution circuit system, the analog instruction execution circuit system is used to execute the analog instructions received from the instruction management circuit system, wherein executing the analog instructions includes: generating or measuring analog signals at the input / output of the processor.

[0135] Example 2 includes the subject matter of Example 1, and wherein the digital instruction execution circuit system is used to execute instructions to load one or more parameters into one or more registers, and wherein the analog instruction execution circuit system is used to execute instructions to generate analog pulses based on the one or more parameters in the one or more registers.

[0136] Example 3 includes the subject matter of any of Examples 1 and 2, and wherein the one or more parameters in the one or more registers are used to control a frequency and an amplitude of the simulated pulses.

[0137] Example 4 includes the subject matter of any of Examples 1-3, and wherein the analog instruction execution circuitry is to execute instructions to generate an analog pulse and measure a reflection of the generated analog pulse.

[0138] Example 5 includes the subject matter of any of Examples 1-4, and wherein the analog instruction execution circuitry operates in a first clock domain, and wherein the digital instruction execution circuitry operates in a second clock domain different from the first clock domain.

[0139] Example 6 includes the subject matter of any one of Examples 1-5, and wherein the processor includes multiple processor cores, wherein each of the multiple processor cores includes an instruction management circuit system, the instruction management circuit system being used to: receive multiple instructions; determine whether each of the multiple instructions is a digital instruction or an analog instruction; send each of the multiple digital instructions to a digital instruction execution circuit system in response to determining that the corresponding instruction is a digital instruction; and send each of the multiple analog instructions to an analog instruction execution circuit system in response to determining that the corresponding instruction is an analog instruction; a digital instruction execution circuit system, the digital instruction execution circuit system being used to execute digital instructions received from the instruction management circuit system; and an analog instruction execution circuit system, the analog instruction execution circuit system being used to execute analog instructions received from the instruction management circuit system, wherein executing the analog instructions includes: generating or measuring analog signals at the input / output of the processor.

[0140] Example 7 includes the subject matter of any of Examples 1-6, and wherein the processor further comprises: a core synchronization matrix for synchronizing between processor cores in the plurality of processor cores.

[0141] Example 8 includes the subject matter of any one of Examples 1-7, and also includes: multiple processors, wherein each processor is in a separate package, wherein each processor of the multiple processors includes: multiple processor cores, wherein each processor core of the multiple processor cores of each processor of the multiple processors includes: an instruction management circuit system, the instruction management circuit system is used to: receive multiple instructions; determine whether each instruction of the multiple instructions is a digital instruction or an analog instruction; in response to determining that the corresponding instruction is a digital instruction, send each digital instruction of the multiple instructions to a digital instruction execution circuit system; and in response to determining that the corresponding instruction is an analog instruction, send each analog instruction of the multiple instructions to an analog instruction execution circuit system; a digital instruction execution circuit system, the digital instruction execution circuit system is used to execute digital instructions received from the instruction management circuit system; and an analog instruction execution circuit system, the analog instruction execution circuit system is used to execute analog instructions received from the instruction management circuit system, wherein executing the analog instruction includes: generating or measuring analog signals at the input / output of the processor.

[0142] Example 9 includes the subject matter of any of Examples 1-8, and wherein each processor of the plurality of processors comprises: a core synchronization matrix for synchronizing with other processors of the plurality of processors.

[0143] Example 10 includes the subject matter of any of Examples 1-9, and wherein the analog instruction execution circuitry comprises: a plurality of digital signal processors, wherein the plurality of digital signal processors are to execute a plurality of analog instructions in parallel.

[0144] Example 11 includes the subject matter of any of Examples 1-10, and further includes: a plurality of qubits, wherein each digital signal processor of the plurality of digital signal processors is used to control two or more qubits of the plurality of qubits.

[0145] Example 12 includes the subject matter of any of Examples 1-11, and wherein the instruction management circuitry is to receive the plurality of instructions in a single clock cycle.

[0146] Example 13 includes the subject matter of any of Examples 1-12, and wherein a latency of transmitting each emulation instruction of the plurality of instructions to the emulation instruction execution circuitry is less than one nanosecond.

[0147] Example 14 includes the subject matter of any of Examples 1-13, and wherein the processor has a von Neumann architecture.

[0148] Example 15 includes a device comprising: a plurality of quantum bits; and a processor, wherein the processor is used to execute digital instructions and analog instructions, wherein executing analog instructions comprises: sending an analog signal to a quantum bit among the plurality of quantum bits, or measuring an analog signal from a quantum bit among the plurality of quantum bits.

[0149] Example 16 includes the subject matter of Example 15, and further includes: multiple processors, wherein each processor is in a separate package, wherein each processor in the multiple processors is used to execute digital instructions and analog instructions, wherein executing the analog instructions includes: sending an analog signal to a quantum bit in the multiple quantum bits, or measuring an analog signal from a quantum bit in the multiple quantum bits.

[0150] Example 17 includes the subject matter of any of Examples 15 and 16, and wherein the processor is configured to execute instructions to load one or more parameters into one or more registers, wherein the processor is configured to execute instructions to generate analog pulses based on the one or more parameters in the one or more registers.

[0151] Example 18 includes the subject matter of any of Examples 15-17, and wherein the one or more parameters in the one or more registers are used to control a frequency and an amplitude of the simulated pulses.

[0152] Example 19 includes the subject matter of any of Examples 15-18, and wherein the processor is to execute instructions to generate a simulated pulse and measure a reflection of the generated simulated pulse.

[0153] Example 20 includes the subject matter of any of Examples 15-19, and wherein the processor comprises: a plurality of processor cores, wherein each of the plurality of processor cores is used to execute digital instructions and analog instructions, wherein executing the analog instructions comprises: sending an analog signal to a quantum bit among the plurality of quantum bits, or measuring an analog signal from a quantum bit among the plurality of quantum bits.

[0154] Example 21 includes the subject matter of any of Examples 15-20, and wherein the processor further comprises: a core synchronization matrix for synchronizing between processor cores in the plurality of processor cores.

[0155] Example 22 includes the subject matter of any of Examples 15-21, and also includes: multiple processors, wherein each processor is in a separate package, wherein each processor of the multiple processors includes: multiple processor cores, wherein each processor core of the multiple processor cores of each processor of the multiple processors is used to execute digital instructions and analog instructions, wherein executing analog instructions includes: sending an analog signal to a quantum bit of the multiple quantum bits, or measuring an analog signal from a quantum bit of the multiple quantum bits.

[0156] Example 23 includes the subject matter of any of Examples 15-22, and wherein each processor of the plurality of processors comprises: a core synchronization matrix for synchronizing with other processors of the plurality of processors.

[0157] Example 24 includes the subject matter of any of Examples 15-23, and wherein the processor comprises: a plurality of digital signal processors, wherein the plurality of digital signal processors are to execute a plurality of analog instructions in parallel.

[0158] Example 25 includes the subject matter of any of Examples 15-24, and wherein each digital signal processor of the plurality of digital signal processors is used to control two or more qubits of the plurality of qubits.

[0159] Example 26 includes the subject matter of any of Examples 15-25, and wherein the processor is to receive multiple instructions in a single clock cycle.

[0160] Example 27 includes the subject matter of any of Examples 15-26, and wherein the processor has a von Neumann architecture.

[0161] Example 28 includes a quantum computing device comprising: a first processor; a plurality of quantum bits; a second processor; and one or more computer-readable media, the one or more computer-readable media including a plurality of instructions for the first processor stored therein, the plurality of instructions, when executed by the first processor, causing the first processor to perform the following operations: sending a plurality of instructions for the second processor to the second processor, wherein the plurality of instructions for the second processor include one or more digital instructions and one or more analog instructions, wherein the one or more analog instructions, when executed by the second processor, cause the second processor to generate or measure an analog signal at an input / output of the second processor.

[0162] Example 29 includes the subject matter of Example 28, and wherein the plurality of instructions for the first processor further causes the first processor to perform the following operations: compile the code into the plurality of instructions for the second processor, wherein compiling the code into the plurality of instructions for the second processor includes: optimizing the one or more digital instructions and the one or more analog instructions in the plurality of instructions for the second processor.

[0163] Example 30 includes the subject matter of any of Examples 28 and 29, and wherein the second processor comprises: a plurality of cores, wherein optimizing the one or more digital instructions and the one or more analog instructions among the plurality of instructions for the second processor comprises: optimizing the one or more digital instructions and the one or more analog instructions among the plurality of instructions for the plurality of cores.

[0164] Example 31 includes the subject matter of any of Examples 28-30, and wherein optimizing the one or more digital instructions and the one or more analog instructions among the multiple instructions for the second processor includes: optimizing the one or more digital instructions and the one or more analog instructions among the multiple instructions for multiple second processors.

[0165] Example 32 includes the subject matter of any of Examples 28-31, and wherein the one or more digital instructions, when executed by the second processor, cause the second processor to load one or more parameters into one or more registers, and wherein the one or more analog instructions, when executed by the second processor, cause the second processor to generate analog pulses based on the one or more parameters in the one or more registers.

[0166] Example 33 includes the subject matter of any of Examples 28-32, and wherein the one or more parameters in the one or more registers are used to control a frequency and an amplitude of the simulated pulses.

[0167] Example 34 includes the subject matter of any of Examples 28-33, and wherein the one or more digital instructions, when executed by the second processor, cause the second processor to generate an analog pulse and measure a reflection of the generated analog pulse.

[0168] Example 35 includes the subject matter of any of Examples 28-34, and wherein the second processor comprises a plurality of processor cores.

[0169] Example 36 includes the subject matter of any of Examples 28-35, and wherein the second processor further comprises: a core synchronization matrix for synchronizing between processor cores in the plurality of processor cores.

[0170] Example 37 includes the subject matter of any of Examples 28-36, and wherein the quantum computing device comprises a plurality of second processors, further comprising scheduling instructions on respective second processors in the plurality of digital / analog processors.

[0171] Example 38 includes the subject matter of any of Examples 28-37, and wherein each second processor of the plurality of second processors comprises: a core synchronization matrix for synchronizing with other second processors of the plurality of second processors.

[0172] Example 39 includes the subject matter of any of Examples 28-38, and wherein the plurality of instructions for the first processor further cause the first processor to perform the following operations: the first processor communicates with respective core synchronization matrices of the plurality of second processors to synchronize the plurality of second processors.

[0173] Example 40 includes the subject matter of any of Examples 28-39, and wherein the second processor comprises: a plurality of digital signal processors, wherein the plurality of digital signal processors are to execute a plurality of analog instructions in parallel.

[0174] Example 41 includes the subject matter of any of Examples 28-40, and wherein each digital signal processor of the plurality of digital signal processors is used to control two or more qubits of the plurality of qubits.

[0175] Example 42 includes the subject matter of any of Examples 28-41, and wherein the second processor has a von Neumann architecture.

[0176] Example 43 includes a method comprising: sending, by a first processor of a quantum computing device, a plurality of instructions for a second processor of the quantum computing device to the second processor, wherein the plurality of instructions for the second processor include one or more digital instructions and one or more analog instructions, wherein the one or more analog instructions, when executed by the second processor, cause the second processor to generate or measure an analog signal at an input / output of the second processor.

[0177] Example 44 includes the subject matter of Example 43, and also includes: compiling the code into the multiple instructions for the second processor by the first processor, wherein compiling the code into the multiple instructions for the second processor includes: optimizing the one or more digital instructions and the one or more analog instructions in the multiple instructions for the second processor.

[0178] Example 45 includes the subject matter of any of Examples 43 and 44, and wherein the second processor comprises: a plurality of cores, wherein optimizing the one or more digital instructions and the one or more analog instructions among the plurality of instructions for the second processor comprises: optimizing the one or more digital instructions and the one or more analog instructions among the plurality of instructions for the plurality of cores.

[0179] Example 46 includes the subject matter of any of Examples 43-45, and wherein optimizing the one or more digital instructions and the one or more analog instructions among the multiple instructions for the second processor includes: optimizing the one or more digital instructions and the one or more analog instructions among the multiple instructions for multiple second processors.

[0180] Example 47 includes the subject matter of any of Examples 43-46, and wherein the one or more digital instructions, when executed by the second processor, cause the second processor to load one or more parameters into one or more registers, and wherein the one or more analog instructions, when executed by the second processor, cause the second processor to generate analog pulses based on the one or more parameters in the one or more registers.

[0181] Example 48 includes the subject matter of any of Examples 43-47, and wherein the one or more parameters in the one or more registers are used to control a frequency and an amplitude of the simulated pulses.

[0182] Example 49 includes the subject matter of any of Examples 43-48, and wherein the one or more digital instructions, when executed by the second processor, cause the second processor to generate an analog pulse and measure a reflection of the generated analog pulse.

[0183] Example 50 includes the subject matter of any of Examples 43-49, and wherein the second processor comprises a plurality of processor cores.

[0184] Example 51 includes the subject matter of any of Examples 43-50, and wherein the second processor further comprises: a core synchronization matrix for synchronizing between processor cores in the plurality of processor cores.

[0185] Example 52 includes the subject matter of any of Examples 43-51, and wherein the quantum computing device comprises a plurality of second processors, further comprising scheduling instructions on respective second processors in the plurality of digital / analog processors.

[0186] Example 53 includes the subject matter of any of Examples 43-52, and wherein each second processor of the plurality of second processors comprises: a core synchronization matrix for synchronizing with other second processors of the plurality of second processors.

[0187] Example 54 includes the subject matter of any of Examples 43-53, and further includes: communicating, by the first processor, with respective core synchronization matrices of the plurality of second processors to synchronize the plurality of second processors.

[0188] Example 55 includes the subject matter of any of Examples 43-54, and wherein the second processor comprises: a plurality of digital signal processors, wherein the plurality of digital signal processors are used to execute a plurality of analog instructions in parallel.

[0189] Example 56 includes the subject matter of any of Examples 43-55, and wherein the quantum computing device includes a plurality of qubits, wherein each of the plurality of digital signal processors is used to control two or more of the plurality of qubits.

[0190] Example 57 includes the subject matter of any of Examples 43-56, and wherein the second processor has a von Neumann architecture.

[0191] Example 58 includes a quantum computing device comprising: a first processor; a plurality of quantum bits; a second processor; and a unit for sending a plurality of instructions for the second processor of the quantum computing device to the second processor, wherein the plurality of instructions for the second processor include one or more digital instructions and one or more analog instructions, wherein the one or more analog instructions, when executed by the second processor, cause the second processor to generate or measure an analog signal at an input / output of the second processor.

[0192] Example 59 includes the subject matter of Example 58, and further includes: a unit for compiling the code by the first processor into the plurality of instructions for the second processor, wherein the unit for compiling the code into the plurality of instructions for the second processor includes a unit for optimizing the one or more digital instructions and the one or more analog instructions in the plurality of instructions for the second processor.

[0193] Example 60 includes the subject matter of any of Examples 58 and 59, and wherein the second processor comprises: a plurality of cores, wherein the unit for optimizing the one or more digital instructions and the one or more analog instructions among the plurality of instructions for the second processor comprises: a unit for optimizing the one or more digital instructions and the one or more analog instructions among the plurality of instructions for the plurality of cores.

[0194] Example 61 includes the subject matter of any of Examples 58-60, and wherein the unit for optimizing the one or more digital instructions and the one or more analog instructions among the multiple instructions for the second processor includes: a unit for optimizing the one or more digital instructions and the one or more analog instructions among the multiple instructions for multiple second processors.

[0195] Example 62 includes the subject matter of any of Examples 58-61, and wherein the one or more digital instructions, when executed by the second processor, cause the second processor to load one or more parameters into one or more registers, and wherein the one or more analog instructions, when executed by the second processor, cause the second processor to generate analog pulses based on the one or more parameters in the one or more registers.

[0196] Example 63 includes the subject matter of any of Examples 58-62, and wherein the one or more parameters in the one or more registers are used to control the frequency and amplitude of the simulated pulses.

[0197] Example 64 includes the subject matter of any of Examples 58-63, and wherein the one or more digital instructions, when executed by the second processor, cause the second processor to generate an analog pulse and measure a reflection of the generated analog pulse.

[0198] Example 65 includes the subject matter of any of Examples 58-64, and wherein the second processor comprises a plurality of processor cores.

[0199] Example 66 includes the subject matter of any of Examples 58-65, and wherein the second processor further comprises: a core synchronization matrix for synchronizing between processor cores in the plurality of processor cores.

[0200] Example 67 includes the subject matter of any of Examples 58-66, and wherein the quantum computing device comprises a plurality of second processors, further comprising means for scheduling instructions on respective second processors in the plurality of digital / analog processors.

[0201] Example 68 includes the subject matter of any of Examples 58-67, and wherein each second processor of the plurality of second processors comprises: a core synchronization matrix for synchronizing with other second processors of the plurality of second processors.

[0202] Example 69 includes the subject matter of any of Examples 58-68, and further includes means for communicating, by the first processor, with respective core synchronization matrices of the plurality of second processors to synchronize the plurality of second processors.

[0203] Example 70 includes the subject matter of any of Examples 58-69, and wherein the second processor comprises: a plurality of digital signal processors, wherein the plurality of digital signal processors are to execute a plurality of analog instructions in parallel.

[0204] Example 71 includes the subject matter of any of Examples 58-70, and wherein each digital signal processor of the plurality of digital signal processors is used to control two or more qubits of the plurality of qubits.

[0205] Example 72 includes the subject matter of any of Examples 58-71, and wherein the second processor has a von Neumann architecture.

[0206] Example 73 includes one or more computer-readable media including a plurality of instructions for a first processor of a quantum computing device stored thereon, the plurality of instructions, when executed, causing the first processor to send a plurality of instructions for a second processor to the second processor, wherein the plurality of instructions for the second processor include one or more digital instructions and one or more analog instructions, wherein the one or more analog instructions, when executed by the second processor, cause the second processor to generate or measure an analog signal at an input / output of the second processor.

[0207] Example 74 includes the subject matter of Example 73, and wherein the plurality of instructions for the first processor also causes the first processor to compile code into the plurality of instructions for the second processor, wherein compiling the code into the plurality of instructions for the second processor includes: optimizing the one or more digital instructions and the one or more analog instructions in the plurality of instructions for the second processor.

[0208] Example 75 includes the subject matter of any of Examples 73 and 74, and wherein the second processor comprises: a plurality of cores, wherein optimizing the one or more digital instructions and the one or more analog instructions among the plurality of instructions for the second processor comprises: optimizing the one or more digital instructions and the one or more analog instructions among the plurality of instructions for the plurality of cores.

[0209] Example 76 includes the subject matter of any of Examples 73-75, and wherein optimizing the one or more digital instructions and the one or more analog instructions among the multiple instructions for the second processor includes: optimizing the one or more digital instructions and the one or more analog instructions among the multiple instructions for multiple second processors.

[0210] Example 77 includes the subject matter of any of Examples 73-76, and wherein the one or more digital instructions, when executed by the second processor, cause the second processor to load one or more parameters into one or more registers, and wherein the one or more analog instructions, when executed by the second processor, cause the second processor to generate analog pulses based on the one or more parameters in the one or more registers.

[0211] Example 78 includes the subject matter of any of Examples 73-77, and wherein the one or more parameters in the one or more registers are used to control the frequency and amplitude of the simulated pulses.

[0212] Example 79 includes the subject matter of any of Examples 73-78, and wherein the one or more digital instructions, when executed by the second processor, cause the second processor to generate an analog pulse and measure a reflection of the generated analog pulse.

[0213] Example 80 includes the subject matter of any of Examples 73-79, and wherein the second processor comprises a plurality of processor cores.

[0214] Example 81 includes the subject matter of any of Examples 73-80, and wherein the second processor further comprises: a core synchronization matrix for synchronizing between processor cores in the plurality of processor cores.

[0215] Example 82 includes the subject matter of any of Examples 73-81, and wherein the quantum computing device comprises a plurality of second processors, further comprising scheduling instructions on respective second processors in the plurality of digital / analog processors.

[0216] Example 83 includes the subject matter of any of Examples 73-82, and wherein each second processor of the plurality of second processors comprises: a core synchronization matrix for synchronizing with other second processors of the plurality of second processors.

[0217] Example 84 includes the subject matter of any of Examples 73-83, and wherein the plurality of instructions for the first processor further cause the first processor to: communicate with respective core synchronization matrices of the plurality of second processors by the first processor to synchronize the plurality of second processors.

[0218] Example 85 includes the subject matter of any of Examples 73-84, and wherein the second processor comprises: a plurality of digital signal processors, wherein the plurality of digital signal processors are used to execute a plurality of analog instructions in parallel.

[0219] Example 86 includes the subject matter of any of Examples 73-85, and wherein each digital signal processor of the plurality of digital signal processors is used to control two or more qubits of the plurality of qubits.

[0220] Example 87 includes the subject matter of any of Examples 73-86, and wherein the second processor has a von Neumann architecture.

[0221] Example 88 includes a quantum computing device comprising a processor configured to: receive an instruction; determine whether the instruction is a digital instruction or an analog instruction; and execute the instruction as an analog instruction in response to determining that the instruction is an analog instruction, wherein executing the instruction comprises generating an analog signal or measuring an analog signal.

[0222] Example 89 includes the quantum computing device of Example 88, wherein the processor is further configured to: receive a second instruction by the processor; determine by the processor whether the second instruction is a digital instruction or an analog instruction; and execute by the processor as a digital instruction in response to determining that the second instruction is a digital instruction.

[0223] Example 90 includes the subject matter of any of Examples 88 and 89, and wherein executing the second instruction comprises loading one or more parameters into one or more registers, wherein executing the instruction comprises generating an analog pulse based on the one or more parameters in the one or more registers.

[0224] Example 91 includes the subject matter of any of Examples 88-90, and wherein the one or more parameters in the one or more registers are used to control the frequency and amplitude of the analog pulses.

[0225] Example 92 includes the subject matter of any of Examples 88-91, and wherein executing the instructions comprises generating an analog pulse and measuring a reflection of the generated analog pulse.

[0226] Example 93 includes the subject matter of any of Examples 88-92, and wherein the processor comprises a plurality of processor cores.

[0227] Example 94 includes the subject matter of any of Examples 88-93, and wherein the processor further comprises: a core synchronization matrix for synchronizing between processor cores in the plurality of processor cores.

[0228] Example 95 includes the subject matter of any of Examples 88-94, and wherein the processor comprises: a plurality of digital signal processors, wherein the plurality of digital signal processors are used to execute a plurality of analog instructions in parallel.

[0229] Example 96 includes the subject matter of any of Examples 88-95, and wherein each digital signal processor of the plurality of digital signal processors is used to control two or more qubits of the plurality of qubits.

[0230] Example 97 includes the subject matter of any of Examples 88-96, and wherein the processor is further for receiving multiple instructions in a single clock cycle.

[0231] Example 98 includes the subject matter of any of Examples 88-97, and wherein the processor has a von Neumann architecture.

[0232] Example 99 includes a method comprising: receiving an instruction by a processor; determining by the processor whether the instruction is a digital instruction or an analog instruction; and executing by the processor as an analog instruction in response to determining that the instruction is an analog instruction, wherein executing the instruction includes generating an analog signal or measuring an analog signal.

[0233] Example 100 includes the method of Example 99, further comprising: receiving a second instruction by the processor; determining by the processor whether the second instruction is a digital instruction or an analog instruction; and executing the second instruction as a digital instruction by the processor in response to determining that the second instruction is a digital instruction.

[0234] Example 101 includes the subject matter of any of Examples 99 and 100, and wherein executing the second instruction includes loading one or more parameters into one or more registers, wherein executing the instruction includes generating an analog pulse based on the one or more parameters in the one or more registers.

[0235] Example 102 includes the subject matter of any of Examples 99-101, and wherein the one or more parameters in the one or more registers are used to control the frequency and amplitude of the analog pulses.

[0236] Example 103 includes the subject matter of any of Examples 99-102, and wherein executing the instructions comprises generating an analog pulse and measuring a reflection of the generated analog pulse.

[0237] Example 104 includes the subject matter of any of Examples 99-103, and wherein the processor comprises a plurality of processor cores.

[0238] Example 105 includes the subject matter of any one of Examples 99 to 104, and wherein the processor further comprises: a core synchronization matrix, the core synchronization matrix being used to synchronize between processor cores in the plurality of processor cores.

[0239] Example 106 includes the subject matter of any of Examples 99-105, and wherein the processor comprises: a plurality of digital signal processors, wherein the plurality of digital signal processors are used to execute a plurality of analog instructions in parallel.

[0240] Example 107 includes the subject matter of any of Examples 99-106, and wherein each of the plurality of digital signal processors is used to control two or more of the plurality of qubits.

[0241] Example 108 includes the subject matter of any of Examples 99-107, and further includes receiving, by the processor, a plurality of instructions in a single clock cycle.

[0242] Example 109 includes the subject matter of any of Examples 99-108, and wherein the processor has a von Neumann architecture.

[0243] Example 110 includes a quantum computing device comprising: a unit for receiving an instruction; a unit for determining whether the instruction is a digital instruction or an analog instruction; and a unit for executing the instruction as an analog instruction in response to determining that the instruction is an analog instruction, wherein the unit for executing the instruction includes a unit for generating an analog signal or measuring an analog signal.

[0244] Example 111 includes the subject matter of Example 110, and further includes: a unit for receiving a second instruction; a unit for determining whether the second instruction is a digital instruction or an analog instruction; and a unit for executing the second instruction as a digital instruction in response to determining that the second instruction is a digital instruction.

[0245] Example 112 includes the subject matter of any of Examples 110 and 111, and wherein the unit for executing the second instruction includes a unit for loading one or more parameters into one or more registers, wherein the unit for executing the instruction includes a unit for generating an analog pulse based on the one or more parameters in the one or more registers.

[0246] Example 113 includes the subject matter of any of Examples 110-112, and wherein the one or more parameters in the one or more registers are used to control a frequency and an amplitude of the simulated pulses.

[0247] Example 114 includes the subject matter of any of Examples 110-113, and wherein the means for executing the instructions comprises means for generating an analog pulse and measuring a reflection of the generated analog pulse.

[0248] Example 115 includes the subject matter of any of Examples 110-114, and wherein the means for executing the instruction as an analog instruction comprises a plurality of digital signal processors, wherein the plurality of digital signal processors are used to execute the plurality of analog instructions in parallel.

[0249] Example 116 includes the subject matter of any of Examples 110-115, and wherein each digital signal processor of the plurality of digital signal processors is used to control two or more qubits of the plurality of qubits.

[0250] Example 117 includes the subject matter of any of Examples 110-116, and further includes means for receiving multiple instructions in a single clock cycle.

[0251] Example 118 includes the subject matter of any of Examples 110-117, and wherein the unit for executing the instruction as an emulated instruction has a von Neumann architecture.

Claims

1. A device comprising: A processor, the processor comprising a processor core, the processor core comprising: Instruction management circuitry, digital instruction execution circuitry, and analog instruction execution circuitry, wherein the instruction management circuitry is used to: Receive multiple instructions; determining whether each instruction of the plurality of instructions is a digital instruction or an analog instruction; In response to determining that the corresponding respective instructions are digital instructions, sending respective digital instructions of the plurality of instructions to the digital instruction execution circuitry; and In response to determining that the corresponding respective instructions are emulation instructions, sending respective emulation instructions of the plurality of instructions to the emulation instruction execution circuit system, The simulation instruction execution circuit system is used to execute simulation instructions received from the instruction management circuit system, wherein executing the simulation instructions includes: generating or measuring simulation signals at the input / output of the processor.

2. The device according to claim 1, wherein: The digital instruction execution circuitry is for executing instructions to load one or more parameters into one or more registers, wherein the analog instruction execution circuitry is for executing instructions to generate analog pulses based on the one or more parameters in the one or more registers.

3. The device according to claim 2, wherein: The one or more parameters in the one or more registers are used to control the frequency and amplitude of the analog pulses.

4. The device according to any one of claims 1 to 3, wherein: The analog instruction execution circuit system is used to execute instructions to generate analog pulses and measure reflections of the generated analog pulses.

5. The device according to any one of claims 1 to 4, wherein: The analog instruction execution circuitry operates in a first clock domain, wherein the digital instruction execution circuitry operates in a second clock domain different from the first clock domain.

6. The device according to any one of claims 1 to 5, wherein: The analog instruction execution circuit system includes: a plurality of digital signal processors, wherein the plurality of digital signal processors are used to execute a plurality of analog instructions in parallel.

7. The apparatus according to claim 6, further comprising: A plurality of qubits, wherein each of the plurality of digital signal processors is used to control two or more qubits of the plurality of qubits.

8. The device according to any one of claims 1 to 7, wherein: The instruction management circuitry is configured to receive the plurality of instructions in a single clock cycle.

9. The device according to any one of claims 1 to 8, wherein: The latency of transmitting each simulation instruction of the plurality of instructions to the simulation instruction execution circuit system is less than one nanosecond.

10. An apparatus comprising: Multiple qubits; as well as processor, The processor is used to execute digital instructions and analog instructions, wherein executing analog instructions includes: sending analog signals to quantum bits among the multiple quantum bits, or measuring analog signals from quantum bits among the multiple quantum bits.

11. The apparatus according to claim 10, further comprising: Multiple processors, where each processor is in a separate package, Among them, each processor among the multiple processors is used to execute digital instructions and analog instructions, wherein executing analog instructions includes: sending an analog signal to a quantum bit among the multiple quantum bits, or measuring an analog signal from a quantum bit among the multiple quantum bits.

12. The device according to any one of claims 10-11, wherein: The processor is configured to execute instructions to load one or more parameters into one or more registers, wherein the processor is configured to execute instructions to generate a simulated pulse based on the one or more parameters in the one or more registers.

13. The device according to claim 12, wherein: The one or more parameters in the one or more registers are used to control the frequency and amplitude of the analog pulses.

14. The device according to any one of claims 10 to 13, wherein: The processor is configured to execute instructions to generate an analog pulse and measure a reflection of the generated analog pulse.

15. The device according to any one of claims 10 to 14, wherein: The processor includes: multiple processor cores, wherein each processor core in the multiple processor cores is used to execute digital instructions and analog instructions, wherein executing analog instructions includes: sending analog signals to quantum bits in the multiple quantum bits, or measuring analog signals from quantum bits in the multiple quantum bits.

16. The device according to claim 15, wherein: The processor further comprises: a core synchronization matrix, wherein the core synchronization matrix is ​​used for synchronizing between processor cores in the plurality of processor cores.

17. The apparatus according to any one of claims 10 to 16, further comprising: A plurality of processors, wherein each processor is in a separate package, wherein each processor of the plurality of processors comprises: a plurality of processor cores, wherein each processor core of the plurality of processor cores of each processor of the plurality of processors is used to execute digital instructions and analog instructions, wherein executing analog instructions comprises: sending analog signals to quantum bits of the plurality of quantum bits, or measuring analog signals from quantum bits of the plurality of quantum bits.

18. The device according to claim 17, wherein: Each processor of the plurality of processors comprises: a core synchronization matrix, and the core synchronization matrix is ​​used for synchronizing with other processors of the plurality of processors.

19. The device according to any one of claims 10 to 18, wherein: The processor includes: a plurality of digital signal processors, wherein the plurality of digital signal processors are used to execute a plurality of analog instructions in parallel.

20. The device according to claim 19, wherein Each digital signal processor of the plurality of digital signal processors is used to control two or more quantum bits of the plurality of quantum bits.

21. The device according to any one of claims 10 to 20, wherein: The processor is configured to receive multiple instructions in a single clock cycle.

22. A quantum computing device comprising: a first processor; Multiple qubits; A second processor; as well as One or more computer-readable media, the one or more computer-readable media including a plurality of instructions for the first processor stored therein, the plurality of instructions, when executed by the first processor, causing the first processor to perform the following operations: A plurality of instructions for the second processor are sent to the second processor, wherein the plurality of instructions for the second processor include one or more digital instructions and one or more analog instructions, wherein the one or more analog instructions, when executed by the second processor, cause the second processor to generate or measure analog signals at an input / output of the second processor.

23. A quantum computing device according to claim 22, wherein: The plurality of instructions for the first processor further cause the first processor to perform the following operations: Compiling the code into the plurality of instructions for the second processor, wherein compiling the code into the plurality of instructions for the second processor comprises optimizing the one or more digital instructions and the one or more analog instructions in the plurality of instructions for the second processor.

24. A quantum computing device according to claim 23, wherein: The second processor comprises: a plurality of cores, wherein optimizing the one or more digital instructions and the one or more analog instructions among the plurality of instructions for the second processor comprises: optimizing the one or more digital instructions and the one or more analog instructions among the plurality of instructions for the plurality of cores.

25. A quantum computing device according to any one of claims 23-24, wherein: Optimizing the one or more digital instructions and the one or more analog instructions in the plurality of instructions for the second processor includes optimizing the one or more digital instructions and the one or more analog instructions in the plurality of instructions for a plurality of second processors.

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