Dynamic hammer management

Abstract

Mitigating or managing the impact on a DRAM device, referred to as a "row hammer", may include a memory controller receiving an activation count threshold value from the DRAM device. The memory controller may detect row activation commands for the DRAM device and count a number of row activation commands. The memory controller may send a mitigation refresh command to the DRAM device based on a result of comparing the counted number of row activation commands with the received activation count threshold value.

Description

Background Art

[0001] Dynamic random access memory ("DRAM") may be included in a wide variety of computing devices. Maintaining data integrity in DRAM is an important consideration.

[0002] It has been observed that repeatedly activating one or more rows of a DRAM array within a single refresh window may compromise data integrity, i.e., may result in corruption of stored data. Repeated activation of one or more rows of a DRAM array may cause one or more cells of physically adjacent rows to leak their stored charge, resulting in an increased probability of bit flips. This phenomenon is often referred to as "row hammering" or "rowhammer" and may be exploited by an attacker to intentionally corrupt stored data.

[0003] A variety of row hammer mitigation methods have been developed. Some row hammer mitigation methods may suppress or limit the rate of row activations when rapid row activations are detected. Other row hammer mitigation methods may refresh potential victim rows when rapid row activations are detected. Row hammer mitigation methods may count the number of row activations that occur within a refresh window. A threshold number of row activations above which the probability of a bit flip is considered unacceptably high may be determined, and when the count of row activations reaches the threshold, mitigation may be applied. It would be desirable to improve mitigation or management of row hammer phenomena. Summary of the invention

[0004] Systems, methods, and other examples are disclosed for mitigating or managing row hammer in dynamic random access memory (DRAM) systems.

[0005] An exemplary method may include: receiving, by a memory controller, an activation count threshold value from a DRAM device. The exemplary method may also include: detecting, by the memory controller, a row activation command for a memory bank of the DRAM device. The exemplary method may also include: counting, by the memory controller, the number of row activation commands. The exemplary method may also include: comparing, by the memory controller, the number of row activation commands with the activation count threshold value. The exemplary method may also include: sending, by the memory controller, a mitigated refresh command to the DRAM device based on a result of comparing the number of row activation commands with the activation count threshold value.

[0006] An exemplary system may include interface logic, activation command detection logic, activation command counting logic, comparison logic, and light refresh logic. The interface logic may be configured to receive an activation count threshold value from a DRAM device. The activation command detection logic may be configured to detect a row activation command for a memory bank of the DRAM device. The activation command counting logic may be configured to count the number of row activation commands. The comparison logic may be configured to compare the number of row activation commands with the activation count threshold value. The light refresh logic may be configured to send a light refresh command to the DRAM device based on a result of comparing the number of row activation commands with the activation count threshold value.

[0007] Another exemplary system may include a unit for receiving an activation count threshold value from a DRAM device. The exemplary system may also include a unit for detecting a row activation command for a memory bank of the DRAM device. The exemplary system may also include a unit for counting the number of row activation commands. The exemplary system may also include a unit for comparing the number of row activation commands with the activation count threshold value. The exemplary system may also include a unit for sending a mitigation refresh command to the DRAM device based on the result of comparing the number of row activation commands with the activation count threshold value.

[0008] An exemplary memory controller may include command generation logic, interface logic, activation command detection logic, activation command counting logic, comparison logic, and refresh mitigation logic. The command generation logic may be configured to generate DRAM commands in response to memory transaction requests, which may include row activation commands and refresh commands. The interface logic may be configured to receive an activation count threshold value from a DRAM device. The activation command detection logic may be configured to detect a row activation command for a memory bank of the DRAM device. The activation command counting logic may be configured to count the number of row activation commands. The comparison logic may be configured to compare the number of row activation commands with the activation count threshold value. The refresh mitigation logic may be configured to send a refresh mitigation command to the DRAM device based on the result of comparing the number of row activation commands with the activation count threshold value.

[0009] An exemplary DRAM device may include: at least one data storage array including a plurality of rows; per-row activation command counting logic; bucketing logic; and bucket selection logic. The per-row activation command counting logic may be configured to count the per-row number of row activation commands for each row of the DRAM device. The bucketing logic may be configured to determine the number of rows in each of a plurality of buckets, including: for each bucket, counting the number of rows for which the row activation commands have a per-row number greater than or equal to the corresponding bucket activation count threshold of the bucket, wherein each bucket has a corresponding bucket activation count threshold different from all other buckets and a corresponding bucket threshold different from all other buckets. The bucket selection logic may be configured to select a bucket with a maximum bucket activation count threshold in the bucket from a subset of buckets having a non-zero number of rows therein. The bucket selection logic may also be configured to select a bucket threshold corresponding to the selected bucket and provide the selected bucket threshold to a memory controller. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In the drawings, like reference numerals refer to like parts throughout the various views unless otherwise indicated. For reference numerals with alphabetic characters, such as "101A" or "101B", the alphabetic characters may distinguish between two similar parts or elements in the same figure. When it is intended that a reference numeral encompass all parts having the same reference numeral in all figures, the alphabetic characters of the reference numeral may be omitted.

[0011] Figure 1 is a block diagram of a DRAM system and a client device according to an exemplary embodiment.

[0012] Figure 2 is similar to Figure 1 00140 00141 00141 A block diagram illustrating memory controller and DRAM features for row hammer mitigation according to an exemplary embodiment.

[0013] Figure 3 is a flow chart illustrating a method for row hammer mitigation by a memory controller according to an exemplary embodiment.

[0014] Figure 4 is a block diagram illustrating a memory controller having a row hammer mitigation system according to an exemplary embodiment.

[0015] Figure 5 An example of the operation of a row hammer mitigation system according to an exemplary embodiment is shown.

[0016] Figure 6 is a flow chart illustrating a method for determining a row hammer activation count threshold by a DRAM device according to an example embodiment.

[0017] Figure 7is a block diagram illustrating hammer activation command count threshold logic according to an exemplary embodiment.

[0018] Fig. 8A is a table illustrating an initial operating state of a row hammer mitigation system according to an exemplary embodiment.

[0019] Figure 8B is a table illustrating later operating states of a row hammer mitigation system according to an exemplary embodiment.

[0020] Figure 8C is a table illustrating later operating states of a row hammer mitigation system according to an exemplary embodiment.

[0021] Fig. 9 is a block diagram of a portable computing device according to an exemplary embodiment. DETAILED DESCRIPTION

[0022] The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” The word “illustrative” may be used herein synonymously with “exemplary.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

[0023] like Figure 1 As shown in , in an illustrative or exemplary embodiment, a system 100 may include a client device 102, a memory controller 104, and a dynamic random access memory ("DRAM") device 105 having one or more memory arrays 106. As described below, the memory controller 104 or alternatively or additionally the DRAM device 105 may include features for mitigating or managing the effects of a phenomenon generally referred to as "row hammer."

[0024] Row hammer is a disturb error that may result in corruption of data stored in the memory array 106. Repeated activation of one or more rows 108, 110, etc. may cause cells in another row 112 that are physically adjacent to the one or more rows 108, 110, etc. (not in the memory array 106). Figure 1 108, 110, etc. may be referred to as "aggressor" rows, and row 112 (shown separately in FIG. 104) may be referred to as "aggressor" rows. In other words, as a result of a row hammer attack, there may be an increased probability that the bit value read from the cell is different from the bit value originally stored in the cell. More specifically, a "1" stored before the row hammer attack may be incorrectly read as a "0" after the row hammer attack, or a "0" stored before the row hammer attack may be incorrectly read as a "1" after the row hammer attack. Rows 108, 110, etc. may be referred to as "aggressor" rows, and row 112 (shown separately in FIG. 104) may be referred to as "aggressor" rows. Figure 1108 and 110. In the example shown, victim row 112 is immediately adjacent to each of aggressor rows 108 and 110. In other examples of row hammer attacks, such a victim row may be adjacent to only one aggressor row. Although only three rows 108, 110, and 112 are shown for purposes of illustration, as will be appreciated by one of ordinary skill in the art, memory array 106 may have any number of rows, such as, for example, 16k, 32k, etc.

[0025] like Figure 2 As shown in , a system 200 may include a client device 202, a cache system 204, a memory controller 206, and a DRAM device 208. Some or all of these elements may be included in a "system on a chip" or "SoC", which includes one or more types of processors, such as a central processing unit ("CPU"), a graphics processing unit ("GPU"), a digital signal processor ("DSP"), a neural processing unit ("NPU"), etc. The client device 202 may be implemented, for example, in a CPU (not separately shown) or an application processor. Although not shown in the figure for clarity, the client device 202 may be implemented in a CPU (not separately shown) or an application processor. Figure 2 As shown in FIG. 1 , the system 200 may be included in a computing device, such as, for example, a portable computing device. The system 200 may be the system 100 ( Figure 1 ) example.

[0026] The client device 202 may issue DRAM transaction requests, which include: a read request, i.e., a request to read data from the DRAM device 208; and a write request, i.e., a request to store data in the DRAM device 208. The DRAM transaction request may also be referred to as a request to access the DRAM device 208. Each DRAM transaction request may include a target address in the DRAM device 208, a size or amount of data to be accessed, and other information. The write request also includes data, which may be referred to as a payload, and the memory controller 206 will store the data in the DRAM device 208 in response to the write request.

[0027] In addition to the features described herein with respect to row hammer mitigation, the structure and operation of memory controller 206 and DRAM device 208 are well understood by those of ordinary skill in the art. Nevertheless, the following brief description is provided as background.

[0028] The memory controller 206 may include command generation logic 209 configured to convert transaction requests into DRAM commands (“Cmd”) and physical DRAM addresses (“Addr”), and provide the commands and addresses to the DRAM devices 208. In addition to generating commands in response to transaction requests, the command generation logic 209 may generate periodic refresh commands. The memory controller 206 may queue the transaction requests and provide the associated commands and addresses to the DRAM devices 208 in a determined order using a scheduling algorithm. When providing commands and addresses to the DRAM devices 208, the memory controller 206 may control the timing of such commands and addresses with respect to each other. Because such aspects are well understood by those of ordinary skill in the art, they are not described in further detail herein. The memory controller 206 may include other logic blocks or elements that are well understood by those of ordinary skill in the art, such as scheduling logic configured to perform the scheduling mentioned above, arbitration logic configured to control the order of commands when the commands are transmitted to the DRAM devices 208 through the memory controller 206, etc., and for the purpose of clarity, Figure 2 Such elements are not shown in FIG.

[0029] DRAM device 208 can be of any type not consistent with the description herein. For example, DRAM device 208 can be a double data rate synchronous DRAM ("DDR-SDRAM"), sometimes referred to as "DDR". As DDR technology has evolved, DDR versions such as fourth-generation low-power DDR ("LPDDR4") and fifth-generation low-power DDR ("LPDDR5") have been developed. DRAM device 208 can include, for example, LPDDR4, LPDDR4X, LPDDR5, LPDDR5X, etc. Other types of DDR include graphics DDR ("GDDR"). Although in the examples described herein, DRAM device 208 can be DDR, in other examples, such DRAM can be another type of low-power DRAM, such as SDRAM in a high-bandwidth memory ("HBM").

[0030] DRAM device 208 may include two ranks 210, which may be referred to as rank_0 and rank_1. Although two ranks 210 are shown in this example, in other examples, there may be only one rank or more than two rank. Because the two ranks 210 are identical to each other, the following description applies to each rank 210. Rank 210 includes two or more ("M") memory banks 212, which may be referred to as memory bank_0 through memory bank_M-1. Each memory bank 212 is organized into a two-dimensional memory array 213 of cells or memory locations, where a memory location in the memory array 213 is accessed by selecting a row and a column. The charge of a cell represents the stored data value, i.e., "1" or "0". The memory array 213 may be Figure 1An example of a memory array 106 is shown in more conceptual form in . The memory array 213 may have any number of rows, such as, for example, 16k, 32k, etc.

[0031] For illustrative purposes, Figure 2 213 are highlighted with cross-hatching. In some examples, rows may also be referred to as word lines. Also, although for clarity purposes, rows are not shown in FIG. Figure 2 Although not shown in FIG. 2 , DRAM device 208 may also be organized into memory bank groups. For example, each rank 210 may be composed of four memory bank groups (not shown), and each of these memory bank groups may be composed of four memory banks. In such an example, DRAM device 208 is therefore composed of 32 distinct (i.e., individually addressable) memory banks 212. Although in FIG. Figure 2 In the example shown in , the DRAM device 208 has two ranks 210, each rank has four memory bank groups, and each of the four memory bank groups has four memory banks 212, but in other examples, such a DRAM may be organized in any other manner including more or fewer ranks, memory banks, memory bank groups, etc. than in the example shown.

[0032] The physical addresses by which the memory controller 206 accesses the DRAM device 208 may include a row address, a column address, a bank group address, and a bank address. Also, although not shown for purposes of clarity, in response to a bank address provided by the memory controller 206 (e.g., a chip select bit included in a read or write command), the bank address decoding logic may select one of the banks 210. Although also not shown for purposes of clarity, in response to a bank address provided by the memory controller 206, the bank address decoding logic may select one of the banks 212 in the selected bank group of the selected bank 210. In response to a row address provided by the memory controller 206, the row address decoder 214 may select a row in the rows of the selected bank 212 of the selected bank group in the selected bank 210. Similarly, in response to a column address provided by the memory controller 206, the column address decoder 216 may select one of the columns of the selected bank 212 of the selected bank group in the selected bank 210. Sequential row addresses may correspond to sequential row physical locations. That is, the row with address X+1 may be physically adjacent to the row with address X, and the row with address X-1 may be physically adjacent to the row with address X. Figure 1 In the depicted example, victim row 112 may have address X, and aggressor rows 108 and 110 may have addresses X+1 and X-1. Sequential row addresses do not necessarily correspond to sequential row physical locations in all DRAMs, but in Figure 1 Such an example is shown in FIG. 1 to more clearly illustrate the hammer principle.

[0033] Each rank 210 may have a read latch 218 for buffering read data, and a write latch 220 for buffering write data. Each rank 210 may also have input / output ("I / O") logic 222 configured to direct read data and write data to and from selected memory locations.

[0034] Each memory bank 212 may have a row buffer 224. The row buffer 224 stores the contents of the selected row. Before a row can be written to or read from, the row must be selected or "opened". In response to an activate ("ACT") command, the DRAM device 208 opens the row, i.e., stores the contents of the row in the row buffer 224. Once the row is opened, the DRAM device 208 can read from or write to any number of columns in the row buffer 224 in response to a read or write command (also known as a column address select ("CAS") command). After the read or write command, data is continuously transferred between the memory controller 206 and the DRAM device 208 in units called "bursts", which can be, for example, eight bits per data signal line. After writing to or reading from the row buffer 224, the row must be restored or "closed". The DRAM device 208 closes the row in response to a precharge ("PRE") command. Storage logic configured to act on the storage array 213, latches 218 and 220, I / O logic 222, etc. in the manner described above in response to row activation, refresh, and other DRAM commands is also included in DRAM device 208, but is not described herein for purposes of clarity. Figure 2 Shown in.

[0035] When converting a read request or a write request, the command generation logic 209 can determine the command required to satisfy the request, and the scheduling and arbitration logic (not shown) can determine the sequence and timing of the command when the command is sent from the memory controller 206 to the DRAM device 208. The command generation logic 209 can also generate refresh commands to perform periodic refresh operations to maintain data integrity. The commands associated with such periodic refresh operations can be referred to as per-bank refresh ("REF" or "Ref") commands. The per-bank refresh command is for a specific or selected bank (rather than all banks).

[0036] A "refresh window" refers to a fixed amount of time ("tREFW") within which all rows of memory bank 212 must receive a refresh operation to maintain data integrity. Within each refresh window, a fixed number of refresh operations (such as, for example, 8192 (i.e., 8K) REF operations) must be performed to refresh all rows of memory bank 212. That is, in such an example, after 8192 REF operations have been performed, all rows in memory bank 212 have been refreshed. A refresh window may be referred to as a sliding window because, although its length tREFW is fixed, a refresh window may occur at any time with respect to other DRAM-related signals.

[0037] As described above, within each refresh window, there may be a threshold number of activations of an aggressor row above which the probability of a bit flip in a victim row is considered unacceptably high. The threshold number of activations may be determined empirically and may vary depending on factors such as the physical distance between adjacent rows, semiconductor process variations, temperature, etc. Similarly, a maximum activation count ("MAC_bank") for a given bank 212 may be determined. MAC_bank is the threshold number of activations of the same row of the same bank above which the probability of a bit flip in a victim row of that bank exceeds the threshold. As long as fewer than MAC_bank+1 same row activations occur within the sliding refresh window (i.e., within tREFW), the probability of a bit flip will not exceed the probability threshold. Conversely, when the (MAC_bank+1)th same row activation occurs within tREFW, the probability of a bit flip will exceed the threshold.

[0038] In addition to the above features of the system 200 that are well understood by those of ordinary skill in the art, a row hammer mitigation feature may be included in the system 200. According to one aspect of the exemplary row hammer mitigation feature, the memory controller 206 may include a row hammer mitigation system 226. According to another aspect of the exemplary row hammer mitigation feature, the DRAM device 208 may include a row hammer threshold logic 228. According to one aspect of the exemplary row hammer mitigation system and method, the row hammer mitigation system 226 of the memory controller 206 may receive a per-bank activation count threshold value, referred to herein as R_threshold, from the row hammer threshold logic 228 of the DRAM device 208. The R_threshold represents a current or dynamic estimate of the number of row activations performed by the DRAM device 208 above which the probability of a bit flip may exceed a probability threshold (although not necessarily the same probability threshold mentioned above). According to another aspect of the exemplary row hammer mitigation system and method, the row hammer mitigation system 226 may count the number of row activation commands and send an additional or mitigation refresh command to the DRAM device 208 when the counted number of row activation commands exceeds the R_threshold.

[0039] In general, the DRAM device 208 may determine R_threshold in any manner. Nevertheless, exemplary methods by which the DRAM device 208 determines or selects R_threshold may be described herein in accordance with other aspects of exemplary row hammer mitigation systems and methods.

[0040] exist Figure 3 , method 300 is shown in the form of a flow chart. As indicated by box 302, method 300 may include: receiving an activation command count threshold value (R_threshold) by a memory controller from a DRAM device. For example, the memory controller may receive the activation command count threshold value in response to polling the DRAM device. In some examples, the activation command count threshold value may be a per-bank activation command count threshold value. As described above, "per bank" refers to only one bank of banks, as opposed to a plurality of banks collectively. It is contemplated that in some examples of the systems and methods described herein, different (per bank) activation command threshold values ​​may be established for different banks.

[0041] As indicated by box 304, method 300 may also include: detecting a row activation command by the memory controller. The row activation command may be a per-bank row activation command, i.e., for a specific bank row in the bank. As indicated by box 306, method 300 may also include: counting the number of row activation commands by the memory controller. The counted number of row activations (which may also be referred to as a row activation command count) may be per bank. That is, each time an activation command for any row in the bank is detected, the row activation command count for that bank may be incremented.

[0042] As indicated by box 308, method 300 may also include: comparing, by the memory controller, the row activation command count with the received activation command count threshold value (R_threshold) for the memory body. As indicated by box 310, method 300 may also include: sending, by the memory controller, a mitigated refresh command to the DRAM device based on the result of comparing the row activation command count with the activation command count threshold value (R_threshold). For example, when the row activation command count is greater than R_threshold, the memory controller may send a mitigated refresh command to the DRAM device. The aforementioned count of the number of row activation commands may be reset in response to the mitigated refresh command.

[0043] exist Figure 4 In FIG. 4 , a row hammer mitigation system 402 is shown in the form of a block diagram. The row hammer mitigation system 402 may be the row hammer mitigation system 226 ( Figure 2 ) example.

[0044] The row hammer mitigation system 402 may include an activate command (ACT) detection logic 404. The activate command detection logic 404 may be configured to monitor a DRAM command flow path 406. The above commands (such as activate and refresh commands) may be transmitted from a memory controller to a DRAM device ( Figure 4 As is understood by those skilled in the art, the command flow path 406 may be generated by the command generation logic 209 ( Figure 2 ) and DRAM devices ( Figure 4 4 and 5. In the embodiment of the present invention, the memory controller 400 and the DRAM device 406 are shown in Figure 4 and any number of other components therebetween (not shown), but for the purpose of clarity, such other components are not shown, and the command flow path 406 is depicted in a conceptual manner. Similarly, a monitoring path 408 is conceptually depicted as a broken line through which the activation command detection logic 404 can monitor the command flow path 406 to indicate that the activation command detection logic 404 does not affect the command flow sent to the DRAM device. The activation command detection logic 404 can be configured to detect a row activation command. Similarly, a portion of a data path 410 through which data can be transmitted between the memory controller and the DRAM device is shown.

[0045] The row hammer mitigation system 402 may also include an activation command count logic 412. The activation command count logic 412 may be configured to increment an activation command count each time the activation command detection logic 404 provides an indication that it has detected an activation command for any row in the memory bank. In some examples, the activation command count logic 412 may be per memory bank and maintain an activation command count for each memory bank.

[0046] The row hammer mitigation system 402 may also include row hammer DRAM interface logic 414. The row hammer DRAM interface logic 414 may be configured to generate polling commands. The polling commands may be generated periodically (i.e., at a polling interval). The polling interval may be an amount of time, and the row hammer DRAM interface logic 414 may include a timer (not shown separately) that triggers continuous operation of the polling command at the polling interval (such as, every P milliseconds (where P is a number)). Alternatively, the polling interval may be a number of command detections (such as an activation command detection), and the row hammer DRAM interface logic 414 may include another activation command counter (i.e., independent of the activation command count logic 412) that triggers the polling command at the polling interval (such as, every P activation commands). The polling command may be transmitted to the command stream path 406 via path 416. The row hammer DRAM interface logic 414 may therefore be configured to poll the DRAM device at such an interval. In some examples, the value of P may be received from a DRAM device and may be adjusted dynamically (ie, during operation of the memory system) by the DRAM device or memory controller based on changes in operating conditions experienced by the DRAM device or memory controller.

[0047] In response to the polling command, the DRAM device may send an activation command count threshold value (R_threshold) to the memory controller. The row hammer DRAM interface logic 414 may receive the activation command count threshold value and store it in the R_threshold register 418. The activation command count threshold value (R_threshold) may be received from the data flow path 410 via the path 420.

[0048] The row hammer mitigation system 402 may include comparison logic 422 and mitigation refresh logic 424. The comparison logic 422 may be configured to receive an activation command count from the activation command count logic 412 and to receive a value of R_threshold from the R_threshold register 418. The comparison logic 422 may be configured to compare the activation command count with the value of R_threshold. The mitigation refresh logic 424 may be configured to send a mitigation refresh command to the DRAM device based on the result of the comparison. For example, the mitigation refresh logic 424 may be configured to send a mitigation refresh command ("RFM") to the DRAM device when the result of the comparison indicates that the count has reached (i.e., has become equal to) the value of R_threshold in the R_threshold register 418. Nevertheless, in other examples, such a mitigation refresh command may be sent before the count has reached the R_threshold.

[0049] The mitigation refresh logic 424 may be configured to provide an indication to the active command count logic 412 each time the mitigation refresh logic 424 sends a mitigation refresh command to the DRAM device. The active command count logic 412 may be configured to reset or initialize the active command count to zero each time the active command detection logic 404 receives an indication from the mitigation refresh logic 424.

[0050] exist Figure 5 , the above-mentioned hammer mitigation system 402 ( Figure 4 ). Example 500 shows a sequence of DRAM commands. Unless otherwise specified, the successive or next DRAM command in example 500 can occur at any amount of time after the previous or preceding DRAM command. Nevertheless, it should be recognized that a row hammer attack typically includes many activation commands that occur in close succession. Figure 5 The activation command ("ACT") shown in FIG. 4 may represent the activation command detection logic 404 ( Figure 4 ) detection. Example 500 may also illustrate the value of R_threshold associated with a command. Example 500 may also illustrate the value of R_threshold associated with a command by activating command counting logic 412 ( Figure 4 ) maintains the value of the activation command count ("ACT count"). The periodic refresh commands are not shown in example 500; rather, it is understood that the DRAM commands shown may occur between two consecutive periodic refresh commands that are not shown for clarity purposes.

[0051] Example 500 begins with four consecutive activation commands 502. In example 500, the consecutive activation commands are received at a fixed rate, and according to the rate, four activation commands may be received during each polling interval. The number four is merely an example, and in other examples where the consecutive activation commands are received at a different fixed rate or at a varying rate, other numbers of activation commands may be received during a polling interval. In example 500, after the four consecutive activation commands 502 (i.e., when the first polling interval elapses), a first polling command 504 is generated. The activation command counting logic 412 ( Figure 4 ) can count the activation commands and send a hammer to the DRAM interface logic 414 every four activation commands ( Figure 4 ) provides a polling indication. In response to the polling indication, the row hammer DRAM interface logic 414 can generate a polling command 504, which can be sent from the memory controller to the DRAM device (as described above).

[0052] In response to the polling command 504, the value of R_threshold may be received from the DRAM device and stored in the R_threshold register 418 ( Figure 4). However, in example 500, the value of R_threshold received from the DRAM device in response to the polling command 504 is a unique identifier (indicated by an "X"). The unique identifier does not represent the value of R_threshold that the DRAM device has determined, but instead represents the DRAM device's determination that it is not necessary to activate the count of commands at this time to mitigate the row hammer attack. Therefore, the response to the polling command can be a valid value of R_threshold or a unique identifier. The row hammer DRAM interface logic 414 ( Figure 4 ) can be configured to detect the unique identifier (i.e., distinguish the unique identifier from a valid value of R_threshold) and, in response, provide an indication to the activation command counting logic 412 to disable counting. In example 500, after receiving a response to the polling command 504, counting remains disabled.

[0053] Example 500 continues with another four consecutive activate commands 506. Then (i.e., when the second polling interval elapses), a second polling command 508 is generated and sent to the DRAM device. In response to the polling command 508, the value of R_threshold can be received from the DRAM device and stored in the R_threshold register 418 ( Figure 4 ). In example 500, the value of R_threshold received from the DRAM device in response to polling command 508 is 6. The value 6 is intended only as an example, and it should be understood that R_threshold can be any value greater than zero. Since a row hammer attack may include many activate commands occurring in close succession, R_threshold can be, for example, on the order of hundreds or thousands or more.

[0054] In response to receiving a valid value for R_THRESHOLD (ie, not a unique identifier), the row hammer DRAM interface logic 414 ( Figure 4 ) can enable the activation command counting logic 412. After being enabled, the activation command counting logic 412 can initialize its activation command count to zero, as described in relation to Figure 5 As shown in the polling command 508.

[0055] Example 500 continues with another four consecutive activation commands 510. Each time the activation command detection logic 404 ( Figure 4 ) detects one of the activation commands 510, the activation command counting logic 412 ( Figure 4 ) increments its activation command count. Then (i.e., when the third polling interval elapses), a third polling command 512 is generated and sent to the DRAM device. In response to the polling command 512, the value of R_threshold may be received from the DRAM device and stored in the R_threshold register 418 ( Figure 4). In example 500, the value of R_threshold received from the DRAM device in response to the polling command 512 is still 6. Note that each time the activation command counting logic 412 increments its activation command count, the comparison logic 422 compares the new (i.e., incremented) activation command count with the value of R_threshold in the R_threshold register 418 (which, in example 500, is 6 at this time). Since the activation command count has not yet reached 6, the activation command counting logic 412 can continue counting in response to other activation commands. After two other activation commands 514, in example 500, the activation command count reaches 6.

[0056] In example 500, comparison logic 422 compares the new activation command count (which is 6 at this time) to the value of R_threshold in R_threshold register 418 (which is also 6 at this time). In response to a determination by comparison logic 422 that the activation command count has reached R_threshold, comparison logic 422 sends a signal to mitigation refresh logic 424 ( Figure 4 ) provides a refresh indication. In response to the refresh indication, the mitigated refresh logic 424 can generate a mitigated refresh ("RFM") command 516, which can be sent from the memory controller to the DRAM device as described above. The activate command detection logic 404 can detect the mitigated refresh command 516 and, in response, reset the activate command count logic 412.

[0057] In example 500, after reset, the command counting logic 412 is activated ( Figure 4 ) is ready to start counting. After two other activate commands 518, the activate command count has reached 2. Also, after two other activate commands 518, the fourth polling interval has elapsed, and therefore, the activate command count logic 412 provides an indication to poll the DRAM device. In response to the polling indication, the row hammer DRAM interface logic 414 ( Figure 4 ) can generate a fourth polling command 520.

[0058] In response to the polling command 520, the value of R_threshold may be received from the DRAM device and stored in the R_threshold register 418 ( Figure 4 In example 500, the value of R_threshold received from the DRAM device in response to the polling command 520 is 3. The row hammer DRAM interface logic 414 ( Figure 4 ) may be configured to send an R_threshold register 418 to the active command counting logic 412 when the value of R_threshold is updated (i.e., the value of R_threshold received from the DRAM device is different from the value of R_threshold then stored in the R_threshold register 418). Figure 4) provides an indication. In example 500, because the value of R_threshold received from the DRAM in response to the polling command 520 is 3, and before the polling command 520, the value of R_threshold in the R_threshold register 418 is 6, the row hammer DRAM interface logic 414 can provide the aforementioned indication to the activation command count logic 412. In response to the indication that the value of R_threshold has been updated, the activation command count logic 412 can reset or initialize the activation count to zero.

[0059] After three other activate commands 522, the activate command count reaches 3, which matches the updated value of R_threshold (ie, the updated value of R_threshold has been reached). Figure 4 ) has reached the R_threshold, mitigating the refresh logic 424 ( Figure 4 ) generates a lighten refresh command 524.

[0060] After another activate command 526, the fifth polling interval has elapsed and, therefore, the activate command counting logic 412 ( Figure 4 ) provides an indication to poll the DRAM device. In response to the polling indication, the row hammer DRAM interface logic 414 ( Figure 4 ) can send a fifth polling command 528 to the DRAM device.

[0061] In the above example 500, when the value of R_threshold is updated (i.e., when the value of R_threshold newly received from the DRAM device is different from the previous value then stored in the R_threshold register 418), the comparison logic 422 immediately begins comparing the activation command count with the new value of R_threshold (rather than the previous value of R_threshold). Instead of using the new value of R_threshold to immediately update the previous value of R_threshold in this manner, the previous value of R_threshold can be retained (i.e., not immediately updated). For example, the difference between the previous value of R_threshold and the then current activation command count can be determined and compared with the new value of R_threshold. If the difference is less than the new value of R_threshold, the previous value of R_threshold can be updated immediately as in example 500. However, if the difference is less than the new value of R_threshold, the previous value of R_threshold can be retained, i.e., continue to be compared with the activation command count.

[0062] Referring to example 500, the difference of 2 between the activation command counts just before the polling command 520 can be subtracted from the previous R_threshold value of 6, resulting in a difference of 4. Because the difference of 4 is not less than the new R_threshold value of 3 (received in response to the polling command 520), the previous value of R_threshold is immediately updated. However, in another example (not shown), if the difference is greater than the new R_threshold value, the previous value of R_threshold will not be immediately updated.

[0063] In response to the polling command 528, a unique identifier is received from the DRAM device. In response to detecting the unique identifier, the row hammer DRAM interface logic 414 ( Figure 4 ) to activate command counting logic 412 ( Figure 4 ) provides an indication to disable counting. In the same manner as described above, after the sixth polling interval has elapsed, the sixth polling command 532 is sent to the DRAM device.

[0064] exist Figure 6 , an exemplary method 600 by which a DRAM device may determine or select R_threshold is shown in flowchart form. As indicated by block 602, method 600 may include: counting, by the DRAM device, a number of row-activate commands per row for each row of the DRAM device.

[0065] As indicated by box 604, method 600 may also include: determining, by the DRAM device, the number of rows in each bucket of a plurality of buckets. The term "bucket" is used herein for the convenience of referring to a collection of storage elements (such as data structures, counters, etc.). The determination (box 604) may include: for each bucket, counting the number of rows for which row activation commands are issued for each number of rows greater than or equal to the corresponding bucket activation count threshold of the bucket. In other words, there are multiple buckets or sets, and each bucket has a unique corresponding bucket activation count threshold (i.e., different from the bucket activation count thresholds of other buckets). Each bucket may also have a unique corresponding bucket R_threshold (i.e., different from the bucket R_thresholds of other buckets). For convenience, the bucket R_threshold may also be referred to as a "bucket threshold." Each bucket maintains a count of the number of rows. When the number of row activation commands for the row is greater than or equal to the bucket activation count threshold of the bucket, the row count may be incremented (conceptually, the row is "added to the bucket"). The following is about Figures 8A-8C An example of using such a bucket is described.

[0066] As indicated by block 606, the method 600 may further include selecting, by the DRAM device (from the subset of buckets containing a non-zero number of rows), a bucket having a maximum bucket activation count threshold. As indicated by block 608, the method 600 may further include selecting, by the DRAM device, a bucket R_threshold of the selected (block 606) bucket. The DRAM device may provide an indication of the selected bucket R_threshold to the memory controller.

[0067] exist Figure 7 In the embodiment of the present invention, a row hammer activation command count threshold logic 702 is shown in the form of a block diagram. The row hammer activation command count threshold logic 702 may be the row hammer threshold logic 228 ( Figure 2 ) example.

[0068] The row hammer active command count threshold logic 702 may include active command detection logic 704. The active command detection logic 704 may be configured to monitor a DRAM command flow path 706 and detect an active command transmitted from a memory controller to a memory logic (not shown) of a DRAM device via the command flow path 706. Also shown is a portion of a data path 710 through which data may be transmitted to and from a memory array of the DRAM device. The active command detection logic 704 may monitor the command flow path 706 via a monitoring path 708.

[0069] The row hammer activate command count threshold logic 702 may also include per-row activate command count logic 712. The per-row activate command count logic 712 may be configured to maintain a separate activate command count for each row in each memory bank and to increment the activate command count for a row each time the activate command detect logic 704 provides an indication that it has detected an activate command for that row.

[0070] The row hammer activation command count threshold logic 702 may also include bucketing logic 714. The bucketing logic 714 may include two or more data storage elements 716 or "buckets", each of which may include a data structure, a counter, etc. The bucketing logic 714 is configured to maintain a row count in each of the data storage elements 716. Each time the activation command count logic 712 increments the activation command count of a row, the bucketing logic 714 may receive the activation command count of the row from the activation command count logic 712. Each bucket or data storage element 716 has associated it with a unique bucket activation command count threshold and a unique bucket R_threshold. When the bucketing logic 714 determines that the activation command count of a row (received from the activation command count logic 712) has reached the bucket activation command count threshold associated with the bucket or data storage element 716, the bucketing logic 714 may increment the row count of the bucket or data storage element 716. Conceptually, the bucketing logic 714 adds the row to the bucket. Conceptually, when other rows reach the bucket activation command count threshold for that bucket, they are added to that bucket. Rows that reach the bucket activation command count thresholds for other buckets are similarly added to those buckets. The row count for each bucket or data storage element 716 thus represents the number of rows with row activation commands for it that are greater than or equal to the number of bucket activation command count thresholds for that bucket or data storage element 716.

[0071] The row hammer activation command count threshold logic 702 may include bucket selection logic 718. At any given time during operation, some of the buckets or data storage elements 716 may have zero row counts (if no row has reached the associated bucket threshold). However, the bucket selection logic 718 may be configured to select the bucket or data storage element 716 having the largest associated bucket activation count threshold from among those buckets or data storage elements 716 having non-zero row counts.

[0072] The bucket selection logic 718 can be configured to store the bucket R_threshold of the selected bucket in the DRAM mode register 720. As understood by those of ordinary skill in the art, the DRAM mode register 720 is a register that a memory controller in a DRAM device can access by sending a certain command to the DRAM device. Such a command is referred to herein as a poll or poll command. The row hammer activation command count threshold logic 702 (or in other examples, another portion of the DRAM device) may include a poll command detection logic 722 configured to detect such a poll command. In response to the detection of the poll command, the contents of the DRAM mode register 720 may be sent to the memory controller via the data path 710.

[0073] In the aforementioned manner, the memory controller may receive the bucket R_threshold of the selected bucket. Figure 4 ) may use the bucket R_threshold received in the manner described above with respect to the activation command count threshold value (R_threshold). Receiving the activation command count threshold value in this manner (i.e., in response to the polling command) may be a step of method 300 ( Figure 3 ) of the above block 302. Figure 4 As described, receiving the activate command count threshold in response to the polling command can occur at intervals. It can be appreciated that because the DRAM device can dynamically (i.e., during operation of the memory system) adjust the activate command count threshold, the row hammer mitigation system and method described herein can advantageously respond to changing operating conditions experienced by the DRAM device.

[0074] The row hammer activation command count threshold logic 702 may also include an aggressor row address buffer 724, an aggressor row activation command count buffer 726, and a refresh command line selection logic 728. The aggressor row address buffer 724 and the aggressor row activation command count buffer 726 may be configured together to keep track of the row experiencing the most activations (i.e., the aggressor row).

[0075] The aggressor row address buffer 724 and the aggressor row activation command count buffer 726 may receive an activation command count from the activation command count logic 712. Each time the activation command count logic 712 increments the activation command count for a row, the activation command count logic 712 may provide an indication of the identification row (e.g., row number) to the aggressor row address buffer 724, and an indication of the (then incremented) activation command count for the row to the aggressor row activation command count buffer 726. The aggressor row activation command count buffer 726 may be configured to hold or store a value indicating a maximum row activation command count. Each time the aggressor row activation command count buffer 726 receives an activation command count for a row from the activation command count logic 712, the aggressor row activation command count buffer 726 may compare the received activation command count with a stored value indicating the maximum row activation command count. If the received activation command count is greater than or equal to the stored value indicating the maximum row activation command count, the aggressor row activation command count buffer 726 may replace the stored value indicating the maximum row activation command count with the received activation command count. Thus, the received activation command count becomes the stored (new) value indicating the maximum row activation command count. Furthermore, each time the aggressor row activation command count buffer 726 replaces its stored value, the aggressor row address buffer 724 may store an associated indication (e.g., a row number) identifying the row. In this manner, the aggressor row address buffer 724 holds or stores a value indicating the row determined to have the maximum activation command count, while the aggressor row activation command count buffer 726 holds or stores a value indicating the activation command count for the row.

[0076] The row hammer activation command count threshold logic 702 may also include refresh command detection logic 713 configured to monitor the command flow path 706 and detect the above-mentioned mitigated refresh command transmitted from the memory controller to the storage logic (not shown) of the DRAM device via the command flow path 706. The refresh command detection logic 713 may be configured to distinguish a mitigated refresh command (RFM) from other (e.g., periodically scheduled or "REF") refresh commands and provide an indication of the detection of the mitigated refresh command to the refresh command line selection logic 728.

[0077] The refresh command line selection logic 728 may be configured to select a victim row for which the detected mitigated refresh command is to be directed. When the refresh command line selection logic 728 receives an indication of the detection of a mitigated refresh command, the refresh command line selection logic 728 may obtain a value indicating a row determined to have the maximum row activation command count from the victim row address buffer 724. The row determined to have the maximum row activation command count when the mitigated refresh command is detected may be referred to as an aggressor row. The refresh command line selection logic 728 may then determine which one or more rows may be physically adjacent to the aggressor row. One or more rows determined to be physically adjacent to the aggressor row may be referred to as victim rows corresponding to the aggressor row. For example, if row X is determined to have the maximum row activation command count, i.e., X is an aggressor row, the refresh command line selection logic 728 may determine that rows X-1 and X+1 are corresponding victim rows. The refresh command line selection logic 728 may then direct the mitigated refresh command to the one or more corresponding victim rows.

[0078] Refresh command line selection logic 728 may send an indication to activate command count logic 712 indicating that refresh command line selection logic 728 has caused a mitigation refresh command to target one or more victim rows. In response to the indication, activate command count logic 712 may be configured to reset or initialize the activate command count of the aggressor row to zero.

[0079] The refresh command detection logic 713 may be additionally configured to detect a type of refresh command other than a mitigated refresh command transmitted from the memory controller to the storage logic of the DRAM device via the command flow path 706 (such as a periodically scheduled refresh command), and provide an indication of such detection to the refresh command line selection logic 728. The refresh command line selection logic 728 may be configured to select a victim row to which such other type of detected mitigated refresh command is to be directed. The refresh command line selection logic 728 may respond differently to the detection of a mitigated refresh command and the detection of other types of refresh commands. Additional buffers similar to the buffers 724 and 726 described above may be provided to identify multiple victim rows, and the refresh command line selection logic 728 may cause different numbers of refresh operations to be directed to different numbers of victim rows based on the type of refresh command detected. For example, in response to the detection of a periodically scheduled refresh command, the refresh command line selection logic 728 may cause only a single refresh operation to be directed to a single victim row, while in response to the detection of a mitigated refresh command, the refresh command line selection logic 728 may cause multiple refresh operations to be directed to multiple victim rows.

[0080] exist Fig. 8A , 8B8C, corresponding tables 802, 804, and 806, which may be implemented as, for example, data structures, are shown. Tables 802-806 may be implemented by the bucketization logic 714 and bucket selection logic 718 ( Figure 7 ) is used. The rows of tables 802-806 represent the following data storage elements or "buckets": an unusable or reference bucket having a bucket activation command count threshold of zero and a bucket R_threshold that is not applicable ("N / A") or empty; a first bucket having a bucket activation command count threshold of 100 and a bucket R_threshold of 300; a second bucket having a bucket activation command count threshold of 250 and a bucket R_threshold of 200; and a third bucket having a bucket activation command count threshold of 500 and a bucket R_threshold of 100. Although in tables 802-806, there are three usable buckets, in other examples, there may be any number of buckets. Moreover, the bucket activation command count thresholds of 100, 250, and 500 and the bucket R_thresholds of 300, 200, and 100 are intended only as examples and may have any values. The following is an example of operations using tables 802-806.

[0081] exist Fig. 8A , table 802 shows an initial operating state in which the unusable buckets have a row count of 65536, meaning that initially, all 65536 rows (e.g., all rows in the exemplary DRAM array) have zero or more activation commands for each of them. Table 802 also shows that in the initial operating state, the first bucket has a row count of zero, meaning that initially, zero rows of the DRAM array have 100 or more activation commands for each of them. Table 802 also shows that in the initial operating state, the second bucket has a row count of zero, meaning that initially, zero rows of the DRAM array have 250 or more activation commands for each of them. Table 802 also shows that in the initial operating state, the third bucket has a row count of zero, meaning that initially, zero rows of the DRAM array have 500 or more activation commands for each of them. In the initial operating state shown in table 802, no bucket is selected because none of the usable buckets (i.e., the first, second, or third buckets) has a non-zero row count. Thus, as described above, in response to polling, a unique identifier may be returned to the memory controller.

[0082] exist Figure 8B , table 804 shows a later operating state (i.e., later in time than Fig. 8A), where the unusable buckets have a row count of 65536, meaning that all 65536 rows have had zero or more activation commands for each of them. Table 804 also shows that in this later operating state, the first bucket has a row count of 6224, meaning that 6224 rows of the DRAM array have had 100 or more activation commands for each of them. Table 804 also shows that in this later operating state, the second bucket has a row count of zero, meaning that zero rows of the DRAM array have had 250 or more activation commands for each of them. Table 804 also shows that in this later operating state, the third bucket has a row count of zero, meaning that zero rows of the DRAM array have had 500 or more activation commands for each of them. In the operating state shown by Table 804, the first bucket can be selected because, among all the buckets with non-zero row counts, the first bucket has the maximum bucket activation command count threshold (100). Thus, as described above, in response to the polling, a bucket R_threshold of 300 associated with the first bucket may be returned to the memory controller.

[0083] exist Figure 8C , table 806 shows a later operating state (i.e., later in time than Figure 8B ), where the unusable bucket has a row count of 65536, meaning that all 65536 rows have had zero or more activation commands for each of them. Table 806 also shows that in this later operating state, the first bucket has a row count of 6224, meaning that the 6224 rows of the DRAM array have had 100 or more activation commands for each of them. Table 806 also shows that in this later operating state, the second bucket has a row count of 554, meaning that the 554 rows of the DRAM array have had 250 or more activation commands for each of them. Table 806 also shows that in this later operating state, the third bucket has a row count of 29, meaning that the 29 rows of the DRAM array have had 500 or more activation commands for each of them. In the operating state shown by Table 806, the third bucket can be selected because, among all the buckets with non-zero row counts, the third bucket has the maximum bucket activation command count threshold (500). Thus, as described above, in response to the polling, a bucket R_threshold of 100 associated with the third bucket may be returned to the memory controller.

[0084] The above-described systems and methods can reduce or mitigate the adverse effects of a row hammer attack. Additional features can be included to adjust the response of the system and method to conditions indicative of a row hammer attack. Such features can reduce "false positive" responses, where the system or method is too sensitive to conditions generally indicative of a row hammer attack, or where the system or method responds too aggressively, potentially resulting in the introduction of a number of mitigation refreshes large enough to affect memory system performance.

[0085] Features that can reduce false positive responses can change or adjust the rate at which the memory controller polls the DRAM system. The memory controller can adjust the polling rate or interval in response to one or more operating conditions in the memory controller, such as, for example, the operating frequency of the memory controller, a measurement of memory bus activity, etc. Features can also be included in which a new polling rate is provided to the memory controller by the DRAM device. For example, in response to being polled by the memory controller, the DRAM device can provide not only a new activate command count threshold value (R_threshold), but also a new polling rate.

[0086] Another feature that can reduce false positive responses can be that in addition to the bucket selection logic 714 selecting the bucket with the largest bucket activation command count threshold from among the subset of buckets with non-zero row counts (i.e., "containing" more than zero rows), the bucket selection logic 714 can select the bucket with the largest bucket activation command count threshold from among the subset of buckets with row counts greater than or equal to an "activation count limit" or threshold L (i.e., "containing" more than L rows), where L is greater than zero. For example, referring to Figures 8A-8C , the first bucket may have an activation count limit L of 5, the second bucket may have an activation count limit L of 3, and the third bucket may have an activation count limit L of 3. In such an example, the bucket selection logic 714 may not select the first bucket unless the row count of the first bucket is greater than or equal to 5, may not select the second bucket unless the row count of the second bucket is greater than or equal to 3, and may not select the third bucket unless the row count of the third bucket is greater than or equal to 3.

[0087] Fig. 9 An example of a portable computing device ("PCD") 900 is shown in which exemplary embodiments of systems, methods, and other examples of hammer mitigation solutions may be provided. The PCD 900 may be, for example, a laptop or palmtop computer, a cellular or smartphone, a personal digital assistant, a navigation device, a smartbook, a portable game console, a satellite phone, etc. For purposes of clarity, some data buses, interconnects, signals, etc. are not shown. Fig. 9. PCD 900 is only one example of a computing device in which a row hammer mitigation solution may be provided. The row hammer mitigation solution may be provided in any type of computing device having a DRAM memory system, such as a desktop computer, a workstation, a data center computing system, an Internet of Things device, etc.

[0088] PCD 900 may include SoC 902. SoC 902 may include a central processing unit ("CPU") 904, a graphics processing unit ("GPU") 906, a digital signal processor ("DSP") 907, an analog signal processor 908, a modem / modem subsystem 954, or other processors. CPU 904 may include one or more CPU cores, such as a first CPU core 904A, a second CPU core 904B, and so on, to an Nth CPU core 904N. CPU 904 or a portion thereof may be the client device 102 ( Figure 1 ) or 202( Figure 2 ) example.

[0089] The display controller 910 and the touch screen controller 912 can be coupled to the CPU 904. A touch screen display 914 external to the SoC 902 can be coupled to the display controller 910 and the touch screen controller 912. The PCD 900 can also include a video decoder 916 coupled to the CPU 904. A video amplifier 918 can be coupled to the video decoder 916 and the touch screen display 914. A video port 920 can be coupled to the video amplifier 918. A universal serial bus (“USB”) controller 922 can also be coupled to the CPU 904, and a USB port 924 can be coupled to the USB controller 922. A subscriber identity module (“SIM”) card 926 can also be coupled to the CPU 904.

[0090] One or more memories may be coupled to the CPU 904. The one or more memories may include both volatile and non-volatile memory. Examples of volatile memory include static random access memory ("SRAM") 928 and dynamic random access memory ("DRAM") 930 and 931. Such memory may be external to the SoC 902 (such as DRAM 930), or external to the SoC 902 (such as DRAM 931). A DRAM controller 932 coupled to the CPU 904 may control the writing of data to the DRAMs 930 and 931 and the reading of data from the DRAMs 930 and 931.

[0091] DRAM controller 932 may be an example of any of the memory controllers described above. Thus, DRAM controller 932 may include the above-described row hammer mitigation system 226 ( Figure 1) or 402( Figure 4 ). DRAM controller 932 may be configured to execute or control the above method 300 ( Figure 3 ). DRAM 930 or 931 may have a configuration similar to that of DRAM device 208 ( Figure 2 ) structure. DRAM 930 or 931 may include the above-mentioned row hammer threshold logic 228 ( Figure 2 ) or 702( Figure 2 ). DRAM controller 930 or 931 may be configured to execute or control the above method 600 ( Figure 6 ).

[0092] A stereo audio CODEC 934 may be coupled to the analog signal processor 908. In addition, an audio amplifier 936 may be coupled to the stereo audio CODEC 934. First and second stereo speakers 938 and 940 may be coupled to the audio amplifier 936, respectively. In addition, a microphone amplifier 942 may be coupled to the stereo audio CODEC 934, and a microphone 944 may be coupled to the microphone amplifier 942. A frequency modulation ("FM") radio tuner 946 may be coupled to the stereo audio CODEC 934. An FM antenna 948 may be coupled to the FM radio tuner 946. In addition, stereo headphones 950 may be coupled to the stereo audio CODEC 934. Other devices that may be coupled to the CPU 904 include one or more digital (e.g., CCD or CMOS) cameras 952.

[0093] A modem or RF transceiver 954 can be coupled to the analog signal processor 908 and the CPU 904. An RF switch 956 can be coupled to the RF transceiver 954 and the RF antenna 958. Additionally, a keypad 960, a mono headset 962 with a microphone, and a vibrator device 964 can be coupled to the analog signal processor 908.

[0094] SoC 902 may have one or more internal or on-chip thermal sensors 970A and may be coupled to one or more external or off-chip thermal sensors 970B. An analog-to-digital converter controller 972 may convert the voltage drops generated by thermal sensors 970A and 970B into digital signals. A power supply 974 and a power management integrated circuit (“PMIC”) 976 may supply power to SoC 902.

[0095] The firmware or software may be stored in any of the above-mentioned memories, such as DRAM 930 or 931, SRAM 928, etc., or may be stored in local memory directly accessible by the processor hardware, and the software or firmware may be executed on the processor hardware. The execution of such firmware or software may control aspects of any of the above-mentioned methods or configure aspects of any of the above-mentioned systems. Any such memory or other non-transitory storage medium having firmware or software stored therein in a computer-readable form for execution by the processor hardware may be an example of a "computer-readable medium", as that term is understood in the patent dictionary.

[0096] Implementation examples are described in the following numbered clauses.

[0097] 1. A method comprising:

[0098] receiving, by a memory controller, an activation count threshold value from a dynamic random access memory (DRAM) device;

[0099] detecting, by the memory controller, a row activation command for a memory bank of the DRAM device;

[0100] counting, by the memory controller, a number of the row activation commands;

[0101] comparing, by the memory controller, the number of row activate commands to the activate count threshold; and

[0102] A mitigate refresh command is sent by the memory controller to the DRAM device based on a result of comparing the number of row activate commands with the activate count threshold value.

[0103] 2. The method of clause 1, wherein receiving the activation count threshold value comprises: polling the DRAM device at a polling interval.

[0104] 3. The method of clause 2, further comprising: receiving, by the memory controller, an indication of the polling interval from the DRAM device.

[0105] 4. The method of clause 2 or 3, further comprising: adjusting, by the memory controller, the polling interval based on one or more operating conditions of the memory controller.

[0106] 5. A method according to any one of clauses 1-4, wherein receiving an activation count threshold value from the DRAM device comprises: receiving a plurality of per-memory-bank activation count threshold values, each per-memory-bank activation count threshold value corresponding to a memory bank among a plurality of memory banks of the DRAM device.

[0107] 6. The method according to any one of clauses 1 to 5, further comprising:

[0108] counting, by the DRAM device, a number of each row of the row activation commands for each row of the DRAM device;

[0109] Determining, by the DRAM device, a number of rows in each of a plurality of buckets, comprising: for each bucket, counting a number of rows for which row activation commands have a number of rows greater than or equal to a corresponding bucket activation count threshold for the bucket, wherein each bucket has a corresponding bucket activation count threshold different from all other buckets and a corresponding bucket threshold different from all other buckets;

[0110] selecting, by the DRAM device, one of the buckets having a maximum bucket activation count threshold from among the subset of the buckets having a non-zero number of rows therein; and

[0111] The bucket threshold of a selected one of the buckets is selected by the DRAM device.

[0112] 7. A method according to clause 6, wherein:

[0113] Each bucket has a corresponding activation count limit; and

[0114] Wherein each bucket in the subset of buckets has a number of rows greater than or equal to the corresponding activation count limit.

[0115] 8. The method according to clause 6 or 7, further comprising:

[0116] determining, by the DRAM device in response to a mitigated refresh command received from the memory controller, a row having a maximum per-row number of row activate commands directed thereto; and

[0117] The rows determined to have the maximum per-row number of row activate commands directed thereto are refreshed by the DRAM device.

[0118] 9. A system comprising:

[0119] interface logic in a memory controller, the interface logic configured to receive an activation count threshold value from a dynamic random access memory (DRAM) device;

[0120] an activate command detection logic in the memory controller, the activate command detection logic being configured to detect a row activate command for a bank of the DRAM device;

[0121] an activate command counting logic in the memory controller, the activate command counting logic being configured to count a number of the row activate commands;

[0122] comparison logic in the memory controller, the comparison logic configured to compare the number of row activate commands to the activate count threshold value; and

[0123] A mitigation refresh logic in the memory controller is configured to send a mitigation refresh command to the DRAM device based on a result of comparing the number of row activate commands to the activate count threshold value.

[0124] 10. The system of clause 9, wherein the interface logic is configured to poll the DRAM device for the per-bank activate count threshold at a polling interval.

[0125] 11. The system of clause 10, wherein the interface logic is further configured to receive an indication of the polling interval from the DRAM device.

[0126] 12. The system of clause 9 or 10, wherein the interface logic is further configured to adjust the polling interval based on one or more operating conditions of the memory controller.

[0127] 13. A system according to any one of clauses 9-12, wherein the interface logic is configured to receive multiple per-memory bank activation count threshold values ​​from the DRAM device, each per-memory bank activation count threshold value corresponding to a memory bank among multiple memory banks of the DRAM device.

[0128] 14. A system according to any one of clauses 9 to 13, further comprising:

[0129] a per-row activation command counting logic in the DRAM device, the per-row activation command counting logic being configured to count a per-row number of the row activation commands for each row of the DRAM device;

[0130] Bucketization logic in the DRAM device, the bucketization logic configured to determine a number of rows in each of a plurality of buckets, comprising: for each bucket, counting a number of rows for which row activation commands have a number of rows greater than or equal to a corresponding bucket activation count threshold for the bucket, wherein each bucket has a corresponding bucket activation count threshold different from all other buckets and a corresponding bucket threshold different from all other buckets; and

[0131] Bucket selection logic in the DRAM device, the bucket selection logic being configured to select one of the buckets having a maximum bucket activation count threshold from a subset of the buckets having a non-zero number of rows therein, and the bucket selection logic being further configured to select the bucket threshold of the selected bucket of the buckets.

[0132] 15. A system according to clause 14, wherein:

[0133] Each bucket has a corresponding activation count limit; and

[0134] Wherein each bucket in the subset of buckets has a number of rows greater than or equal to the corresponding activation count limit.

[0135] 16. A system according to clause 14 or 15, further comprising:

[0136] buffer logic configured to provide an indication of a row having a maximum per-row number of row activate commands directed thereto; and

[0137] A refresh command line selection logic is configured to determine the row having the largest number of row activation commands per row for it in response to a mitigated refresh command received from the memory controller, and refresh the row determined to have the largest number of row activation commands per row for it.

[0138] 17. A system comprising:

[0139] means for receiving an activation count threshold value from a dynamic random access memory (DRAM) device;

[0140] a unit for detecting a row activation command for a memory bank of the DRAM device;

[0141] a unit for counting the number of said row activation commands;

[0142] means for comparing said number of row activate commands to said activation count threshold value; and

[0143] means for sending a mitigated refresh command to the DRAM device based on a result of comparing the number of row activate commands to the activate count threshold value.

[0144] 18. The system of clause 17, wherein the means for receiving the activation count threshold value comprises means for polling the DRAM device at a polling interval.

[0145] 19. The system of clause 18, further comprising means for receiving an indication of the polling interval.

[0146] 20. The system according to clause 18 or 19, further comprising: means for adjusting the polling interval.

[0147] 21. A system according to any one of clauses 17-20, wherein the unit for receiving an activation count threshold value from the DRAM device includes: a unit for receiving a plurality of per-memory body activation count threshold values, each per-memory body activation count threshold value corresponding to a memory body among a plurality of memory bodies of the DRAM device.

[0148] 22. A system according to any one of clauses 17-21, further comprising:

[0149] a unit for counting a number per row of the row activation commands for each row of the DRAM device;

[0150] Means for determining a number of rows in each of a plurality of buckets, comprising: for each bucket, counting a number of rows having row activation commands for it having a number of rows greater than or equal to a corresponding bucket activation count threshold for the bucket, wherein each bucket has a corresponding bucket activation count threshold different from all other buckets and a corresponding bucket threshold different from all other buckets;

[0151] means for selecting one of said buckets having a maximum bucket activation count threshold from among the subset of said buckets having a non-zero number of rows therein; and

[0152] Means for selecting the bucket threshold corresponding to a selected one of the buckets.

[0153] 23. A system according to clause 22, wherein:

[0154] Each bucket has a corresponding activation count limit; and

[0155] Wherein each bucket in the subset of buckets has a number of rows greater than or equal to the corresponding activation count limit.

[0156] 24. A system according to clause 22 or 23, further comprising:

[0157] A unit for determining a row having a maximum number of row activation commands per row for it in response to a mitigated refresh command; and a unit for refreshing the row determined to have the maximum number of row activation commands per row for it.

[0158] 25. A memory controller comprising:

[0159] command generation logic configured to generate dynamic random access memory (DRAM) commands in response to a memory transaction request, the DRAM commands including a row activate command and a refresh command;

[0160] an interface logic configured to receive an activation count threshold value from a DRAM device;

[0161] an activate command detection logic configured to detect a row activate command for a memory bank of the DRAM device;

[0162] an activation command counting logic configured to count the number of the row activation commands;

[0163] comparison logic configured to compare the number of row activate commands to the activate count threshold value; and

[0164] A mitigated refresh logic is configured to send a mitigated refresh command to the DRAM device based on a result of comparing the number of row activate commands with the activate count threshold value.

[0165] 26. The memory controller of clause 25, wherein the interface logic is configured to poll the DRAM device for the per-bank activate count threshold value at a polling interval.

[0166] 27. The memory controller of clause 26, wherein the interface logic is further configured to receive an indication of the polling interval from the DRAM device.

[0167] 28. The memory controller of clause 26 or 27, wherein the interface logic is further configured to adjust the polling interval based on one or more operating conditions of the memory controller.

[0168] 29. A memory controller according to any one of clauses 25-28, wherein the interface logic is configured to receive a plurality of per-bank activation count threshold values ​​from the DRAM device, each per-bank activation count threshold value corresponding to a bank among a plurality of banks of the DRAM device.

[0169] 30. A dynamic random access memory (DRAM) device comprising:

[0170] at least one data storage array comprising a plurality of rows;

[0171] a per-row activation command counting logic configured to count a per-row number of the row activation commands for each row of the DRAM device;

[0172] Bucketization logic configured to determine a number of rows in each of a plurality of buckets, comprising: for each bucket, counting a number of rows having row activation commands for each number of rows greater than or equal to a corresponding bucket activation count threshold for the bucket, wherein each bucket has a corresponding bucket activation count threshold different from all other buckets and a corresponding bucket threshold different from all other buckets; and

[0173] Bucket selection logic configured to select one of the buckets having a maximum bucket threshold from among a subset of the buckets having a non-zero number of rows therein, the bucket selection logic further configured to select the bucket threshold of the selected one of the buckets and provide an indication of the selected bucket threshold to a memory controller.

[0174] 31. A DRAM device according to clause 30, wherein:

[0175] Each bucket has a corresponding activation count limit; and

[0176] Wherein each bucket in the subset of buckets has a number of rows greater than or equal to the corresponding activation count limit.

[0177] 32. A DRAM device according to clause 30 or 31, further comprising:

[0178] buffer logic configured to provide an indication of a row having a maximum per-row number of row activate commands directed thereto; and

[0179] A refresh command line selection logic is configured to determine the row having the largest number of row activation commands per row for it in response to a mitigated refresh command received from the memory controller, and refresh the row determined to have the largest number of row activation commands per row for it.

[0180] Alternative embodiments will be apparent to those of ordinary skill in the art to which the invention relates.Thus, while selected aspects have been shown and described in detail, it will be appreciated that various substitutions and modifications may be made herein.

Claims

1. A method comprising: receiving, by a memory controller, an activation count threshold value from a dynamic random access memory (DRAM) device; detecting, by the memory controller, a row activation command for a memory bank of the DRAM device; counting, by the memory controller, a number of the row activation commands; comparing, by the memory controller, the number of row activate commands with the activate count threshold value; as well as A mitigate refresh command is sent by the memory controller to the DRAM device based on a result of comparing the number of row activate commands with the activate count threshold value.

2. The method according to claim 1, wherein: Receiving the activation count threshold value includes polling the DRAM device at a polling interval.

3. The method according to claim 2, further comprising: An indication of the polling interval is received by the memory controller from the DRAM device.

4. The method according to claim 2, further comprising: The polling interval is adjusted by the memory controller based on one or more operating conditions of the memory controller.

5. The method according to claim 1, wherein: Receiving an activation count threshold value from the DRAM device includes receiving a plurality of per-bank activation count threshold values, each per-bank activation count threshold value corresponding to a bank among a plurality of banks of the DRAM device.

6. The method according to claim 1, further comprising: counting, by the DRAM device, a number of each row of the row activation commands for each row of the DRAM device; Determining, by the DRAM device, a number of rows in each of a plurality of buckets, comprising: for each bucket, counting a number of rows for which row activation commands have a number of rows greater than or equal to a corresponding bucket activation count threshold for the bucket, wherein each bucket has a corresponding bucket activation count threshold different from all other buckets and a corresponding bucket threshold different from all other buckets; selecting, by the DRAM device, one of the buckets having a maximum bucket activation count threshold from among the subset of the buckets having a non-zero number of rows therein; and The bucket threshold of a selected one of the buckets is selected by the DRAM device.

7. The method according to claim 6, wherein: Each bucket has a corresponding activation count limit; and Wherein each bucket in the subset of buckets has a number of rows greater than or equal to the corresponding activation count limit.

8. The method according to claim 6, further comprising: determining, by the DRAM in response to a mitigated refresh command received from the memory controller, a row having a maximum per-row number of row activate commands directed thereto; as well as The rows determined to have the maximum per-row number of row activate commands directed thereto are refreshed by the DRAM.

9. A system comprising: interface logic in a memory controller, the interface logic configured to receive an activation count threshold value from a dynamic random access memory (DRAM) device; an activate command detection logic in the memory controller, the activate command detection logic being configured to detect a row activate command for a bank of the DRAM device; an activate command counting logic in the memory controller, the activate command counting logic being configured to count a number of the row activate commands; comparison logic in the memory controller, the comparison logic configured to compare the number of row activate commands to the activate count threshold value; as well as A mitigation refresh logic in the memory controller is configured to send a mitigation refresh command to the DRAM device based on a result of comparing the number of row activate commands to the activate count threshold value.

10. The system according to claim 9, wherein: The interface logic is configured to poll the DRAM device for the per-bank activate count threshold value at a polling interval.

11. The system according to claim 10, wherein: The interface logic is further configured to receive an indication of the polling interval from the DRAM device.

12. The system according to claim 10, wherein: The interface logic is further configured to adjust the polling interval based on one or more operating conditions of the memory controller.

13. The system according to claim 9, wherein: The interface logic is configured to receive a plurality of per-bank activate count threshold values ​​from the DRAM device, each per-bank activate count threshold value corresponding to a bank among a plurality of banks of the DRAM device.

14. The system of claim 9, further comprising: a per-row activation command counting logic in the DRAM device, the per-row activation command counting logic being configured to count a per-row number of the row activation commands for each row of the DRAM device; Bucketization logic in the DRAM device, the bucketization logic configured to determine a number of rows in each of a plurality of buckets, comprising: for each bucket, counting a number of rows for which row activation commands have a number of rows greater than or equal to a corresponding bucket activation count threshold for the bucket, wherein each bucket has a corresponding bucket activation count threshold different from all other buckets and a corresponding bucket threshold different from all other buckets; and Bucket selection logic in the DRAM device, the bucket selection logic being configured to select one of the buckets having a maximum bucket activation count threshold from a subset of the buckets having a non-zero number of rows therein, and the bucket selection logic being further configured to select the bucket threshold of the selected bucket of the buckets.

15. The system of claim 14, wherein: Each bucket has a corresponding activation count limit; and Wherein each bucket in the subset of buckets has a number of rows greater than or equal to the corresponding activation count limit.

16. The system of claim 14, further comprising: buffer logic configured to provide an indication of a row having a maximum per-row number of row activate commands directed thereto; as well as A refresh command line selection logic is configured to determine the row having the largest number of row activation commands per row for it in response to a mitigated refresh command received from the memory controller, and refresh the row determined to have the largest number of row activation commands per row for it.

17. A system comprising: means for receiving an activation count threshold value from a dynamic random access memory (DRAM) device; a unit for detecting a row activation command for a memory bank of the DRAM device; a unit for counting the number of said row activation commands; means for comparing said number of row activate commands to said activation count threshold value; as well as means for sending a mitigated refresh command to the DRAM device based on a result of comparing the number of row activate commands to the activate count threshold value.

18. The system of claim 17, wherein: The means for receiving the activation count threshold value includes means for polling the DRAM device at a polling interval.

19. The system of claim 18, further comprising: Means for receiving an indication of the polling interval.

20. The system of claim 18, further comprising: Unit for adjusting the polling interval.

21. The system of claim 17, wherein: The unit for receiving an activation count threshold value from the DRAM device includes: a unit for receiving a plurality of per-bank activation count threshold values, each per-bank activation count threshold value corresponding to one of a plurality of banks of the DRAM device.

22. The system of claim 17, further comprising: a unit for counting a number per row of the row activation commands for each row of the DRAM device; Means for determining a number of rows in each of a plurality of buckets, comprising: for each bucket, counting a number of rows having row activation commands for it having a number of rows greater than or equal to a corresponding bucket activation count threshold for the bucket, wherein each bucket has a corresponding bucket activation count threshold different from all other buckets and a corresponding bucket threshold different from all other buckets; means for selecting one of said buckets having a maximum bucket activation count threshold from among the subset of said buckets having a non-zero number of rows therein; and Means for selecting the bucket threshold corresponding to a selected one of the buckets.

23. The system of claim 22, wherein: Each bucket has a corresponding activation count limit; and Wherein each bucket in the subset of buckets has a number of rows greater than or equal to the corresponding activation count limit.

24. The system of claim 22, further comprising: means for determining a row having a maximum per-row number of row activate commands directed thereto in response to a mitigated refresh command; as well as for refreshing cells of the row determined to have the maximum per-row number of row activate commands directed thereto.

25. A memory controller comprising: command generation logic configured to generate dynamic random access memory (DRAM) commands in response to a memory transaction request, the DRAM commands including a row activate command and a refresh command; an interface logic configured to receive an activation count threshold value from a DRAM device; an activate command detection logic configured to detect a row activate command for a memory bank of the DRAM device; an activation command counting logic configured to count the number of the row activation commands; comparison logic configured to compare the number of row activate commands to the activation count threshold value; as well as A mitigated refresh logic is configured to send a mitigated refresh command to the DRAM device based on a result of comparing the number of row activate commands with the activate count threshold value.

26. The memory controller of claim 25, wherein: The interface logic is configured to poll the DRAM device for the per-bank activate count threshold value at a polling interval.

27. The memory controller of claim 26, wherein: The interface logic is further configured to receive an indication of the polling interval from the DRAM device.

28. The memory controller of claim 26, wherein: The interface logic is further configured to adjust the polling interval based on one or more operating conditions of the memory controller.

29. The memory controller of claim 25, wherein: The interface logic is configured to receive a plurality of per-bank activate count threshold values ​​from the DRAM device, each per-bank activate count threshold value corresponding to a bank among a plurality of banks of the DRAM device.

30. A dynamic random access memory (DRAM) device comprising: at least one data storage array comprising a plurality of rows; a per-row activation command counting logic configured to count a per-row number of the row activation commands for each row of the DRAM device; Bucketization logic configured to determine a number of rows in each of a plurality of buckets, comprising: for each bucket, counting a number of rows having row activation commands for each number of rows greater than or equal to a corresponding bucket activation count threshold for the bucket, wherein each bucket has a corresponding bucket activation count threshold different from all other buckets and a corresponding bucket threshold different from all other buckets; and Bucket selection logic configured to select one of the buckets having a maximum bucket threshold from among a subset of the buckets having a non-zero number of rows therein, the bucket selection logic further configured to select the bucket threshold of the selected one of the buckets and provide an indication of the selected bucket threshold to a memory controller.

31. The DRAM device of claim 30, wherein: Each bucket has a corresponding activation count limit; and Wherein each bucket in the subset of buckets has a number of rows greater than or equal to the corresponding activation count limit.

32. The DRAM device of claim 30, further comprising: buffer logic configured to provide an indication of a row having a maximum per-row number of row activate commands directed thereto; as well as A refresh command line selection logic is configured to determine the row having the largest number of row activation commands per row for it in response to a mitigated refresh command received from the memory controller, and refresh the row determined to have the largest number of row activation commands per row for it.

Images