Row hammer mitigation for stacked memory architecture

Abstract

Methods, systems, and apparatus are described for row hammer mitigation for stacked memory architectures. A semiconductor system, such as a memory system, may distribute hammer mitigation operations across circuitry of the semiconductor system. A first interface block of a first die of the semiconductor system may exchange signaling with a second interface block of a second die of the semiconductor system to perform a row hammer mitigation operation. The second die may implement a counter to track a number of access operations associated with respective rows of memory cells of the second die. The second interface block may transmit alert signaling to the first interface block based on a value of a counter, and the first interface block may evaluate the alert signaling and transmit refresh signaling to the second interface block to perform one or more refresh operations.

Description

[0001] Cross Reference

[0002] This patent application claims priority to U.S. patent application No. 18 / 763,963, filed by Eckel et al. on July 3, 2024, entitled “ROW HAMMER MITIGATION FOR STACKED MEMORY ARCHITECTURES,” and U.S. Provisional Patent Application No. 63 / 517,849, filed by Eckel et al. on August 4, 2023, entitled “ROW HAMMER MITIGATION FOR STACKED MEMORY ARCHITECTURES,” each of which is assigned to its assignee and the entire contents of each of which are expressly incorporated herein by reference. Technical Field

[0003] The following relates to one or more systems for memory, including row hammer mitigation for stacked memory architectures. Background Art

[0004] Memory devices are widely used to store information in devices such as computers, user devices, wireless communication devices, cameras, digital displays, and others. Information is stored by programming memory cells within the memory device to various states. For example, a binary memory cell is programmable to one of two supported states, typically represented by a logical 1 or a logical 0. In some instances, a single memory cell may support more than two states, either of which may be stored. To access stored information, a memory device may read (e.g., sense, detect, retrieve, determine) a state from a memory cell. To store information, a memory device may write (e.g., program, set, assign) a state to a memory cell.

[0005] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self-selection memory, chalcogenide memory technology, NOR and NAND memory devices, and others. Memory cells can be described in terms of volatile configurations or non-volatile configurations. Memory cells in non-volatile configurations can maintain a stored logic state for a long time, even in the absence of external power. Memory cells in volatile configurations lose their stored state when disconnected from external power. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 An example of a system supporting row hammer mitigation of a stacked memory architecture according to examples disclosed herein is presented.

[0007] Figure 2 An example of a system supporting row hammer mitigation of a stacked memory architecture according to examples disclosed herein is presented.

[0008] Figure 3 An example of an interface architecture supporting row hammer mitigation for a stacked memory architecture according to examples disclosed herein is shown.

[0009] Figure 4 An example of a system supporting row hammer mitigation of a stacked memory architecture according to examples disclosed herein is presented.

[0010] Figure 5 An example of an architecture supporting row hammer mitigation for a stacked memory architecture according to examples disclosed herein is shown.

[0011] Figure 6 A block diagram showing a logic die supporting row hammer mitigation of a stacked memory architecture according to examples disclosed herein.

[0012] Figure 7 A block diagram showing an array die supporting row hammer mitigation for a stacked memory architecture according to examples disclosed herein.

[0013] Figure 8 and 9 A flow chart illustrating a method of supporting row hammer mitigation for a stacked memory architecture according to examples disclosed herein is shown. DETAILED DESCRIPTION

[0014] Some memory systems may include a semiconductor die stack including one or more memory dies above a logic die, which is operable to access a set of memory arrays distributed across one or more memory dies. This architecture may be implemented as part of a tightly coupled dynamic random access memory (TCDRAM) system, and may support solutions for memory-centric logic, such as a graphics processing unit (GPU) and other implementations. In some examples, the TCDRAM system may be tightly coupled (e.g., physically coupled, electrically coupled) to a processor (e.g., a GPU or other host) as part of a physical memory map accessible to the processor. This coupling may include one or more processors implemented in the same semiconductor die as at least a portion of the TCDRAM system (e.g., as part of a logic die) or a processor implemented in a die that is directly coupled (e.g., fused) to another die that includes at least a portion of the TCDRAM system. Unlike cache-based memory, TCDRAM cannot be supported by an external memory hierarchy with the same physical address. For example, TCDRAM may be associated with and located within a dedicated base address, wherein each portion of the TCDRAM may not overlap within the address.

[0015] In some memory systems implementing semiconductor die stacking, the memory access circuit system may be distributed in multiple semiconductor dies (e.g., distributed across multiple semiconductor dies, distributed between multiple semiconductor dies). For example, multiple semiconductor dies of a TCDRAM system may include a semiconductor die stack (e.g., a stack of multiple directly coupled semiconductor dies), including a first die (e.g., a logic die) operable to access a set of memory arrays distributed across one or more second dies (e.g., an array die). The logic die may access the set of memory arrays via a first interface block (e.g., a memory interface block (MIB)) included in the logic die. The first interface block may communicate with one or more second interface blocks of one or more array dies to access the one or more memory arrays. In some cases, the memory array may be organized in multiple rows, and the rows may be physically located in the memory array close to each other (e.g., adjacent). Each row may include a set of memory cells and may be accessed via a corresponding address (e.g., a physical address). In some cases, the row (e.g., and its associated memory cells) may be subject to adverse access, such as a row hammer attack. A row hammer attack may include repeated access operations to one or more first rows (e.g., aggressor rows), which may adversely affect one or more adjacent rows (e.g., victim rows, neighboring rows). For example, repeated access to a row may disturb memory cells of one or more adjacent rows, such that data stored by the memory cells may be modified (e.g., corrupted, damaged).

[0016] According to examples disclosed herein, a semiconductor system, such as a TCDRAM or other memory system, may distribute row hammer mitigation functionality among multiple dies of the semiconductor system. In some examples, a first interface block, such as a memory interface block (MIB), of a first die, such as a logic die, of the semiconductor system and a second interface block, such as an array die, of a second die, such as an array die, of the semiconductor system may exchange signaling (e.g., one or more signals, one or more indications) to coordinate and perform row hammer mitigation operations. For example, the first interface block may transmit access signaling to the second interface block to access a row of a memory array of the second die. The second die may include counters (e.g., at or associated with a memory array of the array die) each associated with a corresponding row of the memory array (e.g., as a per-row counter). For example, each counter may be operable to track (e.g., count, monitor) the number of access operations (e.g., activations) associated with the corresponding row.

[0017] If the value of the counter satisfies one or more thresholds, the second interface block may transmit alarm signaling to the first interface block. This alarm signaling may indicate a row hammer attack on a row associated with the counter (e.g., an aggressor row). To mitigate the adverse effects of the row hammer attack, the first interface block may evaluate the alarm signaling and may transmit refresh signaling to the second interface block. The refresh signaling may include one or more refresh commands for one or more neighboring rows (e.g., rows of different numbers, victim rows) located close to (e.g., adjacent to) the row. By distributing row hammer mitigation operations across multiple semiconductor dies according to one or more of the described techniques, the system may be configured with a more robust row hammer mitigation procedure, increased system security, and increased reliability, as well as other benefits, compared to other row hammer mitigation techniques in a memory system.

[0018] Features of the present disclosure are illustrated and described in the context of systems and dies (eg, logic dies, array dies). Features of the present disclosure are further illustrated and described in the context of architectures, block diagrams, and flow charts.

[0019] Figure 1 An example of a system 100 that supports row hammer mitigation of a stacked memory architecture according to examples disclosed herein is illustrated. The system 100 may include a portion of an electronic device, such as a computing device, a mobile computing device, a wireless communication device, a graphics processing device, a vehicle, or other system. The system 100 includes a host system 105, a memory system 110, and one or more channels 115 (e.g., for providing a communicative coupling) coupling the host system 105 and the memory system 110. The system 100 may include one or more memory systems 110, but aspects of the one or more memory systems 110 may be described in the context of a single memory system 110.

[0020] The host system 105 may be an example of a processor (e.g., circuitry, processing circuitry, one or more processing components) that uses memory to perform processes, such as a processing system of a computing device, a mobile computing device, a wireless communication device, a graphics processing device, a wearable device, an Internet connection device, a vehicle controller, a single chip system (SoC), or other fixed or portable electronic device, among other examples. The host system 105 may include one or more of an external memory controller 120, a processor 125, a basic input / output system (BIOS) component 130, or other components (e.g., peripheral components, input / output controllers not shown). The components of the host system 105 may be coupled to each other using a bus 135.

[0021] The external memory controller 120 may be configured to enable information (e.g., data, commands, control information, configuration information) communication between components of the system 100 (e.g., between components of the host system 105 (e.g., the processor 125) and the memory system 110). The external memory controller 120 may process (e.g., convert, translate) communications exchanged between the host system 105 and the memory system 110. In some examples, the external memory controller 120 or other components of the system 100 or associated functionality described herein may be implemented by or be part of the processor 125. For example, the external memory controller 120 may be hardware, firmware, or software (e.g., instructions), or some combination thereof, implemented by the processor 125 or other components of the system 100 or the host system 105. Although the external memory controller 120 is illustrated as being external to the memory system 110, in some examples, the external memory controller 120 or its functionality described herein may be implemented by one or more components of the memory system 110 (e.g., the memory system controller 155, the local memory controller 165), or vice versa. In various examples, the host system 105 or the external memory controller 120 may be referred to as a host.

[0022] Processor 125 is operable to provide functionality (e.g., control functionality) for system 100 or host system 105. Processor 125 may be a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof. In some examples, processor 125 may be an example of a central processing unit (CPU), a graphics processing unit (GPU), a general purpose GPU (GPGPU), or a SoC, among other examples.

[0023] In some examples, the system 100 or the host system 105 may include an input component, an output component, or a combination thereof. The input component may include a sensor, a microphone, a keyboard, another processor (e.g., on a printed circuit board), an interface (e.g., a user interface, an interface between other devices), or a peripheral device that interfaces with the system 100 via one or more peripheral components, as well as other examples. The output component may include a display, an audio speaker, a printing device, another processor on a printed circuit board, or a peripheral device that interfaces with the system 100 via one or more peripheral components, as well as other examples.

[0024] The memory system 110 may be a component of the system 100 operable to provide physical memory locations (e.g., addresses) that may be used or referenced by the system 100. The memory system 110 may include a memory system controller 155 and one or more memory dies 160 (e.g., memory chips) for supporting data storage capacity. The memory system 110 may be configured to cooperate with one or more different types of host systems 105, and may respond to and execute commands provided by the host system 105 (e.g., via the external memory controller 120). For example, the memory system 110 (e.g., the memory system controller 155) may receive a write command indicating that the memory system 110 is to store data received from the host system 105, or receive a read command indicating that the memory system 110 is to provide data stored in the memory die 160 to the host system 105, or receive a refresh command indicating that the memory system 110 is to refresh data stored in the memory die 160, as well as other types of commands and operations.

[0025] The memory system controller 155 may include components (e.g., circuitry, logic) operable to control the operation of the memory system 110. The memory system controller 155 may include hardware, firmware, or instructions that enable the memory system 110 to perform various operations, and may be operable to receive, transmit, or execute commands, data, or control information related to the operation of the memory system 110. The memory system controller 155 may be operable to communicate with one or more of the external memory controller 120, one or more memory dies 160, or the processor 125. In some examples, the memory system controller 155 may cooperate with the local memory controller 165 of the memory die 160 to control the operation of the memory system 110.

[0026] Each memory die 160 may include a local memory controller 165 and a memory array 170. The memory array 170 may be a collection of memory cells, each of which may be operable to store one or more bits of data. The memory die 160 may include a two-dimensional (2D) array of memory cells or a three-dimensional (3D) array of memory cells. In some examples, a 2D memory die 160 may include a single memory array 170. In some examples, a 3D memory die 160 may include two or more memory arrays 170, which may be stacked on top of each other or positioned side-by-side with each other (e.g., relative to a substrate).

[0027] The local memory controller 165 may include components (e.g., circuitry, logic) operable to control the operation of the memory die 160. In some examples, the local memory controller 165 may be operable to communicate (e.g., receive or transmit data or commands or both) with the memory system controller 155. In some examples, the memory system 110 may not include a memory system controller 155, and the local memory controller 165 or the external memory controller 120 may perform the various functions described herein. Thus, the local memory controller 165 may be operable to communicate with the memory system controller 155, with other local memory controllers 165, or directly with the external memory controller 120 or the processor 125, or any combination thereof. Examples of components that may be included in the memory system controller 155 or the local memory controller 165 or both may include a receiver for receiving signals (e.g., from the external memory controller 120), a transmitter for transmitting signals (e.g., to the external memory controller 120), a decoder for decoding or demodulating received signals, an encoder for encoding or modulating signals to be transmitted, a sensing component for sensing the state of memory cells of the memory array 170, a writing component for writing states to memory cells of the memory array 170, or various other components operable to support the described operations of the memory system 110.

[0028] The host system 105 (e.g., external memory controller 120) and the memory system 110 (e.g., memory system controller 155) may communicate information (e.g., data, commands, control information, configuration information) using one or more channels 115. Each channel 115 may be an example of a transmission medium that carries information, and each channel 115 may include one or more signal paths (e.g., transmission media, electrical conductors, conductive paths) between terminals associated with components of the system 100. For example, a channel 115 may be associated with a first terminal (e.g., including one or more pins, including one or more pads) at the host system 105 and a second terminal at the memory system 110. A terminal may be an example of a conductive input or output point of a device of the system 100, and a terminal may be operable to serve as part of a channel 115. In some implementations, at least the channel 115 between the host system 105 and the memory system 110 may include or be referred to as a host interface (e.g., a physical host interface). In some implementations, the host interface may include or be associated with interface circuitry (e.g., signal drivers, signal latches) at the host system 105 (e.g., at the external memory controller 120) or at the memory system 110 (e.g., at the memory system controller 155), or both.

[0029] In some examples, channels 115 (e.g., associated signal paths and terminals) may be dedicated to conveying one or more types of information. For example, channels 115 may include one or more command and address channels, one or more clock signal channels, one or more data channels, and other channels or combinations thereof. In some examples, signaling may be conveyed via channels 115 using single data rate (SDR) signaling or double data rate (DDR) signaling. In SDR signaling, one modulation symbol (e.g., signal level) of a signal may be recorded for each clock cycle (e.g., on either a rising or falling edge of a clock signal). In DDR signaling, two modulation symbols of a signal may be recorded for each clock cycle (e.g., on both a rising edge and a falling edge of a clock signal).

[0030] In some examples, at least a portion of system 100 may implement a stacked die architecture in which multiple semiconductor dies are physically and communicatively coupled. In some implementations, one or more semiconductor dies may include multiple instances of interface circuitry (e.g., memory system 110, memory interface block), each associated with accessing a corresponding set of one or more memory arrays 170 of one or more other semiconductor dies. In some cases, the circuitry for accessing one or more memory arrays 170 may be distributed among multiple semiconductor dies in a stack (e.g., a stack of multiple directly coupled semiconductor dies). For example, a first die may include a logic block (e.g., a common logic block, a central logic block, logic circuitry) operable to configure a set of multiple first interface blocks (e.g., MIBs, instances of first interface circuitry) of the first die. In some examples, the system may include a respective controller (e.g., a memory controller, a host interface controller, at least a portion of the memory system controller 155, at least a portion of the external memory controller 120, or a combination thereof) for each first interface block to support access operations (e.g., for accessing one or more memory arrays 170) via the first interface blocks. The system 100 may also include a non-volatile storage device, one or more sensors, or a combination thereof to support various operations of the system 100.

[0031] According to examples disclosed herein, a plurality of semiconductor dies of a memory system 110 (e.g., a TCDRAM system) may include one or more second dies (e.g., memory die 160, array die) stacked with a first die (e.g., a logic die including a host system 105, a logic die coupled to a third die including the host system 105), the first die including an interface block operable to access a group of memory arrays 170 distributed across the one or more second dies. In some cases, memory cells in the memory array group 170 may be subject to adverse access operations, such as row hammer attacks. In order to mitigate (e.g., avoid, reduce) adverse effects caused by row hammer attacks, row hammer mitigation operations may be distributed across the circuitry of the system 100.

[0032] In some examples, a first interface block of a first die and a second interface block of a second die in one or more second dies may exchange signaling to perform row hammer mitigation operations. For example, the memory system 110 may implement a counter to track a respective number of access operations (e.g., activation operations) for respective addresses of respective memory arrays 170 (e.g., respective rows of memory cells of respective memory arrays 170). In some examples, the second interface block may transmit an alarm signaling to the first interface block based on the value of the counter satisfying one or more thresholds. The first interface block may evaluate the alarm signaling and may issue one or more refresh commands to the second interface block in response to the alarm signaling. The refresh command may indicate one or more addresses for refreshing, such as rows (e.g., victim rows) that are adjacent (e.g., proximate) to the row (e.g., aggressor row) associated with the alarm signaling. By exchanging signaling associated with row hammer mitigation between multiple semiconductor dies according to one or more of the described techniques, the system may be configured with a more robust row hammer mitigation procedure, increased security, and increased reliability, among other advantages, compared to other row hammer mitigation techniques.

[0033] In addition to being applied in the systems described herein, the interface technology for stacked memory architectures may also be generally implemented to support artificial intelligence applications. As the use of artificial intelligence increases to support machine learning, analysis, decision making, or other related applications, it may be desirable for electronic devices to support artificial intelligence applications and processes. For example, artificial intelligence applications may be associated with accessing relatively large amounts of data for analytical purposes and may benefit from a memory system that is capable of effectively and efficiently storing relatively large amounts of data or accessing stored data relatively quickly. Implementation of the technology described herein may support artificial intelligence or machine learning techniques by supporting robust protection and efficient access of information via a relatively large number of tightly coupled interfaces (e.g., channels, data paths, supporting stacking) between a host and a memory array of one or more semiconductor dies stacked on a logic die (e.g., by implementing robust hammer mitigation procedures and other benefits in a system including stacked logic dies and semiconductor dies).

[0034] Figure 2An example of a system 200 (e.g., semiconductor system, system coupling semiconductor dies) supporting row hammer mitigation of a stacked memory architecture according to examples disclosed herein is illustrated. The system 200 illustrates an example of a die 205 (e.g., semiconductor die, host die, processor die, logic die) coupled with one or more dies 240 (e.g., dies 240-a-1 and 240-a-2, semiconductor die, memory die, array die). The die 205 or die 240 may be formed using a respective semiconductor substrate (e.g., a crystalline semiconductor material substrate such as silicon, germanium, silicon-germanium, gallium arsenide, or gallium nitride) or a silicon-on-insulator (SOI) substrate (e.g., silicon on glass (SOG), silicon on sapphire (SOS)), or an epitaxial semiconductor material formed on another substrate, among other examples. Although the illustrated example of the system 200 includes two dies 240, the system 200 according to the described techniques may include any number of one or more dies 240 coupled with the die 205. Furthermore, although the non-limiting examples of system 200 herein are generally described in terms of application to a memory system, memory subsystem, memory device, or combination thereof, examples of system 200 are not limited thereto. For example, aspects of the present disclosure may be equally applicable to any computing system, computing subsystem, processing system, processing subsystem, component, device, structure, or other type of system or subsystem used for applications such as data collection, data processing, data storage, networking, communication, power, artificial intelligence, single chip system, control, telemetry, sensing and monitoring, digital entertainment, or any combination thereof.

[0035] System 200 illustrates an example of interface circuitry between a host and memory (e.g., via a host interface, via a physical host interface) implemented in (e.g., distributed among) multiple semiconductor dies (e.g., a stack of directly coupled dies). For example, die 205 may include a set of one or more interface blocks 220 (e.g., interface blocks 220-a-1 and 220-a-2, memory interface blocks), and each die 240 may include a set of one or more interface blocks 245 and one or more memory arrays 250 (e.g., die 240-a-1 includes interface block 245-a-1 coupled to a set of one or more memory arrays 250-a-1, die 240-a-2 includes interface block 245-a-2 coupled to a set of one or more memory arrays 250-a-2). Memory array 250 may be an example of memory array 170 and may include memory cells of various architectures, such as RAM, DRAM, SDRAM, SRAM, FeRAM, MRAM, RRAM, PCM, chalcogenide, NOR, or NAND memory cells, or any combination thereof.

[0036] Although the example of system 200 is illustrated as including one interface block 245 in each die 240, a die 240 in accordance with the described techniques may include any number of one or more interface blocks 245, each coupled to a set of corresponding one or more memory arrays 250 and each coupled to a corresponding interface block 220 of die 205. Thus, the interface circuitry of system 200 may include one or more interface blocks 220 of die 205, wherein each interface block 220 is coupled (e.g., in communication) with a corresponding interface block 245 of die 240 (e.g., external to die 205). In some examples, the coupled combination of interface blocks 220 and interface blocks 245 (e.g., coupled via a bus associated with one or more channels, such as one or more data channels, one or more control channels, one or more clock channels, or a combination thereof) may include or be referred to as a data path associated with a set of corresponding one or more memory arrays 250.

[0037] In some implementations, the die 205 may include a host processor 210. The host processor 210 may be an example of the host system 105 or a portion thereof (e.g., an aspect of the processor 125, the external memory controller 120, or both). The host processor 210 may be configured to perform operations that implement storage of the memory array 250. For example, the host processor 210 may receive data read from the memory array 250 or may transmit data written to the memory array 250, or both (e.g., according to an application or other operation of the host processor 210). Additionally or alternatively, the host processor 210 may be external to the die 205, such as in another semiconductor die or other component that is coupled (e.g., communicatively coupled, directly coupled, bonded) to the die 205 via one or more contacts 212.

[0038] The host processor 210 may be configured to communicate (eg, transmit, receive) signals with the interface block 220 via one or more host interfaces 216 (eg, physical host interfaces). The host interface 216 may implement a reference Figure 1For example, the host processor 210 may be configured to transmit access signaling (e.g., control signaling, access command signaling, configuration signaling) via the host interface 216, which may be received by the interface block 220 to support access operations (e.g., read operations, write operations) to the memory array 250. In some examples, the host interface 216 may include a set of one or more signal paths for each interface block 220, so that the host processor 210 can communicate with each interface block 220 via a corresponding set of signal paths (e.g., according to a selection of a corresponding set of interface blocks 220 for performing access operations via the host processor 210). Additionally or alternatively, the host interface 216 may include one or more signal paths (not shown) shared between multiple interface blocks 220, and the interface blocks 220 or the host processor 210 or both may interpret, ignore, respond to, or suppress response signaling via the shared signal paths of the host interface 216 based on logical indications (e.g., addressing indications associated with the interface blocks 220 or interface enable signals, which may be provided by the host processor 210 or the corresponding interface blocks 220, depending on the signaling direction).

[0039] In some examples, a respective host interface 216 may be coupled between a set of one or more interface blocks 220 and a controller 215 (e.g., host interface 216-a-1 is coupled between interface block 220-a-1 and controller 215-a-1, and host interface 216-a-2 is coupled between interface block 220-a-2 and controller 215-a-2). The one or more interface blocks 220 and controller 215 may communicate (e.g., cooperate) to perform one or more operations associated with the memory array 250 (e.g., scheduling operations, access operations, operations initiated by the host processor 210). The controller 215 may be an instance of a control circuit system (e.g., memory controller circuit system, host interface control circuit system), and may be associated with a respective instance for each interface block 220 that implements one or more aspects of the external memory controller 120 or the memory system controller 155, or a combination thereof. In some examples, controller 215 may be implemented in die 205, whether host processor 210 is included in die 205 or external to die 205, and interface block 220 may communicate with host processor 210 via one or more controllers 215. In some other examples, controller 215 may be implemented external to die 205 (e.g., in another die (not shown) coupled to respective interface block 220 via respective terminals of each of respective host interfaces 216), which may be in the same or different die as that including host processor 210. In some other examples, aspects of one or more controllers 215 may be included in host processor 210. Although the example of system 200 is illustrated as including a controller 215 for each interface block 220, in various examples, the controller 215 may be coupled to any number of one or more interface blocks 220, and a given interface block 220 may operate based on a single controller 215 or by one or more of a group of multiple controllers 215 (e.g., according to a controller multiplexing scheme).

[0040] In some examples, the host processor 210 may determine an access address (e.g., a logical address of the memory array 250, a physical address of the memory array 250, an address of the interface block 220) and determine to which controller 215 to transmit access signaling for the access address (e.g., the controller 215 or the interface block 220 corresponding to the address). In some examples, the address may be associated with a row of memory cells of the memory array 250. The host processor 210 may transmit the access signaling to the determination controller 215, and the determination controller 215 may in turn transmit the access signaling to the corresponding interface block 220. The corresponding interface block 220 may then transmit access signaling to the coupling interface block 245 to access the determination address (e.g., in the corresponding memory array 250).

[0041] The die 205 may also include a logic block 230 (e.g., a shared logic block, a central logic block, a common logic circuit system) that may be configured to communicate (e.g., transmit, receive) signaling with the interface block 220 of the die 205. In some cases, the logic block 230 may be configured to communicate information (e.g., commands, instructions, instructions, data) with one or more interface blocks 220 to facilitate operation of the system 200. For example, the logic block 230 may be configured to transmit configuration signaling (e.g., initialization signaling, evaluation signaling) that may be received by the interface block 220 to support configuration of the interface block 220 or other aspects of operating the die 240 (e.g., via a corresponding interface block 245). The logic block 230 may be coupled to each interface block 220 via a corresponding bus 231 (e.g., bus 231-a-1 associated with interface block 220-a-1, bus 231-a-2 associated with interface block 220-a-2). In some examples, the respective buses 231 may each include a set of respective one or more signal paths so that the logic block 230 can communicate with each interface block 220 via a respective set of signal paths. Additionally or alternatively, the respective buses 231 may include one or more signal paths (not shown) shared between multiple interface blocks 220.

[0042] In some implementations, logic block 230 may be configured to perform signaling communications (e.g., transmit, receive) with host processor 210 (e.g., via bus 232, via contacts 212 of host processor 210 external to die 205) such that logic block 230 may support an interface between interface block 220 and host processor 210. For example, host processor 210 may be configured to transmit initialization signaling (e.g., boot commands) or other configuration or operational signaling, which may be received by logic block 230 to support initialization, configuration, or other operations of interface block 220. Additionally or alternatively, in some implementations, logic block 230 may be configured to perform signaling communications (e.g., transmit, receive) with components external to system 200 via bus 233 (e.g., and via contacts 234) such that logic block 230 may support an interface that bypasses host processor 210. Additionally or alternatively, logic block 230 may communicate with host processor 210 and may communicate with one or more memory arrays 250 of one or more dies 240 (e.g., for performing self-test operations on memory arrays 250). In some examples, such implementations may support evaluation, configuration, or other operations of system 200 during manufacturing, assembly, validation, or other operations associated with system 200 (e.g., prior to coupling with host processor 210, when host processor 210 is not implemented, for operations independent of a host processor) via contacts 234 accessible at a physical interface of the system.

[0043] Each interface block 220 may be coupled to at least one respective bus 221 of die 205 and a respective bus 246 of die 240, which is configured to communicate signaling with the corresponding interface block 245 (e.g., via one or more associated signal paths). For example, interface block 220-a-1 may be coupled to interface block 245-a-1 via bus 221-a-1 and bus 246-a-1, and interface block 220-a-2 may be coupled to interface block 245-a-2 via bus 221-a-2 and bus 246-a-2. In some examples, die 240 may include a bus, such as bus 255, that bypasses the operational circuitry of die 240 (e.g., bypasses the interface block 245 of a given die 240). For example, interface block 220-a-2 may be coupled to interface block 245-a-2 of die 240-a-2 via bus 255-a-1 of die 240-a-1, which may bypass interface block 245 of die 240-a-1. Such techniques may be extended for interconnection between more than two dies 240 (e.g., for interconnection via respective buses 255 of multiple dies 240).

[0044] The respective signal paths of buses 221, 246, and 255 may be coupled to one another from one die to another via various arrangements of contacts at the surfaces of the interfacing dies. For example, bus 221-a-1 may be coupled to bus 246-a-1 via contacts 222-a-1 of die 205 (e.g., at the surface of die 205) and contacts 247-a-1 of die 240-a-1, bus 221-a-2 may be coupled to bus 255-a-1 via contacts 222-a-2 of die 205 and contacts 256-a-1 of die 240-a-1, bus 255-a-1 may be coupled to bus 246-a-2 via contacts 257-a-1 of die 240-a-1 and contacts 247-a-2 of die 240-a-2, and so on. Although each respective bus is illustrated with a single line coupled via a singular contact, it should be understood that each signal path of a given bus may be associated with a respective contact to support separate communication coupling of each signal path via the given bus. In some examples, bus 255 may pass through a portion of die 240 (e.g., in an in-plane direction, along a direction different from the thickness direction, in a waterfall arrangement), which may support the arrangement of contacts 222 along the surface of die 205 to couple with interface blocks 245 of different dies 240 along the stacking direction (e.g., via respective contacts 256 and 257 that do not overlap when viewed along the thickness direction).

[0045] The interconnection of the interface contacts may be supported by a variety of techniques. For example, in a hybrid bonding implementation, the interface contacts may be coupled by fusing the conductive material (e.g., electrically conductive material) of the interface contacts (e.g., without solder or other intervening material between the contacts). For example, in an assembled condition, the coupling of die 205 to die 240-a-1 may include fusing the conductive material of contact 222-a-2 to the conductive material of contact 256-a-1, and the coupling of die 240-a-1 to die 240-a-2 may include fusing the conductive material of contact 257-a-1 to the conductive material of contact 247-a-2, and so on. In some examples, such coupling may include inoperable fusion of contacts (e.g., non-communicative coupling, physical coupling), such as fusion of contact 260-a-1 and contact 256-a-2, both of which are not coupled to the operable circuitry of die 240-a-1 or 240-a-2. In some examples, such techniques may be implemented to improve coupling strength or uniformity (e.g., implementing contact 260 that may not be operably coupled to interface block 245 or interface block 220), or such coupling may be a byproduct of duplication of components that may be operable or inoperable in various configurations. (For example, where for a die 240 having contacts 256 and 257 arranged together, contacts 256-a-1 and 257-a-1 provide a communication path between interface block 245-a-2 and interface block 220-a-2, but contacts 256-a-2 and 257-a-2 do not provide a communication path between interface block 245 and interface block 220).

[0046] In some examples, the fusion of conductive material between the dies (e.g., between contacts) may be accompanied by fusion of other materials at one or more surfaces of the interfacing dies. For example, in an assembled condition, the coupling of die 205 with die 240-a-1 may include fusion of dielectric material 207 (e.g., non-conductive material) of die 205 with dielectric material 242 of die 240-a-1, and the coupling of die 240-a-1 with die 240-a-2 may include fusion of dielectric material 242 of die 240-a-1 with dielectric material 242 of die 240-a-2. In some examples, such dielectric materials may include oxides, nitrides, carbides, oxide-nitrides, oxide-carbides, or other conversions or doping of semiconductor materials of die 205 or die 240, as well as other materials that may support such fusion. However, the coupling between die 205 and die 240 may be implemented according to other techniques, which may implement solder, adhesives, thermal interface materials, and other intervening materials.

[0047] In some examples, the dies 240 may be coupled into a stack (e.g., forming a "cube" or other arrangement of dies 240), and the stack may then be coupled to the die 205. In some examples, a group of respective one or more dies 240 may be coupled to each die 205 of the plurality of dies 205 formed in a wafer (e.g., in a chip-to-wafer bonding arrangement, before dicing the wafer of dies 205), and the dies 205 coupled to their respective groups of dies 240 may be separated from each other (e.g., by dicing at least the wafer of dies 205). In some other examples, a group of respective one or more dies 240 may be coupled to the respective die 205 after the dies 205 are separated from the wafer of dies 205 (e.g., in a chip-to-chip bonding arrangement).

[0048] The buses 221, 246, and 255 may be configured to provide configuration signaling (e.g., coordination signaling, logic signaling, modulation signaling, digital signaling, one or more signals) between the interface block 220 and the corresponding interface block 245, which may involve various modulation or coding techniques through the transmission interface block (e.g., via the driver component of the transmission interface block). In some examples, this signaling may be supported (e.g., accompanied) by clock signaling communicated (e.g., coordinated with the signal transmission) via the corresponding bus. For example, the bus may be configured to pass one or more clock signals transmitted by the interface block 220 for reception by the interface block 245 (e.g., for triggering a latch or other receiving component of the interface block 245 to receive a signal, for supporting the timing control operation of the interface block 245). Additionally or alternatively, the bus may be configured to pass one or more clock signals transmitted by the interface block 245 for reception by the interface block 220 (e.g., for triggering a latch or other receiving component of the interface block 220 to receive a signal, for supporting the timing control operation of the interface block 220). Such clock signals may be associated with the communication (e.g., unidirectional communication, bidirectional communication) of various signaling (e.g., control signaling, command signaling, data signaling, or any combination thereof). For example, a bus may include one or more signal paths for a data bus (e.g., one or more data lanes, a DQ bus, a data interface via an interface block) to communicate according to one or more corresponding clock signals (e.g., a data clock signal) or one or more signal paths for a control bus (e.g., a command / address (C / A) bus, a command interface via an interface block) to communicate according to one or more clock signals (e.g., a control clock signal), or any combination thereof.

[0049] Interface block 220, interface block 245, and logic block 230 may each include circuitry (signaling circuitry, multiplexing circuitry, processing circuitry, controller circuitry) in various configurations (e.g., hardware configurations, logic configurations, software or instruction configurations) that support functionality assigned to the respective blocks for accessing or otherwise operating a set of corresponding memory arrays 250. For example, interface block 220 may include circuitry configured to perform a first subset of operations supporting access of memory arrays 250, and interface block 245 may include circuitry configured to support a second subset of operations supporting access of memory arrays 250. In some examples, interface blocks 220 and 245 may support functional partitioning or distribution of functionality associated with memory system controller 155, local memory controller 165, or both across multiple dies (e.g., die 205 and at least one die 240). In some implementations, logic block 230 may be configured to coordinate or configure aspects of the operation of interface block 220, interface block 245, or both and may support one or more aspects of implementing memory system controller 155. Such operations or subsets of operations may include operations performed in response to commands from host processor 210 or operations performed without commands from host processor 210 (e.g., operations determined or initiated by interface block 220, operations determined or initiated by interface block 245, operations determined or initiated by logic block 230), or various combinations thereof.

[0050] In some implementations, system 200 may include one or more instances of nonvolatile storage devices, such as nonvolatile storage device 235 of die 205, nonvolatile storage device 270 of one or more dies 240, or a combination thereof. In some examples, logic block 230, interface block 220, interface block 245, or a combination thereof may be configured to communicate signaling with the one or more instances of nonvolatile storage devices. For example, logic block 230, interface block 220, or interface block 245 may be appropriately coupled to the one or more instances of nonvolatile storage devices via one or more buses (not shown) or corresponding contacts (not shown) that may each include one or more signal paths operable to convey signaling (e.g., command signaling, data signaling). In some examples, logic block 230, one or more interface blocks 220, one or more interface blocks 245, or a combination thereof may configure one or more operations based on information stored in one or more instances of nonvolatile storage devices. Additionally or alternatively, in some examples, logic block 230, one or more interface blocks 220, one or more interface blocks 245, or a combination thereof may write information (eg, configuration information) stored in one or more instances of non-volatile storage.

[0051] In some embodiments, the system 200 may include one or more sensors (e.g., one or more sensors 237 of the die 205, one or more sensors 275 of the die 240, or a combination thereof). In some embodiments, the logic block 230, the interface block 220, the interface block 245, or a combination thereof may be configured to receive one or more indications based on measurements of one or more sensors of the system 200. For example, the logic block 230, the interface block 220, or the interface block 245 may be coupled to the one or more sensors via one or more buses (not shown) or corresponding contacts (not shown). Such sensors may include temperature sensors, current sensors, voltage sensors, counters, and other types of sensors. In some examples, the logic block 230, the one or more interface blocks 220, the one or more interface blocks 245, or a combination thereof may configure one or more operations based on the output of the one or more sensors. For example, the logic block 230 may configure one or more operations of the interface block 220 based on signaling (e.g., indications, data) received from the one or more sensors. Additionally or alternatively, the interface block 220 may generate access signaling for transmission to a corresponding interface block 245 based on one or more sensors.

[0052] In some examples, the circuitry of interface block 220, interface block 245, or logic block 230, or any combination thereof, may include components (e.g., transistors) formed at least in part from doped portions of a substrate of a respective die. In some examples, the substrate of die 205 may have characteristics that differ from characteristics of a substrate of die 240. Additionally or alternatively, in some examples, transistors formed from the substrate of die 205 may have characteristics that differ from transistors formed from the substrate of die 240 (e.g., according to different transistor architectures).

[0053] In some examples, interface block 220 may support a layout of one or more components within 220. For example, the layout may include paired components sharing access ports (e.g., command ports, data ports). Further, in some examples, the layout may support an interface for controller 215 (e.g., host interface 216) that is different from an interface for interface block 245 (e.g., via bus 221). For example, host interface 216 may be synchronous and have separate channels for read and write operations, while the interface via buses 221 and 246 may be asynchronous and support both read and write operations with the same channel.

[0054] The die 240 may include one or more cells 265 (e.g., modules) separated from a semiconductor wafer having a pattern (e.g., a two-dimensional pattern) of cells 265. Although each die 240 of the system 200 is illustrated as having a single cell 265 (e.g., cell 265-a-1 of die 240-a-1, cell 265-a-2 of die 240-a-2), a die 240 according to the described techniques may include any number of cells 265 that may be arranged in various patterns (e.g., groups of one or more cells 265 along a row direction, groups of one or more cells 265 along a column direction, and other patterns). Each cell 265 may include at least the circuitry of a corresponding interface block 245 and a memory array 250, a bus 251, a bus 246, and one or more contacts 247 corresponding to the corresponding interface block 245. In some instances, each unit 265 may also appropriately include one or more buses 255, contacts 256, contacts 257, or contacts 260 (e.g., associated with corresponding interface blocks 245 of units 265 of different dies 240), which may support various degrees of stackability or modularity between units 265 of other dies 240 or via units 265 of other dies 240.

[0055] In some examples, the interface block 220 may include circuitry configured to receive first access command signaling from the host processor 210 or controller 215 (e.g., via the host interface 216, from the host processor 210 or controller 215 external to the die 205 via one or more contacts 212) and transmit second access command signaling to a corresponding (e.g., coupled) interface block 245 based on (e.g., in response to) the received first access command signaling. The interface block 245 may thus include circuitry configured to receive second access command signaling from the corresponding interface block 220 and, in some examples, access a corresponding set of one or more memory arrays 250 based on (e.g., in response to) the received second access command signaling. In various examples, the first access command signaling may include an access command associated with an operation type (e.g., a read operation, a write operation, a refresh operation, a memory management operation), which may be associated with an indication of an address (e.g., a logical address, a physical address) of the one or more memory arrays 250. In some examples, the first access command signaling may include an indication of a logical address associated with the memory array 250, and the circuit system of the interface block 220 may be configured to generate a second access command signaling to indicate a physical address associated with the memory array 250 (e.g., a row address, a column address, using a logical-to-physical (L2P) table or other mapping or calculation functionality of the interface block 220).

[0056] In some examples, to support write operations of the system 200, the circuitry of the interface block 220 may be configured to receive first data signaling associated with the first access command signaling (e.g., from the host processor 210, from the controller 215, via the host interface 216, from the host processor 210 or the controller 215 external to the die 205 via one or more contacts 212) and transmit second data signaling (e.g., associated with the second access command signaling) based on the received first access command signaling and the first data signaling. The interface block 245 may thus be configured to receive the second data signaling and write data to the one or more memory arrays 250 based on the received second access command signaling and the second data signaling (e.g., according to the indicated address associated with the first access command signaling). In some instances, interface block 220 may include error control functionality (e.g., error detection circuitry, error correction circuitry, error correction code (ECC) logic, an ECC engine) that supports interface block 220 in generating second data signaling based on performing error control operations using received first data signaling (e.g., detecting or correcting errors in the first data signaling, determining one or more parity bits conveyed in the second data signaling and written with the data).

[0057] In some examples, to support read operations of system 200, the circuitry of interface block 245 may be configured to read data from memory array 250 based on received second access command signaling and transmit first data signaling based on the read data. Interface block 220 may thus be configured to receive first data signaling and transmit second data signaling based on the received first data signaling (e.g., to host processor 210, to controller 215, via host interface 216, to host processor 210 or controller 215 external to die 205 via one or more contacts 212). In some examples, interface block 220 may include error control functionality that enables interface block 220 to generate second data signaling based on performing error control operations using received first data signaling (e.g., detecting or correcting errors in the first data signaling, which may include calculations involving one or more parity bits received with the first data signaling).

[0058] In some examples, access command signaling and other signaling transmitted by the interface block 220 to the interface block 245 may be generated (e.g., based on access command signaling received from the host processor 210, based on start signaling received from the host processor 210, without receiving or otherwise independently of signaling from the host processor 210) according to various determination or generation techniques configured at the interface block 220 (e.g., based on a configuration modified at the interface block 220 for accessing the memory array 250). In some examples, such techniques may involve signaling or other coordination with the logic block 230, the host processor 210, one or more controllers 215, one or more instances of non-volatile storage devices, one or more sensors, or any combination thereof. Such techniques may support the interface block 220 in configuring aspects of access operations and other operations performed by the corresponding interface block 245 on the memory array 250. For example, interface block 220 may include evaluation circuitry, access configuration circuitry, signaling circuitry, scheduling circuitry, repair circuitry, refresh circuitry, error control circuitry, adverse access circuitry, and other circuitry that may be operable to configure operations associated with one or more dies (e.g., operations associated with accessing memory array 250 of die 240).

[0059] In some cases, memory cells in the memory array 250 may be subjected to adverse access operations, such as a row hammer attack, that may modify (e.g., destroy, corrupt) data stored by the memory cells. As part of the row hammer attack, a row of memory cells (e.g., an aggressor row) of the memory array 250 may experience repeated (e.g., a number exceeding a threshold) access operations, for example, within a relatively short duration. In order to reduce the adverse effects associated with the row hammer attack, the system 200 may distribute the row hammer mitigation operations across multiple dies of the system 200 (e.g., across the die 205 and one or more dies 240). For example, the interface block 220 and the interface block 245 may exchange signaling to perform the row hammer mitigation operations. For example, the system 200 may utilize a counter (e.g., at or coupled to the memory array 250) to track the number of access operations (e.g., activations) to corresponding rows of one or more memory arrays 250. In some examples, the interface block 245 may transmit an alarm signaling to the interface block 220 based on the value of one of the counters satisfying one or more thresholds. Interface block 220 may evaluate the received alarm signaling and may issue one or more refresh commands to interface block 245 in response to the alarm signaling. For example, the alarm signaling may include a value indicating which of the one or more thresholds are satisfied by the value of a counter or whether there is an error associated with a counter. The refresh command may indicate one or more rows (e.g., victim rows) that are adjacent (e.g., proximate) to the row associated with the alarm signaling (e.g., aggressor row) for refresh. By exchanging signaling associated with row hammer mitigation between multiple semiconductor dies according to one or more of the described techniques, the interface circuitry of the multiple semiconductor dies may support row hammer mitigation within a TCDRAM system and may be configured with a more robust row hammer mitigation procedure, improved reliability, and other advantages compared to other row hammer mitigation techniques.

[0060] Figure 3 An example of an interface architecture 300 that supports row hammer mitigation of a stacked memory architecture according to examples disclosed herein is illustrated. The interface architecture 300 illustrates an example of an interface block 245-b (e.g., of die 240) coupled to an interface block 220-b (e.g., of die 205). The interface block 245-b may be communicatively coupled to the interface block 220-b via one or more of a bus 301, a bus 302, a bus 303, and a bus 304, each of which may be an example of one or more signal paths of bus 221 and bus 246 as well as bus 255, as appropriate.

[0061] The interface block 245-b includes a control interface 310 (e.g., a command interface) that can be configured to communicate with the interface block 220-b for signaling. For example, the control interface 310 can include a circuit system (e.g., a receiver, one or more latches) configured to receive control signaling (e.g., modulation control signaling, access command signaling, configuration signaling, address signaling, such as row address signaling or column address signaling) via the bus 301-a. The control interface 310 can also include a circuit system configured to receive clock signaling (e.g., clock signaling associated with the control interface 310, clock signaling with one or more phases (e.g., true and complementary phases), dk_t / c signaling from the interface block 220-b) via the bus 302-a. The control interface 310 can use the bus 302-a to receive control signaling of the bus 301-a (e.g., for triggering one or more latches). The control interface 310 may transmit (eg, forward) control signaling, clock signaling (eg, for timing of other operations of the interface block 245 - b ) to the interface controller 320 .

[0062] Interface block 245-b also includes two data interfaces 330 (e.g., data interfaces 330-a-1 and 330-a-2), which may also be configured for signaling communication with interface block 220-b. Each data interface 330 may include a corresponding bus and circuitry, the operation of which may be associated with (e.g., controlled by, coordinated with, operated based on) control signaling via control interface 310. Although the example of interface block 245-b includes two such data interfaces 330 associated with control interface 310 (e.g., in a "channel pair" arrangement), the techniques described for interface block 245 may include any number of one or more data interfaces 330 and associated buses and circuitry for a given control interface 310 of interface block 245. Each data interface 330 may be associated with a corresponding data path circuit system, which may include corresponding first-in-first-out (FIFO) and serialization / deserialization (SERDES) circuit systems (e.g., FIFO / SERDES 340), corresponding write / sense circuit systems 350, corresponding synchronization and sequencing circuit systems (e.g., synchronization / sequencing logic 360), and corresponding timing circuit systems 370, as well as interconnecting signal paths (e.g., one or more buses). However, in some other examples, the data path circuit systems may be arranged in a different manner or may include different circuit system components, which may include circuit systems dedicated to the corresponding data paths or shared between data paths, or various combinations thereof. Each data interface 330 may also be associated with a set of corresponding one or more memory arrays 250. In some examples, each memory array 250 may be understood to include corresponding addressing circuit systems, such as storage body logic or decoders (e.g., row decoders, column decoders), and other array circuit systems. However, in some other examples, at least a portion of this circuit system may be included in the interface block 245.

[0063] Each data interface 330 may include circuitry (e.g., one or more latches, one or more drivers) configured to communicate (e.g., receive, transmit) data signaling (e.g., modulated data signaling, DQ signaling) via the corresponding bus 303. Each data interface 330 may also include circuitry for communicating clock signaling via the corresponding bus 304, which may support the data interface 330 to receive a clock signal (e.g., a first clock signaling associated with the data interface 330, a clock signaling having one or more phases (e.g., true and complementary phases), DQS_t / c signaling from the interface block 220-b, clock signaling associated with a data reception or write operation) or the data interface 330 to transmit a clock signal (e.g., a second clock signaling associated with the data interface 330, RDQS_t / c signaling to the interface block 220-b, clock signaling associated with a data transmission or read operation), or both. Each data interface 330 may transmit clock signaling (eg, received clock signaling, DQS_t / c signaling) to the synchronization / sequencing logic 360 via a respective bus (eg, for timing of other operations of the interface block 245 - b ).

[0064] The interface controller 320 may support various control or configuration functionalities of the interface block 245-b for accessing the coupled memory array 250 or otherwise managing the operation of the coupled memory array 250. For example, the interface controller 320 may support access command coordination or configuration, delay or timing compensation, access command buffering (e.g., according to a FIFO or other organizational scheme), mode registers or logic for configuration settings or test functionality, and other functions or combinations thereof. For each data path of the interface block 245 (e.g., associated with a corresponding data interface 330), the interface controller 320 may be configured to transmit signaling (e.g., address signaling, such as row address or row activation signaling) to the corresponding memory array 250 via a bus 321. For each data path of the interface block 245, the interface controller 320 may communicate signaling (e.g., timing signaling (which may be based on clock signaling received from the control interface 310), configuration signaling) with the corresponding timing circuit system 370 and synchronization / sequencing logic 360 via a corresponding bus.

[0065] For each data path, a respective timing circuitry 370 may support timing of various operations (e.g., activation, coupling operations, signal latching, signal driving) relative to timing signaling received from the interface controller 320. For example, the timing circuitry 370 may include a timing chain (e.g., a global column timing chain) configured to generate one or more clock signals or other enable signals for controlling the operation of the respective data paths, and such signaling may include transitions (e.g., rising edge transitions, falling edge transitions, on / off transitions) that are offset from transitions of the signaling from the interface controller 320, occur at a different rate than the transitions, or otherwise differ from the transitions to support a given operation or combination of operations. For example, the timing circuitry 370 may be configured to transmit signaling (e.g., column select signaling, column address signaling) to the respective memory array 250, transmit signaling (e.g., latch or driver timing signaling) to the respective write / sense circuitry 350, and transmit signaling (e.g., timing signaling) to the respective synchronization / sequencing logic.

[0066] For each data path, a respective FIFO / SERDES 340 may be configured to convert between data signaling of a first bus width (e.g., a relatively wider bus width, a data read / write (DRW) bus, a bus for communicating with a write / sense circuitry 350 having a relatively greater number of signal paths) and a second bus width (e.g., a relatively narrower bus width, a bus for communicating with a data interface 330 having a relatively lesser number of signal paths). In some examples, such conversion may be accompanied by changing the signaling rate between signaling from the data interface 330 and the write / sense circuitry 350 (e.g., for maintaining a given throughput). In various examples, the FIFO / SERDES 340 may receive data signaling from the data interface 330 and transmit data signaling to the write / sense circuitry 350 (e.g., for supporting write operations), or may receive data signaling from the sense circuitry 350 and transmit data signaling to the data interface 330 (e.g., for supporting read operations). In some examples (eg, for supporting read operations), the FIFO / SERDES 340 may be configured to transmit clock signaling (eg, RDQS_t / c signaling) to the data interface 330, which may be forwarded to the interface block 220-b.

[0067] The timing or other synchronization of the operations performed by the FIFO / SERDES 340 may be supported by one or more clock signals and other signaling received from the corresponding synchronization / sequencing logic 360. For example, the synchronization / sequencing logic 360 may generate or otherwise coordinate clock signaling to support different signaling rates for different buses (e.g., based on received clock signaling). Additionally or alternatively, the FIFO / SERDES 340 may operate in one direction (e.g., for data transmission to the data interface 330, for data reception from the data interface 330) or other modes based on configuration signaling received from the synchronization / sequencing logic 360.

[0068] For each data path, a respective write / sense circuitry 350 may be configured to support access (e.g., data signaling, write signaling, read signaling) of a respective group of one or more memory arrays 250. For example, the write / sense circuitry 350 may be coupled to the memory arrays 250 via a bus (e.g., a global input / output (GIO) bus), which may include respective signal paths associated with each memory array 250 or may include signal paths shared by all memory arrays 250 of the group, in which case the memory array circuitry may include multiplexing circuitry operable to couple the bus with selected ones of the memory arrays 250. In some examples, the bus between the write / sense circuitry and the group of one or more memory arrays 250 may include the same number of signal paths as the bus between the write / sense circuitry 350 and the FIFO / SERDES 340 (e.g., for signaling GIO[287:0]) or the same number of signal paths as the number of columns in each memory array 250. In some other examples, the memory array 250 may include a number of columns that is an integer multiple of the number of signal paths of the bus, in which case the memory array circuitry (e.g., each memory array 250) may include decoding circuitry operable to couple a subset of the memory cell columns or associated circuitry to the bus.

[0069] To support write operations, write / sense circuitry 350 may be configured to drive signaling operable to write one or more logic states to memory cells of memory array 250 (e.g., based on received data, based on received timing signaling, based on data signaling received via bus 303, and based on control signaling received via bus 301-a). In some examples, such signaling may be transmitted to or otherwise associated with supporting circuitry of memory array 250 (e.g., as an output of a signal corresponding to the logic state to be written), such as sense amplifier circuitry, voltage sources, current sources, or other driver circuitry operable to apply a bias across a storage element of a memory cell (e.g., across a capacitor, across a ferroelectric capacitor) or to apply a charge, current, or other signaling to a storage element of a memory cell (e.g., applying current to a chalcogenide or other configurable memory material, applying charge to a gate of a NAND memory cell), as well as other examples.

[0070] To support read operations, the write / sense circuitry 350 may be configured to receive signaling, which the write / sense circuitry 350 may further amplify for communication through the interface block 245-b. For example, the write / sense circuitry 350 may be configured to receive signaling corresponding to a logic state read from the memory array 250, but at a relatively low driver strength (e.g., relatively 'analog' signaling, which may be associated with a relatively low drive strength of a sense amplifier of the memory array 250). The write / sense circuitry 350 may therefore include further sense amplification (e.g., data sense amplifiers (DSAs) between a signal path between the write / sense circuitry and the set of one or more memory arrays and a corresponding signal path between the write / sense circuitry and the FIFO / SERDES), each of which may have a relatively high drive strength (e.g., for driving relatively 'digital' signaling).

[0071] Features of interface architecture 300 may be repeated in various numbers and arrangements to support semiconductor systems having multiple dies, such as various instances of system 200. In an example embodiment, each die 240 may be configured with 64 instances of interface block 245-b, which may support a data signaling width of 9,216 signal paths for each die 240 (e.g., where each bus 303 of a channel pair is associated with 72 signal paths). For system 200 having a stack of 8 dies 240 coupled to die 205, die 205 may thus be configured with 512 instances of interface block 220-b, thereby supporting a total data signaling width of 73,738 signal paths for system 200. However, in other embodiments, die 205 and die 240 may be configured with different numbers of interface blocks 220 and 245, respectively, and system 200 may be configured with different numbers of dies 240 per die 205.

[0072] In some examples, each memory array 250 may be organized with rows of memory cells, each row being associated with an address of the memory array 250. Each memory array 250 may be associated with (e.g., coupled to, including) a set of counters 380 (e.g., located in the die 240). The set of counters 380 may track access operations associated with the memory array 250 and may include a respective counter 380 for each row of the memory array 250. For example, each counter 380 may track a respective number of access operations (e.g., activations) to a respective row of the memory array 250. In some examples, the interface controller 320 may operate (e.g., read, increment, write, reset) the counters 380 via a bus 321. Additionally or alternatively, the interface controller 320 may operate the counters 380 via a dedicated bus 322 (e.g., a dedicated GIO bus, a dedicated access line). By tracking the number of access operations to the memory array 250, the counters 380 may be used by the interface controller 320 to detect a row hammer attack on the memory array 250. For example, interface controller 320 may compare the value of counter 380 to one or more thresholds and determine, based on the comparison, that the row associated with counter 380 is subject to a row hammer attack based on the value satisfying at least one of the one or more thresholds.

[0073] In some examples, interface block 220-b and interface block 245-b may exchange signaling (e.g., via one or more signal paths of bus 301, via one or more alert pins of bus 301) to perform row hammer mitigation operations. For example, interface block 245-b (e.g., interface controller 320) may detect a row hammer attack associated with memory array 250 (e.g., to a row of memory array 250) and may transmit alert signaling to interface block 220-b. Interface block 220 may evaluate the received alert signaling and may issue one or more refresh commands to interface block 245-b (e.g., via bus 301) in response to the alert signaling. The refresh command may instruct interface block 245-b (e.g., interface controller 320) to refresh one or more rows (e.g., victim rows) of memory array 250 that are adjacent to the row (e.g., aggressor row) associated with the alert signaling based on a value included in the alert signaling. By exchanging signaling associated with row hammer mitigation between multiple semiconductor dies (e.g., die 205 and one or more dies 240) according to one or more of the described techniques, the system can support row hammer mitigation within a TCDRAM system and can be configured with a more robust row hammer mitigation procedure, improved reliability, and other advantages compared to other row hammer mitigation techniques.

[0074] Figure 4An example of a block diagram of a system 400 supporting row hammer mitigation of a stacked memory architecture according to examples disclosed herein is shown. The system 400 illustrates an example of an interface block 245-c (e.g., of a die 240) coupled to an interface block 220-c (e.g., of a die 205). The interface block 245-c may be communicatively coupled to the interface block 220-c. The interface block 245-c may be coupled to one or more memory arrays 250 (including the memory array 250-c). The one or more memory arrays 250 may each include a plurality of rows 405 (e.g., rows 405-a-1 to 405-a-7), and each row 405 may include a group of memory cells. Each row 405 of the one or more memory arrays 250 may be associated with a corresponding counter 380-b (e.g., counters 380-b-1 to counters 380-b-7 corresponding to rows 405-a-1 to 405-a-7). Interface block 245-c and interface block 220-c can communicate signaling (e.g., access signaling 410, alarm signaling 415, refresh signaling 420, or other signaling, such as via bus 301) to support the row hammer mitigation procedures described herein to improve system security and reliability, such as by protecting data stored at memory array 250-c from unexpected or malicious data modifications.

[0075] In some cases, the system 400 may be subject to a row hammer attack, in which a large number of access commands are issued (e.g., via the interface block 220-c in a relatively small amount of time) to a row 405 of the memory array 250, which may be referred to as the aggressor row 405. Due to the continuous access commands, charge from the aggressor row 405 may leak to or from one or more memory cells of other rows 405 (e.g., adjacent rows 405 not associated with the addresses in the access commands) near the aggressor row 405 (which may be referred to as the victim row 405). The charge leakage or other associated disturbances may affect the state (e.g., charge) of the memory cells in the victim row, which may result in modification of data stored in the memory cells of the victim row. Therefore, the system 400 may perform a row hammer mitigation procedure to reduce (e.g., avoid) such adverse effects, which may include refreshing the state (e.g., logical state, electrical state) of the memory cells of the victim row (e.g., to restore their correct state).

[0076] According to the techniques described herein, the interface block 245-c may communicate signaling (e.g., one or more signals) with the interface block 220-c to perform one or more mitigation procedures to, for example, support row hammer mitigation in a system (e.g., a TCDRAM system) in which memory access circuitry is partitioned between multiple semiconductor dies. For example, the interface block 220-c may transmit access signaling 410 (e.g., an activate (ACT) command, an access command, one or more signals, an access signal) that instructs the interface block 245-c to activate a row 405-a of the memory array 250-c (e.g., a row 405-a of the memory array 250-c of the die 240 as part of an access operation to the row 405-a). In some examples, the access signaling 410 may indicate parameters associated with the row 405-a to be activated (e.g., a pseudo channel (PC), a bank address, a row address). For example, the bus 221 through which the interface block 220-c and the interface block 245-c communicate may include multiple PCs, where different PCs may be associated with a common command signal path and a corresponding data signal path. For example, a first PC and a second PC of the bus 221 may share the same command signal path (e.g., bus 301, bus 302), but may include separate data signal paths (e.g., bus 303, bus 304). To indicate (e.g., identify) the row 405-a for activation, the parameters of the access signaling 410 may indicate the PC through which the row 405-a is accessed, the bank address of the memory bank that includes the row 405-a, and the row address of the row 405-a within the memory bank.

[0077] Based on the access signaling 410, the interface block 245-c may activate the row 405-a of the memory array 250-c, e.g., as part of or independent of an access operation to the row 405-a. Each counter 380-b may be used (e.g., maintained, incremented) to track (e.g., count) a respective number of activations of the corresponding row 405-a (e.g., a respective number of access operations to the corresponding row 405-a). For example, the counter 380-b may be implemented as a per-row counter to count a respective number of activations of each row 405-a. For example, the counter 380-b-1 may be used to track the number of activations of the row 405-a-1, the counter 380-b-2 may be used to track the number of activations of the row 405-a-2, and so on. Thus, based on accessing the row 405-a, the interface block 245-c may read the value of the counter 380-b used to track the number of activations of the row 405-a and may increment the value. The interface block 245-c may compare the value of the counter 380-b to one or more thresholds and may generate an alarm signaling 415 (e.g., a hammer alarm signaling, one or more signals, an alarm signal) based on the comparison. For example, based on the comparison, the interface block 245-c may determine whether the value of the counter 380-b satisfies one of the one or more thresholds. In some instances, the interface block 245-c may write the incremented value back to the counter 380-b. In some other instances, if the value of the counter satisfies one of the one or more thresholds, the interface block 245-c may reset at least a portion of the counter 380-b. In some cases, the interface block 245-c may detect an error associated with the value of the counter 380-b based on reading the value of the counter. In some such instances, the interface block 245-c may generate an alarm signaling 415 based on detecting an error and may reset the counter 380-b.

[0078] In some cases, the interface block 245-c may cause one or more procedures associated with the counter 380-b (e.g., reading the counter 380-b, incrementing the counter 380-b, transmitting one or more portions of the alarm signaling 415, writing the counter 380-b, resetting the counter 380-b) to be performed concurrently with one or more access operations associated with processing (e.g., servicing) the access signaling 410 request (e.g., performing a read operation or a write operation on the row 405-a). For example, the interface block 245-c may perform one or more access operations on the row 405-a while performing a corresponding number of one or more operations that track activations (e.g., access operations) of the row 405-a.

[0079] To perform an access operation on row 405-a, interface block 245-c may issue signaling (e.g., to write / sense circuit system 350-a), such as row activation signaling, column activation signaling, or a combination thereof. In some cases, the duration between row activations that are successively signaled by interface block 245-c may be based on internal operations of interface block 245-c associated with counter 380-b (e.g., each row internal operation). For example, the operations of reading the value of counter 380-b, incrementing the value of counter 380-b, and writing the incremented value to counter 380-b may result in an increase in the duration between consecutively issued row activations (e.g., an additional 8 nanoseconds). Therefore, in some instances, in order to accommodate the execution of internal operations associated with counter 380-b, interface block 245-c may delay issuing subsequent row activation signaling at least until the internal operation (e.g., writing the incremented value to counter 380-b) is completed.

[0080] In some examples, the counter 380-b may be a multi-bit (e.g., 14-bit) counter, and different subsets of the bits of the counter 380-b may be used to determine whether the value of the counter 380-b satisfies one or more thresholds or identifies an error associated with the counter 380-b. For example, each counter 380-b may include a plurality of portions 425 (e.g., portion 425-a, portion 425-b, portion 425-c) corresponding to respective subsets of one or more bits of the counter 380-b. The interface block 245-c may use the portions 425 to determine whether the value of the counter 380-b satisfies one or more thresholds or identifies an error associated with the counter 380-b. For example, the counter 380-b may include a portion 425-a (e.g., a row hammer 1 (RH1) counter) for tracking the number of activations (e.g., access operations) of the corresponding row 405-a, which may indicate whether the value of the counter 380-b satisfies a first threshold. If the value of counter 380 - b satisfies the first threshold, interface block 245 - c may reset portion 425 - a .

[0081] The counter 380-b may also include a portion 425-b (e.g., a row hammer 2 (RH2) counter) that may track the number of occurrences that the counter 380-b (e.g., portion 425-a) satisfies a first threshold. For example, the interface block 245-c may increment the portion 425-b based on the value of the counter 380-b satisfying the first threshold, such as incrementing the portion 425-b each time the portion 425-a satisfies the first threshold (e.g., each time the portion 425-a is reset). The portion 425-b may indicate whether the value of the counter 380-b satisfies a second threshold. If the counter 380-b satisfies the second threshold, the interface block 245-c may reset the portion 425-b (e.g., and the portion 425-a). The counter 380-b may also include a portion 425-c (e.g., one or more parity bits, a cyclic redundancy check (CRC) portion, an error correction code (ECC) portion) that the interface block 245-c may use to identify an error associated with the counter 380-b. In some examples, if portion 425-c indicates a counter error, interface block 245-c may reset both portion 425-a and portion 425-b. Reading the value of counter 380-b may include reading portions 425-a, 425-b, and 425-c. Interface block 245-c may compare portions 425-a and 425-b to first and second thresholds, respectively, and use portion 425-c to determine whether there is an error associated with counter 380-b.

[0082] The interface block 245-c may generate alarm signaling 415 according to various alarm types based on comparing the value of the counter 380-b to one or more thresholds or identifying an error in the counter 380-b. A first alarm type (e.g., RH1 alarm, RHALERT1) may be associated with the value of the counter 380-b (e.g., in portion 425-a) satisfying a first threshold. A second alarm type (e.g., RH2 alarm, RHALERT2) may be associated with the value of the counter 380-b (e.g., in portion 425-b) satisfying a second threshold. In some instances, the second threshold may be greater than the first threshold (e.g., may be a multiple of the first threshold), for example, based on the RH2 counter incrementing in response to the first threshold being satisfied. A third alarm type (e.g., counter error alarm, RHALERTERR) may be associated with the interface block 245-c identifying an error (e.g., permanent error, transient error) of the counter 380-b (e.g., indicated by portion 425-c). The fourth alarm type may be associated with the failure of the value of the counter 380-b to meet one or more thresholds (e.g., the first threshold and the second threshold) and the failure to identify an error of the counter 380-b. The interface block 245-c may transmit different alarm values ​​via the alarm signaling 415 (e.g., via, for example, an alarm pin of the bus 301) according to the different alarm types described herein. In some examples, if the value of the counter 380-b fails to meet one or more thresholds, the interface block 245-c may refrain from generating the alarm signaling 415 according to the fourth alarm type (e.g., no alarm). For example, the fourth alarm type may correspond to no alarm being sent.

[0083] In some examples, in addition to the four alarm types described (e.g., RH1 alarm, RH2 alarm, counter error alarm, fourth alarm), interface block 245-c and interface block 220-c may also support implementation of other alarm types. For example, one or more additional alarm types (e.g., row hammer 3 (Rh3) alarm, row hammer 4 (RH4) alarm, etc.) may be associated with the corresponding value of the counter satisfying one or more additional corresponding thresholds (e.g., third threshold, fourth threshold, etc.). In some examples, counter 380-b may include one or more additional portions 425 to track the corresponding number of row activations, the corresponding number of occurrences where the value of the counter satisfies one or more thresholds, or both. For example, additional portion 425 may track the number of occurrences where counter 380-b (e.g., portion 425-b) satisfies the second threshold.

[0084] The interface block 220-c may receive the alarm signaling 415 and may evaluate the alarm signaling 415. For example, the alarm signaling 415 may include different values ​​for different alarm types (e.g., RH1ALERT, RH2ALERT, RHALERTERR), and the interface block 220-c may generate and transmit the refresh signaling 420 (e.g., for one or more refresh operations) to the interface block 245-c based on the alarm type. For example, if the alarm signaling 415 indicates a two-bit value for an alarm, a value of '00' may correspond to (e.g., indicate) a fourth alarm type (e.g., no alarm, continue operation), a value of '01' may correspond to a first alarm type, a value of '10' may correspond to a second alarm type, and a value of '11' may correspond to a third alarm type (e.g., error), although other numbers of bits and other bit value combinations may be implemented to indicate an alarm type.

[0085] The interface block 220-c may determine which row 405-a (e.g., the aggressor row) is associated with the alarm signaling 415 based on a duration (e.g., a number of clock cycles) between transmitting the access signaling 410 and receiving the alarm signaling 415 (e.g., the timing of the alarm signaling 415 may be deterministic). For example, a row hammer alarm may be asserted according to a deterministic duration (e.g., a number of clock cycles, such as 13 command clock cycles) after the access signaling 410 (e.g., the activate command) is transmitted to the interface block 245-c (e.g., the alarm signaling 415 may be transmitted to the interface block 220-c). Thus, the interface block 220-c may determine the row 405-a for which the alarm signaling 415 is indicating an alarm based on having issued the access signaling 410 to the row 405-a (e.g., the number of clock cycles before receiving the alarm signaling 415).

[0086] The refresh signaling 420 may include one or more refresh commands (e.g., targeted auto-refresh (TAREF) commands) for one or more rows 405-a based on the alarm type. Each refresh command may indicate one or more parameters (e.g., PC, memory bank address, victim row address) associated with the one or more rows 405-a to be refreshed. In some examples, if the alarm type is a first alarm type (e.g., RH1ALERT), the refresh signaling 420 may include multiple refresh commands (e.g., at least two refresh commands) for refreshing multiple rows 405-a that are close to (e.g., directly adjacent to, adjacent to) the row 405-a associated with the alarm signaling 415 (e.g., the aggressor row) (e.g., the row 405-a attacked by the row hammer). For example, if the alarm signaling 415 indicates the first alarm type associated with row 405-a-4, the interface block 220-c may issue corresponding refresh commands to rows 405-a-3 and 405-a-5 that are directly adjacent to row 405-a-4. In some examples, a single refresh command may indicate multiple rows 405 to be refreshed, and the interface block 220-c may issue a single refresh command to rows 405-a-3 and 405-a-5.

[0087] If the alarm type indicates a second alarm type (e.g., RH2ALERT) or a third alarm type (e.g., RHALERTERR), the refresh signaling 420 may include multiple sets of refresh commands (e.g., at least four respective refresh commands for four rows 405-a). For example, in response to the second alarm type being associated with row 405-a-4, the interface block 220-c may issue respective refresh commands to row 405-a-2, row 405-a-3, row 405-a-5, and row 405-a-6. In some examples, a single refresh command may indicate multiple rows 405 to be refreshed, and the interface block 220-c may issue one or more refresh commands to indicate the refresh of rows 405-a-2, 405-a-3, 405-a-5, and 405-a-6. In some examples, the second alarm type may cause additional rows 405-a to be refreshed relative to the first alarm type due to a higher number of activations (e.g., of row 405-a-4) associated with indicating the second alarm type relative to the first alarm type. For example, the higher number of activations may be associated with additional charge leakage from aggressor row 405-a, which may modify data in additional rows 405-a that are located farther away from aggressor row 405-a than adjacent victim rows 405-a associated with the first alarm type, for example. For example, the second alarm type may indicate that rows 405-a that are not directly adjacent to aggressor row 405-a may be affected by a row hammer attack on aggressor row 405-a. Thus, rows 405-a that are not directly adjacent to aggressor row 405-a may be indicated by alarm signaling 415 to be refreshed. In some instances, if the alarm type indicates an additional alarm type (e.g., a RH3 alarm, a RH4 alarm, etc.), then in addition to the row 405-a associated with the second alarm type indicated for refresh, the refresh signaling 420 may also indicate a refresh for other rows 405-a (e.g., rows 405-a-1, 405-a-7, etc.), for example due to a higher number of activations of the aggression rows 405-a associated with the additional alarm type.

[0088] In some examples, if the third alarm type is indicated, e.g., due to an error in reading the value of the counter 380-b, it may be unclear whether the first threshold is met, the second threshold is met, or neither the first nor the second threshold is met. Thus, the interface block 245-c may assume that the second threshold is met (e.g., as a conservative assumption) and issue a refresh command to refresh both the directly adjacent and non-directly adjacent rows 405-a to, e.g., support robust row hammer mitigation when an error occurs. If the alarm type is a fourth alarm type (e.g., indicating no alarm and no counter error), the interface block 220-c may not generate the refresh signaling 420.

[0089] Supporting various alarm types for row hammer mitigation operations described herein may improve the robustness of row hammer mitigation techniques, improve system security and data protection against row hammer attacks, and improve performance of row hammer mitigation operations. For example, supporting the second alarm type and issuing a refresh command to a non-directly adjacent row 405-a may prevent a relatively long and sustained row hammer attack on the aggressor row 405-a, which may affect the non-directly adjacent row 405-a in addition to the directly adjacent row 405-a. Additionally or alternatively, supporting the first alarm type and issuing a refresh command to the directly adjacent row 405-a may reduce the number of rows 405-a that are refreshed relative to the second alarm type, which may reduce latency or power consumption associated with row hammer mitigation. Furthermore, supporting the third type of alarm may protect against row hammer attacks when a counter error occurs.

[0090] The interface block 220-c may receive multiple alarms for multiple rows 405-a. In some examples, the multiple rows 405-a associated with the multiple alarms may have addresses that are close to each other (e.g., adjacent). In such examples, the interface block 220-c may reduce the number of refresh commands of the refresh signaling 420. For example, the interface block 220-c may receive a first alarm for row 405-a-4 with a first alarm type and a second alarm for row 405-a-5 with a first alarm type, which may result in refresh commands for row 405-a-3 and row 405-a-5 (associated with row 405-a-4) and for row 405-a-4 and row 405-a-6 (associated with row 405-a-5). However, interface block 220-c may exclude refresh commands for row 405-a-4 and row 405-a-5 from refresh signaling 420 based on row 405-a-4 being adjacent to row 405-a-5.

[0091] In some examples, the refresh signaling 420 may additionally or alternatively include a refresh command (e.g., an auto-refresh (AREF) command) that is not directed to a specific row 405-a, but may instruct the interface block 245-c to refresh multiple rows 405-a (e.g., of memory banks). For example, the interface block 220-c may periodically issue such refresh commands to maintain the status of the multiple rows (e.g., as part of a system maintenance procedure). Such refresh commands may indicate one or more parameters (e.g., PC, memory bank address) of the multiple rows 405-a.

[0092] In some examples, the refresh signaling 420 may be based on whether the row 405-a associated with the alert signaling 415 is a spare row (e.g., a repair row). For example, the access signaling 410 may indicate accessing a row 405-a that is a spare row (e.g., a redundant row, a replacement row), which may be physically located away from other rows 405-a of the memory array 250-c (e.g., in a different memory array 250, in a different portion of the memory array 250), but may be logically located adjacent to one or more of the other rows 405-a.

[0093] In response to receiving the refresh signaling 420, the interface block 245-c may perform one or more refresh operations based on the indication included in the refresh signaling 420. In some examples, the interface block 245-c may also increment the corresponding counter 380-b associated with the row 405-a refreshed according to the one or more refresh commands. For example, if the refresh signaling 420 includes a target refresh command (e.g., a TAREF command) for row 405-a-3, the interface block 245-c may also increment the associated counter 380-b-3 because performing a refresh of row 405-a-3 may include activating row 405-a-3. In some cases, if the refresh command is an auto-refresh command (e.g., an AREF command), the interface block 245-c may reset the counter 380-b (e.g., both the RH1 counter and the RH2 counter) corresponding to the row 405-a associated with the auto-refresh command (e.g., and may not increment the counter 380-b).

[0094] Figure 5 An example of an architecture 500 that supports row hammer mitigation of a stacked memory architecture according to examples disclosed herein is shown. The architecture 500 may illustrate a portion of a die 240. For example, the architecture 500 illustrates an example of a control region 505 (e.g., of an interface block 245) that includes control logic 510. In some examples, the control logic 510 may include or may be an example of a control interface 310, an interface controller 320, or a combination thereof. In some examples, the control region 505 may be a region of the die 240 (e.g., an interface block 245) that includes bank logic. The control region 505 may be associated with one or more memory arrays 250-d (e.g., arranged according to channel pairs). For example, the control logic 510 may control access to various regions of the memory array 250-d (e.g., one or more counter regions 515-a, one or more redundant regions 520-a, one or more ECC regions 525-a, and one or more memory regions 540-a), where each region is associated with a corresponding access line 530-a (e.g., GIO).

[0095] The counter region 515-a may be a portion of the memory array 250-d for maintaining the counter 380. For example, the memory cells of the counter region 515-a may be accessed to read and write the value of the counter 380 to support the row hammer mitigation operations described herein. The redundant region 520-a may be a portion of the memory array 250-d including redundant memory cells, such as spare rows. The ECC region 525-a may be a portion of the memory array 250-d in which information associated with ECC operations, such as parity bits, may be stored. The memory region 540-a may be a portion of the memory array 250-d for storing data to the memory cells of the memory region 540-a.

[0096] In some implementations, the memory array 250-d may include one or more counters 380 (e.g., to support row hammer mitigation operations). In some cases, to access the one or more counters 380, the device may use an access line 530-a (e.g., access line 530-a-1) shared with data signaling associated with the memory array 250-d or other access lines 530-a associated with other regions. However, using shared access lines (e.g., access line 530-a) may increase latency and signaling overhead in the memory system.

[0097] According to the techniques described herein, the control logic 510 may be operable to couple (e.g., directly couple) with the counter region 515-a via a conductive line 535-a coupled to a dedicated access line 530-a. For example, the memory array 250-d may include a dedicated access line 530-a (e.g., a dedicated GIO line, a dedicated column line, a dedicated bus) coupled to the memory cells of the counter region 515-a, and the control logic 510 may access the memory cells via the conductive line 535-a. For example, the control logic 510 may directly access the counter 380 (e.g., rather than accessing the counter 380 via the access line 530-a of other regions) using the conductive line 535-a and the access line 530-a (e.g., the access line 530-a-4 coupled to the counter region 515-a-1, the access line 530-a-5 coupled to the counter region 515-a-2).

[0098] In some examples, the interface block 245 may read the counter 380 via the conductive line 535-a and the access line 530-a using the control logic 510 based on receiving access signaling for a row of the memory array 250-d. In some examples, the counter section 515-a may include a column decoder (e.g., a dedicated column decoder), and the control logic 510 may access the counter 380 of the counter section 515-a via the column decoder using the dedicated access line 530-a. The control logic 510 may increment the value of the counter 380 based on the interface block 245 accessing the row of the memory array 250-d associated with the counter 380 (e.g., using a word line spanning the memory section 540, the ECC section 525, the redundant section 520, and the counter section 515). The control logic 510 may compare the value of the counter 380 (e.g., after incrementing) to one or more thresholds (e.g., as referenced Figure 4 ), and the interface block 245 may transmit an alarm signaling based on the comparison (e.g., to the interface block 220). The control logic 510 may write the incremented value back to the counter 380 via the conductive line 535-a and the access line 530-a. Thus, the dedicated conductive line 535-a and the access line 530-a may improve reliability and reduce delays associated with the row hammer mitigation procedure.

[0099] Figure 6 A block diagram 600 is shown of a logic die 620 (eg, die 205) supporting row hammer mitigation of a stacked memory architecture according to examples disclosed herein. The logic die 620 may be a reference Figures 1 to 5 20. The logic die 620 or various components thereof (e.g., interface block 220) may be examples of means for performing various aspects of row hammer mitigation of the stacked memory architecture described herein. For example, the logic die 620 (e.g., interface block 220) may include an access signaling component 625, an alert signaling component 630, a refresh signaling component 635, a command generation component 640, a row determination component 645, or any combination thereof. Components of each of these components or subcomponents thereof (e.g., one or more processors, one or more memories) may communicate directly or indirectly with each other (e.g., via one or more buses).

[0100] The access signaling component 625 may be configured as or otherwise support means for transmitting first signaling (e.g., one or more first signals, a first signal) including a first command to activate a row of a memory array of a second semiconductor die (e.g., array die, die 240) coupled to a first semiconductor die (e.g., logic die 620) from a first interface (e.g., interface block 220) of the first semiconductor die to a second interface (e.g., interface block 245) of the second semiconductor die. The alarm signaling component 630 may be configured as or otherwise support means for receiving, at the first interface, second signaling (e.g., one or more second signals, a second signal) including an alarm message associated with a row hammer mitigation operation associated with the row of the memory array from the second interface based on transmitting the first signaling. The refresh signaling component 635 may be configured as or otherwise support means for transmitting third signaling (e.g., one or more third signals, a third signal) including a second command to refresh one or more rows of the memory array adjacent to the row of the memory array based on the alarm message from the first interface to the second interface.

[0101] In some examples, the command generation component 640 may be configured as or otherwise support means for generating, by the first interface, third signaling including a second command indicating a refresh of a first row of the memory array adjacent to the row and a second row of the memory array based on an alert message indicating that a number of activations of the row satisfies a first threshold.

[0102] In some examples, the command generation component 640 may be configured as or otherwise support means for generating, by the first interface, third signaling including a second command that indicates refreshing of a first group of rows and a second group of rows of a memory array adjacent to the row based on an alarm message indicating that a number of activations of the row satisfies a second threshold greater than the first threshold or indicating an error associated with a counter used to count activations of the row.

[0103] In some examples, row determination component 645 can be configured or otherwise support means for determining, by the first interface, that the second signaling is associated with a row based on a duration between transmitting the first signaling and receiving the second signaling.

[0104] In some examples, the alarm signaling component 630 can be configured to or otherwise support means for receiving, at the first interface, from the second interface, a second alarm message associated with a second row hammer mitigation operation associated with a second row adjacent to the row. In some examples, the third signaling is transmitted based on receiving the alarm message and the second alarm message.

[0105] In some examples, the second command to refresh the one or more rows is based on whether the row is a spare row of the memory array.

[0106] In some examples, the described functionality of logic die 620 or its various components may be supported by or may refer to at least a portion of at least one processor, where such at least one processor may include one or more processing elements (e.g., a controller, a microprocessor, a microcontroller, a digital signal processor, a state machine, discrete gate logic, discrete transistor logic, discrete hardware components, or any combination of one or more of such elements). In some examples, the described functionality of logic die 620 or its various components may be implemented at least in part by instructions (e.g., stored in a memory, a non-transitory computer-readable medium) that are executable by such at least one processor.

[0107] Figure 7 A block diagram 700 is shown of an array die 720 (eg, die 240) supporting row hammer mitigation of a stacked memory architecture according to examples disclosed herein. The array die 720 may be a reference Figures 1 to 5 720 or various components thereof (e.g., interface block 245) may be examples of means for performing various aspects of row hammer mitigation of stacked memory architectures described herein. For example, array die 720 (e.g., interface block 245) may include access signaling component 725, counter operation component 730, alarm signaling component 735, refresh component 740, or any combination thereof. Components of each of these components or subcomponents thereof (e.g., one or more processors, one or more memories) may communicate directly or indirectly with each other (e.g., via one or more buses).

[0108] The access signaling component 725 may be configured as or otherwise support means for receiving, at a second interface (e.g., interface block 245) of a second semiconductor die (e.g., array die 720), from a first interface (e.g., interface block 220) of a first semiconductor die (e.g., logic die, die 205) operable to couple with the second semiconductor die, first signaling (e.g., one or more first signals, a first signal) including a first command to activate a row of a memory array of the second semiconductor die. The counter operation component 730 may be configured as or otherwise support means for incrementing, by the second interface, a value of a counter associated with a row based on activating the row according to the first signaling. In some examples, the counter operation component 730 may be configured as or otherwise support means for reading, by the second interface, the value of the counter after incrementing the value of the counter. The alarm signaling component 735 may be configured as or otherwise support means for transmitting second signaling (e.g., one or more second signals, a second signal) including an alarm message associated with a row hammer mitigation operation associated with the row based on the value of the read counter from the second interface to the first interface.

[0109] In some examples, the refresh component 740 may be configured as or otherwise support means for receiving, at the second interface, from the first interface, a third signaling (e.g., one or more third signals, a third signal) including a second command to refresh one or more rows of the memory array adjacent to the row of the memory array based on the alert message. In some examples, the refresh component 740 may be configured as or otherwise support means for refreshing the one or more rows based on the second command.

[0110] In some examples, the alarm message indicates that the value of the counter satisfies a first threshold. In some examples, the counter operation component 730 may be configured to or otherwise support means for: resetting a first portion of the counter based on the value of the counter satisfying the first threshold; and incrementing a second portion of the counter based on resetting the first portion of the counter.

[0111] In some examples, the alarm message indicates that the value of the counter satisfies a second threshold greater than the first threshold.In some examples, the counter operation component 730 can be configured or otherwise support means for resetting the counter based on the value of the counter satisfying the second threshold.

[0112] In some examples, the alarm message indicates an error associated with the counter.In some examples, the counter operation component 730 can be configured or otherwise support means for resetting the counter based on identifying an error.

[0113] In some examples, the described functionality of array die 720 or its various components may be supported by or may refer to at least a portion of at least one processor, where such at least one processor may include one or more processing elements (e.g., a controller, a microprocessor, a microcontroller, a digital signal processor, a state machine, discrete gate logic, discrete transistor logic, discrete hardware components, or any combination of one or more of such elements). In some examples, the described functionality of array die 720 or its various components may be implemented at least in part by instructions (e.g., stored in a memory, a non-transitory computer-readable medium) that are executable by such at least one processor.

[0114] Figure 8 A flow chart illustrating a method 800 for supporting row hammer mitigation of a stacked memory architecture according to examples disclosed herein is shown. The operations of the method 800 may be implemented by a logic die (e.g., die 205) or a component thereof (e.g., interface block 220) described herein. For example, the operations of the method 800 may be implemented by reference to Figures 1 to 6 The logic die described herein performs. In some examples, the logic die may execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the logic die may use dedicated hardware to perform aspects of the described functions.

[0115] At 805, the method may include transmitting one or more first signals including a first command to activate a row of a memory array of a second semiconductor die coupled to a first semiconductor die (e.g., a logic die) from a first interface of the first semiconductor die to a second interface of the second semiconductor die. For example, the die 205 may include an interface block 220 that transmits (e.g., via bus 221, bus 301) access signaling 410 to activate a row 405 of the memory array 250 to an interface block 245 of the die 240. In some examples, aspects of operation 805 may be referred to as Figure 6 The access signaling component 625 described above performs the above.

[0116] At 810, the method may include receiving, at the first interface, one or more second signals from the second interface including an alarm message associated with a row hammer mitigation operation associated with a row of the memory array based on transmitting the one or more first signals. For example, the interface block 220 of the die 205 may receive (e.g., via the bus 221, the bus 301) the alarm signaling 415 from the interface block 245 of the die 240 for a row hammer mitigation operation associated with the row 405 of the memory array 250. In some examples, aspects of operation 810 may be referred to as Figure 6 The warning signaling component 630 described above performs.

[0117] At 815, the method may include transmitting, from the first interface to the second interface, one or more third signals including a second command to refresh one or more rows of the memory array adjacent to the row of the memory array based on the alert message. For example, the interface block 220 of the die 205 may transmit (e.g., via the bus 221, the bus 301) to the interface block 245 of the die 240 refresh signaling 420 indicating a refresh operation of the one or more rows 405 of the memory array 250. In some examples, aspects of operation 815 may be referred to as Figure 6 The refresh signaling component 635 described above performs the above.

[0118] In some examples, the apparatus described herein may perform one or several methods, such as method 800. The apparatus may include features, circuitry, logic, means, or instructions (such as a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following aspects of the present disclosure, or any combination thereof:

[0119] Aspect 1: A method, apparatus, or non-transitory computer-readable medium comprising operations, features, circuit systems, logic, means, or instructions, or any combination thereof, for: transmitting one or more first signals comprising a first command to activate a row of a memory array of a second semiconductor die coupled to a first semiconductor die from a first interface of the first semiconductor die to a second interface of the second semiconductor die; receiving, at the first interface, one or more second signals comprising an alarm message associated with a row hammer mitigation operation associated with the row of the memory array from the second interface based on transmitting the one or more first signals; and transmitting one or more third signals comprising a second command to refresh one or more rows of the memory array adjacent to the row of the memory array from the first interface to the second interface based on the alarm message.

[0120] Aspect 2: The method, apparatus or non-transitory computer-readable medium according to Aspect 1, further comprising the following operations, features, circuit systems, logic, components or instructions or any combination thereof: generating, by the first interface, the one or more third signals comprising the second command, the second command indicating a refresh of a first row of the memory array adjacent to the row and a second row of the memory array based on the alarm message indicating that the number of activations of the row satisfies a first threshold.

[0121] Aspect 3: A method, apparatus or non-transitory computer-readable medium according to any one of Aspects 1 to 2, further comprising the following operations, features, circuit systems, logic, components or instructions or any combination thereof: generating the one or more third signals including the second command by the first interface, the second command indicating that a first group of rows and a second group of rows of the memory array adjacent to the row are refreshed based on the alarm message indicating that the number of activations of the row satisfies a second threshold greater than the first threshold or indicating an error associated with a counter used to count activations of the row.

[0122] Aspect 4: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 3, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: determining by the first interface that the one or more second signals are associated with the row based on the duration between transmitting the one or more first signals and receiving the one or more second signals.

[0123] Aspect 5: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 4, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: receiving, at the first interface, from the second interface, a second alarm message associated with a second row hammer mitigation operation associated with a second row adjacent to the row, and wherein the one or more third signals are transmitted based on receiving the alarm message and the second alarm message.

[0124] Fig. 9 A flowchart illustrating a method 900 for supporting row hammer mitigation of a stacked memory architecture according to examples disclosed herein is shown. The operations of the method 900 may be implemented by an array die (e.g., die 240) or a component thereof (e.g., interface block 245) described herein. For example, the operations of the method 900 may be implemented by reference to Figures 1 to 5 7 and the array die described in . In some examples, the array die may execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the array die may use dedicated hardware to perform aspects of the described functions.

[0125] At 905, the method may include receiving, at a second interface of a second semiconductor die (e.g., an array die), from a first interface of a first semiconductor die operable to couple with the second semiconductor die, one or more first signals including a first command to activate a row of a memory array of the second semiconductor die. For example, the interface block 245 of the die 240 may receive (e.g., via bus 246, bus 301) access signaling 410 to activate row 405 of the memory array 250 from the interface block 220 of the die 205. In some examples, aspects of operation 905 may be described with reference to FIG. Figure 7 The access signaling component 725 described above performs the above.

[0126] At 910, the method may include incrementing, by the second interface, a value of a counter associated with a row based on activating the row according to the one or more first signals. For example, interface block 245 of die 240 may increment a value of counter 380 based on activating row 405 according to access signaling 410. In some examples, aspects of operation 910 may be described by reference to Figure 7 The counter operation component 730 described above performs the above.

[0127] At 915, the method may include reading the value of the counter by the second interface after incrementing the value of the counter. For example, the interface block 245 of the die 240 may read the value of the counter 380 after incrementing the counter 380. In some examples, aspects of operation 915 may be referred to as Figure 7 The counter operation component 730 described above performs the above.

[0128] At 920, the method may include transmitting one or more second signals including an alarm message associated with a row hammer mitigation operation associated with the row from the second interface to the first interface based on the value of the read counter. For example, the interface block 245 of the die 240 may transmit the alarm signaling 415 indicating the alarm message associated with the row hammer mitigation operation to the interface block 220 of the die 205 (e.g., via the bus 246, the bus 301) based on the value of the read counter 380. In some examples, aspects of operation 920 may be referred to as Figure 7 The warning signaling component 735 described above performs the above.

[0129] In some examples, the apparatus described herein may perform one or several methods, such as method 900. The apparatus may include features, circuitry, logic, means, or instructions (such as a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following aspects of the present disclosure, or any combination thereof:

[0130] Aspect 6: A method, apparatus, or non-transitory computer-readable medium comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: receiving, at a second interface of a second semiconductor die from a first interface of a first semiconductor die operable to couple with the second semiconductor die, one or more first signals comprising a first command to activate a row of a memory array of the second semiconductor die; incrementing, by the second interface, a value of a counter associated with the row based on activating the row according to the one or more first signals; reading, by the second interface, the value of the counter after incrementing the value of the counter; and transmitting, from the second interface to the first interface, one or more second signals comprising an alarm message associated with a row hammer mitigation operation associated with the row based on reading the value of the counter.

[0131] It should be noted that the methods described herein describe possible implementations, and that the operations and steps may be rearranged or otherwise modified and other implementations are possible. Furthermore, portions from two or more of the methods may be combined.

[0132] An apparatus is described. The following provides an overview of aspects of the apparatus described herein:

[0133] Aspect 7: An apparatus comprising: a first semiconductor die comprising: a first interface, the first interface comprising a first circuit system operable to transmit one or more access signals; and a second semiconductor die coupled to the first semiconductor die, the second semiconductor die comprising: one or more memory arrays; and a second interface coupled to the first interface and the one or more memory arrays, the second interface comprising a second circuit system operable to access the one or more memory arrays based on receiving the one or more access signals, wherein the apparatus is operable to: transmit one or more first signals from the second interface to the first interface based on a value of a counter associated with a number of access operations to the one or more memory arrays; transmit one or more second signals indicating refresh operations associated with one or more addresses of the one or more memory arrays from the first interface to the second interface based on the first interface receiving the one or more first signals; and perform the refresh operation by the second interface based on the second interface receiving the one or more second signals.

[0134] Aspect 8: The apparatus of aspect 7, wherein the second circuitry of the second interface is further operable to: compare the value of the counter to one or more thresholds; and transmit the one or more first signals to the first interface based on the comparison.

[0135] Aspect 9: An apparatus according to Aspect 8, wherein the second circuit system of the second interface is further operable to: read the value of the counter based on receiving the one or more access signals from the first interface; increment the value of the counter based on accessing the one or more memory arrays, wherein the value of the counter is compared with the one or more thresholds after the increment; and write the incremented value to the counter.

[0136] Aspect 10: An apparatus according to any one of Aspects 7 to 9, wherein the second circuit system of the second interface is further operable to: perform one or more access operations on addresses of the one or more memory arrays; and perform one or more operations concurrently with performing the one or more access operations to use the counter to track the number of access operations to the addresses.

[0137] Aspect 11: The apparatus of any of aspects 7 to 10, wherein the one or more first signals are transmitted based on the value of the counter indicating that a number of access operations to addresses of the one or more memory arrays satisfies one or more thresholds.

[0138] Aspect 12: An apparatus according to Aspect 11, wherein the one or more first signals indicate that the value of the counter satisfies a first threshold among the one or more thresholds, and the apparatus is further operable to: reset the first part of the counter by the second interface based on the value of the counter satisfying the first threshold; increment the second part of the counter by the second interface based on the value of the counter satisfying the first threshold; and generate the one or more second signals indicating the refresh operation by the first interface, wherein the refresh operation is based on the one or more first signals indicating that the value of the counter satisfies the first threshold and is for a second address different from the address and a third address different from the address.

[0139] Aspect 13: An apparatus according to Aspect 11, wherein the one or more first signals indicate that the value of the counter satisfies a second threshold among the one or more thresholds that is greater than a first threshold among the one or more thresholds, and the apparatus is further operable to: reset the counter by the second interface based on the value of the counter satisfying the second threshold; and generate the one or more second signals indicating that the refresh operation is for a first group of addresses different from the address and a second group of addresses different from the address based on the one or more first signals indicating that the value of the counter satisfies the second threshold.

[0140] Aspect 14: An apparatus according to Aspect 11, wherein the one or more first signals indicate an error associated with the counter, and the apparatus is further operable to: reset the counter based on the error by the second interface; and generate the one or more second signals indicating that the refresh operation is for a first group of addresses different from the address and a second group of addresses different from the address based on the one or more first signals indicating the error by the first interface.

[0141] Aspect 15: An apparatus according to any one of Aspects 7 to 14, wherein the first circuit system of the first interface is further operable to determine addresses of the one or more memory arrays associated with the one or more first signals based on a duration between transmitting the one or more access signals from the first interface and receiving the one or more first signals from the second interface.

[0142] Aspect 16: An apparatus according to any one of Aspects 7 to 15, wherein the one or more first signals are associated with a first address of the one or more memory arrays and a second address of the one or more memory arrays adjacent to the first address, and wherein the first circuit system of the first interface is operable to: determine, based on the proximity of the first address to the second address, that the one or more addresses used for the refresh operation are adjacent to the first address or the second address and do not include the first address and the second address.

[0143] Aspect 17: An apparatus according to any one of Aspects 7 to 16, wherein the apparatus is further operable to: transmit one or more third signals indicating a second refresh operation associated with a set of addresses of the one or more memory arrays from the first interface to the second interface; and reset, by the second interface, a corresponding counter associated with each address in the set of addresses based on the one or more third signals.

[0144] Clause 18: The apparatus of any of clauses 7 to 17, wherein the second signaling indicating the refresh operation is based on the one or more addresses being associated with a spare row of the one or more memory arrays.

[0145] Aspect 19: The apparatus of any of aspects 7 to 18, wherein the second semiconductor die comprises: the counter; and one or more dedicated access lines coupled with the second interface for accessing the counter.

[0146] An apparatus is described. The following provides an overview of aspects of the apparatus described herein:

[0147] Aspect 20: An apparatus comprising: a first semiconductor die comprising a first interface, the first interface comprising a circuit system operable to: transmit one or more first signals comprising a first command to activate a row of a memory array of the second semiconductor die to a second interface of a second semiconductor die coupled to the first semiconductor die; receive one or more second signals comprising an alarm message associated with a row hammer mitigation operation associated with the row of the memory array from the second interface based on transmitting the one or more first signals; and transmit one or more third signals comprising a second command to refresh one or more rows of the memory array adjacent to the row of the memory array based on the alarm message to the second interface.

[0148] Aspect 21: An apparatus according to Aspect 20, wherein the circuit system of the first interface is operable to: generate the third signaling including the second command, the second command indicating refreshing a first row of the memory array and a second row of the memory array that are different from the row based on the alarm message indicating that the number of activations of the row satisfies a first threshold.

[0149] Aspect 22: An apparatus according to Aspect 20, wherein the circuit system of the first interface is operable to: generate the third signaling including the second command, the second command indicating a refresh of a first group of rows and a second group of rows of the memory array different from the row based on the alarm message indicating that the number of activations of the row satisfies a second threshold greater than the first threshold or indicating an error associated with a counter used to count activations of the row.

[0150] Aspect 23: The apparatus of any of aspects 20 to 22, wherein the circuitry of the first interface is operable to: determine that the second signaling is associated with the row based on a duration between transmitting the first signaling and receiving the second signaling.

[0151] Aspect 24: An apparatus according to any one of Aspects 20 to 23, wherein the circuit system operable to transmit the third signaling is further operable to: transmit the third signaling based on receiving the alarm message and receiving a second alarm message associated with a second row hammer mitigation operation associated with a second row adjacent to the row.

[0152] Aspect 25: The apparatus of any of aspects 20 to 24, wherein the second command to refresh the one or more rows is based on whether the row is a spare row of the memory array.

[0153] An apparatus is described. The following provides an overview of aspects of the apparatus described herein:

[0154] Aspect 26: A device comprising: a second semiconductor die comprising a second interface, the second interface comprising a circuit system operable to: receive first signaling including a command to activate a row of a memory array of the second semiconductor die from a first interface of a first semiconductor die; increment a value of a counter associated with the row based on activating the row according to the first signaling; read the value of the counter after incrementing the value of the counter; and transmit second signaling including an alarm message associated with a row hammer mitigation operation associated with the row to the first interface based on reading the value of the counter.

[0155] Aspect 27: An apparatus according to Aspect 26, wherein the circuit system of the second interface is further operable to: receive third signaling from the first interface including a second command to refresh one or more rows of the memory array adjacent to the row of the memory array based on the alarm message; and refresh the one or more rows based on the second command.

[0156] Aspect 28: An apparatus according to any one of Aspects 26 to 27, wherein the alarm message indicates that the value of the counter satisfies a first threshold, and the circuit system of the second interface is further operable to: reset the first part of the counter based on the value of the counter satisfying the first threshold; and increment the second part of the counter based on resetting the first part of the counter.

[0157] Aspect 29: An apparatus according to any one of Aspects 26 to 27, wherein the alarm message indicates that the value of the counter satisfies a second threshold greater than the first threshold, and the circuit system of the second interface is further operable to: reset the counter based on the value of the counter satisfying the second threshold.

[0158] Aspect 30: The apparatus of any one of aspects 26 to 27, wherein the alarm message indicates an error associated with the counter, the circuitry of the second interface further operable to: reset the counter based on identifying the error.

[0159] The information and signals described herein may be represented using any of a variety of different techniques and technologies. For example, data, instructions, commands, information, signals, bits, or signaling symbols that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some figures may illustrate a signal as a single signal; however, a signal may represent a signal bus, where the bus may have various bit widths.

[0160] The terms "electronic communication," "conductive contact," "connection," and "coupling" may refer to a relationship between components that supports the flow of signals between the components. Components are considered to be in electronic communication (e.g., conductive contact, connection, coupling) with each other if there is any electrical path (e.g., conductive path) between the components that can support the flow of signals (e.g., charge, current, voltage) between the components at any time. At any given time, the conductive path between components that are in electronic communication (e.g., conductive contact, connection, coupling) with each other may be an open circuit or a closed circuit based on the operation of the device that includes the connected components. The conductive path between the connected components may be a direct conductive path between the components, or the conductive path between the connected components may be an indirect conductive path that may include intermediate components (e.g., switches, transistors, or other components). In some examples, the flow of signals between the connected components may be interrupted for a period of time, for example, using one or more intermediate components (e.g., switches or transistors).

[0161] The term "coupled" (e.g., "electrically coupled") may refer to a condition that transitions from an open-circuit relationship between components, where signals cannot currently be communicated between the components (e.g., via conductive paths), to a closed-circuit relationship between the components, where signals can be communicated between the components (e.g., via conductive paths). When a component, such as a controller, couples other components together, the component causes a change that allows signals to flow between the other components via conductive paths that previously did not allow signals to flow.

[0162] The term "isolation" refers to a relationship between components where a signal cannot currently flow between the components. Components are isolated from one another if an open circuit exists between the components. For example, when a switch positioned between two components is opened, the components separated by the switch are isolated from one another. When a controller isolates two components, the controller causes a change that prevents a signal from flowing between the components using a conductive path that previously permitted the signal to flow.

[0163] As used herein (including in the claims), the article "a" before a noun is open-ended and should be understood to refer to "at least one" of those nouns or "one or more" of those nouns. Therefore, the terms "one", "at least one", "one or more", and "at least one of one or more" are interchangeable. For example, if a claim recites "a component" that performs one or more functions, each of the individual functions may be performed by a single component or any combination of multiple components. Therefore, the term "a component" having a characteristic or performing a function may refer to "at least one of one or more components" having a specific characteristic or performing a specific function. The subsequent use of the term "the / said" to refer to a component introduced with the article "a" may refer to any or all of the one or more components. For example, a component introduced with the article "a" may be understood to mean "one or more components", and then referring to "the component" in the claim may be understood to be equivalent to referring to "at least one of one or more components".

[0164] The description set forth herein describes example configurations in conjunction with the accompanying drawings and does not represent all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration" rather than "preferred" or "superior to other examples". The "Detailed Description" includes specific details for providing an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some examples, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0165] In the accompanying drawings, similar components or features may have the same reference label. In addition, various components of the same type may be distinguished by following the reference label with a dash and a second label that distinguishes the similar components. If only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label, regardless of the second reference label.

[0166] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored as one or more instructions (e.g., code) on a computer-readable medium or transmitted via a computer-readable medium. Other examples and implementations are within the scope of the present disclosure and the appended claims. For example, due to the nature of software, the functions described herein may be implemented using software executed by a processor, hardware, firmware, hardwiring, or a combination of any of these. Features implementing the functions may also be physically located at various locations, including being distributed so that portions of the functions are implemented at different physical locations.

[0167] For example, the various descriptive blocks and modules described in connection with the present disclosure may be implemented or executed with a processor designed to perform the functions described herein, such as a DSP, ASIC, FPGA, discrete gate logic, discrete transistor logic, discrete hardware components, other programmable logic devices, or any combination thereof. A processor may be an example of a microprocessor, a controller, a microcontroller, a state machine, or any type of processor. A processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

[0168] As used herein (including in the claims), "or" used in a list of items (e.g., a list of items preceded by a phrase such as "at least one of" or "one or more of") indicates an inclusive list, so that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Moreover, as used herein, the phrase "based on" should not be interpreted as referring to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on."

[0169] Computer-readable media include both non-transitory computer storage media and communication media, including any media that facilitates the transfer of a computer program from one location to another. Non-transitory storage media may be any available media that can be accessed by a computer. For example, but not limited to, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disk (CD) ROM or other optical disk storage devices, magnetic disk storage devices or other magnetic storage devices or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and can be accessed by a computer or processor. Moreover, any connection is appropriately referred to as computer-readable media. For example, if the software is transmitted from a website, server or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technology (such as infrared, radio and microwave), then coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technology (such as infrared, radio and microwave) are included in the definition of media. As used herein, disk and disc include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0170] The description herein is provided to enable persons skilled in the art to make or use the present disclosure. Persons skilled in the art will appreciate various modifications of the present disclosure, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but should be given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A system comprising: A first semiconductor die comprising: a first interface comprising first circuitry operable to transmit one or more access signals; and a second semiconductor die coupled to the first semiconductor die, the second semiconductor die comprising: one or more memory arrays; and a second interface coupled to the first interface and the one or more memory arrays, the second interface comprising second circuitry operable to access the one or more memory arrays based on receiving the one or more access signals, Wherein the system is operable to: transmitting one or more first signals from the second interface to the first interface based on a value of a counter associated with a number of access operations to the one or more memory arrays; transmitting one or more second signals indicating a refresh operation associated with one or more addresses of the one or more memory arrays from the first interface to the second interface based on the first interface receiving the one or more first signals; and The refresh operation is performed by the second interface based on receiving the one or more second signals by the second interface.

2. The system of claim 1 , wherein the second circuitry of the second interface is further operable to: comparing the value of the counter to one or more thresholds; and The one or more first signals are transmitted to the first interface based on the comparison.

3. The system of claim 2, wherein the second circuitry of the second interface is further operable to: reading the value of the counter based on receiving the one or more access signals from the first interface; incrementing the value of the counter based on accessing the one or more memory arrays, wherein the value of the counter is compared to the one or more threshold values ​​after the incrementing; and The incremented value is written to the counter.

4. The system of claim 1 , wherein the second circuitry of the second interface is further operable to: performing one or more access operations on addresses of the one or more memory arrays; and Concurrently with performing the one or more access operations, one or more operations are performed to track a number of access operations to the address using the counter. 5 . The system of claim 1 , wherein the one or more first signals are transmitted based on the value of the counter indicating that a number of access operations to addresses of the one or more memory arrays satisfies one or more thresholds.

6. The system of claim 5, wherein the one or more first signals indicate that the value of the counter satisfies a first threshold of the one or more thresholds, the system further operable to: resetting, by the second interface, a first portion of the counter based on the value of the counter satisfying the first threshold; incrementing, by the second interface, a second portion of the counter based on the value of the counter satisfying the first threshold; and The one or more second signals are generated by the first interface to indicate the refresh operation for a second address different from the address and a third address different from the address based on the one or more first signals indicating that the value of the counter satisfies the first threshold.

7. The system of claim 5, wherein the one or more first signals indicate that the value of the counter satisfies a second threshold of the one or more thresholds that is greater than a first threshold of the one or more thresholds, the system further operable to: resetting, by the second interface, the counter based on the value of the counter satisfying the second threshold; and The one or more second signals indicating that the refresh operation is for a first set of addresses different from the address and a second set of addresses different from the address are generated by the first interface based on the one or more first signals indicating that the value of the counter satisfies the second threshold.

8. The system of claim 5, wherein the one or more first signals indicate an error associated with the counter, the system further operable to: resetting the counter by the second interface based on the error; and The one or more second signals indicating that the refresh operation is for a first set of addresses different from the address and a second set of addresses different from the address are generated by the first interface based on the one or more first signals indicating the error.

9. The system of claim 1 , wherein the first circuitry of the first interface is further operable to determine addresses of the one or more memory arrays associated with the one or more first signals based on a duration between transmitting the one or more access signals from the first interface and receiving the one or more first signals from the second interface.

10. The system of claim 1, wherein the one or more first signals are associated with a first address of the one or more memory arrays and a second address of the one or more memory arrays adjacent to the first address, and wherein the first circuitry of the first interface is operable to: The one or more addresses for the refresh operation are determined to be adjacent to the first address or the second address and exclude the first address and the second address based on the first address being adjacent to the second address.

11. The system of claim 1 , wherein the system is further operable to: transmitting one or more third signals indicative of a second refresh operation associated with a set of addresses of the one or more memory arrays from the first interface to the second interface; and A respective counter associated with each address in the set of addresses is reset by the second interface based on the one or more third signals.

12. The system of claim 1, wherein the one or more second signals indicative of the refresh operation are based on the one or more addresses being associated with a spare row of the one or more memory arrays.

13. The system of claim 1 , wherein the second semiconductor die comprises: the counter; and One or more dedicated access lines coupled to the second interface for accessing the counter.

14. An apparatus comprising: A first semiconductor die comprising a first interface including circuitry operable to: transmitting one or more first signals including a first command to activate a row of a memory array of the second semiconductor die to a second interface of a second semiconductor die coupled to the first semiconductor die; receiving from the second interface one or more second signals including an alert message associated with a row hammer mitigation operation associated with the row of the memory array based on transmitting the one or more first signals; and One or more third signals including a second command to refresh one or more rows of the memory array adjacent to the row of the memory array are transmitted to the second interface based on the alert message.

15. The apparatus of claim 14, wherein the circuitry of the first interface is operable to: The one or more third signals are generated including the second command indicating refreshing a first row of the memory array and a second row of the memory array different from the row based on the alarm message indicating that the number of activations of the row satisfies a first threshold.

16. The apparatus of claim 14, wherein the circuitry of the first interface is operable to: The one or more third signals include generating the second command, the second command indicating refreshing a first group of rows and a second group of rows of the memory array different from the row based on the alarm message indicating that the number of activations of the row satisfies a second threshold greater than the first threshold or indicating an error associated with a counter used to count activations of the row.

17. The apparatus of claim 14, wherein the circuitry of the first interface is operable to: The one or more second signals are determined to be associated with the row based on a duration between transmitting the one or more first signals and receiving the one or more second signals.

18. The apparatus of claim 14, wherein the circuitry operable to transmit the one or more third signals is further operable to: The one or more third signals are transmitted based on receiving the alarm message and receiving a second alarm message associated with a second row hammer mitigation operation associated with a second row adjacent to the row.

19. The apparatus of claim 14, wherein the second command to refresh the one or more rows is based on whether the row is a spare row of the memory array.

20. A method comprising: transmitting one or more first signals including a first command to activate a row of a memory array of a second semiconductor die coupled to the first semiconductor die from a first interface of the first semiconductor die to a second interface of the second semiconductor die; receiving, at the first interface, from the second interface one or more second signals including an alert message associated with a row hammer mitigation operation associated with the row of the memory array based on transmitting the one or more first signals; and One or more third signals including a second command to refresh one or more rows of the memory array adjacent to the row of the memory array are transmitted from the first interface to the second interface based on the alert message.

21. The method according to claim 20, further comprising: The one or more third signals including the second command are generated by the first interface, the second command indicating refreshing a first row of the memory array and a second row of the memory array adjacent to the row based on the alarm message indicating that the number of activations of the row meets a first threshold.

22. The method of claim 20, further comprising: The one or more third signals including the second command are generated by the first interface, the second command indicating that a first group of rows and a second group of rows of the memory array adjacent to the row are refreshed based on the alarm message indicating that the number of activations of the row satisfies a second threshold greater than the first threshold or indicating an error associated with a counter used to count activations of the row.

23. The method of claim 20, further comprising: It is determined, by the first interface, that the one or more second signals are associated with the row based on a duration between transmitting the one or more first signals and receiving the one or more second signals.

24. The method of claim 20, further comprising: receiving, at the first interface from the second interface, a second alarm message associated with a second row hammer mitigation operation associated with a second row adjacent to the row, The one or more third signals are transmitted based on receiving the alert message and the second alert message.

25. An apparatus comprising: a second semiconductor die comprising a second interface, the second interface comprising circuitry operable to: receiving from a first interface of a first semiconductor die one or more first signals including a command to activate a row of a memory array of the second semiconductor die; incrementing a value of a counter associated with the row based on activating the row in accordance with the one or more first signals; reading the value of the counter after incrementing the value of the counter; and One or more second signals including an alarm message associated with a row hammer mitigation operation associated with the row are transmitted to the first interface based on reading the value of the counter.

26. The apparatus of claim 25, wherein the circuitry of the second interface is further operable to: receiving from the first interface one or more third signals including a second command to refresh one or more rows of the memory array adjacent to the row of the memory array based on the alert message; and The one or more rows are refreshed based on the second command.

27. The apparatus of claim 25, wherein the alarm message indicates that the value of the counter satisfies a first threshold, the circuitry of the second interface further operable to: resetting a first portion of the counter based on the value of the counter satisfying the first threshold; and A second portion of the counter is incremented based on resetting the first portion of the counter.

28. The apparatus of claim 25, wherein the alarm message indicates that the value of the counter satisfies a second threshold greater than a first threshold, the circuitry of the second interface further operable to: The counter is reset based on the value of the counter satisfying the second threshold.

29. The apparatus of claim 25, wherein the alarm message indicates an error associated with the counter, the circuitry of the second interface further operable to: The counter is reset based on identifying the error.

30. A method comprising: receiving, at a second interface of a second semiconductor die from a first interface of a first semiconductor die operable to couple with the second semiconductor die, one or more first signals including a first command to activate a row of a memory array of the second semiconductor die; incrementing, by the second interface, a value of a counter associated with the row based on activating the row in accordance with the one or more first signals; reading the value of the counter by the second interface after incrementing the value of the counter; and One or more second signals including an alarm message associated with a row hammer mitigation operation associated with the row are transmitted from the second interface to the first interface based on reading the value of the counter.

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