System and method for performing read operations

Abstract

A memory device includes a memory array having memory cells, a page buffer coupled to the memory array through bit lines. The page buffer includes a latch and a control logic unit coupled to the page buffer and configured to: perform a first read operation on the memory cell; selecting a first plurality of memory cells in a first state and a second plurality of memory cells in a second state from among the memory cells based on the first read operation; performing a second read operation on the first plurality of memory cells; selecting a third plurality of memory cells from the first plurality of memory cells based on the second read operation; performing a third read operation on a third plurality of memory cells; and determine a read development time based on the third read operation.

Description

Technical Field

[0001] The present description relates generally to the field of semiconductor technology, and more particularly, to systems and methods for performing read operations in NAND memories. Background Art

[0002] As memory devices are shrinking to smaller die sizes to reduce manufacturing costs and increase storage density, scaling of planar memory cells faces challenges due to process technology limitations and reliability issues. For example, three-dimensional (3D) memory architectures can address density and performance limitations in planar memory cells.

[0003] In NAND flash memory, many layers of memory cells can be stacked vertically, so that the storage density per unit area can be greatly increased. Vertically stacked memory cells can form a storage string, in which the channels of the memory cells are connected in each storage string. Each memory cell can be addressed by a word line and a bit line. The data (i.e., logic state) of the memory cells in the entire storage page sharing the same word line can be read or programmed at the same time. However, due to the rapid scaling, reliability may be a concern for NAND flash memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and enable one or more persons skilled in the relevant art to make and use the present disclosure.

[0005] Figure 1 and Figure 2A-2B A memory system having one or more memory chips according to some embodiments is shown.

[0006] Figure 3 A schematic diagram of a memory device according to some embodiments is shown.

[0007] Figure 4 A schematic diagram of a memory device according to some embodiments is shown.

[0008] Figure 5 Schematic diagram showing exemplary threshold voltage distributions for a memory device according to some embodiments.

[0009] Fig. 6A An exemplary schematic circuit diagram of a memory device according to some embodiments is shown.

[0010] Figure 6B An exemplary schematic diagram of a page buffer of a memory device according to some embodiments is shown.

[0011] Figure 7 shows an example of a method according to some embodiments Figure 6B 0 is an exemplary signal waveform of the voltage level of the sensing node in .

[0012] Fig. 8A An exemplary method 800 of performing a read operation on a memory device is shown in accordance with some embodiments.

[0013] Figure 8B According to some embodiments, Fig. 8A Example threshold voltage distributions and data structures during a process flow in FIG.

[0014] When combined with the accompanying drawings, the features and advantages of the present disclosure will become more apparent from the specific embodiments described below, in which similar reference numerals identify corresponding elements in all the accompanying drawings. In the accompanying drawings, similar reference numerals generally indicate the same, functionally similar and / or structurally similar elements.

[0015] Aspects of the present disclosure will be described with reference to the accompanying drawings. DETAILED DESCRIPTION

[0016] Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. Those skilled in the relevant art will recognize that other configurations and arrangements may be used without departing from the spirit and scope of the present disclosure. It will be apparent to those skilled in the relevant art that the present disclosure may also be employed in various other applications.

[0017] It should be noted that references in the specification to "one embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," etc. indicate that the described embodiments may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, it is within the knowledge of a person skilled in the relevant art to implement such feature, structure, or characteristic in conjunction with other embodiments, whether or not explicitly described.

[0018] Typically, a term can be understood at least in part from usage in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least in part on the context, terms such as "one" or "the" can also be understood to convey singular usage or to convey plural usage. In addition, the term "based on" can be understood to not necessarily be intended to convey a collection of exclusive factors, but can allow for the presence of additional factors that are not necessarily explicitly described, which also depends at least in part on the context.

[0019] As used herein, the term "substrate" refers to a material on which subsequent material layers are added. The substrate includes a "top" surface and a "bottom" surface. The top surface of the substrate is typically where the semiconductor device is formed, and therefore, unless otherwise specified, the semiconductor device is formed on the top side of the substrate. The bottom surface is opposite to the top surface, and therefore, the bottom side of the substrate is opposite to the top side of the substrate. The substrate itself can be patterned. The material added on top of the substrate can be patterned or can remain unpatterned. In addition, the substrate can include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of a non-conductive material (such as glass, plastic or sapphire wafer).

[0020] As used herein, the term "layer" refers to a material portion including an area with thickness. The layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, and the top side is relatively far from the substrate. The layer can extend over the entire lower layer or overlying structure, or can have a range less than the range of the lower layer or overlying structure. In addition, the layer can be a region of a uniform or non-uniform continuous structure, which has a thickness less than the thickness of the continuous structure. For example, the layer can be located between the top surface and the bottom surface of the continuous structure or between any set of horizontal planes at the top surface and the bottom surface. The layer can extend horizontally, vertically and / or along a tapered surface. The substrate can be a layer, wherein one or more layers can be included, and / or one or more layers can be provided on it, above it and / or below it. The layer can include multiple layers. For example, the interconnect layer can include one or more conductive and contact layers (wherein contact portions, interconnect lines and / or vertical interconnect channels (VIA) are formed) and one or more dielectric layers.

[0021] As used herein, the term "nominal / nominal" refers to an expected value or target value for a characteristic or parameter set for a component or process step during the design phase of a product or process, as well as a range of values ​​above and / or below the expected value. The range of values ​​may be due to slight variations in manufacturing processes or tolerances. As used herein, the term "approximately" or "roughly" indicates a value of a given quantity that may vary based on a particular technology node associated with the subject semiconductor device. Based on a particular technology node, the term "approximately" or "roughly" may indicate a value of a given quantity that varies within, for example, 10-30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0022] Currently, in memory devices, especially in high-density memory devices, threshold voltage (Vt) distribution shift is a common and critical problem that may be affected by many factors, such as charge loss of programmed cells over time, noise, long NAND service life, etc. After the Vt distribution shifts, the predefined read level cannot track the Vt distribution, resulting in read failure. A system and method for performing a read operation in a NAND memory is needed to track the Vt distribution.

[0023] Figure 1 A block diagram of an electronic device S1 having a storage system 10 according to some embodiments is shown. In some embodiments, the electronic device S1 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a car computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having storage therein. The storage system 10 (e.g., a NAND storage system) may include a memory controller 20 and one or more semiconductor memory devices 25-1, 25-2, 25-3, ..., 25-n. Each semiconductor memory device 25 (hereinafter referred to as a "memory device") may be a NAND device (e.g., "flash memory", "NAND flash memory" or "NAND"). The storage system 10 may communicate with a host 15 through a memory controller 20, wherein the memory controller 20 may be connected to one or more memory chips 25-1, 25-2, 25-3, ..., 25-n via one or more storage channels 30-1, 30-2, 30-3, ..., 30-n. In some embodiments, each memory device 25 may be managed by the memory controller 20 via one or more memory channels 30 - 1 , 30 - 2 , 30 - 3 , . . . , 30 - n .

[0024] In some embodiments, the host 15 may include a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 15 may send data to be stored at the storage system 10 and / or retrieve data from the data stored in the storage system 10.

[0025] In some embodiments, the memory controller 20 may process I / O requests received from the host 15, ensure data integrity and efficient storage, and manage the memory device 25. To perform these tasks, the memory controller 20 may run firmware 21, which may be executed by one or more processors 22 (e.g., microcontroller unit, CPU) of the memory controller 20. For example, the memory controller 20 may run firmware 21 to map logical addresses (e.g., addresses associated with host data utilized by the host) to physical addresses in the memory device 25 (e.g., the actual location where the data is stored). The memory controller 20 also runs firmware 21 to manage defective memory blocks in the memory device 25, where the firmware 21 may remap logical addresses to different physical addresses, i.e., move data to different physical addresses. The memory controller 20 may also include one or more memories 23 (e.g., DRAM, SRAM, EPROM, etc.), which may be used to store various metadata used by the firmware 21. In some embodiments, the memory controller 20 may also perform error recovery through an error correction code (ECC) engine 29. ECC is used to detect and correct raw bit errors that occur within each memory device 25.

[0026] In some embodiments, the memory channel 30 may provide data and control communication between the memory controller 20 and each memory device 25 via a data bus. The memory controller 20 may select one of the memory devices 25 according to a chip enable signal.

[0027] In some embodiments, Figure 1 Each memory device 25 in may include one or more memory devices 100, wherein each memory device may be a NAND memory.

[0028] In some embodiments, the memory controller 20 and one or more memory devices 25 may be integrated into various types of storage devices, for example, included in the same package (e.g., a universal flash storage (UFS) package or an eMMC package). That is, the storage system 10 may be implemented and packaged into different types of terminal electronic products. Figure 2A In one example shown in FIG. 2 , the memory controller 20 and the single memory device 25 may be integrated into a memory card 26. The memory card 26 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 26 may also include a computer that connects the memory card 26 to a host (e.g., Figure 1The host 15) is coupled to the memory card connector 24. Figure 2B In another example shown in FIG. 1 , the memory controller 20 and the plurality of memory devices 25 may be integrated into a solid state drive (SSD) 27. The SSD 27 may also include a processor that connects the SSD 27 to a host (e.g., Figure 1 The SSD connector 28 is coupled to the host 15).

[0029] Figure 3 A top view of a memory device 100 is shown, according to some embodiments. Figure 3 The exemplary configurations shown in are given as non-limiting examples, and it should be understood that the memory is scalable. In some embodiments, the memory device 100 may include one or more memory planes 101, wherein each memory plane may include multiple memory blocks 103. The same and simultaneous operations may occur at each memory plane 101. A memory block 103, which may be megabytes (MB) in size, is the minimum size for performing an erase operation. For example, the memory device 100 may include four memory planes 101. For example, each memory plane 101 may include six memory blocks 103. Each memory block 103 may include multiple memory cells, wherein each memory cell may be addressed by interconnections (e.g., bit lines and word lines). The bit lines and word lines may be arranged vertically (e.g., in rows and columns, respectively), forming an array of metal lines. In Figure 3 In FIG. 1 , the directions of the bit lines and word lines are marked as “BL” and “WL”.

[0030] In some embodiments, the memory device 100 may also include a peripheral region 105, i.e., a region surrounding the memory plane 101. The peripheral region 105 may include many digital, analog, and / or mixed signal circuits for supporting the functions of the memory device, such as page buffers, row and column decoders, and sense amplifiers. As will be apparent to those of ordinary skill in the art, the peripheral circuits use active semiconductor devices and / or passive semiconductor devices, such as transistors, diodes, capacitors, resistors, etc.

[0031] In some embodiments, Figure 3 The arrangement of the memory planes 101 in the memory device 100 and the arrangement of the memory blocks 103 in each memory plane 101 shown in FIG. 1 are only used as examples, which do not limit the scope of the present disclosure.

[0032] Figure 4A schematic diagram of a memory device 100 according to some embodiments is shown. In some embodiments, the memory device 100 may include one or more memory blocks 103 (e.g., 103-1, 103-2, 103-3). Each memory block 103 may include a plurality of memory strings 212. Each memory string 212 includes a plurality of memory cells 340. The memory cells 340 sharing the same word line form a memory page 432. The memory string 212 may also include at least one field effect transistor (e.g., MOSFET) at each end, which is controlled by a lower select gate ("LSG") 332 and a top select gate ("TSG") 334, respectively. The lower select gate ("LSG") may also be referred to as a bottom select gate ("BSG"). The drain terminal of the top select transistor 334-T may be connected to a bit line 341, and the source terminal of the lower select transistor 332-T may be connected to an array common source ("ACS") 430. The ACS 430 may be shared by the memory strings 212 in the entire memory block and is also referred to as a common source line.

[0033] In some embodiments, the memory device 100 may also include peripheral circuits, which may include many digital, analog and / or mixed signal circuits for supporting the functions of the memory block 103, for example, a page buffer 52, a row decoder / word line driver 40, a column decoder / bit line driver 50, a controller 70, a voltage generator 65, and an input / output buffer 55. The controller 70 may include one or more control circuits. In some aspects, the controller 70 may include one or more registers, buffers, and / or memories to store one or more trim settings described in the present disclosure. As will be apparent to those of ordinary skill in the art, these circuits may include active semiconductor devices and / or passive semiconductor devices, such as transistors, diodes, capacitors, resistors, etc.

[0034] In some embodiments, the memory block 103 may be coupled to the row decoder / word line driver 40 via a word line ("WL") 333, a lower select gate ("LSG") 332, and a top select gate ("TSG") 334. The memory block 103 may be coupled to the page buffer 52 via a bit line ("BL") 341. The row decoder / word line driver 40 may select one of the memory blocks 103 on the memory device 100 in response to an X-path control signal provided by the controller 70. The row decoder / word line driver 40 may transfer a voltage provided from the voltage generator 65 to the word line according to the X-path control signal. During read and program operations, the row decoder / word line driver 40 may select a read voltage V read and programming voltage V pgm is transmitted to the selected word line and turns on the voltage Vpass sent to unselected word lines.

[0035] In some embodiments, the column decoder / bit line driver 50 can set the inhibit voltage V to inhibit Transfer to the unselected bit lines, and connect the selected bit lines to the ground. In other words, the column decoder / bit line driver 50 can be configured to select or deselect one or more storage strings 212 according to the Y path control signal from the controller 70. The page buffer 52 can be configured to read data from the storage block 103 and program (write) the data to the storage block 103 according to the Y path control signal from the controller 70. For example, the page buffer 52 can store data of one page to be programmed into one storage page 432. In another example, the page buffer 52 can perform a verification operation to ensure that the data has been properly programmed into each storage cell 340. In yet another example, during a read operation, the page buffer 52 can sense the current flowing through the bit line 341 reflecting the logical state (i.e., data) of the storage cell 340, and amplify the small signal to a measurable amplification rate.

[0036] In some embodiments, to increase the efficiency of the write operation, the column decoder / bit line driver 50 may set the bias voltage V to V according to the Y path control signal from the controller 70 and the data to be programmed from the page buffer 52. bias transferred to the selected bit line.

[0037] In some embodiments, the input / output buffer 55 can transfer I / O data from / to the page buffer 52 and transfer the address ADDR or command CMD to the controller 70. In some embodiments, the input / output buffer 55 can function as a memory controller 20 (in the memory device 25) Figure 1 The function of the interface between the memory device 100 and the memory device 100 is as follows.

[0038] In some embodiments, the controller 70 may control the page buffer 52 and the row decoder / word line driver 40 in response to a command CMD transmitted by the input / output buffer 55. During a programming operation, the controller 70 may control the row decoder / word line driver 40 and the page buffer 52 to program a selected memory cell. During a read operation, the controller 70 may control the row decoder / word line driver 40 and the page buffer 52 to read a selected memory cell. The X-path control signal and the Y-path control signal include a row address X-ADDR and a column address Y-ADDR that may be used to locate a selected memory cell in the memory block 103. The row address X-ADDR may include a page index PD, a block index BD, and a plane index PL to identify a memory page 432, a memory block 103, and a memory plane 101 (in Figure 3The column address Y-ADDR may identify a byte or word in the data of the storage page 432.

[0039] In some embodiments, the voltage generator 65 may generate voltages to be supplied to the word lines and the bit lines under the control of the controller 70. The voltages generated by the voltage generator 65 include a read voltage V read , programming voltage V pgm , on-state voltage V pass , Suppression voltage V inhibit , bit line bias voltage V bias wait.

[0040] Notice, Figure 1 , Figure 2A-2B and Figure 3-Figure 4 The arrangement of electronic components in the memory system 10 and the memory device 100 in FIG. 1 is shown as a non-limiting example. In some embodiments, the memory system 10 and the memory device 100 may have other layouts and may include additional components. Figure 4 The components shown on the memory device 100 (eg, the controller 70 , the I / O buffer 55 ) may also be moved out of the memory device 100 as independent electrical components in the memory system 10 . Figure 4 The components on the memory device 100 shown in FIG. 1 (eg, the controller 70 , the I / O buffer 55 ) may also be moved to other components in the storage system 10 , for example, a portion of the controller 70 may be combined with the memory controller 20 , and vice versa.

[0041] Figure 5 Schematic diagram showing exemplary threshold voltage distributions for a memory device according to some embodiments.

[0042] Back to Figure 4 In some embodiments, the memory block 103 may be formed based on floating gate technology. In some embodiments, the memory block 103 may be formed based on charge trapping technology. NAND flash memory based on charge trapping may provide high storage density and high inherent reliability. In a logical state (“state”, for example, the threshold voltage V th ) depends on the number of charge carriers trapped in the storage film of the memory cell 340.

[0043] In some embodiments, in a NAND flash memory, a read operation and a write operation (also referred to as a program operation) may be performed on a memory page 432 , and an erase operation may be performed on a memory block 103 .

[0044] In some embodiments, in a NAND memory, the memory cell 340 can be in an erased state ER or a programmed state P1. Initially, the memory cell 340 in the memory block 103 can be reset to an erased state as a logic "1" by implementing a negative voltage difference between the control gate 333 and the channel so that the charge carriers trapped in the storage film of the memory cell 340 can be removed. For example, the control gate 333 of the memory cell 340 can be set to ground and a high positive voltage (erase voltage V erase ) is applied to ACS 430 to induce a negative voltage difference. In the erased state ER (“state ER”), the threshold voltage V of the memory cell 340 can be th Reset to lowest value.

[0045] In some embodiments, during programming (ie, writing), a programming voltage V may be applied to control gate 333, for example. pgm (e.g., a positive voltage pulse between 10V and 20V) and grounding the corresponding bit line 341 determines a positive voltage difference between the control gate 333 and the channel. Thus, charge carriers (e.g., electrons) can be injected into the storage film of the memory cell 340, thereby increasing the threshold voltage V of the memory cell 340. th Thus, memory cell 340 may be programmed to programming state P1 ("state P1" or logic "0").

[0046] In some embodiments, the threshold voltage V of the memory cell may be measured or sensed. th During a read operation, a read voltage V may be applied to the control gate 333 of the memory cell. read , and the current flowing through the memory cell can be measured at the bit line 341. A turn-on voltage V can be applied to the unselected word lines. pass , to turn on the unselected storage cells.

[0047] In some embodiments, the NAND flash memory can be configured to operate in a single-level cell (SLC) mode. In order to increase the storage capacity, the NAND flash memory can also be configured to operate in a multi-level cell (MLC) mode, a triple-level cell (TLC) mode, a quad-level cell (QLC) mode, or a combination of any of these modes. In SLC mode, the memory cell stores 1 bit and has two logical states, logic {1 and 0}, i.e., states ER and S1. In MLC mode, the memory cell stores 2 bits and has four logical states, logic {11, 10, 01, and 00}, i.e., states ER, M1, M2, and M3. In TLC mode, the memory cell stores 3 bits and has eight logical states, logic {111, 110, 101, 100, 011, 010, 001, 000}, i.e., states ER and states T1-T7. In the QLC mode, the memory cell stores 4 bits and has 16 logic states, logic {1111, 1110, 1101, 1100, 1011, 1010, 1001, 1000, 0111, 0110, 0101, 0100, 0011, 0010, 0001, 0000}, i.e., state ER and states Q1-Q15. The memory controller 20 of the memory system 10 (see Figure 1 ) can convert data received from the host 15 into corresponding logical states of storage cells on the memory device 100, and vice versa.

[0048] In some aspects of the QLC mode, states P1-P15 correspond to states Q1-Q15. In some aspects, each state of the memory cell may correspond to a threshold voltage V th A specific range, where the threshold voltage V th The distribution can be represented by a probability density. In some aspects, an incremental step pulse programming (ISPP) scheme can be used to program states other than the erased state ER, where the step pulse V step To incrementally increase the programming voltage V pgm For example, the QLC state can be programmed from state ER having a lower threshold voltage to state Q15 having a highest threshold voltage.

[0049] In some aspects, after programming, during a verification process, states P1-P15 can be verified by using one or more predefined read reference voltages. By applying one or more of the predefined read reference voltages to the control gate of the target memory cell, the threshold voltage V of the memory cell can be determined. th range.

[0050] For example, to verify whether a memory cell is in state ER, a read reference voltage V R1 If the target memory cell is in state ER, the threshold voltage V th Below the reading reference voltage V R1 The target memory cell can be turned on and a conductive path is formed in the channel. If the target memory cell is in any of the states P1-P15, the threshold voltage V th Higher than the predefined read reference voltage V R1 The target memory cell is thus turned off. By measuring or sensing the current through the target memory cell at the corresponding bit line via the page buffer 52, the threshold voltage V th or status.

[0051] In some aspects, as shown in diagram 510, to determine the states ER and P1-P15 for the QLC mode, a matrix including V R1 、V R13 、V R14 and V R15 For example, in QLC mode, the threshold voltage of state ER is lower than V R1 , the threshold voltage of state P15 is higher than V R15 , where the threshold voltage of state P14 is at V R14 With V R15 and the threshold voltage of state P13 is between V R13 With V R14 between.

[0052] In some aspects, as shown in diagram 520, the threshold voltage V of each state in P1-P15 is th The distribution may shift over time. As shown in diagram 520, changes in the threshold voltage distribution of the memory cells may be shown differently depending on the programming state. For example, in the case of lower programming states P1, P2, and P3, the distribution may tend to shift slightly to the right. In addition, in the case of upper programming states P12, P13, P14, and P15, the distribution may tend to expand slightly to the left. By adding a predefined read reference voltage (including, for example, V R1 、V R13 、V R14 and V R15 ) is applied to the control gate of the target memory cell, and the threshold voltage V thThe range of may not be properly determined. In some aspects, the valley may include an intersection between a first threshold voltage distribution of a first state and a second threshold voltage distribution of a second state. The second state may include an adjacent or neighboring state of the first state. For example, valley 530 may include an intersection between a threshold voltage distribution of a programming state P14 and a threshold voltage distribution of a programming state P15.

[0053] In memory devices, especially in high-density memory devices, threshold voltage (Vt) distribution shift is a common and critical problem, which may be affected by many factors, such as charge loss of programmed cells over time, noise, long NAND service life, etc. After the Vt distribution shifts, the predefined read level cannot track the Vt distribution, thereby causing read failure.

[0054] Fig. 6A An exemplary schematic circuit diagram 600 of a memory device according to aspects of the present disclosure is shown. The exemplary schematic circuit diagram 600 includes a memory block 604 and a peripheral circuit 602. In some aspects, the exemplary schematic circuit diagram 600 includes a plurality of memory strings 610, 620, and 630, wherein each of the memory strings 610, 620, and 630 has a plurality of memory cells 608. The memory string 610 also includes at least one field effect transistor (e.g., MOSFET) at each end, which is controlled by a lower select gate (LSG) 612 and a top select gate (TSG) 614, respectively. The memory cell 608 can be controlled by a control gate, wherein the control gate can be connected to a word line 640 of the exemplary schematic circuit diagram 600. The drain terminal of the TSG 614 can be connected to a bit line 618, and the source terminal of the LSG 612 can be connected to an array common source (ACS) 616. The ACS 616 can be shared by the memory strings 610 in the entire memory block and is also referred to as a common source line. In some examples, memory string 620 may be associated with bit line 628 , and memory string 630 may be associated with bit line 638 .

[0055] In some aspects, the exemplary schematic circuit diagram 600 can be formed based on floating gate technology. In some aspects, the exemplary schematic circuit diagram 600 can be formed based on charge trapping technology. NAND flash memory based on charge trapping can provide high storage density and high inherent reliability. The stored data or logic state (e.g., the threshold voltage V of the memory cell 608) th ) depends on the amount of charge trapped in the storage layer. In some aspects, the memory block 604 can be a three-dimensional (3D) memory device, and the exemplary schematic circuit diagram 600 can be a 3D memory array, where the memory cells 608 can be stacked vertically on top of each other.

[0056] In a NAND memory, the memory cell 608 can be in an erased state ER or a programmed state P1. Initially, all of the memory cells 608 in the exemplary schematic circuit diagram 600 can be reset to the erased state ER as a logic "1" by implementing a negative voltage difference between the control gate and the source terminal (e.g., the array common source 616) of the memory cell, so that all trapped electron charges in the storage layer of the memory cell 608 can be removed. For example, the negative voltage difference can be induced by setting the control gate of the memory cell 608 to ground and applying a high positive voltage to the array common source 616. In the erased state ER ("state ER"), the threshold voltage V th can be reset to a minimum value and can be measured or sensed at bit line 618 .

[0057] During programming (ie, writing), a programming voltage V may be applied to the control gate. pgm (eg, a positive voltage pulse between 10 V and 20 V), so that electronic charge (eg, electrons) can be injected into the storage layer of the memory cell 608, thereby increasing the threshold voltage V of the memory cell 608. th Thus, memory cell 608 is programmed to state P1. In some examples, memory cell 608 may be programmed to different states, such as P2-P15 in QLC mode.

[0058] Figure 6B FIG. 1 shows an exemplary schematic diagram of a page buffer of a memory device according to some embodiments. Figure 4 The page buffer 52 and Figure 1-6A The elements in Figure 6B However, not all of the depicted components may be used, and one or more embodiments may include additional components not shown in the figures. Changes may be made to the arrangement and types of components without departing from the spirit or scope of the claims set forth herein. Additional, different, or fewer components may be provided.

[0059] like Figure 6B As shown, page buffer 52 includes a first page buffer structure 658, a second page buffer structure 668, a third page buffer structure 678, and a latch 680. Latch 680 is connected to first page buffer structure 658, second page buffer structure 668, and third page buffer structure 678 to perform a read operation of a memory device (e.g., memory device 100). In some examples, first page buffer structure 658 can be connected to first page buffer structure 658, second page buffer structure 668, and third page buffer structure 678. Fig. 6A The bit line 618 in is connected to the memory string 610. In some examples, the second page buffer structure 668 can be connected to the memory string 610 by Fig. 6AThe bit line 628 in is connected to the memory string 620. In some examples, the third page buffer structure 678 can be Fig. 6A The bit line 638 in is connected to the memory string 630 .

[0060] like Figure 6B As shown, the first page buffer structure 658 includes a sense node (SO) 650, a precharge path 652, an SO discharge path 654, and a sense latch 656. The second page buffer structure 668 includes a sense node (SO) 660, a precharge path 662, an SO discharge path 664, and a sense latch 666. The third page buffer structure 678 includes a sense node (SO) 670, a precharge path 672, an SO discharge path 674, and a sense latch 676.

[0061] As reference Figure 4 As described, during a read operation, the row decoder / word line driver 40 may set the read voltage V according to the X path control signal received from the controller 70. read The page buffer 52 may be configured to read data from and to the memory block 103 according to a Y path control signal from the controller 70. During a read operation, the page buffer 52 may sense a current flowing through the bit line 341 reflecting the logic state (i.e., data) of the memory cell 340 and amplify the small signal to a measurable amplification ratio.

[0062] During a read operation, the first page buffer structure 658 can precharge the bit line 618 through the precharge path 652 by the control logic unit (e.g., the control circuit 70), and can sense whether the selected memory cell is turned on or off at the SO 650. The second page buffer structure 668 and the third page buffer structure 678 can precharge the bit lines connected to the second page buffer structure 668 and the third page buffer structure 678, respectively, based on the same procedure as the precharge operation of the first page buffer structure 658 described above.

[0063] During a read operation, the bit line 618 and the SO 650 may be precharged to a predetermined level during a precharge period. A current may be generated (e.g., in a channel) so as to flow into the first page buffer structure 658 through the bit line 618. During a development period with a development time, when a selected memory cell is in a first state (e.g., a turn-on cell), the charge charged at the SO 650 may be discharged to the array common source (ACS) 616 through the bit line 618 and to the channel of the cell string through the SO discharge path 654. In this case, because the current flowing to the first page buffer structure 658 is relatively large, the speed at which the voltage of the SO 650 drops may be relatively fast. On the other hand, during a development period with a development time, when a selected memory cell is in a second state (e.g., a turn-off cell), it may be difficult for the charge charged at the SO 650 to be discharged to the ACS 616 through the bit line 618. Therefore, because the current flowing to the first page buffer structure 658 is relatively small, the speed at which the voltage of the SO 650 drops may be relatively slow.

[0064] During the latch period, the state of the SO 650 associated with the selected memory cell may be latched to the sense latch 656 as a first state of the selected memory cell having a logic value of 1. Alternatively, the state of the SO 650 associated with the selected memory cell may be latched to the sense latch 656 as a second state of the selected memory cell having a logic value of 0. In some examples, the threshold voltage of the selected memory cell in the first state is greater than the read voltage in the read operation, and the threshold voltage of the selected memory cell in the second state is less than the read voltage in the read operation. In some examples, when the memory cell is turned on when the read voltage level is applied, the memory cell is in the first state, and when the memory cell is turned off when the read voltage level is applied, the memory cell is in the second state.

[0065] In some examples, the second page buffer structure 668 and the third page buffer structure 678 can discharge the bit lines connected to the second page buffer structure 668 and the third page buffer structure 678, respectively, based on the same procedure as the operation of the first page buffer structure 658 described above, and sense the state of the sensing node as the first state or the second state of the selected memory cell.

[0066] After the latch period, latch 680 may store data associated with each of sense latches 656, sense latch 666, and sense latch 676. Latch 680 may perform one or more modifications to the stored data associated with each of sense latches 656, sense latch 666, and sense latch 676. In some examples, latch 680 may modify the logic value of the data associated with each of sense latches 656, sense latch 666, and sense latch 676. For example, latch 680 may modify a logic value of 1 to a logic value of 0. Alternatively, latch 680 may modify a logic value of 0 to a logic value of 1.

[0067] In some examples, during a read operation, the development time during the development period may be different for each of the first page buffer structure 658, the second page buffer structure 668, and the third page buffer structure 678. The sense nodes, precharge paths, SO discharge paths, and sense latches associated with each of the first page buffer structure 658, the second page buffer structure 668, and the third page buffer structure 678 may be individually controlled in different configurations.

[0068] Figure 7 shows an example of a method according to some embodiments Figure 6B 6 and 650. Figure 1-6B The elements in Figure 7 However, not all of the illustrated components may be used, and one or more embodiments may include additional components not shown in the figures. Changes may be made to the arrangement and types of components without departing from the spirit or scope of the claims set forth herein. Additional, different, or fewer components may be provided.

[0069] refer to Figure 7 , it can be simply shown that the level change of the sensing node SO (for example, the sensing node 650, 660 or 670) according to the threshold voltage level of the memory cell and the latch result according to the development period. The time period 710 from time T0 to time T1 can be referred to as Figure 6B The precharge period discussed, the time period 720 from time T1 to time T2 may be referred to as Figure 6BThe development period discussed. During the development period, the change in the voltage level of the sensing node SO of the strongly turned-on cell may correspond to the curve C1. The strongly turned-on cell or the strongly turned-off cell may not be significantly affected by the slight change in the development time. The voltage change of the sensing node SO for sensing the memory cell may correspond to the curve C2, and the threshold voltage of each of the memory cells may be located near the read voltage. Curve C2 shows the development slope of the memory cell having a threshold voltage slightly lower than the read voltage. The time period 730 between time T2 and T3 may be referred to as the reference Figure 6B The sensing period in question.

[0070] In some examples, in the case where the memory cell has a threshold voltage relatively higher than the read voltage, the level change of the sensing node SO may be relatively small. In the case where the memory cell has a threshold voltage relatively lower than the read voltage, the level change of the sensing node SO may be relatively large. In some aspects, the memory cell having a threshold voltage distribution around a valley (e.g., valley 530) between a first threshold voltage distribution in a first state and a second threshold voltage distribution in a second state may be a memory cell located at a boundary between a turn-on cell and a turn-off cell. Therefore, the difference between the turn-on cell and the turn-off cell with respect to the memory cell may be changed according to the development time. That is, even if the development time is slightly reduced, each memory cell in the memory cell having a threshold voltage distribution around the valley may be determined as a "turn-off cell". On the other hand, even if the development time is slightly increased, each memory cell in the memory cell having a threshold voltage distribution around the valley may be determined as a "turn-on cell". That is, in a memory cell having a threshold voltage level similar to a read voltage level to be provided to a word line, a sensing operation may be performed in the same manner as a sensing operation using a read voltage increased by reducing the development time. On the other hand, in a memory cell having a threshold voltage level similar to a read voltage level to be supplied to a word line, a sensing operation may be performed identically to a sensing operation using a read voltage reduced by increasing a development time.

[0071] Therefore, sensing the sensing node SO a plurality of times at the time point when the development time is changed may be the same as changing the word line voltage and precharging and sensing the bit line.

[0072] Fig. 8A An exemplary method 800 for performing a read operation on a memory device according to some embodiments is shown. Figure 1-Figure 7 The elements in Fig. 8A . can be stored by a storage system (e.g., Figure 110) performs example 800. It should be understood that process flow 800 is not exhaustive, and other operation steps may also be performed before, after, or between any of the operation steps shown. In some embodiments, some operation steps of process flow 800 may be omitted, or other operation steps not described here for simplicity may be included. In some embodiments, the operation steps of process flow 800 may be performed in different orders, and / or the operation steps of process flow 800 may vary.

[0073] At step 802, a first read operation is performed on a memory cell (eg, memory cell 608) in a memory device (eg, memory device 100). In one example, the first operation may include applying a predetermined read voltage (eg, Figure 5 V R15 ) to determine the state of one or more memory cells (eg, P15). In some aspects, as shown in diagram 520, the threshold voltage V for each state in P1-P15 is th The distribution can shift over time.

[0074] At step 804, based on the first read operation, a first plurality of memory cells in a first state and a second plurality of memory cells in a second state are selected from the memory cells. In some examples, a threshold voltage of each of the first plurality of memory cells in the first state may be greater than a read voltage in the first read operation, and a threshold voltage of each of the second plurality of memory cells in the second state may be less than a read voltage in the first read operation. In some examples, the first state of the memory cell may correspond to a logic value of 1 in a sense latch. In some examples, the second state of the memory cell may correspond to a logic value of 0 in a sense latch. In some examples, one or more bit lines or sense nodes associated with the first plurality of memory cells may be precharged after the first read operation. One or more bit lines or sense nodes associated with the second plurality of memory cells may not be precharged after the first read operation.

[0075] At step 806, a second read operation is performed on the first plurality of memory cells, including steps 816, 826, and 836. At step 816, first data is sensed from the first plurality of memory cells through the first set of bit lines (e.g., bit line 618) during a first development time. In some examples, the first development time may be related to Figure 7The development period and sensing period discussed are associated. At step 826, first data is sensed from the first plurality of memory cells through the second group of bit lines (e.g., bit line 628) during a second development time. At step 836, first data is sensed from the first plurality of memory cells through the third group of bit lines (e.g., bit line 638) during a third development time. In some examples, the first development time may include a time period (e.g., "T"), the second development time may include a time period that is twice the first development time (e.g., "2T"), and the third development time may include a time period that is three times the first development time (e.g., "3T"). In some examples, the number of development times may not be limited to three, and may include any number. In some examples, the number of development times may be selected based on different numbers of groups of bit lines.

[0076] In some examples, a first discharge path associated with the bit lines of the first group (e.g., SO discharge path 654) may be disabled after a first development time. In some examples, a second discharge path associated with the bit lines of the second group (e.g., SO discharge path 664) may be disabled after a second development time. In some examples, a third discharge path associated with the bit lines of the third group (e.g., SO discharge path 674) may be disabled after a third development time to thereby perform a second read operation on the first plurality of memory cells.

[0077] In some examples, the first data corresponding to each memory cell in the first plurality of memory cells is latched to a logic value of one or zero by one or more sense latches (e.g., sense latches 656, 666, and 676) based on the second read operation. The first data can be transmitted to latch 680 and modified in latch 680. The modified logic value corresponding to each memory cell in the first plurality of memory cells can be obtained by latch 680. In some examples, the logic value one can be modified to a logic value zero. Alternatively, the logic value zero can be modified to a logic value one.

[0078] At step 808, a third plurality of memory cells are selected from the first plurality of memory cells based on the second read operation. In some examples, the third plurality of memory cells may be selected from the first plurality of memory cells based on the modified logical value. In some examples, the modified logical value corresponding to each memory cell in the third plurality of memory cells may be one. In some examples, the modified logical value corresponding to each memory cell in the third plurality of memory cells may be a predetermined value.

[0079] At step 810, a third read operation is performed on the third plurality of memory cells, including steps 820 and 830. At step 820, second data is sensed from the third plurality of memory cells through the bit lines of the second group during the fourth development time. At step 830, second data is sensed from the third plurality of memory cells through the bit lines of the third group during the fifth development time. In some examples, the fourth development time is shorter than the second development time, and the fifth development time is shorter than the third development time. In some examples, the first difference between the second development time and the first development time and the second difference between the third development time and the second development time may be the same. In some examples, the third difference between the second development time and the fourth development time and the fourth difference between the third development time and the fifth development time may be the same. In some examples, the third difference and the fourth difference may be the same as the first development time. In some examples, the fourth development time may be equal to the first development time. In some examples, the fifth development time may be equal to the second development time.

[0080] In some examples, a second discharge path associated with the bit lines of the second group may be disabled after a fourth development time; and a third discharge path associated with the bit lines of the third group may be disabled before a fifth development time to thereby perform a third read operation on a third plurality of memory cells.

[0081] In some examples, second data corresponding to each memory cell in the third plurality of memory cells may be latched to a logic value of one or zero based on the third read operation.

[0082] In some examples, a first number of memory cells associated with a first group of bit lines corresponding to a logical value of one may be determined. A second number of memory cells associated with a second group of bit lines corresponding to a logical value of one may be determined. A third number of memory cells associated with a third group of bit lines corresponding to a logical value of one may be determined.

[0083] At step 812 , a read development time is determined based on the third read operation.

[0084] In some examples, the first number, the second number, and the third number may be compared to obtain a minimum number among the first number, the second number, and the third number. A group of bit lines among the first group of bit lines, the second group of bit lines, and the third group of bit lines corresponding to the minimum number among the first number, the second number, and the third number may be determined. A development time associated with the determined group of bit lines among the first group of bit lines, the second group of bit lines, and the third group of bit lines may be determined as a read development time. The bit lines of the first group corresponding to the minimum number among the first number, the second number, and the third number may be determined. The first development time associated with the bit lines of the first group may be determined as the read development time. The read development time may be an optimal development time for determining a data state (e.g., P15) of a memory device for use in Figure 5 The predefined read level (e.g., V R15 ) to minimize the impact of threshold voltage (Vt) distribution shift.

[0085] In some examples, the first group of bit lines may include a first number of bit lines. In some examples, the second group of bit lines may include a second number of bit lines. In some examples, the third group of bit lines may include a third number of bit lines. In some examples, the first number, the second number, and the third number may be the same.

[0086] In some examples, the fourth development time may be the same as the first development time; and the fifth development time may be the same as the second development time.

[0087] Figure 8B According to some embodiments, Fig. 8A Example threshold voltage distributions and data structures during a process flow in FIG. Fig. 8A and Figure 1-Figure 7 To describe Figure 8B However, not all of the illustrated components may be used, and one or more embodiments may include additional components not shown in the figures. Changes may be made to the arrangement and types of components without departing from the spirit or scope of the claims set forth herein. Additional, different, or fewer components may be provided.

[0088] Figure 8B Includes a first data structure 892 , a second data structure 896 and a third data structure 890 .

[0089] In some examples, Fig. 8A During the first read operation at step 802 of step 804, the first data structure 892 may include data associated with latches (e.g., 680) associated with one or more memory cells in a page buffer (e.g., page buffer 52). For example, the first data structure 892 may be associated with Figure 6BThe first data structure 892 may include D_S_g0, D_S_g1, D_S_g2, D_S_g3, and D_S_g4 corresponding to the first bit line group g0, the second bit line group g1, the third bit line group g2, the fourth bit line group g3, and the fifth bit line group g4. Each of D_S_g0, D_S_g1, D_S_g2, D_S_g3, and D_S_g4 may include a logic value of 1 or 0 to indicate the first state or the second state of the memory cell.

[0090] As reference Figure 6B As described, during the latch period, the state of SO 650 associated with the selected memory cell can be latched to sense latch 656 as a first state of the selected memory cell having a logic value of 1. Alternatively, the state of SO 650 associated with the selected memory cell can be latched to sense latch 656 as a second state of the selected memory cell having a logic value of 0. In some examples, the threshold voltage of the selected memory cell in the first state is greater than the read voltage in the read operation, and the threshold voltage of the selected memory cell in the second state is less than the read voltage in the read operation. After the latch period, latch 680 can store data associated with each of sense latches 656, sense latch 666, and sense latch 676 as data associated with the bit line, such as first data structure 892.

[0091] In some examples, during the second read operation at step 806, the second data structure 896 may include data associated with one or more sense latches (e.g., sense latches 656, 666, and 676) and latches (e.g., 680) associated with one or more memory cells in the page buffer (e.g., page buffer 52). As described above, a second read operation is performed on the first plurality of memory cells, including steps 816, 826, and 836. The second data structure 896 may include data associated with five sense latches SO_g0, SO_g1, SO_g2, SO_g3, and SO_g4. Each of SO_g0, SO_g1, SO_g2, SO_g3, and SO_g4 may correspond to a sense latch associated with a first bit line group g0, a second bit line group g1, a third bit line group g2, a fourth bit line group g3, and a fifth bit line group g4. The sense latches may be or include the sense latches 656 , 666 , and 676 .

[0092] In some examples, second data structure 896 includes second data structures 896A, 896B, and 896C. Second data structure 896A may include data associated with one or more sense latches associated with the first plurality of memory cells. Second data structure 896A may include data associated with one or more sense latches associated with the first plurality of memory cells. After steps 816, 826, and 836 in step 806, second data structure 896B may include data associated with one or more sense latches associated with the first plurality of memory cells. After steps 816, 826, and 836 in step 806, second data structure 896C may include modified data associated with one or more latches (e.g., 680) associated with the first plurality of memory cells in a page buffer (e.g., page buffer 52). As described in reference Figure 6B and Fig. 8A As described, the latches in the page buffer may modify the data associated with the sense latches SO_g0, SO_g1, SO_g2, SO_g3, and SO_g4 to modify a logic value of 1 to a logic value of 0, and vice versa. The latches in the page buffer may provide the modified data in the second data structure 896C.

[0093] In some examples, during the third read operation at step 810, the third data structure 890 may include data associated with one or more sense latches (e.g., sense latches 656, 666, and 676) and latches (e.g., 680) associated with one or more memory cells in the page buffer (e.g., page buffer 52). As described above, the third read operation is performed on the third plurality of memory cells, including steps 820 and 830.

[0094] The third data structure 890 includes third data structures 890A, 890B, and 890C. In some examples, the third data structure 890A may include data associated with one or more sense latches associated with the third plurality of memory cells. In some examples, after steps 820 and 830 in step 810, the third data structure 890B may include data associated with one or more sense latches associated with the third plurality of memory cells. In some examples, after steps 820 and 830 in step 810, the third data structure 890C may include data associated with latches (e.g., 680) associated with the third plurality of memory cells in the page buffer (e.g., page buffer 52).

[0095] In some examples, the read development time is determined based on the third data structure 890C, as described above with reference to step 812 .

[0096] In some examples, one or more cell quantities associated with the first data structure 892, the second data structure 896, and the third data structure 890 in the first state or the second state may correspond to Figure 8B One or more regions in the exemplary threshold voltage distribution shown in .

[0097] In the present disclosure, after the first read operation and the second read operation, the read development time is determined based on the third read operation. The read development time may be an optimal development time for determining a data state (eg, P15) of the memory device to use Figure 5 The predefined read level (e.g., V R15 ) to minimize the impact of threshold voltage (Vt) distribution shift.

[0098] In addition, two advantages of the present disclosure may include: (1) improved reading efficiency can be achieved by obtaining the Vt distribution of multiple regions in the threshold voltage distribution at one time, which not only saves the reading sensing time but also saves the cell number counting time; (2) improved system design can be achieved by only one latch in the page buffer (e.g., latch 680), thereby improving one or more circuit designs and performances.

[0099] The foregoing description of the specific embodiments will so completely reveal the overall nature of the present disclosure that others can easily modify and / or transform the various applications of these specific embodiments by applying the knowledge within the art without undue experimentation and without departing from the overall concept of the present disclosure. Therefore, based on the disclosure and guidance given herein, such transformations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments. It will be understood that the words or terms in this article are for descriptive purposes rather than for limiting purposes, so that the terms or words of this specification will be interpreted by those skilled in the art based on the disclosure and guidance.

[0100] Embodiments of the present disclosure have been described above with the aid of functional building blocks, which illustrate implementations of specific functions and their relationships. For ease of description, the boundaries of these functional building blocks have been arbitrarily defined herein. As long as specific functions and relationships are properly performed, alternative boundaries may be defined.

[0101] The Summary and Abstract sections may set forth one or more, but not all, exemplary embodiments of the present disclosure as contemplated by the inventor(s), and thus, are not intended to limit the present disclosure and the appended claims in any way.

[0102] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A NAND memory device, comprising: A storage array, wherein the storage array has storage cells; a page buffer coupled to the memory array via a bit line, wherein the page buffer includes a latch; and a control logic unit, the control logic unit being coupled to the page buffer and configured to: performing a first read operation on the storage unit; selecting, from the memory cells, a first plurality of memory cells in a first state and a second plurality of memory cells in a second state based on the first read operation; performing a second read operation on the first plurality of memory cells, comprising: sensing first data from the first plurality of memory cells through a first set of bit lines during a first development time, sensing first data from the first plurality of memory cells through a second set of bit lines during a second development time, and sensing first data from the first plurality of memory cells through a third set of bit lines during a third development time; selecting a third plurality of memory cells from the first plurality of memory cells based on the second read operation; performing a third read operation on the third plurality of memory cells, comprising: sensing second data from the third plurality of memory cells through the bit lines of the second group during a fourth development time, and sensing second data from the third plurality of memory cells through the bit lines of the third group during a fifth development time, wherein the fourth development time is shorter than the second development time, and the fifth development time is shorter than the third development time; and A read development time is determined based on the third read operation.

2. The NAND memory device according to claim 1, wherein: A threshold voltage of each of the first plurality of memory cells in the first state is greater than a read voltage in the first read operation, and a threshold voltage of each of the second plurality of memory cells in the second state is less than a read voltage in the first read operation.

3. The NAND memory device according to claim 1, wherein: The control logic unit is further configured to: disabling a first discharge path associated with the first set of bit lines after the first development time; disabling a second discharge path associated with the second set of bit lines after the second development time; and A third discharge path associated with the third group of bit lines is disabled after the third development time to thereby perform the second read operation on the first plurality of memory cells.

4. The NAND memory device according to claim 1, wherein: The control logic unit is further configured to: latching the first data corresponding to each memory cell of the first plurality of memory cells to a logic value of one or zero based on the second read operation; modifying the latched first data, comprising: obtaining a modified logic value corresponding to each memory cell in the first plurality of memory cells; and The third plurality of memory cells are selected from the first plurality of memory cells, wherein the modified logic value corresponding to each memory cell in the third plurality of memory cells is one.

5. The NAND memory device according to claim 1, wherein: The control logic unit is further configured to: disabling a second discharge path associated with the second set of bit lines after the fourth development time; and A third discharge path associated with the third group of bit lines is disabled after the fifth development time to thereby perform the third read operation on the third plurality of memory cells.

6. The NAND memory device according to claim 1, wherein: The control logic unit is further configured to: latching the second data corresponding to each memory cell in the third plurality of memory cells to a logic value of one or zero based on the third read operation; and Determine a first number of memory cells associated with the bit lines of the first group corresponding to logic value one, a second number of memory cells associated with the bit lines of the second group corresponding to logic value one, and a third number of memory cells associated with the bit lines of the third group corresponding to logic value one.

7. The NAND memory device according to claim 6, wherein: The control logic unit is further configured to: comparing the first number, the second number, and the third number to obtain a minimum number among the first number, the second number, and the third number; determining a group of bit lines corresponding to the minimum number among the first number, the second number, and the third number among the bit lines of the first group, the bit lines of the second group, and the bit lines of the third group; and Determine the timing of read development.

8. The NAND memory device according to claim 1, wherein: The first group of bit lines includes a first number of bit lines; wherein the second group of bit lines includes a second number of bit lines; wherein the third group of bit lines includes a third number of bit lines; and wherein the first number, the second number, and the third number are the same.

9. The NAND memory device according to claim 1, further comprising: a first difference between the second development time and the first development time; and a second difference between the third development time and the second development time, wherein the first difference and the second difference are the same.

10. The NAND memory device according to claim 1, wherein: The fourth development time and the first development time are the same; and the fifth development time and the second development time are the same.

11. The NAND memory device according to claim 4, wherein: The control logic unit is also configured to modify the latched first data, further comprising: modifying the latched first data having the logic value one to a logic value zero; and modifying the latched first data having the logic value zero to a logic value one.

12. A method for operating a memory device, comprising: performing a first read operation on a memory cell in the memory device; selecting, from the memory cells, a first plurality of memory cells in a first state and a second plurality of memory cells in a second state based on the first read operation; performing a second read operation on the first plurality of memory cells, comprising: sensing first data from the first plurality of memory cells through a first set of bit lines during a first development time, sensing first data from the first plurality of memory cells through a second set of bit lines during a second development time, and sensing first data from the first plurality of memory cells through a third set of bit lines during a third development time; selecting a third plurality of memory cells from the first plurality of memory cells based on the second read operation; performing a third read operation on the third plurality of memory cells, comprising: sensing second data from the third plurality of memory cells through the bit lines of the second group during a fourth development time, and sensing second data from the third plurality of memory cells through the bit lines of the third group during a fifth development time, wherein the fourth development time is shorter than the second development time, and the fifth development time is shorter than the third development time; and A read development time is determined based on the third read operation.

13. The method according to claim 12, wherein: A threshold voltage of each of the first plurality of memory cells in the first state is greater than a read voltage in the first read operation, and a threshold voltage of each of the second plurality of memory cells in the second state is less than a read voltage in the first read operation.

14. The method according to claim 12, further comprising: disabling a first discharge path associated with the first set of bit lines after the first development time; disabling a second discharge path associated with the bit lines of the second group after the second development time; as well as A third discharge path associated with the third group of bit lines is disabled after the third development time to thereby perform the second read operation on the first plurality of memory cells.

15. The method according to claim 12, further comprising: latching the first data corresponding to each memory cell of the first plurality of memory cells to a logic value of one or zero based on the second read operation; modifying the latched first data, comprising: obtaining a modified logic value corresponding to each memory cell of the first plurality of memory cells; and The third plurality of memory cells are selected from the first plurality of memory cells, wherein the modified logic value corresponding to each memory cell in the third plurality of memory cells is one.

16. The method according to claim 12, further comprising: disabling a second discharge path associated with the bit lines of the second group after the fourth development time; as well as A third discharge path associated with the third group of bit lines is disabled after the fifth development time to thereby perform the third read operation on the third plurality of memory cells.

17. The method according to claim 12, further comprising: latching the second data corresponding to each memory cell in the third plurality of memory cells to a logic value of one or zero based on the third read operation; as well as Determine a first number of memory cells associated with the bit lines of the first group corresponding to logic value one, a second number of memory cells associated with the bit lines of the second group corresponding to logic value one, and a third number of memory cells associated with the bit lines of the third group corresponding to logic value one.

18. The method according to claim 17, further comprising: comparing the first number, the second number, and the third number to obtain a minimum number among the first number, the second number, and the third number; determining a group of bit lines corresponding to the minimum number among the first number, the second number, and the third number among the bit lines of the first group, the bit lines of the second group, and the bit lines of the third group; as well as Determine the timing of read development.

19. The method according to claim 12, wherein: The first group of bit lines includes a first number of bit lines; wherein the second group of bit lines includes a second number of bit lines; wherein the third group of bit lines includes a third number of bit lines; and wherein the first number, the second number, and the third number are the same.

20. The method of claim 12, further comprising: a first difference between the second development time and the first development time; and a second difference between the third development time and the second development time, wherein the first difference and the second difference are the same.

21. The method according to claim 12, wherein: The fourth development time and the first development time are the same; and the fifth development time and the second development time are the same.

22. The method of claim 15, further comprising: modifying the latched first data having the logic value one to a logic value zero; as well as The latched first data having the logic value zero is modified to a logic value one.

23. A memory system comprising: a memory array having a memory cell coupled to one of a plurality of bit lines; a page buffer coupled to the memory array through the bit lines, wherein the page buffer includes a latch; and a control logic unit, the control logic unit being coupled to the page buffer and configured to: performing a first read operation on the storage unit; selecting, from the memory cells, a first plurality of memory cells in a first state and a second plurality of memory cells in a second state based on the first read operation; performing a second read operation on the first plurality of memory cells, comprising: sensing first data from the first plurality of memory cells through a first set of bit lines during a first development time, sensing first data from the first plurality of memory cells through a second set of bit lines during a second development time, and sensing first data from the first plurality of memory cells through a third set of bit lines during a third development time; selecting a third plurality of memory cells from the first plurality of memory cells based on the second read operation; performing a third read operation on the third plurality of memory cells, comprising: sensing second data from the third plurality of memory cells through the bit lines of the second group during a fourth development time, and sensing second data from the third plurality of memory cells through the bit lines of the third group during a fifth development time, wherein the fourth development time is shorter than the second development time, and the fifth development time is shorter than the third development time; and A read development time is determined based on the third read operation.

24. The memory system of claim 23, wherein: A threshold voltage of each of the first plurality of memory cells in the first state is greater than a read voltage in the first read operation, and a threshold voltage of each of the second plurality of memory cells in the second state is less than a read voltage in the first read operation.

25. The memory system of claim 23, wherein: The control logic unit is further configured to: disabling a first discharge path associated with the first set of bit lines after the first development time; disabling a second discharge path associated with the second set of bit lines after the second development time; and A third discharge path associated with the third group of bit lines is disabled after the third development time to thereby perform the second read operation on the first plurality of memory cells.

26. The memory system of claim 23, wherein: The control logic unit is further configured to: latching the first data corresponding to each memory cell of the first plurality of memory cells to a logic value of one or zero based on the second read operation; modifying the latched first data, comprising: obtaining a modified logic value corresponding to each memory cell in the first plurality of memory cells; and The third plurality of memory cells are selected from the first plurality of memory cells, wherein the modified logic value corresponding to each memory cell in the third plurality of memory cells is one.

27. The memory system of claim 23, wherein: The control logic unit is further configured to: disabling a second discharge path associated with the second set of bit lines after the fourth development time; and A third discharge path associated with the third group of bit lines is disabled after the fifth development time to thereby perform the third read operation on the third plurality of memory cells.

28. The memory system of claim 23, wherein: The control logic unit is further configured to: latching the second data corresponding to each memory cell in the third plurality of memory cells to a logic value of one or zero based on the third read operation; and Determine a first number of memory cells associated with the bit lines of the first group corresponding to logic value one, a second number of memory cells associated with the bit lines of the second group corresponding to logic value one, and a third number of memory cells associated with the bit lines of the third group corresponding to logic value one.

29. The memory system of claim 28, wherein: The control logic unit is further configured to: comparing the first number, the second number, and the third number to obtain a minimum number among the first number, the second number, and the third number; determining a group of bit lines corresponding to the minimum number among the first number, the second number, and the third number among the bit lines of the first group, the bit lines of the second group, and the bit lines of the third group; and Determine the timing of read development.

30. The memory system of claim 23, wherein: The first group of bit lines includes a first number of bit lines; wherein the second group of bit lines includes a second number of bit lines; wherein the third group of bit lines includes a third number of bit lines; and wherein the first number, the second number, and the third number are the same.

31. The memory system of claim 23, further comprising: a first difference between the second development time and the first development time; and a second difference between the third development time and the second development time, wherein the first difference and the second difference are the same.

32. The memory system of claim 23, wherein: The fourth development time and the first development time are the same; and the fifth development time and the second development time are the same.

33. The memory system of claim 26, wherein: The control logic unit is also configured to modify the latched first data, further comprising: modifying the latched first data having the logic value one to a logic value zero; and modifying the latched first data having the logic value zero to a logic value one.

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