Semiconductor memory device

Abstract

According to one embodiment, a semiconductor memory device includes: a first chip including a first pillar having a first memory cell and a second memory cell connected in series; a second chip including a second pillar having a third memory cell and a fourth memory cell connected in series; and a third chip including a row decoder that connects a first word line connected to the gate of the first memory cell, a second word line connected to the gate of the third memory cell, and a third word line connected to the gate of each of the second memory cell and the fourth memory cell.

Description

Technical Field

[0001] An embodiment of the present invention relates to a semiconductor memory device. Background Art

[0002] As a semiconductor memory device, a NAND (Not-And) type flash memory is known.

[0003] [Background Technology Literature]

[0004] [Patent Document]

[0005] Patent Document 1: U.S. Patent No. 10811393

[0006] Patent Document 2: U.S. Patent No. 10797028

[0007] Patent Document 3: U.S. Patent No. 8584061 Summary of the invention

[0008] [Problems to be solved by the invention]

[0009] According to one embodiment of the present invention, a semiconductor memory device having improved reliability is provided.

[0010] [Technical solutions to the problem]

[0011] A semiconductor memory device of an embodiment includes: a first chip including a first column having a first memory cell and a second memory cell connected in series, a first bit line connected to one end of the first column, and a first source line connected to the other end of the first column; a second chip including a second column having a third memory cell and a fourth memory cell connected in series, a second bit line connected to one end of the second column, and a second source line connected to the other end of the second column; and a third chip including a sense amplifier commonly connected to the first bit line and the second bit line, and a row decoder that respectively connects a first word line connected to a gate of the first memory cell, a second word line connected to a gate of the third memory cell, and a third word line connected to a gate of each of the second memory cell and the fourth memory cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 This is a block diagram showing the overall configuration of a memory system including the semiconductor memory device according to the first embodiment.

[0013] Figure 2 It is a plan view showing a circuit configuration of a memory cell array included in the semiconductor memory device according to the first embodiment.

[0014] Figure 3It is a perspective view showing a circuit configuration of a memory cell array included in the semiconductor memory device according to the first embodiment.

[0015] Figure 4 This is a circuit diagram of a row decoder included in the semiconductor memory device according to the first embodiment.

[0016] Figure 5 It is a cross-sectional view showing the arrangement of an array chip and a circuit chip included in the semiconductor memory device according to the first embodiment.

[0017] Figure 6 It is a perspective view showing the arrangement of an array chip and a circuit chip included in the semiconductor memory device according to the first embodiment.

[0018] Figure 7 It is a cross-sectional view of a memory cell array included in the semiconductor memory device according to the first embodiment.

[0019] Figure 8 It is a diagram showing the configuration of a block included in the semiconductor memory device according to the first embodiment and changes in the data writing state by a sub-block erase operation.

[0020] Fig. 9 This is a command sequence for a write operation in the semiconductor memory device according to the first embodiment.

[0021] Fig.10 This is a diagram showing the structure of a memory address in the semiconductor memory device according to the first embodiment.

[0022] Fig.11 Is based on Fig.10 A diagram showing the order in which data is written to memory addresses.

[0023] Fig.12 1 and 2 are diagrams showing the configuration of blocks in the semiconductor memory device according to the first embodiment and changes in the data writing state by a writing operation of the sub-block SB1 .

[0024] Fig.13 1 is a timing chart showing voltages of respective wirings during a write operation in the sub-block SB1 in the semiconductor memory device according to the first embodiment.

[0025] Fig.14 1 and 2 are diagrams showing the configuration of blocks in the semiconductor memory device according to the first embodiment and changes in the data writing state by the writing operation of the sub-block SB0 .

[0026] Fig.15 1 is a timing chart showing voltages of respective wirings during a write operation in the sub-block SB0 in the semiconductor memory device according to the first embodiment.

[0027] Fig.16It is a cross-sectional view showing the arrangement of an array chip and a circuit chip included in a semiconductor memory device according to a first modification of the first embodiment.

[0028] Fig.17 It is a perspective view showing a circuit configuration of a memory cell array included in a semiconductor memory device according to a first modification of the first embodiment.

[0029] Fig.18 This is a circuit diagram of a row decoder included in a semiconductor memory device according to a first modification of the first embodiment.

[0030] Fig.19 1 is a diagram showing a block configuration included in a semiconductor memory device according to a first modification of the first embodiment and a data writing state by a writing operation of a sub-block SB1 .

[0031] Fig. 20 1 and 2 are diagrams showing a block configuration of a semiconductor memory device according to a second modification of the first embodiment and a data writing state by a writing operation of a sub-block SB1 .

[0032] Fig.21 It is a diagram showing the structure of a memory address in the semiconductor memory device according to the second embodiment.

[0033] Fig. 22 Is based on Fig.21 A diagram showing the order in which data is written to memory addresses.

[0034] Fig.23 1 and 2 are diagrams showing the configuration of blocks included in the semiconductor memory device according to the second embodiment and changes in the data writing state by a writing operation of the sub-block SB0 .

[0035] Fig.24 It is a cross-sectional view of a memory cell array included in a semiconductor memory device according to a first variation of the second embodiment.

[0036] Fig.25 1 and 2 are diagrams showing a block configuration of a semiconductor memory device according to a first modification of the second embodiment and a change in a data write state by a write operation of the sub-block SB0 .

[0037] Fig.26 It is a cross-sectional view showing the arrangement of an array chip and a circuit chip included in a semiconductor memory device according to a third modification of the second embodiment.

[0038] Fig. 27 It is a perspective view showing a circuit configuration of a memory cell array included in a semiconductor memory device according to a second variation of the second embodiment.

[0039] Fig.281 and 2 are diagrams showing a block configuration included in a semiconductor memory device according to a second modification of the second embodiment and changes in a data write state by a write operation of the sub-block SB0 . DETAILED DESCRIPTION

[0040] Hereinafter, the embodiments will be described with reference to the accompanying drawings. In addition, in the following description, the same symbols are marked for the constituent elements having substantially the same function and structure. In the case where repeated description is not necessary, it may be omitted. In addition, each embodiment shown below is an example of an embodiment of a device or method for concretizing the technical idea of ​​the embodiment. The technical idea of ​​the embodiment does not specify the material, shape, structure, configuration, etc. of the constituent parts as follows. The technical idea of ​​the embodiment can be subjected to various changes without departing from the scope of the main purpose of the invention. The embodiment or its changes are included in the invention described in the claims and the scope of its equivalent.

[0041] 1. First Implementation Method

[0042] A semiconductor memory device according to the first embodiment will be described.

[0043] 1.1 Composition

[0044] 1.1.1 Overall Structure of a Semiconductor Memory Device

[0045] First, refer to Figure 1 , an example of the overall structure of the semiconductor storage device 1 is described. Figure 1 1 is a block diagram showing the overall configuration of a memory system including the semiconductor memory device 1. Figure 1 In the figure, a part of the connection between the components is indicated by the arrow line, but the connection between the components is not limited to this.

[0046] like Figure 1 As shown, the memory system includes a semiconductor memory device 1 and a memory controller 2 .

[0047] The semiconductor memory device 1 is, for example, a three-dimensional stacked NAND flash memory, which includes a plurality of nonvolatile memory cell transistors three-dimensionally arranged on a semiconductor substrate.

[0048] The memory controller 2 instructs the semiconductor memory device 1 to perform a read operation, a write operation, an erase operation, etc. based on a request from a host device (not shown). In addition, the memory controller 2 manages the memory space of the semiconductor memory device 1 .

[0049] The semiconductor memory device 1 includes a plurality of external connection terminals PD. The semiconductor memory device 1 is connected to the memory controller 2 via the external connection terminals PD. In addition, the semiconductor memory device 1 is supplied with a power supply voltage from the outside via the external connection terminals PD.

[0050] The semiconductor memory device 1 is configured to be controllable by the memory controller 2. For example, the semiconductor memory device 1 transmits and receives a signal DQ and timing signals DQS and DQSn with the memory controller 2. The signal DQ is, for example, data DT, a memory address ADD, or a command CMD. The memory address ADD is information indicating the location of a memory cell transistor in the memory cell array 100. For example, the command CMD includes a command for executing a read operation, a write operation, an erase operation, etc. The timing signals DQS and DQSn are timing signals used when inputting and outputting the data DT. The timing signal DQSn is an inversion signal of the timing signal DQS.

[0051] In addition, the semiconductor memory device 1 receives various control signals from the memory controller 2. For example, the control signals include a chip enable signal CEn, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WEn, and a read enable signal REn.

[0052] The chip enable signal CEn is a signal for enabling the semiconductor memory device 1. The command latch enable signal CLE is a signal indicating that the signal DQ is a command. The address latch enable signal ALE is a signal indicating that the signal DQ is an address. The write enable signal WEn is a signal for extracting the signal DQ when the signal DQ is a command CMD or a memory address ADD. Each time the signal WEn is switched, the command CMD or the memory address ADD is extracted to the semiconductor memory device 1. The read enable signal REn is a signal for enabling the memory controller 2 to read data from the semiconductor memory device 1. For example, when the semiconductor memory device 1 outputs data, based on the signal REn, it generates the signals DQS and DQSn.

[0053] The semiconductor memory device 1 transmits a ready busy signal RBn to the memory controller 2. The ready busy signal RBn is a signal indicating whether the semiconductor memory device 1 cannot receive a command CMD from the memory controller 2 (busy state) or can receive a command CMD from the memory controller 2 (ready state).

[0054] Next, the internal structure of semiconductor memory device 1 will be described.

[0055] The semiconductor memory device 1 includes a plurality of array chips 3 and a circuit chip 4 . Figure 1 In the example shown, the semiconductor memory device 1 includes two array chips 3a and 3b. The number of array chips 3 is not limited to two.

[0056] The array chip 3 is a chip on which an array of nonvolatile memory cell transistors is provided.

[0057] The circuit chip 4 is a chip provided with a circuit for controlling the array chip 3. For example, the semiconductor memory device 1 has a structure in which a plurality of array chips 3 and circuit chips 4 are bonded together (hereinafter, also referred to as a "bonded structure"). In the following, when neither the array chip 3 nor the circuit chip 4 is limited, they are simply referred to as "chips".

[0058] The semiconductor memory device 1 includes a memory cell array 100. The memory cell array 100 is an area where nonvolatile memory cell transistors are arranged three-dimensionally. The memory cell array 100 is provided in array chips 3a and 3b. Hereinafter, a portion of the memory cell array 100 provided in the array chip 3a is marked as "memory cell array 100a". A portion of the memory cell array 100 provided in the array chip 3b is marked as "memory cell array 100b". That is, the memory cell array 100 includes the memory cell arrays 100a and 100b.

[0059] The memory cell array 100 includes a plurality of blocks BLK. Figure 1 In the example, the memory cell array 100 includes two blocks BLK0 and BLK1. The block BLK is, for example, a collection of multiple memory cell transistors that erase data together. In the present embodiment, one block BLK is set in an area where a portion of the memory cell array 100a is combined with a portion of the memory cell array 100b. That is, the block BLK includes multiple memory cell transistors set in the memory cell array 100a and multiple memory cell transistors set in the memory cell array 100b. The multiple memory cell transistors in the block BLK are associated with rows and columns.

[0060] The block BLK includes a plurality of string units SU. The string unit SU is, for example, a collection of a plurality of NAND strings NS selected collectively in a write operation or a read operation. Figure 1 In the example, each block BLK includes four string units SU0, SU1, SU2, and SU3. For example, the memory cell array 100a (array chip 3a) includes string units SU0 and SU1 of each block BLK. The memory cell array 100b (array chip 3b) includes string units SU2 and SU3 of each block. In addition, the configuration of the string units SU contained in the array chips 3a and 3b is arbitrary.

[0061] The string unit SU includes a plurality of NAND strings NS. The NAND string NS includes a set of a plurality of memory cell transistors connected in series.

[0062] The number of blocks BLK in the memory cell array 100 and the number of string units SU in the block BLK are arbitrary. The circuit configuration of the memory cell array 100 will be described later.

[0063] Next, the circuit chip 4 will be described. The circuit chip 4 includes a row decoder 20 , a sense amplifier 30 , an input / output circuit 40 , and a peripheral circuit unit 50 .

[0064] The row decoder 20 is a decoding circuit for the row address RA (block address BA). The row decoder 20 is connected to the input / output circuit 40, the address register 51, the row driver 55, and the memory cell array 100. The row decoder 20 selects any block BLK in the memory cell array 100 based on the decoding result of the row address RA (block address BA). The row decoder 20 applies a voltage to the row-direction wiring (the word line and the selection gate line described later) of the selected block BLK.

[0065] The sense amplifier 30 is a circuit for writing and reading data DT. The sense amplifier 30 is connected to the input / output circuit 40, the address register 51, the column driver 56, and the memory cell array 100. The sense amplifier 30 reads data DT from the memory cell array 100 during a read operation. In addition, the sense amplifier 30 supplies a voltage based on the write data DT to the memory cell array 100 during a write operation. The sense amplifier 30 can apply a voltage to the wiring in the column direction (a bit line described later).

[0066] The input / output circuit 40 is a circuit for inputting and outputting the signal DQ and various control signals. The input / output circuit 40 is connected to the memory controller 2 via the external connection terminal PD. In addition, the input / output circuit 40 is connected to the address register 51, the command register 52, the sequencer 53, and the sense amplifier 30.

[0067] When the input signal DQ is data DT (write data), the input / output circuit 40 receives the input signal DQ based on the timing signals DQS and DQSn. Furthermore, the input / output circuit 40 transmits the data DT to the sense amplifier 30. Furthermore, the input / output circuit 40 outputs the data DT (read data) to the memory controller 2 together with the timing signals DQSn and DQSn.

[0068] When the input signal DQ is the memory address ADD, the input / output circuit 40 transmits the memory address ADD to the address register 51. When the input signal DQ is the command CMD, the input / output circuit 40 transmits the command CMD to the command register 52.

[0069] The input-output circuit 40 transmits various control signals received from the memory controller 2 to the sequencer 53 .

[0070] The input-output circuit 40 transmits the ready / busy signal RBn received from the sequencer 53 to the memory controller 2 .

[0071] The peripheral circuit section 50 controls the operation in the memory cell array 100. The peripheral circuit section 50 includes an address register 51, a command register 52, a sequencer 53, a voltage generating circuit 54, a row driver 55, and a column driver 56.

[0072] The address register 51 is a register for temporarily storing a memory address ADD. The address register 51 is connected to the input-output circuit 40, the row driver 55, the row decoder 20, and the sense amplifier 30. The address register 51 receives the memory address ADD from the input-output circuit 40. For example, the memory address ADD includes a row address RA and a column address CA. The row address RA is an address for specifying the wiring in the row direction of the memory cell array 100. The column address CA is an address for specifying the wiring in the column direction of the memory cell array 100. For example, the row address RA includes a block address BA and a page address PA. For example, the block address BA is used to select a block BLK. Hereinafter, the selected block BLK is marked as "selected block BLK". In addition, the unselected block BLK is marked as "non-selected block BLK". The page address PA is used to select the wiring in the row direction (word line and select gate line). The column address CA is used to select the wiring in the column direction (bit line). For example, the address register 51 sends the page address PA to the row driver 55. The address register 51 sends the block address BA to the row decoder 20. The address register 51 sends the column address CA to the sense amplifier 30 .

[0073] The command register 52 is a register for temporarily storing the command CMD. The command register 52 is connected to the input / output circuit 40 and the sequencer 53. The command register 52 transmits the command CMD to the sequencer 53.

[0074] The sequencer 53 is a circuit that controls the overall operation of the semiconductor memory device 1. The sequencer 53 can function as a controller of the semiconductor memory device 1. For example, the sequencer 53 is connected to the input / output circuit 40, the voltage generating circuit 54, the row driver 55, the column driver 56, the row decoder 20, and the sense amplifier 30. For example, the sequencer 53 controls the voltage generating circuit 54, the row driver 55, the column driver 56, the row decoder 20, and the sense amplifier 30. For example, the sequencer 53 performs a write operation, a read operation, an erase operation, etc. based on the command CMD.

[0075] The voltage generating circuit 54 generates voltages for writing, reading, and erasing operations based on the control of the sequencer 53. The voltage generating circuit 54 is connected to the sequencer 53, the row driver 55, and the column driver 56. The voltage generating circuit 54 supplies voltages to the row driver 55 and the column driver 56.

[0076] The row driver 55 is a driver that supplies voltage to the row decoder 20. The row driver 55 is connected to the sequencer 53, the voltage generating circuit 54, and the row decoder 20. For example, the row driver 55 supplies voltage to the row decoder 20 based on the row address RA (page address PA).

[0077] The column driver 56 is a driver that supplies a voltage to the sense amplifier 30. The column driver 56 is connected to the sequencer 53, the voltage generating circuit 54, and the sense amplifier 30. For example, the column driver 56 supplies a voltage to the sense amplifier 30.

[0078] 1.1.2 Circuit structure of memory cell array

[0079] Next, refer to Figure 2 and Figure 3 , an example of the circuit structure of the memory cell array 100 is described. Figure 2 1 is a plan view showing the circuit configuration of the memory cell array 100 . Figure 3 1 is a perspective view showing the circuit structure of the memory cell array 100. Figure 2 and Figure 3 The example of FIG. 1 shows the circuit configuration of block BLK0, but the same applies to other blocks BLK. Hereinafter, the direction in which the word lines WL extend in each array chip 3 is marked as the X direction. The direction in which the bit lines BL extend, which intersects the X direction, is marked as the Y direction. The direction in which the array chips 3a and 3b and the circuit chip 4 are stacked, which intersects the X direction and the Y direction, is marked as the Z direction.

[0080] like Figure 2 As shown, for example, the block BLK0 includes four string units SU0-SU3. More specifically, the memory cell array 100a includes string units SU0 and SU1 of the block BLK0. The memory cell array 100b includes string units SU2 and SU3 of the block BLK0.

[0081] Each string unit SU includes a plurality of NAND strings NS.

[0082] The NAND string NS includes a plurality of memory cell transistors MC and selection transistors ST1 and ST2 . Figure 2 In the example of , the NAND string NS includes 192 memory cell transistors MC0 to MC191. In addition, the number of memory cell transistors MC included in the NAND string NS is arbitrary.

[0083] The memory cell transistor MC stores data in a non-volatile manner. The memory cell transistor MC includes a control gate and a charge accumulation layer. The memory cell transistor MC can be a MONOS (Metal-Oxide-Nitride-Oxide-Silicon) type or a FG (Floating Gate) type. The MONOS type uses an insulating layer in the charge accumulation layer. The FG type uses a conductor in the charge accumulation layer. The following describes the case where the memory cell transistor MC is a MONOS type.

[0084] The selection transistors ST1 and ST2 are used to select the string unit SU during various operations. Hereinafter, the selected string unit SU is marked as "selected string unit SU". In addition, the unselected string unit SU is marked as "non-selected string unit SU". The number of the selection transistors ST1 and ST2 is arbitrary. It is sufficient that the selection transistors ST1 and ST2 are included in one or more NAND string NS.

[0085] The memory cell transistor MC and the current paths of the selection transistors ST1 and ST2 in each NAND string NS are connected in series. Figure 2 In the example, from the bottom to the top of the paper, the current paths are connected in series in the order of the selection transistor ST1, the memory cell transistors MC0 to MC191, and the selection transistor ST2. That is, from the bit line BL to the source line SL, the selection transistor ST1, the memory cell transistors MC0 to MC191, and the selection transistor ST2 are connected in order. The drain of the selection transistor ST1 is connected to any bit line BL. The source of the selection transistor ST2 is connected to the source line SL.

[0086] The control gates of the plurality of memory cell transistors MC0 to MC191 in the block BLK are respectively connected in common to the word lines WL0 to WL191. In the present embodiment, each block BLK includes the word lines WL connected to the memory cell transistors MC of the memory cell array 100a, the word lines WL connected to the memory cell transistors MC of the memory cell array 100b, and the word lines WL commonly connected to the memory cell transistors MC of the memory cell array 100a and the memory cell transistors MC of the memory cell array 100b. That is, the memory cell array 100a (array chip 3a) and the memory cell array 100b (array chip 3b) share a portion of the word lines WL.

[0087] In the following, the word line WL individually set for each array chip 3 is marked as "individual word line WL". In the case of limiting the word line WL connected to the memory cell transistor MC of the memory cell array 100a (array chip 3a) and not connected to the memory cell transistor MC of the memory cell array 100b (array chip 3b), it is marked as "individual word line WLa". In the case of limiting the word line WL connected to the memory cell transistor MC of the memory cell array 100b (array chip 3b) and not connected to the memory cell transistor MC of the memory cell array 100a (array chip 3a), it is marked as "individual word line WLb. In the case of limiting the word line WL commonly connected to the memory cell transistor MC of the memory cell array 100a (array chip 3a) and the memory cell transistor MC of the memory cell array 100b (array chip 3b), it is marked as "common word line WLc. In other words, the individual word line WLa connects the array chip 3a with the row decoder 20. The individual word line WLb connects the array chip 3b and the row decoder 20. The common word line WLc connects the array chips 3a and 3b and the row decoder 20.

[0088] Figure 2 In the example, a plurality of memory cell transistors MC0 of string cells SU0 and SU1 of block BLK0 of memory cell array 100a are connected in common to an individual word line WLa0. A plurality of memory cell transistors MC0 of string cells SU2 and SU3 of block BLK0 of memory cell array 100b are connected in common to an individual word line WLb0. A plurality of memory cell transistors MC1 of string cells SU0 to SU3 of blocks BLK0 of memory cell arrays 100a and 100b are connected in common to a common word line WLc1. Other memory cell transistors MC are also similarly connected to corresponding common word lines WLc. For example, a plurality of memory cell transistors MC191 of string cells SU0 to SU3 are connected in common to a common word line WLc191. In other words, memory cell array 100a (array chip 3a) and memory cell array 100b (array chip 3b) do not share word line WL0, but share word lines WL1 to WL191. That is, the memory cell transistor MC arranged on the source line SL side of the NAND string NS is connected to the common word line WLc, and the memory cell transistor MC arranged on the bit line BL side is connected to the individual word line WL. In addition, the number of common word lines WLc in each block BLK and the arrangement of the target common word lines WLc are arbitrary. In other words, the number and arrangement of individual word lines WLa and WLb in each block BLK are arbitrary.

[0089] In each block BLK, gates of a plurality of selection transistors ST1 in the string unit SU are connected in common to one selection gate line SGD. Figure 2In the example, the gates of the multiple selection transistors ST1 in the string unit SU0 are connected in common to the selection gate line SGD0. Similarly, the gates of the multiple selection transistors ST1 in the string unit SU1 are connected in common to the selection gate line SGD1. The gates of the multiple selection transistors ST1 in the string unit SU2 are connected in common to the selection gate line SGD2. The gates of the multiple selection transistors ST1 in the string unit SU3 are connected in common to the selection gate line SGD3.

[0090] In each block BLK, the gates of multiple selection transistors ST2 in multiple string units SU of the memory cell array 100a (array chip 3a) are commonly connected to one selection gate line SGS. Similarly, the gates of multiple selection transistors ST2 in multiple string units SU of the memory cell array 100b (array chip 3b) are commonly connected to one selection gate line SGS. Hereinafter, the selection gate line SGS connected to the selection transistor ST2 of the memory cell array 100a and not connected to the selection transistor ST2 of the memory cell array 100b will be marked as "selection gate line SGSa". The selection gate line SGS connected to the selection transistor ST2 of the memory cell array 100b and not connected to the selection transistor ST2 of the memory cell array 100a will be marked as "selection gate line SGSb". Figure 2 In the example, the gates of the multiple selection transistors ST2 in the string units SU0 and SU1 are commonly connected to the selection gate line SGDa. Similarly, the gates of the multiple selection transistors ST2 in the string units SU2 and SU3 are commonly connected to the selection gate line SGDb. That is, the memory cell array 100a and the memory cell array 100b do not share the selection gate line SGS. In addition, the memory cell array 100a and the memory cell array 100b may also share the selection gate line SGS. Alternatively, like the selection gate line SGD, the selection gate line SGS may be set for each string unit SU.

[0091] The individual word lines WLa and WLb, the common word line WLc, and the select gate lines SGD and SGS are respectively connected to the row decoder 20. The row decoder 20 can apply different voltages to the individual word line WLa and the individual word line WLb.

[0092] The drains of the multiple selection transistors ST1 in the string unit SU are respectively connected to different bit lines BL. In other words, the bit line BL is commonly connected to one NAND string NS in each string unit SU of each block BLK. In other words, the memory cell array 100a and the memory cell array 100b share the bit line BL. The same column address CA is assigned to the multiple NAND strings NS connected to one bit line BL. Figure 2In the example, each string unit SU includes n+1 (n is an integer greater than 0) NAND strings NS. That is, the string unit SU includes n+1 selection transistors ST1. The drains of the n+1 selection transistors ST1 in the string unit SU are respectively connected to n+1 bit lines BL0 to BLn. The bit lines BL0 to BLn are respectively connected to the sense amplifier 30.

[0093] The multiple string units SU of the multiple blocks BLK of the memory cell array 100a (array chip 3a) are connected to one source line SL in common. That is, the sources of the multiple selection transistors ST2 in the memory cell array 100a are connected to one source line SL in common. Similarly, the multiple string units SU of the multiple blocks BLK of the memory cell array 100b (array chip 3b) are connected to one source line SL in common. That is, the sources of the multiple selection transistors ST2 in the memory cell array 100b are connected to one source line SL in common. Hereinafter, in the case of limiting the source line SL connected to the selection transistor ST2 of the memory cell array 100a and not connected to the selection transistor ST2 of the memory cell array 100b, it is marked as "source line SLa". In the case of limiting the source line SL connected to the selection transistor ST2 of the memory cell array 100b and not connected to the selection transistor ST2 of the memory cell array 100a, it is marked as "source line SLb". In addition, the memory cell array 100 a and the memory cell array 100 b may share the source line SL.

[0094] Hereinafter, a set of multiple memory cell transistors MC connected to one word line WL in one string unit SU is labeled as a "unit group CU". For example, when the memory cell transistor MC stores 1 bit of data, the storage capacity of the unit group CU is defined as "1 page of data". Based on the number of bits of data stored in the memory cell transistor MC, the unit group CU may have a storage capacity of more than 2 pages of data.

[0095] like Figure 3 As shown, in the Z direction, the array area (string units SU2 and SU3) of the block BLK0 of the memory cell array 100b is arranged above the array area (string units SU0 and SU1) of the block BLK0 of the memory cell array 100a. That is, the NAND string NS of the memory cell array 100a and the NAND string NS of the memory cell array 100b arranged above the NAND string NS are included in the same block BLK. Figure 3In the example of FIG. 1 , in one block BLK, a plurality of memory cell transistors MC arranged in the X direction and the Y direction are connected in common to one word line WL. In each of the memory cell arrays 100a and 100b, the NAND strings NS arranged in the Y direction are connected in common to the bit line BL. Furthermore, the NAND strings NS of the memory cell array 100a and the NAND strings NS of the memory cell array 100b arranged in the Z direction are connected in common to one bit line BL.

[0096] 1.1.3 Line Decoder Circuit Configuration

[0097] Next, refer to Figure 4 , the circuit structure of the row decoder 20 is described. Figure 4 2 is a circuit diagram of the row decoder 20. In the following description, when the source and drain of a transistor are not limited, either the source or the drain of the transistor is marked as “one end of the transistor”, and the other of the source or the drain of the transistor is marked as “the other end of the transistor”.

[0098] like Figure 4 As shown, the row decoder 20 includes a plurality of row decoder units 200 provided for each block BLK. Figure 4 In the example, although the row decoder unit 200 corresponding to the block BLK0 is shown, the row decoder units 200 corresponding to other blocks BLK have the same structure.

[0099] The row decoder unit 200 includes a block decoder 201, a level shifter 202, a WL switch circuit group WLSW, a SGD switch circuit group SGDSW, and a SGS switch circuit group SGSSW.

[0100] The block decoder 201 decodes the block address BA. The block decoder 201 is connected to the level shifter 202 and the SGD switch circuit group SGDSW. The block decoder 201 sends the result (signal) of decoding the block address BA to the level shifter 202 and the SGD switch circuit group SGDSW. The block decoder 201 is connected to a plurality of switch circuits (transistors T2) of the SGD switch circuit group SGDSW via the signal line RDECn. The transistor T2 of the SGD switch circuit group SGDSW is controlled based on the voltage of the signal applied to the signal line RDECn. In addition, the signal line RDECn may also be connected to the level shifter 202.

[0101] The level shifter 202 shifts the potential level of the signal received from the block decoder 201. For example, the level shifter 202 shifts the voltage (potential) level of the high ("H") level signal received from the block decoder 201 to the voltage VRDEC. The level shifter 202 is connected to a plurality of switch circuits (transistors T3) of the WL switch circuit group WLSW, a plurality of switch circuits (transistors T1) of the SGD switch circuit group SGDSW, and a plurality of switch circuits (transistors T4) of the SGS switch circuit group SGSSW via the signal line TG. The transistor T3 of the WL switch circuit group WLSW, the transistor T1 of the SGD switch circuit group SGDSW, and the transistor T3 of the SGS switch circuit group SGSSW are controlled based on the voltage of the signal applied to the signal line TG.

[0102] The SGD switch circuit group SGDSW is a set of multiple switch circuits that control the connection between the row driver 55 and the multiple selection gate lines SGD. The SGD switch circuit group SGDSW includes multiple high-voltage n-channel MOS transistors T1 and T2. The transistors T1 and T2 function as switch circuits that control the connection between the row driver 55 and the selection gate lines SGD. Figure 4 In the example of , the SGD switch circuit group SGDSW includes transistors T1_0 to T1_3 and T2_0 to T2_3. In addition, the number and arrangement of transistors T1 and T2 are designed based on the configuration of the select gate line SGD.

[0103] One end of the transistor T1_0 is connected to the selection gate line SGD0. The other end of the transistor T1_0 is connected to the row driver 55 via the wiring SGD0_SEL. The gate of the transistor T1_0 is connected to the signal line TG.

[0104] One end of the transistor T2_0 is connected to the selection gate line SGD0. The other end of the transistor T2_0 is connected to the row driver 55 via the wiring SGD0_USEL. The gate of the transistor T2_0 is connected to the signal line RDECn.

[0105] One end of the transistor T1_1 is connected to the selection gate line SGD1. The other end of the transistor T1_1 is connected to the row driver 55 via the wiring SGD1_SEL. The gate of the transistor T1_1 is connected to the signal line TG.

[0106] One end of the transistor T2_1 is connected to the selection gate line SGD1. The other end of the transistor T2_1 is connected to the row driver 55 via the wiring SGD1_USEL. The gate of the transistor T2_1 is connected to the signal line RDECn.

[0107] One end of the transistor T1_2 is connected to the selection gate line SGD2. The other end of the transistor T1_2 is connected to the row driver 55 via the wiring SGD2_SEL. The gate of the transistor T1_2 is connected to the signal line TG.

[0108] One end of the transistor T2_2 is connected to the selection gate line SGD2. The other end of the transistor T2_2 is connected to the row driver 55 via the wiring SGD2_USEL. The gate of the transistor T2_2 is connected to the signal line RDECn.

[0109] One end of the transistor T1_3 is connected to the selection gate line SGD3. The other end of the transistor T1_3 is connected to the row driver 55 via the wiring SGD3_SEL. The gate of the transistor T1_3 is connected to the signal line TG.

[0110] One end of the transistor T2_3 is connected to the selection gate line SGD3. The other end of the transistor T2_3 is connected to the row driver 55 via the wiring SGD3_USEL. The gate of the transistor T2_3 is connected to the signal line RDECn.

[0111] The row driver 55 applies a voltage corresponding to the selected block BLK to the wirings SGD0_SEL to SGD3_SEL, and applies a voltage corresponding to the non-selected block BLK to the wirings SGD0_USEL to SGD3_USEL.

[0112] The WL switch circuit group WLSW is a set of multiple switch circuits that control the connection between the row driver 55 and the multiple word lines WL. The WL switch circuit group WLSW includes multiple high-voltage n-channel MOS transistors T3. The transistor T3 functions as a switch circuit that controls the connection between the row driver 55 and the word lines WL. Figure 4 In the example, the WL switch circuit group WLSW includes transistors T3_a0, T3_b0, ..., T3_k (k is an integer greater than 1), ..., T3_191. For example, the variable k represents the boundary between the transistor T3 corresponding to the individual word line WL and the transistor T3 corresponding to the common word line WLc. For example, transistors T3_a0 to T3_a(k-1) correspond to individual word lines WLa0 to WLa(k-1), respectively. Transistors T3_b0 to T3_b(k-1) correspond to individual word lines WLb0 to WLb(k-1), respectively. Transistors T3_k to T3_191 correspond to common word lines WLck to WLc191, respectively. In addition, the number and configuration of transistors T3 are designed based on the configuration of the word line WL.

[0113] One end of the transistor T3_a0 is connected to the individual word line WLa0. The other end of the transistor T3_a0 is connected to the row driver 55 via the wiring CGa0. The gate of the transistor T3_a0 is connected to the signal line TG.

[0114] One end of transistor T3_b0 is connected to individual word line WLb0. The other end of transistor T3_b0 is connected to row driver 55 via wiring CGb0. The gate of transistor T3_b0 is connected to signal line TG. That is, individual word line WLa0 and individual word line WLb0 are connected to different switch circuits (transistor T3).

[0115] One end of the transistor T3_k is connected to the common word line WLck. The other end of the transistor T3_k is connected to the row driver 55 via the wiring CGk. The gate of the transistor T3_k is connected to the signal line TG.

[0116] One end of the transistor T3_191 is connected to the common word line WLc191. The other end of the transistor T3_191 is connected to the row driver 55 via the wiring CG191. The gate of the transistor T3_191 is connected to the signal line TG.

[0117] The row driver 55 applies a voltage corresponding to the selection block BLK to the wirings CGa0 , CGb0 , and CG1 to CG191 .

[0118] The SGS switch circuit group SGSSW is a set of multiple switch circuits that control the connection between the row driver 55 and the multiple select gate lines SGS. The SGS switch circuit group SGSSW includes multiple high-breakdown voltage n-channel MOS transistors T4. The transistors T4 function as switch circuits that control the connection between the row driver 55 and the select gate lines SGS. Figure 4 In the example of FIG. 1 , the SGS switch circuit group SGSSW includes two high-voltage n-channel MOS transistors T4_a and T4_b. The number and arrangement of the transistors T4 are designed based on the configuration of the select gate line SGS.

[0119] One end of the transistor T4_a is connected to the selection gate line SGSa. The other end of the transistor T4_a is connected to the row driver 55 via the wiring GSGSa. The gate of the transistor T4_a is connected to the signal line TG.

[0120] One end of the transistor T4_b is connected to the selection gate line SGSb. The other end of the transistor T4_b is connected to the row driver 55 via the wiring GSGSb. The gate of the transistor T4_b is connected to the signal line TG.

[0121] The row driver 55 applies a voltage corresponding to the selected block BLK to the wirings GSGSa and GSGSb.

[0122] For example, in a write operation, a read operation, or an erase operation, when the block address BA is consistent with the corresponding block BLK0, the block decoder 201 sends a signal of "H" level to the level shifter 202, and applies a low (Low) ("L") level voltage (for example, ground voltage Vss) to the signal line RDECn. As a result, the level shifter 202 applies the voltage VRDEC to the signal line TG as an "H" level voltage. In addition, when the block address BA is inconsistent with the corresponding block BLK0, the block decoder 201 sends a signal of "L" level to the level shifter 202, and applies an "H" level voltage to the signal line RDECn. As a result, the level shifter 202 applies an "L" level voltage to the signal line TG. When the "H" level voltage is applied to the signal line TG, the transistors T1, T3, and T4 are set to the on state. In addition, when the "H" level voltage is applied to the signal line RDECn, the transistor T2 is set to the on state. In addition, the “H” level voltage applied to the signal line RDECn is lower than the “H” level voltage (voltage VRDEC) applied to the signal line TG.

[0123] 1.1.4 Chip Configuration

[0124] Next, refer to Figure 5 , an example of the configuration of each chip is described. Figure 5 3 is a cross-sectional view showing the arrangement of array chips 3a and 3b and circuit chip 4. Figure 5 In the example of FIG. 1 , in order to simplify the description, one individual word line WLa and WLb, one common word line WLc, and one bit line BL are shown respectively. Also, the select gate lines SGD and SGS and the source line SL are omitted.

[0125] Hereinafter, when the Z direction is defined, the direction from the array chip 3 toward the circuit chip 4 is referred to as the Z1 direction, and the direction opposite to the Z1 direction is referred to as the Z2 direction.

[0126] like Figure 5 As shown, array chip 3a is bonded on circuit chip 4 toward Z2 direction. Moreover, array chip 3b is bonded on array chip 3a. In other words, circuit chip 4 is bonded on the surface of array chip 3a facing Z1 direction. Moreover, array chip 3b is bonded on the surface of array chip 3a facing Z2 direction. In other words, circuit chip 4, array chip 3a and array chip 3b are laminated in sequence toward Z2 direction.

[0127] A row decoder 20 and a sense amplifier 30 are provided on a semiconductor substrate 400 of the circuit chip 4 .

[0128] Memory cell arrays 100a and 100b are provided in array chips 3a and 3b, respectively.

[0129] The block BLK is formed by a part of the memory cell array 100a and a part of the memory cell array 100b arranged in the Z direction. The common word line WLc is shared by the memory cell array 100a and the memory cell array 100b. The individual word line WLa is connected to the memory cell transistor MC of the memory cell array 100a, and is not connected to the memory cell transistor MC of the memory cell array 100b. The individual word line WLb is connected to the memory cell transistor MC of the memory cell array 100b, and is not connected to the memory cell transistor MC of the memory cell array 100a.

[0130] The bit line BL is shared by the memory cell array 100 a and the memory cell array 100 b .

[0131] 1.1.5 Configuration of storage cell array

[0132] Next, refer to Figure 6 , an example of the configuration of the memory cell array 100 is described. Figure 6 3 is a perspective view showing the arrangement of array chips 3a and 3b and circuit chip 4. Figure 6 In the example of FIG. 1 , for simplicity of description, one individual word line WLa and WLb, a common word line WLc, a bit line BL, and a signal line (eg, a signal line for transmitting a signal DQ) are shown respectively. In addition, the selection gate lines SGD and SGD and the source line SL are omitted.

[0133] like Figure 6 As shown, the array chip 3a includes a memory cell array 100a, a WL connection portion 110a, a BL connection portion 120a, and a signal connection portion 130a. Similarly, the array chip 3b includes a memory cell array 100b, a WL connection portion 110b, a BL connection portion 120b, and a signal connection portion 130b.

[0134] The WL connecting portions 110 a and 110 b are regions where contact plugs, wirings, and the like are provided to connect the word line WL and the select gate lines SGD and SGS to the row decoder 20 .

[0135] Figure 6 In the example, the WL connection portion 110a is arranged adjacent to the memory cell array 100a in the X direction. The word line WL provided in the memory cell array 100a is led out to the WL connection portion 110a. The word line WL provided in the memory cell array 100a is connected to the contact plug electrically connected to the row decoder 20 in the WL connection portion 110a. In addition, the configuration of the WL connection portion 110a is arbitrary. For example, a plurality of WL connection portions 110a may be provided. In addition, the WL connection portion 110a may also be provided in the memory cell array 100a.

[0136] Similarly, the WL connection portion 110b is arranged adjacent to the memory cell array 100b in the X direction. Moreover, the WL connection portion 110b is arranged above the WL connection portion 110a. The word line WL provided in the memory cell array 100b is led out to the WL connection portion 110b. The word line WL provided in the memory cell array 100b is connected to the contact plug electrically connected to the row decoder 20 in the WL connection portion 110b. In addition, the configuration of the WL connection portion 110b is arbitrary. For example, a plurality of WL connection portions 110b may be provided. In addition, the WL connection portion 110b may also be provided in the memory cell array 100b.

[0137] For example, the individual word line WLa is connected to the row decoder 20 via the WL connecting portion 110 a .

[0138] For example, the individual word line WLb is connected to the row decoder 20 via the WL connecting portions 110a and 110b. The individual word line WLb is not electrically connected to the word line WL provided in the memory cell array 100a in the WL connecting portion 110a.

[0139] For example, the common word line WLc is connected to the row decoder 20 via WL connecting portions 110a and 110b. The word line WL of the memory cell array 100a and the word line WL of the memory cell array 100b are electrically connected at the WL connecting portion 110a.

[0140] The BL connecting portions 120 a and 120 b are regions where contact plugs, wirings, and the like that connect the bit lines BL and the sense amplifiers 30 are provided.

[0141] Figure 6 In the example, the BL connection portion 120a is arranged adjacent to the memory cell array 100a in the Y direction. The bit line BL provided in the memory cell array 100a is led out to the BL connection portion 120a. The bit line BL provided in the memory cell array 100a is connected to the contact plug electrically connected to the sense amplifier 30 in the BL connection portion 120a. In addition, the configuration of the BL connection portion 120a is arbitrary. For example, a plurality of BL connection portions 120a may be provided.

[0142] Similarly, the BL connection portion 120b is arranged adjacent to the memory cell array 100b in the Y direction. Moreover, the BL connection portion 120b is arranged above the BL connection portion 120a. The bit line BL provided in the memory cell array 100b is led out to the BL connection portion 120b. The bit line BL provided in the memory cell array 100b is connected to the contact plug electrically connected to the sense amplifier 30 in the BL connection portion 120b. In addition, the configuration of the BL connection portion 120b is arbitrary. For example, a plurality of BL connection portions 120b may be provided.

[0143] The bit line BL is connected to the sense amplifier 30 via the BL connecting portions 120a and 120b. The bit line BL of the memory cell array 100a and the bit line BL of the memory cell array 100b are electrically connected at the BL connecting portion 120a.

[0144] The signal connection portions 130 a and 130 b are regions where signal lines (contact plugs, wirings, etc.) are provided to connect the external connection terminals PD and the input / output circuit 40 . Figure 6 In the example, the signal connection part 130a is arranged at the end of the array chip 3a in the Y direction. Similarly, the signal connection part 130b is arranged at the end of the array chip 3b in the Y direction. For example, along the Z direction, the input-output circuit 40 and the signal connection parts 130a and 130b are arranged. In addition, the arrangement of the signal connection parts 130a and 130b is arbitrary. For example, the signal connection parts 130a and 130b can also be arranged in plurality.

[0145] The signal connection portion 130b is provided with an external connection terminal PD. For example, the external connection terminal PD is connected to the input / output circuit 40 via a signal line provided in the signal connection portions 130a and 130b. The signal line is not electrically connected to the memory cell arrays 100a and 100b.

[0146] The circuit chip 4 includes, for example, a WL connection portion 21 and a BL connection portion 31 .

[0147] The WL connection portion 21 is a region where contact plugs and wirings are provided to connect the row decoder 20 to the word line WL and the selection gate lines SGD and SGS. In the circuit chip 4, the word line WL and the selection gate lines SGD and SGS are connected to the row decoder 20 via the WL connection portion 21. The WL connection portion 21 and the WL connection portions 110a and 110b are arranged along the Z direction. In addition, the row decoder 20 is arranged adjacent to the WL connection portion 21. For example, a row decoder 20 may be arranged in the WL connection portion 21. Figure 4 The row decoder 20 described herein includes a WL switch circuit group WLSW, a SGD switch circuit group SGDSW, and a SGS switch circuit group SGSSW.

[0148] The BL connection portion 31 is a region where contact plugs and wirings are provided to connect the sense amplifier 30 to the bit line BL. In the circuit chip 4, the bit line BL is connected to the sense amplifier 30 via the BL connection portion 31. The BL connection portion 31 and the BL connection portions 120a and 120b are arranged along the Z direction. In addition, the sense amplifier 30 is arranged adjacent to the BL connection portion 31.

[0149] 1.1.6 Cross-sectional structure of memory cell array

[0150] Next, refer to Figure 7, an example of the cross-sectional structure of the memory cell array 100 is described. Figure 7 is a cross-sectional view of the memory cell array 100 . Figure 7 In the example of FIG. 3 , the case where five word lines WL0 to WL4 are provided in each array chip 3 is described. More specifically, Figure 7 In the example of , the array chip 3a includes an individual word line WLa0 and common word lines WLc1 to WLc4. In addition, the array chip 3b includes an individual word line WLb0 and common word lines WLc1 to WLc4.

[0151] like Figure 7 As shown, the semiconductor memory device 1 has a bonded structure in which array chips 3a and 3b are bonded to a circuit chip 4. The chips are electrically connected to each other via electrodes provided on the chips.

[0152] First, the internal structure of the array chip 3a will be described.

[0153] The array chip 3a includes a memory cell array 100a and various wiring layers for connecting to other chips.

[0154] The array chip 3 a includes insulating layers 301 , 305 , 310 , and 313 , wiring layers 302 , 304 , and 308 , a semiconductor layer 303 , and conductors 306 , 307 , 309 , 311 , 312 , and 314 .

[0155] In the memory cell array 100a, a plurality of insulating layers 301 and a plurality of wiring layers 302 are alternately stacked layer by layer. Figure 7 In the example, seven wiring layers 302 functioning as the selection gate line SGD, the word lines WL0a0 and WLc1 to WLc4, and the selection gate line SGS are sequentially stacked toward the Z2 direction.

[0156] The insulating layer 301 may include silicon oxide (SiO), for example. The wiring layer 302 includes a conductive material. The conductive material may include a metal material, an n-type semiconductor, or a p-type semiconductor. As the conductive material of the wiring layer 302, for example, a stacked structure of titanium nitride (TiN) / tungsten (W) is used. In this case, TiN is formed in a manner covering W. In addition, the wiring layer 302 may include a high dielectric constant material such as aluminum oxide (AlO). In this case, the high dielectric constant material is formed in a manner covering the conductive material.

[0157] For example, the plurality of wiring layers 302 are separated for each block BLK by a component SLT extending in the X direction. The component SLT includes an insulating layer 305. The insulating layer 305 may include SiO. In addition, the component SLT may include a conductor that is electrically connected to the semiconductor layer 303 and is not electrically connected to the wiring layer 302. In this case, the insulating layer 305 is formed so as to surround the side surface of the component SLT. Moreover, the inside of the insulating layer 305 is buried with a conductor.

[0158] In the Z2 direction, a semiconductor layer 303 is provided above the wiring layer 302 that functions as a selection gate line SGS. An insulating layer 301 is provided between the wiring layer 302 and the semiconductor layer 303. The semiconductor layer 303 functions as a source line SL. In the Z2 direction, a wiring layer 304 is provided above the semiconductor layer 303. The wiring layer 304 is used as a wiring layer for electrically connecting the semiconductor layer 303 to other chips. The wiring layer 304 includes a conductive material. The conductive material may include a metal material, an n-type semiconductor, or a p-type semiconductor. For example, the wiring layer 304 includes aluminum (Al).

[0159] In the memory cell array 100a, a plurality of memory pillars MP are provided. For example, the memory pillar MP has a substantially cylindrical shape extending in the Z direction. One memory pillar MP corresponds to one NAND string NS. The memory pillar MP penetrates (passes) through a plurality of wiring layers 302. The end of the memory pillar MP in the Z2 direction is in contact with the semiconductor layer 303.

[0160] In the Z1 direction, above the end of the memory column MP, a conductor 306 is provided. For example, the conductor 306 has a substantially cylindrical shape. The conductor 306 functions as a contact plug. Above the conductor 306, a conductor 307 is provided. For example, the conductor 307 has a substantially cylindrical shape. The conductor 307 functions as a contact plug. In the Z1 direction, above the memory column MP, a plurality of wiring layers 308 are provided. The wiring layer 308 extends in the Y direction. The plurality of wiring layers 308 are arranged and configured in the X direction. The wiring layer 308 functions as a bit line BL. The wiring layer 308 is electrically connected to any memory column MP via the conductors 306 and 307. That is, one end of the memory column MP is connected to the source line SL. The other end of the memory column MP is connected to the bit line BL. The conductors 306 and 307 and the wiring layer 308 may include metal materials such as W, Al, or copper (Cu).

[0161] In the Z1 direction, a conductor 309 is provided on the wiring layer 308. In other words, in the BL connection portion 120a, the wiring layer 308 (bit line BL) is connected to the conductor 309. For example, the conductor 309 has a substantially cylindrical shape. The conductor 309 functions as a contact plug. The conductor 309 may include a metal material such as W, Al, or Cu.

[0162] In the Z1 direction, an insulating layer 310 is disposed on the insulating layer 301. The insulating layer 310 may include SiO.

[0163] A plurality of conductors 311 are provided in the same layer as the insulating layer 310. The conductors 311 function as electrodes for electrically connecting to other chips. The conductors 311 may contain Cu.

[0164] In the Z1 direction, a conductor 311 is provided on the conductor 309 .

[0165] Alternatively, a plurality of wiring layers may be provided between the conductor 311 and the wiring layer 308 .

[0166] In the Z2 direction, the conductor 312 is provided on the wiring layer 308. In other words, in the BL connection portion 120a, the wiring layer 308 (bit line BL) is connected to the conductor 312. For example, the conductor 312 has a substantially cylindrical shape. The conductor 312 functions as a contact plug. The conductor 312 may include a metal material such as W, Al, or Cu.

[0167] In the Z2 direction, an insulating layer 313 is provided on the wiring layer 304 and the insulating layer 301. The insulating layer 313 may include SiO.

[0168] A plurality of conductors 314 are provided in the same layer as the insulating layer 313. The conductors 314 function as electrodes for electrically connecting to other chips. The conductors 314 may contain Cu.

[0169] In the Z2 direction, a conductor 314 is provided on the conductor 312 .

[0170] Next, the internal structure of the memory column MP will be described.

[0171] The memory pillar MP includes a blocking insulating film 320 , a charge accumulation layer 321 , a tunnel insulating film 322 , a semiconductor layer 323 , a core layer 324 , and a cap layer 325 .

[0172] More specifically, a memory hole MH is provided that penetrates (passes through) a plurality of wiring layers 302. The memory hole MH corresponds to the memory pillar MP. The end of the memory hole MH in the Z2 direction reaches the semiconductor layer 303. On the side of the memory hole MH, a blocking insulating film 320, a charge accumulation layer 321, and a tunnel insulating film 322 are stacked in order from the outside. For example, when the memory hole MH is cylindrical, the blocking insulating film 320, the charge accumulation layer 321, and the tunnel insulating film 322 each have a cylindrical shape. The semiconductor layer 323 is provided in contact with the side of the tunnel insulating film 322. The end of the semiconductor layer 323 in the Z2 direction is in contact with the semiconductor layer 303. The semiconductor layer 323 is a region where the channels of the memory cell transistor MC and the selection transistors ST1 and ST2 are formed. Therefore, the semiconductor layer 323 functions as a signal line that connects the current paths of the selection transistor ST2, the memory cell transistors MC0 to MC4, and the selection transistor ST1. The inside of the semiconductor layer 323 is buried by the core layer 324. A cap layer 325 is provided on the ends of the semiconductor layer 323 and the core layer 324 in the Z1 direction and is in contact with the tunnel insulating film 322. That is, the memory pillar MP includes the semiconductor layer 323 extending in the Z direction through the plurality of wiring layers 302.

[0173] The blocking insulating film 320, the tunnel insulating film 322, and the core layer 324 may include SiO. The charge accumulation layer 321 may include silicon nitride (SiN). The semiconductor layer 323 and the cap layer 325 may include, for example, polysilicon.

[0174] The memory pillar MP is combined with the wiring layer 302 functioning as the word line WL to form a memory cell transistor MC. Figure 7 In the example, in the array chip 3a, the memory column MP is respectively combined with the wiring layer 302 that functions as the word line WL0a0 and WLc1~WLc4, thereby forming the memory cell transistors MC0~MC5. Similarly, in the array chip 3b, the memory column MP is respectively combined with the wiring layer 302 that functions as the word line WL0b0 and WLc1~WLc4, thereby forming the memory cell transistors MC0~MC5. In addition, the memory column MP is combined with the wiring layer 302 that functions as the selection gate line SGD, thereby forming the selection transistor ST1. The memory column MP is combined with the wiring layer 302 that functions as the selection gate line SGS, thereby forming the selection transistor ST2. In other words, the memory column MP has the memory cell transistor MC and the selection transistors ST1 and ST2.

[0175] Next, the internal structure of the array chip 3b will be described. The following description will focus on the differences from the array chip 3a.

[0176] In the array chip 3b, the conductors 312 and 314 described in the configuration of the array chip 3a are discarded. The other configurations are the same as those of the array chip 3a. Figure 7 In the example, the 7-layer wiring layer 302 that functions as the selection gate line SGD, the word lines WL0b0 and WLc1 to WLc4, and the selection gate line SGS are stacked in sequence toward the Z2 direction. The wiring layer 308 of the array chip 3b is electrically connected to the wiring layer 308 of the array chip 3a via the conductors 309 and 311 of the array chip 3b and the conductors 312 and 314 of the array chip 3a.

[0177] Next, the circuit chip 4 will be described.

[0178] The circuit chip 4 includes a plurality of transistors Tr and various wiring layers. The plurality of transistors Tr are used for the row decoder 20 and the sense amplifier 30, etc.

[0179] More specifically, the circuit chip 4 includes a semiconductor substrate 400 , insulating layers 401 , 402 , and 410 , a gate insulating film 403 , a gate electrode 404 , conductors 405 , 407 , 409 , and 411 , and wiring layers 406 and 408 .

[0180] An element isolation region is provided near the surface of the semiconductor substrate 400. The element isolation region electrically isolates, for example, an n-type well region and a p-type well region provided near the surface of the semiconductor substrate 400. The element isolation region is buried by an insulating layer 401. The insulating layer 401 may include SiO.

[0181] On the semiconductor substrate 400, an insulating layer 402 is provided. The insulating layer 402 may include SiO.

[0182] The transistor Tr includes a gate insulating film 403 provided on a semiconductor substrate 400, a gate electrode 404 provided on the gate insulating film 403, and a source and a drain (not shown) formed on the semiconductor substrate 400. The source and the drain are electrically connected to a wiring layer 406 via a conductor 405. The conductor 405 extends in the Z2 direction. The conductor 405 functions as a contact plug. A conductor 407 is provided on the wiring layer 406. The conductor 407 extends in the Z2 direction. The conductor 407 functions as a contact plug. A wiring layer 408 is provided on the conductor 407. A conductor 409 is provided on the wiring layer 408. The conductor 409 extends in the Z2 direction. The conductor 409 functions as a contact plug. The wiring layers 406 and 408 are made of a conductive material. The conductors 405, 407, and 409, and the wiring layers 406 and 408 may include a metal material, a p-type semiconductor, or an n-type semiconductor. The number of wiring layers provided in the circuit chip 4 is arbitrary.

[0183] In the Z2 direction, an insulating layer 410 is disposed on the insulating layer 402. The insulating layer 410 may include SiO.

[0184] A plurality of conductors 411 are provided in the same layer as the insulating layer 410. The conductors 411 function as electrodes for electrically connecting to other chips. For example, one conductor 411 is provided on one conductor 409. The conductor 411 may include a metal material such as Cu. The conductor 411 of the circuit chip 4 is in contact (electrically connected) with the conductor 311 of the array chip 3a.

[0185] 1.2 Erase Action

[0186] Next, the erase operation is described. The erase operation of this embodiment includes a block erase operation and a sub-block erase operation. In the block erase operation, one block BLK is selected to perform the erase operation. In the sub-block erase operation, one sub-block SB in the block BLK is selected to perform the erase operation. The block BLK can be divided into a plurality of sub-blocks SB in which a plurality of word lines WL are set as one unit.

[0187] Next, refer to Figure 8 , a specific example of the sub-block erasing action is described. Figure 8 It is a diagram showing the structure of the block BLK and the change in the data writing state by the sub-block erasing operation. Figure 8 The example of SB1 shows the sub-block erasing operation of the sub-block SB1. The same is true for the other sub-blocks SB.

[0188] like Figure 8 As shown, one circle represents one unit cell CU. A black circle represents a state where data is written to the unit cell CU (a state where valid data is stored). A white circle represents a state where data of the unit cell CU is erased (a state where no valid data is stored).

[0189] Figure 8 In the example, block BLK0 includes six string units SU0 to SU5. String units SU0 to SU2 are provided in memory cell array 100a. String units SU3 to SU5 are provided in memory cell array 100b. In each of memory cell arrays 100a and 100b, 192 word lines WL0 to WL191 are provided.

[0190] More specifically, the string cells SU0-SU2 of the memory cell array 100a are connected to individual word lines WLa0-WLa63 and common word lines WLc64-WLc191. The string cells SU3-SU5 of the memory cell array 100b are connected to individual word lines WLb0-WLb63 and common word lines WLc64-WLc191. That is, the memory cell arrays 100a and 100b do not share the word lines WL0-WL63, but share the word lines WL64-WL191.

[0191] For example, a collection of cell groups CU of string cells SU0 to SU2 of the memory cell array 100a connected to individual word lines WLa0 to WLa63 and a collection of cell groups CU of string cells SU3 to SU5 of the memory cell array 100b connected to individual word lines WLb0 to WLb63 is set as sub-block SB0. A collection of cell groups CU of string cells SU0 to SU2 of the memory cell array 100a connected to common word lines WLc64 to WLc127 and a collection of cell groups CU of string cells SU3 to SU5 of the memory cell array 100b is set as sub-block SB1. A collection of cell groups CU of string cells SU0 to SU2 of the memory cell array 100a connected to common word lines WLc128 to WLc191 and a collection of cell groups CU of string cells SU3 to SU5 of the memory cell array 100b is set as sub-block SB2.

[0192] Figure 8 (a) in FIG. 1 shows a state where data is written to all unit groups CU in block BLK0. In this state, for example, a sub-block erase operation of sub-block SB1 is performed. Figure 8 As shown in (b) in FIG. 1 , the data of the cell group CU in the sub-block SB1 of the memory cell arrays 100a and 100b are erased.

[0193] 1.3 Write Action

[0194] Next, the programming operation is described. The programming operation includes a programming operation and a programming verification operation.

[0195] The programming action is an action to increase the threshold voltage of the memory cell transistor MC by injecting electrons into the charge accumulation layer (or to maintain the threshold voltage by hardly injecting electrons into the charge accumulation layer). Hereinafter, the memory cell transistor MC that increases the threshold voltage is marked as "memory cell transistor MC of the programming object". In addition, the memory cell transistor MC that does not increase the threshold voltage is marked as "memory cell transistor MC of programming prohibited". In the programming action, each memory cell transistor MC is set as a programming object or programming prohibited based on the write data stored in the sense amplifier 30. For example, when the write data is "0", the memory cell transistor MC is set as a programming object. In addition, when the write data is "1", the memory cell transistor MC is set as programming prohibited.

[0196] The programming verification action is an action to read data after the programming action and determine whether the threshold voltage of the memory cell transistor MC reaches the target level (the state of the write target). In the following, the case where the number of memory cell transistors MC whose threshold voltage reaches the target level is greater than the preset number is marked as "verification passed", and the case where the number of memory cell transistors MC whose threshold voltage reaches the target level does not reach the preset number is marked as "verification failed". More specifically, for example, in the programming verification action, if the number of failed bits of the read data does not reach the preset reference value, it is determined as "verification passed". On the other hand, if the number of failed bits of the read data is greater than the preset reference value, it is determined as "verification failed". As a result of the programming verification action, the memory cell transistor MC whose threshold voltage has not reached the state of the write target is set as the memory cell transistor MC of the programming object. In addition, the memory cell transistor MC whose threshold voltage reaches the state of the write target is set as the memory cell transistor MC of the programming prohibited.

[0197] By repeating a combination of a program operation and a program verification operation (hereinafter referred to as a "program loop"), the threshold voltage of the memory cell transistor MC rises to a target level.

[0198] 1.3.1 Command sequence for write action

[0199] Next, refer to Fig. 9 , an example of a command sequence for a write action is described. Fig. 9 is the command sequence for write action. Fig. 9 In the example of FIG. 1 , signals CEn, CLE, ALE, WEn, and REn other than signal DQ and signal RBn are omitted for simplicity of explanation. In the following, in signal DQ, commands are indicated by circular frames, memory addresses are indicated by square frames, and data are indicated by hexagonal frames.

[0200] like Fig. 9 As shown, the memory controller 2 first sends a command "80h" to the semiconductor memory device 1. The command "80h" is a command to notify that a write operation is to be performed.

[0201] Next, the memory controller 2 sends a memory address ADD, data DT, and command “10h” to the semiconductor memory device 1. Command “10h” is a command to instruct execution of a write operation. The memory address ADD can be sent in multiple cycles based on the configuration of the memory cell array 100.

[0202] When receiving the command “10h”, the sequencer 53 sets the ready busy signal RBn to the “L” level and executes the write operation.

[0203] When the write operation is completed, the sequencer 53 sets the ready busy signal RBn to the "H" level.

[0204] 1.3.2 Memory Address

[0205] Next, refer to Fig.10 , an example of memory address ADD is explained. Fig.10 This is a diagram of the structure of the memory address ADD.

[0206] like Fig.10 As shown, the memory address ADD includes a block address BA, a page address PA, and a column address CA. Fig.10 In the example, the column address CA is set on the lower-order address side, and the block address BA is set on the upper-order address side.

[0207] The column address CA is, for example, a 16-bit binary representation range from address CA0 to address CA15. For example, the number of bits of the column address CA is arbitrarily set based on the number of bit lines BL (data length of one page of data).

[0208] The page address PA is, for example, a region represented by 11 bits in binary from address RA0 to address RA10. The number of bits of the page address PA is arbitrarily set based on, for example, the configuration of the block BLK.

[0209] The block address BA is, for example, a range represented by the address RA11 to the address RAi (i is an integer greater than 11). The number of bits of the block address BA is arbitrarily set based on, for example, the number of blocks BLK.

[0210] Next, the structure of the page address PA will be described in detail.

[0211] Fig.10 In the example of , the page address PA includes a string cell address, an array address, a word line address, and a subblock address from the lower address side. For example, the selection order of the cell group CU in the write operation or the read operation is based on the address order of the page address PA.

[0212] The string unit address is address information for selecting a string unit SU, that is, selecting a gate line SGD. For example, when one array chip 3 includes four string units SU, the string unit address is represented by a 2-bit address RA0 and an address RA1. In addition, the number of bits of the string unit address is arbitrarily set based on, for example, the number of string units SU included in one array chip 3.

[0213] The array address is address information for selecting the array chip 3. For example, when the semiconductor memory device 1 includes two array chips 3a and 3b, that is, when the memory cell array 100 includes memory cell arrays 100a and 100b, the array address is represented by a 1-bit address RA2. The number of bits of the array address is arbitrarily set based on the number of array chips 3, for example.

[0214] The word line address is address information for selecting a word line WL in a sub-block SB. When a sub-block SB includes 64 word lines WL, the word line address is represented by 6-bit addresses RA3 to RA8. The number of bits of the word line address is arbitrarily set based on, for example, the number of word lines WL included in the sub-block SB.

[0215] The sub-block address is address information for selecting a sub-block SB in a block BLK. When a block BLK includes three or four sub-blocks SB, the sub-block address is represented by two-bit addresses RA9 and RA10. The number of bits of the sub-block address is arbitrarily set, for example, based on the number of sub-blocks SB included in the block BLK.

[0216] 1.3.3 Data writing order

[0217] Next, refer to Fig.11 , an example of the order in which data is written is described. Fig.11 Is based on Fig.10 The diagram shows the order in which data at the memory address ADD is written. Fig.11 The example schematically shows the cross-sectional structure of the string unit SU in the block BLK0. One square in each string unit SU represents one unit group CU corresponding to one word line WL. That is, one square corresponds to one write operation. In addition, Fig.11 The numbers in the squares indicate the writing order (selection order) of the data of the unit group CU.

[0218] like Fig.11 As shown, for example, the block BLK0 includes eight string units SU0-SU7. The string units SU0-SU3 are disposed in the memory cell array 100a. The string units SU4-SU7 are disposed in the memory cell array 100b.

[0219] For example, first, in the state where the word line WL0 and the array chip 3a (memory cell array 100a) are selected, the string cell address of the lower-order address is incremented. That is, the string cells SU0 to SU3 of the memory cell array 100a are selected in sequence (write order "1" to "4"). Next, the array address of the upper-order address is incremented, and the array chip 3b (memory cell array 100b) is selected. In the above state, the string cell address of the lower-order address is incremented. That is, the string cells SU4 to SU7 of the memory cell array 100b are selected in sequence (write order "5" to "8"). Next, the word line address located in the upper order of the array address is incremented. Thus, the word line WL1 is selected. As in the case of the word line WL0, the string cells SU0 to SU3 of the memory cell array 100a (write order "9" to "12") and the string cells SU4 to SU7 of the memory cell array 100b (write order "13" to "16") are selected in sequence. Thereafter, similarly, the word line WL and the string unit SU are selected.

[0220] 1.3.4 Specific example of selecting a cell group connected to a common word line

[0221] Next, a specific example in which a selected cell unit CU (hereinafter referred to as “selected cell unit CU”) is connected to the common word line WLc in a write operation will be described.

[0222] 1.3.4.1 Block composition and data writing status

[0223] First, refer to Fig.12 , the structure of block BLK and the data writing status are explained. Fig.12 It is a diagram showing the structure of the block BLK and the change in the data writing state by the writing operation of the sub-block SB1.

[0224] like Fig.12 As shown, one circle represents one unit cell CU. A black circle represents a state where data is written to the unit cell CU (a state where valid data is stored). A white circle represents a state where data of the unit cell CU is erased (a state where no valid data is stored). A double circle represents a selected unit cell CU.

[0225] The structure of block BLK0 is Figure 8 The same is true for the description of . Sub-block SB0 does not share the word line WL. Sub-blocks SB1 and SB2 share the word line WL.

[0226] More specifically, the string units SU0-SU2 of the memory cell array 100a are connected to individual word lines WLa0-WLa63 and common word lines WLc64-WLc191. The unit groups CU corresponding to the individual word lines WLa0-WLa63 are included in the sub-block SB0. The unit groups CU corresponding to the common word lines WLc64-WLc127 are included in the sub-block SB1. The unit groups CU corresponding to the common word lines WLc128-WLc191 are included in the sub-block SB2.

[0227] The string units SU3 to SU5 of the memory cell array 100b are connected to individual word lines WLb0 to WLb63 and common word lines WLc64 to WLc191. The cell groups CU corresponding to the individual word lines WLb0 to WLb63 are included in the sub-block SB0. The cell groups CU corresponding to the common word lines WLc64 to WLc127 are included in the sub-block SB1. The cell groups CU corresponding to the common word lines WLc128 to WLc191 are included in the sub-block SB2.

[0228] Fig.12 (a) in FIG. 1 represents a state where the data of sub-block SB1 is erased by a sub-block erase operation. For example, in the state, a write operation of sub-block SB1 is performed. Thus, Fig.12 As shown in (b), data is written sequentially from the cell group CU of the string cell SU0 of the memory cell array 100a connected to the common word line WLc64. In the case of the write operation of the sub-block SB1, there is a cell group CU in the data write state on the bit line BL side and the source line SL side of the selected cell group CU.

[0229] 1.3.4.2 Voltage of Each Wiring During Writing Operation

[0230] Next, refer to Fig.13 , the voltage of each wiring during the write operation is described. Fig.13 3 is a timing chart showing the voltage of each wiring during the writing operation of the sub-block SB1. Fig.13 The example represents one programming loop. In the following description, the word line WL selected as the object of the write action is marked as "selected word line WL_sel". In the case of limiting the word line WL whose data has been erased among the word lines WL that are not selected as the object of the write action (hereinafter, marked as "unselected word line WL"), it is marked as "unselected word line WL_unsel_e". In the case of limiting the word line WL whose data has been written among the unselected word lines WL, it is marked as "unselected word line WL_unsel_p". Fig.12In the example (b), the common word line WLc64 of the sub-block SB1 is selected. In this case, the common word line WLc64 is the selected word line WL_sel. The common word lines WLc65 to WLc127 are the unselected word lines WL_unsel_e. The individual word lines WLa0 to WLa63, WLb0 to WLb63, and WLc128 to WLc191 are the unselected word lines WL_unsel_p.

[0231] like Fig.13 As shown, first, the programming operation at times T0 to T8 will be described.

[0232] In the programming operation, the period from time T0 to time T3 is a precharge period of the channel of the selected memory cell transistor MC (hereinafter referred to as “selected memory cell transistor MC”).

[0233] At time T0, the channel of each NAND string NS in the selection block BLK is precharged to prohibit writing. More specifically, the sense amplifier 30 applies the voltage Vddsa to the bit line BL. The voltage Vddsa is a positive voltage higher than the voltage Vss. The voltage Vsrc_p is applied to the source line SL (source lines SLa and SLb). The voltage Vsrc_p is a voltage for the purpose of improving the precharging of the channel and the cut-off characteristics of the selection transistor ST2. The voltage Vsrc_p is a positive voltage higher than the voltage Vss. In addition, the voltage Vsrc_p can also be the same voltage value as the voltage Vddsa. The row decoder 20 applies the voltage Vsgd_p to the selection gate line SGD corresponding to the selection string unit SU. The voltage Vsgd_p is a voltage higher than the threshold voltage of the selection transistor ST1. The selection transistor ST1 is set to the on state. As a result, the voltage of the bit line BL above the voltage Vss is applied to the channel of the NAND string NS in the selection string unit SU. The row decoder 20 applies voltage Vsg to the selection gate line SGS and the selection gate line SGD corresponding to the non-selected string unit SU. Voltage Vsg is a voltage higher than voltage Vddsa. Thus, a higher voltage can be applied from the bit line BL or the source line SL to the channel of the NAND string NS in the non-selected string unit SU within the range of the voltage applied to the bit line BL or the source line SL. In addition, the row decoder 20 applies voltage Vpre1 ​​to the non-selected word line WL_unsel_p. Voltage Vpre1 ​​is a voltage higher than the threshold voltage of the written memory cell transistor MC. Thus, the memory cell transistor MC to which data has been written is set to the on state. The row decoder 20 applies voltage Vss to the non-selected word line WL_unsel_e. The threshold voltage of the memory cell transistor MC from which data has been erased is lower than voltage Vss. Therefore, the threshold voltage of the memory cell transistor MC from which data has been erased is set to the on state. The row decoder 20 applies voltage Vss to the selection word line WL_sel. The selected memory cell transistor MC is set to the on state because the data has been erased. In addition, the row decoder 20 can also apply a voltage Vpre_sel to the selected word line WL_sel. The voltage Vpre_sel is a voltage higher than the voltage Vss. Through these actions, the channels of each NAND string NS in the selection block BLK are precharged from the bit line BL or the source line SL.

[0234] At time T1, the row decoder 20 applies voltage Vss to the select gate line SGS and the select gate line SGD corresponding to the non-selected string unit SU. The select transistor ST2 and the select transistor ST1 corresponding to the non-selected string unit SU are set to an off state. As a result, the channels of each NAND string NS in the non-selected string unit SU are set to a floating state.

[0235] In the described state, the sense amplifier 30 applies a voltage Vss to the bit line BL corresponding to the "0" data, that is, the bit line BL corresponding to the selection memory cell transistor MC of the programming object. Thus, the voltage Vss is applied to the channel of the selection memory cell transistor MC corresponding to the programming object in the selection string unit SU (the channel is discharged). On the other hand, the sense amplifier 30 continues to apply a voltage Vddsa to the bit line BL corresponding to the "1" data, that is, the bit line BL corresponding to the selection memory cell transistor MC of the programming prohibited. Therefore, the selection transistor ST1 corresponding to the selection memory cell transistor MC of the programming prohibited is set to the disconnected state. Thus, the channel of the selection memory cell transistor MC corresponding to the programming prohibited in the selection string unit SU is set to a floating state. That is to say, each channel in the non-selection string unit SU and the channel of the selection memory cell transistor MC corresponding to the programming prohibited in the selection string unit SU are set to a floating state.

[0236] At time T2 , the row decoder 20 applies the voltage Vss to the unselected word line WL_unsel_p.

[0237] The time period from T3 to T7 is a period during which a write pulse is applied.

[0238] At time T3, the row decoder 20 applies the voltage Vpass_e to the selected word line WL_sel and the unselected word line WL_unsel_e. The row decoder 20 applies the voltage Vpass-pa to the individual word line WLa in the unselected word line WL_unsel_p. The row decoder 20 applies the voltage Vpass-pb to the individual word line WLb in the unselected word line WL_unsel_p. The row decoder 20 applies the voltage Vpass-p to the common word line WLc in the unselected word line WL_unsel_p. The voltage Vpass_e is the voltage applied to the memory cell transistor MC in the erased state. The voltage Vpass_e is a voltage that can be set independently of the threshold voltage of the memory cell transistor MC in the written state. The voltages Vpass_p, Vpass_pa, and Vpass_pb are the voltages applied to the memory cell transistor MC in the written state. The voltages Vpass_p, Vpass_pa, and Vpass_pb are voltages that turn on the memory cell transistor MC without depending on the threshold voltage of the memory cell transistor MC. In addition, the voltages Vpass_p, Vpass_pa, and Vpass_pb are higher than the voltage Vpre1. For example, when the cell group CU of the memory cell array 100a (array chip 3a) is selected, the voltages Vpass_p, Vpass_pa, and Vpass_pb are in the relationship of Vpass_pa < Vpass_p < Vpass_pb. In addition, for example, when the cell group CU of the memory cell array 100b (array chip 3b) is selected, the voltages Vpass_p, Vpass_pa, and Vpass_pb are in the relationship of Vpass_pa > Vpass_p > Vpass_pb. In addition, the voltages Vpass_e, Vpass_p, Vpass_pa, and Vpass_pb may also be different for each word line WL.

[0239] Each channel in the unselected string unit SU and the channel corresponding to the programming-prohibited selected memory cell transistor MC in the selected string unit SU are in a floating state. When the potential of the word line WL rises, the potential of these channels rises due to coupling (hereinafter, referred to as "channel boosting"). By channel boosting, the potential difference between the word line WL and the channel is limited to a range where writing does not occur.

[0240] At this time, in the array chip 3 that does not include the selection unit group CU (hereinafter, marked as "non-selection array chip 3"), all string units SU are set to a non-selection state. That is, the channel of each NAND string NS in the non-selection array chip 3 is set to a floating state. In the said state, the voltage (for example, voltage Vpass_pb) of the individual word line WL corresponding to the non-selection word line WL_unsel_p on the non-selection array chip 3 side is set to be higher than the voltage Vpass_p of other non-selection word lines WL_unsel_p. As a result, the potential difference between the word line WL on the non-selection array chip 3 side and the channel is further reduced. Thereby, the influence of write interference on the non-selection array chip 3 side is reduced. That is to say, the offset of the threshold voltage of the memory cell transistor MC that is not the programming object is suppressed.

[0241] In addition, in the selection array chip 3, in order to suppress the shift of the threshold voltage of the memory cell transistor MC connected to the non-selected word line WL, the voltage (for example, voltage Vpass_pa) of the individual word line WL corresponding to the non-selected word line WL_unsel_p is set to be lower than the voltage Vpass_p of the other non-selected word lines WL_unsel_p. The voltage Vss is applied to the channel of the selected memory cell transistor MC corresponding to the programming object. Therefore, the potential difference between the word line WL on the side of the selection array chip 3 and the channel is further reduced. As a result, the influence of the write disturbance on the side of the selection array chip 3 is reduced.

[0242] Here, the voltage waveform applied to the unselected word line WL_unsel_p during the period from time T2 to time T4 can be considered to be similar to Fig.13 The dotted line equivalent waveform shown. At time T2, the row decoder 20 may not apply the voltage Vss to the non-selected word line WL_unsel_p, but continue to apply the voltage Vpre1. In the solid line waveform of the non-selected word line WL_unsel_p, at time T2, the voltage Vss is applied to the non-selected word line WL_unsel_p (the voltage Vpre1 ​​is discharged). Therefore, the potential of the precharged channel decreases during the period from time T2 to T3. During the period from time T3 to T4, when the potential applied to the non-selected word line WL_unsel_p rises to the voltage Vpre1, the potential of the channel is restored to the precharge potential during the period from time T1 to T2. Moreover, thereafter, the potential of the channel is increased only by the difference between the voltage Vpass_p and the voltage Vpre1. In this case, the potential of the channel corresponding to the unselected word line WL_unsel_p can become lower than the potential of the channel corresponding to the unselected word line WL_unsel_e.

[0243] At time T4, the row decoder 20 applies voltage Vpgm to the selection word line WL_sel. Voltage Vpgm is a high voltage used to inject electrons into the charge accumulation layer of the selection memory cell transistor MC of the programming object. Voltage Vpgm is a voltage higher than voltages Vpass_e, Vpass_e, Vpass_pa, and voltage Vpass_pb. As a result, in the selection memory cell transistor MC of the programming object, the potential difference (Vpgm-Vss) between the selection word line WL_sel and the channel becomes larger. As a result, electrons are injected into the charge accumulation layer, and the threshold voltage of the selection memory cell transistor MC rises. On the other hand, in the selection memory cell transistor MC of the programming prohibited, the potential difference between the selection word line WL_sel and the channel is smaller than that of the memory cell transistor MC of the programming object due to channel boosting. As a result, electrons are hardly injected into the charge accumulation layer, and the threshold voltage of the memory cell transistor MC is maintained (the threshold voltage does not change to the extent that the state of the write target is transformed into a higher distribution).

[0244] At time T5, the row decoder 20 applies the voltage Vpass-e to the selected word line WL_sel, that is, discharges the voltage Vpgm.

[0245] During the period from time T6 to time T8, the row decoder 20 discharges the voltage applied to the selected word line WL_sel, the unselected word line WL_unsel_e, and the unselected word line WL_unsel_p. For example, the potential of the selected word line WL_sel, the unselected word line WL_unsel_e, and the unselected word line WL_unsel_p is reduced to the voltage Vp2v. The voltage Vp2v is a voltage higher than the voltage Vss.

[0246] At time T7, the row decoder 20 applies the voltage Vss to the selection gate lines SGD and SGS, and also applies the voltage Vss to the source line SL. Thus, the programming operation is completed.

[0247] Next, the program verification operation at times T8 to T9 will be described.

[0248] At time T8, the row decoder 20 applies voltage Vvfy to the selected word line WL_sel. Voltage Vvfy is a verification voltage. Voltage Vvfy is based on the target level of the write action (the state of the write target). The sequencer 53 determines whether the verification is passed or failed based on the result of comparing the threshold voltage of the memory cell transistor MC with voltage Vvfy. The row decoder 20 applies voltage Vread to the non-selected word line WL_unsel_e and the non-selected word line WL_unsel_p. Voltage Vread is a voltage that is higher than voltage Vvfy and sets the memory cell transistor MC to the on state regardless of the threshold voltage of the memory cell transistor MC. Thus, the non-selected memory cell transistor MC is set to the on state. The row decoder 20 applies voltage Vsg to the selection gate line SGS and the selection gate line SGD corresponding to the selection string unit SU. In addition, the row decoder 20 applies voltage Vss to the selection gate line SGD corresponding to the non-selected string unit SU. Thus, in the selection string unit SU, the selection transistor ST1 is set to the on state. In addition, in the non-selection string unit SU, the selection transistor ST1 is set to the off state. In addition, the row decoder 20 may also apply the voltage Vss just after the moment T8, after temporarily applying a voltage higher than the voltage Vss to the selection gate line SGD corresponding to the non-selection string unit SU. Thus, the selection transistor ST1 is temporarily set to the on state. By temporarily setting the selection transistor ST1 of the non-selection string unit SU to the on state, the channel of the NAND string NS of the non-selection string unit SU is discharged.

[0249] The sense amplifier 30 applies a voltage Vbl_r to the bit line. The voltage Vbl_r is a positive voltage higher than the voltage Vss. The voltage Vsrc_r is applied to the source line SL. The voltage Vsrc_r is a voltage higher than the voltage Vss and lower than the voltage Vbl_r. During the period from time T8 to time T9, the sense amplifier 30 reads the data of the selected memory cell transistor MC.

[0250] At time T9, the row decoder 20 applies voltage Vss to the selected word line WL_sel, the unselected word line WL_unsel_e, the unselected word line WL_unsel_p, the selected gate lines SGD and SGS. The sense amplifier 30 applies voltage Vss to the bit line BL. The voltage Vss is applied to the source line SL. Thus, the program verification operation ends.

[0251] 1.3.5 Specific example of selecting a cell group connected to a separate word line

[0252] Next, a specific example in which the selected cell unit CU is connected to the individual word line WL in the write operation will be described. The following description will focus on the points different from the case in which the selected cell unit CU is connected to the common word line WLc.

[0253] 1.3.5.1 Block composition and data writing status

[0254] First, refer to Fig.14 , the structure of block BLK and the data writing status are explained. Fig.14 It is a diagram showing the structure of the block BLK and the change in the data writing state by the writing operation of the sub-block SB0.

[0255] like Fig.14 As shown, the block BLK0 is composed of Fig.12 same.

[0256] Fig.14 (a) in FIG. 1 shows a state where the data of the sub-block SB0 is erased by the sub-block erase operation. For example, in the state, a write operation of the sub-block SB0 is performed. Then, data is written sequentially from the cell group CU of the string unit SU0 of the memory cell array 100a connected to the individual word line WLa0. Fig.14 The example (b) shows a state where the cell group CU of the string cell SU0 of the memory cell array 100a connected to the individual word line WLa63 is selected. In this way, in the write operation of the sub-block SB0, similarly to the write operation of the sub-block SB1, there is a case where the cell group CU in the data write state exists on the bit line BL side and the source line SL side of the selected cell group CU.

[0257] 1.3.5.2 Voltage of Each Wiring During Writing Operation

[0258] Next, refer to Fig.15 , the voltage of each wiring during the write operation is described. Fig.15 2 is a timing chart showing the voltage of each wiring during the writing operation of the sub-block SB0. Fig.15 The example represents 1 programming cycle.

[0259] like Fig.15 As shown, the voltages applied to the unselected word lines WL_unsel_e, WL_unsel_p, WL_unsel_pa, and WL_unsel_pb, the select gate lines SGD and SGS, and the source line SL are Fig.13 same.

[0260] During the period from time T0 to time T4, the voltage applied to the selected word line WL_sel is Fig.13 same.

[0261] At time T4, the row decoder 20 applies different voltages to each individual word line WL in the group of individual word lines WL (individual word lines WLa and WLb) corresponding to the selected word line WL_sel. The row decoder 20 applies voltage Vpgm to the selected word line WL_sel (individual word line WL) on the selected array chip 3 side. In addition, the row decoder 20 applies voltage Vpass_e to the selected word line WL_sel (individual word line WL) on the non-selected array chip 3 side. More specifically, for example, when the individual word line WLa63 is selected, the row decoder 20 applies voltage Vpagm to the individual word line WLa63, and applies voltage Vpass_e to the individual word line WLb63 that forms the group of the individual word line WLa63. By applying voltage Vpass_e to the individual word line WL on the non-selected array chip 3 side (without applying voltage Vpagm), the influence of write disturbance on the non-selected array chip 3 side is reduced.

[0262] During the period from time T6 to time T8, the voltage applied to the selected word line WL_sel is Fig.13 same.

[0263] At time T8, the row decoder 20 applies different voltages to each individual word line WL in the group of individual word lines WL (individual word lines WLa and WLb) corresponding to the selected word line WL_sel. The row decoder 20 applies voltage Vvfy to the selected word line WL_sel (individual word line WL) on the selected array chip 3 side. In addition, the row decoder 20 applies voltage Vread to the selected word line WL_sel (individual word line WL) on the non-selected array chip 3 side. More specifically, for example, when the individual word line WLa63 is selected, the row decoder 20 applies voltage Vvfy to the individual word line WLa63, and applies voltage Vread to the individual word line WLb63 that forms the group of the individual word line WLa63.

[0264] 1.4 Effects of this Implementation

[0265] According to the configuration of this embodiment, it is possible to improve the reliability of the semiconductor memory device 1. This effect will be described in detail.

[0266] For example, a method of stacking a plurality of memory cell arrays (array chips) is known in order to achieve high integration of semiconductor memory devices. When the word lines WL of each memory cell array are connected to a circuit chip, the number of word lines WL connected to a row decoder increases. The circuit scale of the row decoder increases as the number of memory cell arrays increases. Therefore, the area of ​​the circuit chip increases.

[0267] In contrast, according to the configuration of this embodiment, a portion of a plurality of word lines WL can be shared among a plurality of array chips 3 stacked on the circuit chip 4. In other words, a common word line WLc can be provided. This can suppress an increase in the circuit scale of the row decoder 20. Therefore, an increase in the chip area of ​​the semiconductor memory device 1 can be suppressed.

[0268] Furthermore, if the configuration of this embodiment is adopted, a part of a plurality of word lines can be individually provided in a plurality of array chips 3. That is, individual word lines WL can be provided. Thus, a part of a plurality of word lines WL connected to each array chip 3 can be controlled according to each array chip 3. In the write operation, different voltages can be applied to the individual word lines WL of each array chip 3. Thus, the influence of write disturbance can be reduced. That is, the offset of the threshold voltage of the memory cell transistor MC caused by write disturbance can be suppressed. Therefore, erroneous reading can be suppressed, and the reliability of the semiconductor memory device 1 can be improved.

[0269] 1.5 Variations of the First Embodiment

[0270] Next, a modification of the first embodiment will be described. Hereinafter, the description will be mainly focused on the points different from the first embodiment.

[0271] 1.5.1 Variation 1

[0272] First, a first modification of the first embodiment will be described. In the first modification, a case where the arrangement of the common word lines WLc and the individual word lines WL is different from that of the first embodiment will be described.

[0273] 1.5.1.1 Circuit Configuration of Memory Cell Array

[0274] First, refer to Fig.16 and Fig.17 , an example of the circuit structure of the memory cell array 100 is described. Fig.16 1 is a plan view showing the circuit configuration of the memory cell array 100 . Fig.17 1 is a perspective view showing the circuit structure of the memory cell array 100. Fig.16 and Fig.17 The example shows the circuit configuration of the block BLK0, but the circuit configuration of other blocks BLK is the same.

[0275] like Fig.16 and Fig.17As shown, in this example, multiple memory cell transistors MC0 of string cells SU0 and SU1 of memory cell array 100a and multiple memory cell transistors MC191 of string cells SU0 and SU1 of memory cell array 100b are commonly connected to a common word line WLc0. Multiple memory cell transistors MC191 of string cells SU0 and SU1 of memory cell array 100a are commonly connected to an individual word line WLa191. Multiple memory cell transistors MC191 of string cells SU2 and SU3 of memory cell array 100b are commonly connected to an individual word line WLb191. That is, the memory cell transistor MC arranged on the source line SL side of the NAND string NS is connected to an individual word line WL, and the memory cell transistor MC arranged on the bit line BL side is connected to a common word line WLc. Other configurations are similar to those of the first embodiment. Figure 2 and Figure 3 same.

[0276] 1.5.1.2 Line Decoder Circuit Configuration

[0277] Next, refer to Fig.18 , the circuit structure of the row decoder 20 is described. Fig.18 is a circuit diagram of the row decoder 20.

[0278] like Fig.18 As shown, the WL switch circuit group WLSW includes transistors T3_0, T3_0, T3_1, T3_a 191, and T3_b 191. In addition, the number and arrangement of transistors T3 are designed based on the arrangement of word lines WL.

[0279] One end of the transistor T3_0 is connected to the common word line WLc0. The other end of the transistor T3_0 is connected to the row driver 55 via the wiring CG0. The gate of the transistor T3_0 is connected to the signal line TG.

[0280] One end of the transistor T3_a191 is connected to the individual word line WLa191. The other end of the transistor T3_a191 is connected to the row driver 55 via the wiring CG0. The gate of the transistor T3_a191 is connected to the signal line TG.

[0281] One end of the transistor T3_b191 is connected to the individual word line WLb191. The other end of the transistor T3_b191 is connected to the row driver 55 via the wiring CGb191. The gate of the transistor T3_b191 is connected to the signal line TG. That is, the individual word line WLa191 and the individual word line WLb191 are connected to different switch circuits.

[0282] The row driver 55 applies a voltage corresponding to the selection block BLK to the wirings CG0 , CG1 , CGa191 , and CGb191 .

[0283] Other circuit configurations are similar to those of the first embodiment. Figure 4 same.

[0284] 1.5.1.3 Block composition and data writing status

[0285] First, refer to Fig.19 , the structure of block BLK and the data writing status are explained. Fig.19 It is a diagram showing the structure of the block BLK and the data writing state using the writing operation of the sub-block SB1.

[0286] like Fig.19 As shown, block BLK0 includes six string units SU0-SU5. String units SU0-SU2 are arranged in memory cell array 100a. String units SU3-SU5 are arranged in memory cell array 100b. Sub-blocks SB0 and SB1 share a word line WL. Sub-block SB2 does not share a word line WL.

[0287] More specifically, the string units SU0 to SU2 of the memory cell array 100a are connected to the common word lines WLc0 to WLc127 and the individual word lines WLa128 to WLa191. The unit group CU corresponding to the common word lines WLc0 to WLc63 is included in the sub-block SB0. The unit group CU corresponding to the common word lines WLc64 to WLc127 is included in the sub-block SB1. The unit group CU corresponding to the individual word lines WLa128 to WLa191 is included in the sub-block SB2.

[0288] The string units SU3 to SU5 of the memory cell array 100b are connected to the common word lines WLc0 to WLc127 and the individual word lines WLb128 to WLb191. The cell groups CU corresponding to the common word lines WLc0 to WLc63 are included in the sub-block SB0. The cell groups CU corresponding to the common word lines WLc64 to WLc127 are included in the sub-block SB1. The cell groups CU corresponding to the individual word lines WLb128 to WLb191 are included in the sub-block SB2.

[0289] For example, in the write operation of the sub-block SB1, Fig.12 Similarly, data is written in order from the cell group CU of the string cell SU0 of the memory cell array 100a connected to the common word line WLc64. In this case, the first embodiment is applied to each wiring. Fig.13 The voltage of the description.

[0290] 1.5.2 Example 2

[0291] Next, a second modification of the first embodiment will be described. In the second modification, a case where the arrangement of the common word lines WLc and the individual word lines WL is different from that of the first embodiment and the first modification of the first embodiment will be described.

[0292] refer to Fig. 20 , a specific example of the configuration of the word line WL is described. Fig. 20 1 is a diagram showing a data writing state using a writing operation of the sub-block SB1.

[0293] like Fig. 20 As shown, block BLK0 includes six string units SU0 to SU5. String units SU0 to SU2 are provided in memory cell array 100a. String units SU3 to SU5 are provided in memory cell array 100b. In this example, individual word lines WL are provided near the ends of each sub-block SB, and common word lines WL are provided in the center.

[0294] More specifically, for example, the string units SU0 to SU2 of the memory cell array 100a are connected to individual word lines WLa0, WLa63, WLa64, WLa127, WLa128, and WLa191, and common word lines WLc1 to WLc62, WLc65 to WLc126, and WLc129 to WLc190. The unit group CU corresponding to the individual word lines WLa0 and WLa63 and the common word lines WLc1 to WLc62 is included in the sub-block SB0. The unit group CU corresponding to the individual word lines WLa64 and WLa127 and the common word lines WLc65 to WLc126 is included in the sub-block SB1. The unit group CU corresponding to the individual word lines WLa128 and WLa191 and the common word lines WLc129 to WLc190 is included in the sub-block SB2.

[0295] The string units SU3 to SU5 of the memory cell array 100b are connected to individual word lines WLb0, WLb63, WLb64, WLb127, WLb128, and WLb191, and common word lines WLc1 to WLc62, WLc65 to WLc126, and WLc129 to WLc190. The cell groups CU corresponding to the individual word lines WLb0 and WLb63 and the common word lines WLc1 to WLc62 are included in the sub-block SB0. The cell groups CU corresponding to the individual word lines WLb64 and WLb127 and the common word lines WLc65 to WLc126 are included in the sub-block SB1. The cell groups CU corresponding to the individual word lines WLb128 and WLb191 and the common word lines WLc129 to WLc190 are included in the sub-block SB2.

[0296] For example, in the write operation of the sub-block SB1, data is first written in order from the cell group CU of the string cell SU0 of the memory cell array 100a connected to the individual word line WLa64. When the write operation is performed on the cell group CU of the string cell SU0 connected to the individual word line WLa64, the first embodiment is applied to each wiring. Fig.15 The voltage of the description.

[0297] 1.5.3 Effects of Variations of the First Implementation Example

[0298] With the configurations of the first and second modified examples, the same effects as those of the first embodiment can be obtained.

[0299] In write disturbance, in addition to write disturbance caused by insufficient electric field between the control gate and the channel and write disturbance when the electric field between the control gate and the channel is too strong, there is also hot carrier injection type write disturbance in which hot carriers generated there jump into the charge accumulation layer due to the potential difference between the source and the drain of the memory cell transistor MC. For example, in the NAND string NS, they are easy to be generated in the memory cell transistor MC near the selection gate lines SGD and SGS that become physically discontinuous, or in the part where the characteristics of the memory cell transistor MC change greatly due to the change of the processing shape of the memory hole MH (for example, the diameter of the memory hole MH, etc.). Therefore, even near the end of the sub-block SB, it is possible to be easily generated physically or electrically. In contrast, if the second variation of the first embodiment is configured, individual word lines WL can be set near the end of the sub-block SB. Thus, write disturbance can be suppressed.

[0300] 2. Second Implementation Method

[0301] Next, the second embodiment will be described. In the second embodiment, a different writing order will be described. The following description will focus on the differences from the first embodiment.

[0302] 2.1 Memory Address

[0303] First, refer to Fig.21 , an example of memory address ADD is explained. Fig.21 This is a diagram of the structure of the memory address ADD.

[0304] like Fig.21 As shown, the memory address ADD includes a block address BA, a page address PA, and a column address CA. Fig.21 In the example of , the page address PA includes a string cell address, a word line address, and an array address from the lower-order address side. Fig.21 The example does not contain sub-block addresses.

[0305] In this example, the array address is located at the upper level of the word line address. Therefore, for example, in the state where the array chip 3a is selected in the array address, the word line address is incremented. Moreover, after the increment of the word line address reaches the end, the array address is incremented to select the array chip 3a. Therefore, after the writing in the memory cell array 100a is completed, the memory cell array 100b is selected.

[0306] 2.2 Data writing order

[0307] Next, refer to Fig. 22 , an example of the order in which data is written is described. Fig. 22 Is based on Fig.21 The diagram shows the order in which data at the memory address ADD is written.

[0308] like Fig.21 As shown, the block BLK0 includes eight string units SU0 to SU7. The string units SU0 to SU3 are disposed in the memory cell array 100a. The string units SU4 to SU7 are disposed in the memory cell array 100b. Fig. 22 In the example, block BLK0 includes word lines WL0-WL2.

[0309] For example, first, in the state where the array chip 3a (memory cell array 100a) and the word line WL0 are selected, the string cell address of the lower-level address is incremented. That is, the string cells SU0 to SU3 (write order "1" to "4") of the memory cell array 100a are selected in sequence. Next, the word line address is incremented and the word line WL1 is selected. In the state, the string cell address is incremented. That is, the string cells SU0 to SU3 (write order "5" to "8") are selected in sequence. Next, the word line address is incremented. Thus, the word line WL2 is selected. In the state, the string cell address is incremented. That is, the string cells SU0 to SU3 (write order "9" to "12") are selected in sequence. When the word line address increments until it reaches the end, the upper-level address, that is, the array address, is incremented. Thus, the array chip 3b is selected. In other words, when the write action in the memory cell array 100a is completed, the memory cell array 100b is selected. Similar to the array chip 3a, first, in the state where the word line WL0 is selected, the string cell address is incremented. That is, the string cells SU4 to SU7 are selected in sequence (the writing order is "13" to "16"). Next, the word line address is incremented, and the word line WL1 is selected. In the above state, the string cell address is incremented. That is, the string cells SU4 to SU7 are selected in sequence (the writing order is "17" to "20"). Next, the word line address is incremented. Thus, the word line WL2 is selected. In the above state, the string cell address is incremented. That is, the string cells SU4 to SU7 are selected in sequence (the writing order is "21" to "24"). Thus, the writing operation in the memory cell array 100b is completed.

[0310] 2.3 Specific example of block structure and data writing status

[0311] Next, refer to Fig.23 , a specific example of the structure of the block BLK and the data writing status is described. Fig.23 It is a diagram showing the structure of the block BLK and the change in the data writing state by the writing operation of the sub-block SB0.

[0312] like Fig.23 As shown, block BLK0 includes six string units SU0-SU5. String units SU0-SU2 are arranged in memory cell array 100a. String units SU3-SU5 are arranged in memory cell array 100b. In each of memory cell arrays 100a and 100b, 192 word lines WL0-WL191 are arranged.

[0313] More specifically, for example, the memory cell array 100a is set as a sub-block SB0. The string units SU0 to SU2 of the memory cell array 100a are connected to common word lines WLc0 to WLc127 and individual word lines WLa128 to WLa191. That is, word lines WLa128 to WLa191 are provided on the source line SL side.

[0314] The memory cell array 100b is set as a sub-block SB1. The string units SU3 to SU5 of the memory cell array 100b are connected to common word lines WLc0 to WLc127 and individual word lines WLb128 to WLb191. That is, individual word lines WLb128 to WLb191 are provided on the source line SL side.

[0315] Fig.23 (a) in FIG. 1 shows a state where the sub-block SB0, that is, the data of the memory cell array 100a, is erased by a sub-block erase operation. For example, in the state, a write operation of the sub-block SB0 is performed. Thus, data is written sequentially from the cell group CU of the string unit SU0 connected to the common word line WLc0. Fig.23 The example (b) shows a state where the cell group CU of the string unit SU0 connected to the common word line WLc63 is selected.

[0316] like Fig.23 As shown in (b) of FIG. 1 , when the write operation of sub-block SB0 is executed, there is a case where data has already been written to the sub-block SB1 (array chip 3b). In this case, in order to suppress the write disturbance in the non-selected array chip 3b, the first embodiment is applied to each wiring. Fig.13 and Fig.15More specifically, in the write operation of the sub-block SB0, when the cell group CU connected to any one of the common word lines WLc0 to WLc127 is a programming target, the voltage of the first embodiment is applied to each wiring. Fig.13 When the cell group CU connected to any one of the individual word lines WLa127 to WLa191 is a programming target, the voltage of the first embodiment is applied to each wiring. Fig.15 The same applies to the write operation of the sub-block SB1.

[0317] 2.4 Effects of this Implementation

[0318] According to the configuration of this embodiment, the same effects as those of the first embodiment can be obtained.

[0319] 2.5 Variations of the Second Embodiment

[0320] Next, a modification of the second embodiment will be described. Hereinafter, the description will be mainly focused on the differences from the second embodiment.

[0321] 2.5.1 Example 1

[0322] First, a first modification of the second embodiment will be described. In the first modification, a case where the arrangement of the common word lines WLc and the individual word lines WL is different from that of the second embodiment will be described.

[0323] 2.5.1.1 Cross-sectional structure of memory cell array

[0324] First, refer to Fig.24 , an example of the cross-sectional structure of the memory cell array 100 is described. Fig.24 is a cross-sectional view of the memory cell array 100 . Fig.24 The example of 1 shows one memory column MP of the array chip 3a. The configuration of the memory column MP of the array chip 3b is also the same. Fig.24 In the example, a part of the plurality of wiring layers 302 is omitted.

[0325] like Fig.24 As shown, for example, the memory pillar MP includes three memory pillars LMP, MMP, and UMP. The memory pillars LMP, MMP, and UMP are stacked in the Z1 direction to form one memory pillar MP.

[0326] The memory column LMP has a substantially cylindrical shape. The memory column LMP extends in the Z direction. The memory column LMP penetrates (passes) a plurality of wiring layers 302 that function as word lines WL128 to WL191 and a selection gate line SGS. The end of the memory column LMP in the Z2 direction is in contact with the semiconductor layer (source line SL) 303.

[0327] The memory pillar MMP has a substantially cylindrical shape. The memory pillar MMP extends in the Z direction. The memory pillar MMP penetrates (passes) a plurality of wiring layers 302 that function as word lines WL64 to WL127, respectively. The end of the memory pillar LMP in the Z2 direction is in contact with the memory pillar LMP.

[0328] The memory pillar UMP has a substantially cylindrical shape. The memory pillar UMP extends in the Z direction. The memory pillar UMP penetrates (passes) a plurality of wiring layers 302 that function as the selection gate line SGD and the word lines WL0 to WL63. The end of the memory pillar UMP in the Z2 direction is in contact with the memory pillar UMP.

[0329] For example, word lines WL0, WL63, WL64, WL127, WL128, and WL191 located at the ends of memory pillars LMP, MMP, and UMP are set as individual word lines WLa. In addition, word lines WL1 to WL62, WL65 to WL126, and WL129 to WL190 located in the center of memory pillars LMP, MMP, and UMP are set as common word lines WLc.

[0330] 2.5.1.2 Specific example of block structure and data writing status

[0331] Next, refer to Fig.25 , a specific example of the structure of the block BLK and the data writing status is described. Fig.25 It is a diagram showing the structure of the block BLK and the change in the data writing state by the writing operation of the sub-block SB0.

[0332] like Fig.25 As shown, in this example, individual word lines WL are provided near the ends of the memory pillars LMP, MMP, and UMP, and a common word line WL is provided in the center.

[0333] More specifically, for example, string units SU0-SU2 of the memory cell array 100a are connected to individual word lines WLa0, WLa63, WLa64, WLa127, WLa128 and WLa191, and common word lines WLc1-WLc62, WLc65-WLc126 and WLc129-WLc190.

[0334] The string units SU3 to SU5 of the memory cell array 100 b are connected to individual word lines WLb0 , WLb63 , WLb64 , WLb127 , WLb128 , and WLb191 , and common word lines WLc1 to WLc62 , WLc65 to WLc126 , and WLc129 to WLc190 .

[0335] As in the second embodiment, in the write operation of the sub-block SB0, when the cell group CU connected to any one of the common word lines WLc1 to WLc62, WLc65 to WLc126, and WLc129 to WLc190 is a programming target, the programming method of the first embodiment is applied to each wiring. Fig.13 When the cell group CU connected to any one of the individual word lines WLa0, WLa63, WLa64, WLa127, WLa128, and WLa191 is a programming target, the voltage of the first embodiment is applied to each wiring. Fig.15 The same applies to the write operation of the sub-block SB1.

[0336] 2.5.2 Example 2 of variation

[0337] Next, a second modification of the second embodiment will be described. In the second modification, a case where the arrangement of the common word lines WLc and the individual word lines WL is different from that of the second embodiment and the first modification of the second embodiment will be described.

[0338] 2.5.2.1 Circuit Configuration of Memory Cell Array

[0339] First, refer to Fig.26 and Fig. 27 , an example of the circuit structure of the memory cell array 100 is described. Fig.26 1 is a plan view showing the circuit configuration of the memory cell array 100 . Fig. 27 1 is a perspective view showing the circuit structure of the memory cell array 100. Fig.26 and Fig. 27 The example shows the circuit configuration of the block BLK0, but the circuit configuration of other blocks BLK is the same.

[0340] like Fig.16 and Fig.17 As shown, in this example, each current path is connected in series in the order of the selection transistor ST2, the memory cell transistors MC0 to MC191, and the selection transistor ST1. That is, from the source line SL toward the bit line BL, the selection transistor ST2, the memory cell transistors MC0 to MC191, and the selection transistor ST1 are connected in order.

[0341] The multiple memory cell transistors MC0 of the string cells SU0 and SU1 of the memory cell array 100a and the multiple memory cell transistors MC0 of the string cells SU2 and SU3 of the memory cell array 100b are connected in common to the common word line WLc0. The multiple memory cell transistors MC0 of the string cells SU0 and SU1 of the memory cell array 100a and the multiple memory cell transistors MC191 of the string cells SU0 and SU1 of the memory cell array 100b are connected in common to the individual word line WLa191. The multiple memory cell transistors MC191 of the string cells SU2 and SU3 of the memory cell array 100b are connected in common to the individual word line WLb191. That is, the memory cell transistors MC arranged on the source line SL side of the NAND string NS are connected to the common word line WLc, and the memory cell transistors MC arranged on the bit line BL side are connected to the individual word line WL. The other configurations are the same as those of the first embodiment. Figure 2 and Figure 3 same.

[0342] 2.5.2.2 Specific example of block structure and data writing status

[0343] Next, refer to Fig.28 , a specific example of the structure of the block BLK and the data writing status is described. Fig.28 It is a diagram showing the structure of the block BLK and the change in the data writing state by the writing operation of the sub-block SB0.

[0344] like Fig.28 As shown, in this example, string units SU0 to SU2 of the memory cell array 100a are connected to common word lines WLc0 to WLc127 and individual word lines WLa128 to WLa191. That is, individual word lines WLa128 to WLa191 are provided on the bit line BL side.

[0345] The string units SU3 to SU5 of the memory cell array 100b are connected to common word lines WLc0 to WLc127 and individual word lines WLb128 to WLb191. That is, the individual word lines WLb128 to WLb191 are provided on the bit line BL side.

[0346] As in the second embodiment, in the write operation of the sub-block SB0, when the cell group CU connected to any one of the common word lines WLc0 to WLc127 is a programming target, the programming method of the first embodiment is applied to each wiring. Fig.13 When the cell group CU connected to any one of the individual word lines WLa128 to WLa191 is a programming target, the voltage of the first embodiment is applied to each wiring. Fig.15 The same applies to the write operation of the sub-block SB1.

[0347] 2.5.3 Effects of this Implementation

[0348] According to the configuration of this embodiment, the same effects as those of the second embodiment can be obtained.

[0349] 3. Others

[0350] The semiconductor memory device of the embodiment includes: a first chip (3a), including a first column (MP) having a first memory cell (MC63) and a second memory cell (MC64) connected in series, a first bit line (BL) connected to one end of the first column, and a first source line (SL) connected to the other end of the first column; a second chip (3b), including a second column (MP) having a third memory cell (MC63) and a fourth memory cell (MC64) connected in series, a second bit line (BL) connected to one end of the second column, and a second source line (SL) connected to the other end of the second column; and a third chip (4), including a sense amplifier (30) commonly connected to the first bit line and the second bit line, and a row decoder (20) respectively connecting a first word line (WLa63) connected to the gate of the first memory cell, a second word line (WLb63) connected to the gate of the third memory cell, and a third word line (WLc64) connected to the gate of each of the second memory cell and the fourth memory cell.

[0351] By applying the above-described embodiment, a semiconductor memory device with improved reliability can be provided.

[0352] In addition, the embodiment is not limited to the above-described form, and various changes can be made.

[0353] The term “connected” in the above-described embodiments also includes a state of being indirectly connected with other elements such as transistors or resistors interposed therebetween.

[0354] Although several embodiments of the present invention have been described, the embodiments are presented as examples and are not intended to limit the scope of the invention. The novel embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the invention. The embodiments or their variations are included in the scope or spirit of the invention, and are also included in the invention described in the claims and their equivalents.

Claims

1. A semiconductor storage device comprising: The first chip includes: A first column having a first storage unit and a second storage unit connected in series, a first bit line connected to one end of the first column, and a first source line connected to the other end of the first column; The second chip includes: A second column having a third storage unit and a fourth storage unit connected in series, a second bit line connected to one end of the second column, and a second source line connected to the other end of the second column; and The third chip includes: a sense amplifier commonly connected to the first bit line and the second bit line, and The row decoder connects a first word line connected to a gate of the first memory cell, a second word line connected to a gate of the third memory cell, and a third word line connected to gates of the second memory cell and the fourth memory cell, respectively.

2. The semiconductor memory device according to claim 1, wherein In a write operation of the first memory cell, the row decoder applies a first voltage to the first word line, applies a second voltage lower than the first voltage to the second word line, and applies a third voltage lower than the first voltage to the third word line.

3. The semiconductor memory device according to claim 2, wherein The first column further comprises a fifth storage unit connected in series with the first storage unit and the second storage unit; The second column further comprises a sixth storage unit connected in series with the third storage unit and the fourth storage unit; and The gate of the fifth memory cell is connected to the row decoder via a fourth word line; The gate of the sixth memory cell is connected to the row decoder via the fifth word line; In the write operation of the first memory cell, the row decoder applies a fourth voltage lower than the first voltage to the fourth word line, and applies a fifth voltage higher than the fourth voltage and lower than the first voltage to the fifth word line.

4. The semiconductor memory device according to claim 3, wherein In the write operation of the first storage unit, after the row decoder applies the sixth voltage to the second word line and the seventh voltage higher than the sixth voltage to the third to fifth word lines during the first period, the second voltage is applied to the second word line, the third voltage is applied to the third word line, the fourth voltage is applied to the fourth word line, and the fifth voltage is applied to the fifth word line during the second period.

5. The semiconductor memory device according to claim 1, wherein In the write operation of the second memory cell, the row decoder applies the eighth voltage to the third word line, applies the ninth voltage lower than the eighth voltage to the first word line, and applies the tenth voltage higher than the ninth voltage and lower than the eighth voltage to the second word line.

6. The semiconductor memory device according to claim 5, wherein The first column further comprises a seventh storage unit connected in series with the first storage unit and the second storage unit; and The second column further comprises an eighth storage unit connected in series with the third storage unit and the fourth storage unit; and The gate of the seventh memory cell and the gate of the eighth memory cell are commonly connected to the row decoder via a sixth word line; In the write operation of the second memory cell, the row decoder applies an eleventh voltage, which is higher than the ninth voltage and lower than the tenth voltage, to the sixth word line.

7. The semiconductor memory device according to claim 1, wherein The third chip further includes a driving circuit for supplying voltage to the row decoder; and The row decoder comprises: a first switch circuit connected between the first word line and the driver circuit; a second switch circuit connected between the second word line and the driver circuit; and The third switch circuit is connected between the third word line and the driver circuit.

8. The semiconductor memory device according to claim 1, wherein The first column further comprises: a first selection transistor connected in series with the first memory cell and the second memory cell, and having a gate connected to the row decoder via a first selection gate line; The second column further includes a second selection transistor connected in series with the third memory cell and the fourth memory cell, and a gate of the transistor is connected to the row decoder via a second selection gate line.

9. The semiconductor memory device according to claim 8, wherein In a write operation of the first memory cell, the row decoder applies a twelfth voltage to the first selection gate line, and applies a thirteenth voltage lower than the twelfth voltage to the second selection gate line.

10. The semiconductor memory device according to claim 1, wherein The writing action includes a programming action and a programming verification action; and In the programming verification action in the writing action of the first memory cell, the row decoder applies the 14th voltage to the first word line, applies the 15th voltage higher than the 14th voltage to the second word line, and applies the 16th voltage higher than the 14th voltage to the third word line.

11. The semiconductor memory device according to claim 1, wherein The writing action includes a programming action and a programming verification action; and In the program verification operation in the write operation of the second memory cell, the row decoder applies a 17th voltage to the third word line, and applies an 18th voltage higher than the 17th voltage to the first word line and the second word line.

12. The semiconductor memory device according to claim 1, wherein The first pillars and the second pillars extend in a first direction, respectively, and are arranged side by side in the first direction.

13. The semiconductor memory device according to claim 1, wherein The second chip is bonded to the first surface of the first chip, and the third chip is bonded to the second surface of the first chip adjacent to the first surface.

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