Method for improving thermal fatigue resistance of lead-free solder interconnection BGA packaging welding spot

Abstract

The invention discloses a method for improving thermal fatigue resistance of lead-free solder interconnection BGA packaging welding spots, and relates to the field of welding for electronic packaging. A #-shaped micro-nano structure surface is processed on the surface of a PCB substrate by adopting ultrafast laser, the #-shaped micro-nano structure is a latticed linear groove microstructure formed by transversely and longitudinally crossing a plurality of transverse parallel grooves and a plurality of longitudinal parallel grooves, the adjacent distance between the transverse parallel grooves and the longitudinal parallel grooves is 80-120 microns, the width of the grooves is 10-20 microns, and the width of the grooves is 10-20 microns. The depth of the groove is about 30-50 microns, groove parameters are adjusted by adjusting ultrafast laser processing parameters, and the interior and the periphery of the groove are covered with a large number of microparticles; solder balls are planted on the bare chip through a heating plate, and the chip and the processed PCB substrate are welded and packaged through a hot air welding machine. The surface specific surface area and the structure richness are improved, and the problems that an existing BGA packaging welding spot is poor in thermal fatigue resistance, poor in durability and the like can be solved.

Description

Technical Field

[0001] The invention relates to the field of welding for electronic packaging, and in particular to a BGA packaging preparation method for improving thermal fatigue resistance. Background Art

[0002] Electronic packaging technology is one of the core technologies of the semiconductor industry and the integrated circuit industry. In recent years, electronic packaging technology has developed rapidly. BGA ball grid array packaging is a form of surface IC packaging. This packaging form greatly increases the packaging density and reduces the packaging volume. However, due to the miniaturization of electronic devices, the density of electronic packaging has gradually increased, and the size of integrated circuit packaging has gradually decreased, causing the solder joints to be subjected to the combined effects of heat, electricity, and force during service, resulting in a series of reliability problems in the solder joints. Electronic equipment is frequently started during use, which puts the electronic package in a thermal fatigue state due to temperature changes, seriously affecting the service life of the electronic package. The internal heat dissipation effect of the device and the change in ambient temperature cause the temperature of the device to fluctuate, and the inelastic deformation in the solder causes the CTE mismatch between the welding layers. This repeated thermal fatigue state causes the internal cracks of the solder joint to initiate and expand, eventually causing the solder joint to fail. For the BGA packaging structure, the device is subjected to the combined effects of heat and force during service, causing the solder joint to undergo plastic deformation. When the solder joint is in a thermal fatigue state for a long time, its mechanical properties, microstructure, and crystal orientation will change significantly.

[0003] In view of this, we propose a method to improve the thermal fatigue resistance of lead-free solder interconnect BGA package solder joints. Summary of the invention

[0004] The purpose of the present invention is to provide a method for improving the thermal fatigue resistance of lead-free solder interconnected BGA package solder joints. By processing densely arranged tic-tac-toe microstructures on the surface of the pad by ultrafast laser, the surface specific surface area and structural richness are increased. The method can be used to solve the problems of poor reliability, poor thermal fatigue resistance, and poor durability of existing BGA package solder joints.

[0005] In order to achieve the above-mentioned purpose, the present invention provides a densely arranged tic-tac-toe micro-surface, which is prepared by ultrafast laser processing technology.

[0006] A method for improving the thermal fatigue resistance of lead-free solder interconnection BGA packaging solder joints, characterized in that the substrate surface is processed by ultrafast laser to have a tic-tac-toe micro-nano structure surface, the tic-tac-toe micro-nano structure is a grid-like linear groove microstructure formed by multiple horizontal parallel and multiple vertical parallel horizontal and vertical intersections, the adjacent spacing between multiple horizontal parallel grooves and multiple vertical parallel grooves is 80-120μm, the groove width is 10-20μm, the groove depth is about 30-50um, the groove parameters are adjusted by adjusting the ultrafast laser processing parameters, and a large number of microparticles are covered inside and around the grooves. A solder ball is bonded to the chip pin, and the solder ball is heated to melt and bond with the chip pin, and the substrate and the chip are packaged in BGA.

[0007] Preferably, the substrate is a PCB substrate.

[0008] Preferably, the material of the chip is the chip material used for power devices.

[0009] Preferably, the substrate and the chip are arranged in parallel, and the surfaces of the substrate and the chip facing each other are planes.

[0010] The above method specifically comprises the following steps:

[0011] First, place the PCB substrate in a container containing pickling solution, and then place the container in an ultrasonic cleaner for cleaning; then take out the PCB substrate and let it stand to dry;

[0012] Then use sandpaper to grind the PCB substrate to ensure that the oxide layer of the Cu pad of the PCB substrate is completely removed and the connection surface is level, and then polish it;

[0013] Then the laser control system is started, and the parameters of the ultrafast laser processing equipment are adjusted to prepare the tic-tac-toe micro-nano structure.

[0014] Then, the pre-treated PCB substrate is placed within the irradiation range of the laser beam, and the translation stage is adjusted to ensure that the welding material is within the irradiation area of ​​the laser. Then, the ultrafast laser processing equipment is controlled according to the target pattern, and the laser processing time, power and other parameters are adjusted to process the surface of the PCB substrate to prepare a tic-tac-toe micro-nano structure.

[0015] Finally, the solder balls are implanted on the bare chip through the heating plate, and the chip is welded and packaged with the processed PCB substrate through a hot air welder for use and experimental research.

[0016] The pickling solution uses 30% HNO3; the thickness of the PCB substrate is 2.0mm, and the surface of the Cu pad of the PCB substrate adopts a nickel-plated gold immersion process to prevent oxidation; the solder ball uses a SAC305 solder ball with a diameter of 300μm; the chip uses a CTBGA228 model chip produced by Amkor, which contains 228 solder joints; the size of the BGA packaged device is 20mm×20mm×2mm, the BGA is a hollow structure, there are three rows of solder joints on each side, the outermost side has 22 solder joints, the solder joint diameter is 300μm, and the solder joint center distance is 500μm;

[0017] The present invention provides a method for improving the thermal fatigue resistance of lead-free solder interconnected BGA package solder joints. The method has the advantage of improving the specific surface area and structural richness of the surface by ultrafast laser processing of densely arranged tic-tac-toe microstructures. The method can be used to solve the problems of poor reliability, poor thermal fatigue resistance, and poor durability of existing BGA package solder joints. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of this patent. For ordinary technicians in this field, other drawings can be obtained based on the following drawings without creative work.

[0019] Figure 1 It is a schematic diagram of chip and substrate packaging;

[0020] Among them, 1: substrate, 2: pin, 3: chip, 4: solder ball

[0021] Figure 2 Schematic diagram of the scanning path process of processing the surface of a BGA substrate using an ultrafast laser;

[0022] Figure 3 This is the surface morphology of the BGA substrate after ultrafast laser processing;

[0023] Figure 4 This is a cross-sectional microscopic image of a lead-free solder joint made on a BGA substrate after processing it using an ultrafast laser.

[0024] Figure 5 These are cross-sectional microscopic morphologies of samples with initial cracks after thermal shock tests; (a) Example, (b) Comparative Example 1, (c) Comparative Example 2, and (d) Comparative Example 3.

[0025] Table 1 is a comparison of the initial crack generation time of each connection structure. DETAILED DESCRIPTION

[0026] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other. The described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. The present invention will be described in detail below with reference to the drawings and in combination with the embodiments.

[0027] The present invention provides a BGA packaging substrate with a microstructured surface prepared by ultrafast laser to improve the thermal fatigue reliability of solder joints. Further, the substrate is a PCB substrate.

[0028] Furthermore, the material of the chip is the chip material used in power devices.

[0029] Furthermore, the substrate is arranged parallel to the chip, and the surface of the substrate opposite to the chip is a plane.

[0030] The present invention will be further described below in conjunction with examples, but the present invention is not limited to the following examples.

[0031] Example 1: The following specifically describes the implementation method of the patent

[0032] 1. Chip and substrate preparation: Remove burrs on the surface or edges of the chip and substrate to be packaged to ensure smooth subsequent processes, then place them in alcohol for ultrasonic cleaning, dry them after cleaning to remove contaminants at the connection, and set them aside.

[0033] 2. Chip ball planting: According to the chip pin size, select a lead-free solder ball with a diameter of 0.3mm, with a specific composition of Sn96.5% / Ag3% / Cu0.5%. Use BGA package special flux paste to apply to the chip pin area, and then place the solder ball at the corresponding pin. After completion, use tweezers to place it on the preheating table. After preheating at 300℃ for one minute, start the hot air gun, and set the parameters to preheating interval 250℃, lasting 60s, heating interval 350℃, lasting 60s, reflow interval 450℃, lasting 120s, cooling interval lasting 60s, and the wind speed in each interval is set to 2. Observe the quality of ball planting after cooling. If there are defects, re-solder and set aside.

[0034] 3. Substrate preparation: Place the substrate on the ultrafast laser processing table, use a laser rangefinder to level and focus, and then place it at the processing position. Adjust the laser parameters as follows: laser power 6W, scanning speed 300mm / s, scanning groove spacing 100um, laser repetition frequency 400KHz, pulse width 12ps, scan 5 times, as shown in Figure 1 The figure shown is processed, and then cleaned with anhydrous ethanol for later use.

[0035] 4. Chip packaging: Apply flux evenly to the chip solder balls obtained in step 2, then place the chip with the ball-planting surface facing down and the substrate processing surface facing up in step 3, so that the solder balls are aligned with the pin positions; then place it on the preheating table, preheat it at 300°C for two minutes, start the hot air gun, adjust the wind speed to 4, and keep other parameters the same as in step 2; after cooling, observe whether the welding positions are consistent and whether the welding is firm.

[0036] 5. Hot and cold shock test: Place the samples after observing the morphological characteristics into the hot and cold shock test equipment, set the temperature range to -40-125℃, keep them at -40℃ and 125℃ for 15 minutes respectively, and take them out after every 100 cycles to observe the quality of the solder joints, compare the generation and expansion of cracks, and judge the thermal fatigue reliability of the solder joints.

[0037] Comparative Example 1: The following specifically describes the implementation method of the patent

[0038] Except that the ultrafast laser processing is not performed and the ball bonding is performed directly on the pre-treated substrate, the rest is basically the same as that of Example 1.

[0039] The connection structure is subjected to thermal shock test, and the results are shown in Figure 5 .

[0040] Comparative Example 2: The following specifically describes the implementation method of the patent

[0041] Except for the ultrafast laser processing parameters in step 3, the rest is basically the same as in Example 1.

[0042] The parameters of the ultrafast laser processing equipment in this comparative example are: laser power 6W, scanning speed 300mm / s, scanning groove spacing 120um, laser repetition frequency 400KHz, pulse width 12ps, scanning 5 times, as shown in Figure 1 The connection structure is processed by hot and cold shock test, and the results are shown in Figure 5 .

[0043] Comparative Example 3: The following specifically describes the implementation method of the patent

[0044] Except for the ultrafast laser processing parameters in step 3, the rest is basically the same as in Example 1.

[0045] The parameters of the ultrafast laser processing equipment in this comparative example are: laser power 6W, scanning speed 300mm / s, scanning groove spacing 100um, laser repetition frequency 400KHz, pulse width 12ps, scanning 10 times, as shown in Figure 1 The graphics shown are processed;

[0046] The connection structure is subjected to thermal shock test, and the results are shown in Figure 5 .

[0047] Table 1

[0048]

[0049] The implementation steps of the present invention are described in detail above in conjunction with the accompanying drawings. This embodiment is implemented on the premise of the technical solution of the present invention, and a detailed implementation method and a specific operation process are given. However, the protection scope of the present invention is not limited to the following embodiments. Those skilled in the art can modify and polish it without changing the spirit and content of the present invention.

Claims

1. A method for improving the thermal fatigue resistance of lead-free solder interconnect BGA package solder joints, characterized in that: The substrate surface is processed by ultrafast laser to have a tic-tac-toe micro-nano structure surface, wherein the tic-tac-toe micro-nano structure is a grid-like linear groove microstructure formed by a plurality of transverse parallel lines and a plurality of longitudinal parallel lines intersecting each other, the adjacent spacing between the plurality of transverse parallel grooves and the plurality of longitudinal parallel grooves is 80-120 μm, the groove width is 10-20 μm, the groove depth is 30-50 μm, the groove parameters are adjusted by adjusting the ultrafast laser processing parameters, and a large number of micro-particles are covered inside and around the grooves; solder balls are bonded to the chip pins, and the solder balls are heated to melt and bond the chip pins together, and the substrate and the chip are packaged in BGA.

2. The method according to claim 1, characterized in that The substrate is a PCB substrate.

3. The method according to claim 1, characterized in that The chip is made of the same material as used in power devices.

4. The method according to claim 1, characterized in that The substrate is arranged in parallel with the chip, and the surface of the substrate opposite to the chip is a plane.

5. The method according to claim 1, characterized in that The specific steps include: First, place the PCB substrate in a container containing pickling solution, and then place the container in an ultrasonic cleaner for cleaning; then take out the PCB substrate and let it stand to dry; Then use sandpaper to grind the PCB substrate to ensure that the oxide layer of the Cu pad of the PCB substrate is completely removed and the connection surface is level, and then polish it; Then the laser control system is started, and the parameters of the ultrafast laser processing equipment are adjusted to prepare the tic-tac-toe micro-nano structure. Then, the pre-treated PCB substrate is placed within the irradiation range of the laser beam, and the translation stage is adjusted to ensure that the welding material is within the irradiation area of ​​the laser. Then, the ultrafast laser processing equipment is controlled according to the target pattern, and the laser processing time, power and other parameters are adjusted to process the surface of the PCB substrate to prepare a tic-tac-toe micro-nano structure. Finally, the solder balls are implanted on the bare chip through the heating plate, and the chip is welded and packaged with the processed PCB substrate through a hot air welder for use and experimental research.

6. The method according to claim 5, characterized in that The pickling solution uses 30% HNO3; the thickness of the PCB substrate is 2.0mm, and the surface of the Cu pad of the PCB substrate adopts a nickel-plated gold immersion process to prevent oxidation; the solder ball uses a SAC305 solder ball with a diameter of 300μm; the chip uses a CTBGA228 model chip produced by Amkor, which includes 228 solder joints; the size of the BGA packaged device is 20mm×20mm×2mm, the BGA is a hollow structure, there are three rows of solder joints on each side, there are 22 solder joints on the outermost side, the solder joint diameter is 300μm, and the solder joint center distance is 500μm.

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