Semiconductor device and method of suppressing creep of underfill material on back surface of semiconductor die

Abstract

A semiconductor device has a first substrate with a surface. The thickness of the first substrate is less than 120 microns. The surface is subjected to a grinding operation. The surface of the first substrate is then polished to produce a polished surface. The first substrate is singulated into a plurality of semiconductor dies. A semiconductor die is over the interposer. The interposer has a second substrate and a conductive via formed through the second substrate. The interposer also has a first insulating layer formed over the first surface of the second substrate, a first conductive layer formed over the first surface, a second insulating layer formed over the second surface of the second substrate, a second conductive layer formed over the second surface, and a bump formed over the second conductive layer. An underfill material is deposited around the semiconductor die. The polishing surface inhibits the underfill material from progressing onto the polishing surface.

Description

Technical Field

[0001] The present invention relates generally to semiconductor devices, and more particularly, to semiconductor devices and methods for inhibiting creep of underfill material onto a back surface of a semiconductor die. Background Art

[0002] Semiconductor devices are common in modern electrical products. Semiconductor devices perform a wide range of functions such as signal processing, high-speed computing, sending and receiving electromagnetic signals, controlling electrical devices, optoelectronics, and creating visual images for television displays. Semiconductor devices are found in the fields of communications, power conversion, networking, computers, entertainment, and consumer products. Semiconductor devices are also found in military applications, aviation, automobiles, industrial controllers, and office equipment.

[0003] Semiconductor wafers typically include multiple semiconductor dies. Semiconductor dies can perform various functions, including micro-electromechanical systems (MEMS). MEMS devices can have sensors or other transducers formed on the back surface and active sensor interface components formed on the active surface. The back surface can undergo a grinding operation to flatten the surface. However, grinding creates grooves, scratches and other damage in the back surface. The semiconductor dies are singulated and can be mounted to inserts for electrical interconnection. For environmental protection, bottom fill materials are deposited around the semiconductor dies. However, it is known that bottom fill materials can creep onto the back surface of the semiconductor die and sink into grooves, scratches and other damage on the back surface. The creeping bottom fill material may damage the sensor, resulting in lower yields and higher manufacturing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1a-1i illustrates a semiconductor wafer having a plurality of semiconductor dies undergoing a grinding operation followed by a polishing operation;

[0005] Figure 2a-2d Figure 1 illustrates the formation of an interconnection insert;

[0006] Figure 3a-3f The semiconductor die is shown disposed over the interposer and an underfill material is deposited around the semiconductor die;

[0007] Figure 4 illustrates an interconnect structure formed over an interposer and an underfill material that is smaller than the height of the interconnect structure;

[0008] Figure 5a-5b An interposer and a semiconductor die are shown disposed over a package substrate; and

[0009] Figure 6 A printed circuit board (PCB) is shown with different types of packages arranged on the surface of the PCB. DETAILED DESCRIPTION

[0010] The present invention is described in one or more embodiments in the following description with reference to the figures, wherein the same numerals represent the same or similar elements. Although the present invention is described according to the best mode for achieving the purpose of the present invention, it will be appreciated by those skilled in the art that the present invention is intended to cover substitutions, modifications and equivalents that may be included within the spirit and scope of the present invention as defined by the appended claims and their equivalents, as supported by the following disclosure and the accompanying drawings. The features shown in the figures are not necessarily drawn to scale. Elements having similar functions in the figures are assigned the same reference numerals. The term "semiconductor die" as used herein refers to both the singular and plural forms of the term, and therefore may refer to both a single semiconductor device and a plurality of semiconductor devices.

[0011] Semiconductor devices are typically manufactured using two complex manufacturing processes: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves forming multiple die on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components that are electrically connected to form a functional circuit. Active electrical components such as transistors and diodes have the ability to control the flow of current. Passive electrical components such as capacitors, inductors, and resistors create the relationship between voltage and current that is necessary to perform the circuit function.

[0012] Back-end manufacturing refers to cutting or singulating the completed wafer into individual semiconductor die, and encapsulating the semiconductor die for structural support, electrical interconnection and environmental isolation. In order to singulate the semiconductor die, the wafer is scribed and broken along the non-functional area of ​​the wafer (referred to as saw road or scribing line). The wafer is singulated using a laser cutting tool or saw blade. After singulation, the individual semiconductor die is arranged on a package substrate, and the package substrate includes pins or contact pads for interconnection with other system components. Then, the contact pads formed on the semiconductor die are connected to the contact pads in the package. Electrical connection can be achieved using a conductive layer, a bump, a columnar bump, a conductive paste or a bonding wire. Encapsulant or other molding materials are deposited on the package to provide physical support and electrical isolation. The completed package is then inserted into the electrical system, and the functions of the semiconductor device are made available to other system components.

[0013] Figure 1aA semiconductor wafer 100 is shown having a base substrate material 102 such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk material for structural support. A plurality of semiconductor dies or electrical components 104 are formed on the wafer 100, separated by non-active, inter-die wafer regions or saw streets 106. The saw streets 106 provide cutting areas to singulate the semiconductor wafer 100 into individual semiconductor dies 104. In one embodiment, the semiconductor wafer 100 has a width or diameter of 100-450 millimeters (mm).

[0014] Figure 1b A cross-sectional view of a portion of a semiconductor wafer 100 is shown. Each semiconductor die 104 has a back surface 108 and an active surface 110, the active surface 110 containing analog or digital circuits, which are implemented as active devices, passive devices, conductive layers, and dielectric layers formed in the die, and are electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed in the active surface 110 to implement analog circuits or digital circuits, such as digital signal processors (DSPs), application-specific integrated circuits (ASICs), memories, or other signal processing circuits. The semiconductor die 104 may also include IPDs for RF signal processing, such as inductors, capacitors, and resistors. In one embodiment, the semiconductor die 104 is a MEMS device. For example, the semiconductor die 104 may have a sensor formed on the back surface 108, such as a pressure or temperature sensor, and an active sensor interface component formed on the active surface 110.

[0015] Conductive layer 112 is formed over active surface 110 using PVD, CVD, electrolytic plating, chemical plating, or other suitable metal deposition processes. Conductive layer 112 may be one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable conductive materials. Conductive layer 112 serves as a contact pad electrically connected to the circuit on active surface 110.

[0016] Conductive bump material is deposited on the conductive layer 112 using evaporation, electrolytic plating, chemical plating, ball drop or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder and combinations thereof, as well as optional flux solution. For example, the bump material can be eutectic Sn / Pb, high lead solder or lead-free solder. The bump material is bonded to the conductive layer 112 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form a ball or bump 114. In one embodiment, the bump 114 is formed on an under-bump metallization (UBM) having a wetting layer, a barrier layer and an adhesive layer. The bump 114 can also be compression bonded or thermocompressed to the conductive layer 112. The bump 114 represents a type of interconnect structure that can be formed on the conductive layer 112. The interconnect structure can also use bonding wires, conductive pastes, columnar bumps, microbumps or other electrical interconnects.

[0017] Semiconductor wafer 100 and semiconductor die 104 may be considered as thin devices, for example, less than 120.0 μm thick. Semiconductor die 104 may be used in a chip-on-wafer (CoW) process for small devices, as described in detail below. Figure 1c In the embodiment of the present invention, the semiconductor wafer 100 is inverted and the back surface 108 is subjected to a grinding operation using a grinder 120 to remove surface roughness. Nevertheless, the grinding operation still leaves grooves, scratches and other damage 124 in the surface 122, such as Figure 1d A top view of the semiconductor die 104 is shown. Figure 1e is a cross-sectional view of grooves, scratches, and other damage 124 in surface 122. Grooves, scratches, and other damage 124 may have a depth of 100.0 nanometers. Figure 3d As discussed in , grooves, scratches, and other damage 124 in surface 122 can cause underfill to creep into surface 122. Underfill creep introduces epoxy and other contaminants to surface 122. Underfill creep can leave epoxy and other contaminants in grooves, scratches, and other damage 124 in surface 122. Underfill contamination can adversely affect the functional performance of semiconductor die 104 as a MEMS device. For example, underfill creep can cause defects in the back surface sensor of semiconductor die 104.

[0018] exist Figure 1f 1 , the surface 122 is polished with a polisher 126 to remove grooves, scratches, and other damage 124 from the surface 122. Polishing may involve dry polishing, chemical mechanical polishing, dry etching, and other suitable polishing processes, leaving a surface 128 with a smooth, mirror-like finish. Figure 1g is a top view of the smooth, mirror-like finish of surface 128 . Figure 1his a cross-sectional view of a smooth, mirror-finished surface 128 where grooves, scratches and other damage 124 have been removed by the polishing process.

[0019] exist Figure 1i In the embodiment of the present invention, a saw blade or laser cutting tool 129 is used to singulate the semiconductor wafer 100 through the saw streets 106 into individual semiconductor dies 104. The individual semiconductor dies 104 can be inspected and electrically tested to be identified as known good dies or known good units (KGD / KGU) after singulation. Specifically, the semiconductor dies 104 have a surface 128 that originates from Figure 1f-1h The semiconductor die 104 may have a small size, for example, 0.4 mm x 0.4 mm.

[0020] Figure 2a A substrate or interposer 130 is shown made of a base material 131 such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk material for structural support. Substrate 130 has a major surface 132 and a major surface 134 opposite surface 132 .

[0021] exist Figure 2b In the embodiment of the present invention, a plurality of vias are formed through the substrate 130 using an etching process or laser direct ablation (LDA). The vias are filled with a conductive material to form conductive vias 136 extending between the surface 132 and the surface 134 of the substrate 130.

[0022] exist Figure 2c In the embodiment, an insulating or passivation layer 138 is formed on the surface 132 using PVD, CVD, printing, lamination, spin coating, spray coating, sintering or thermal oxidation. The insulating layer 138 includes one or more layers of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), solder resist, polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO) and other materials with similar insulating and structural properties. Portions of the insulating layer 138 are removed using an etching process or LDA to form an opening or through hole extending to the conductive via 136 for further electrical interconnection.

[0023] Conductive layer 140 is formed over insulating layer 138 using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layer 140 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. Conductive layer 140 extends through the opening in insulating layer 138 to conductive via 136. Conductive layer 140 serves as a redistribution layer (RDL) that provides electrical interconnection across substrate 130.

[0024] An insulating or passivation layer 146 is formed over the surface 134 using PVD, CVD, printing, lamination, spin coating, spray coating, sintering, or thermal oxidation. The insulating layer 146 comprises one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, solder resist, polyimide, BCB, PBO, and other materials having similar insulating and structural properties. Portions of the insulating layer 146 are removed using an etching process or LDA to form openings or through holes extending to the conductive vias 136 for further electrical interconnection.

[0025] Conductive layer 148 is formed on insulating layer 146 using PVD, CVD, electrolytic plating, chemical plating process or other suitable metal deposition process. Conductive layer 140 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag or other suitable conductive materials. Conductive layer 148 extends through the opening in insulating layer 146 to conductive via 136. Additional insulating layers such as 138 and 146 and conductive layers such as 140 and 148 can be formed on surface 132 and surface 134, respectively. Conductive layer 148 serves as an RDL, which provides electrical interconnection across substrate 130. Therefore, portions of conductive layer 140 are connected to portions of conductive layer 148 through conductive via 136.

[0026] exist Figure 2d In the embodiment, a conductive bump material is deposited on the conductive layer 148 using evaporation, electrolytic plating, chemical plating, ball drop or screen printing processes. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder and combinations thereof, and an optional flux solution. For example, the bump material can be eutectic Sn / Pb, high lead solder or lead-free solder. The bump material is bonded to the conductive layer 148 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form a ball or bump 150. In one embodiment, the bump 150 is formed on the UBM having a wetting layer, a barrier layer and an adhesive layer. The bump 150 can also be compression bonded or thermocompressed bonded to the conductive layer 148. The bump 150 represents a type of interconnect structure that can be formed on the conductive layer 148. The interconnect structure can also use bonding wires, conductive pastes, columnar bumps, microbumps or other electrical interconnects.

[0027] The combination of substrate 130 , conductive vias 136 , insulating layers 138 and 146 , conductive layers 140 and 148 , and bumps 150 constitute a bumped base wafer or interposer 152 .

[0028] exist Figure 3aIn the embodiment, electrical components 154a-154b are disposed on the surface 132 of the substrate 130. The electrical components 154a-154b are disposed on the raised base wafer 152, wherein the bumps 114 are oriented toward the raised base wafer 152, and the polished back surface 128 is oriented away from the raised base wafer. The electrical components 154a-154b may be from Figure 1i The semiconductor die 104. Alternatively, the electrical components 154a-154b may include other semiconductor dies, semiconductor packages, surface mount devices, RF components, discrete electrical devices, or integrated passive devices (IPDs).

[0029] The electrical components 154a-154b are positioned over the conductive layer 140 of the raised base wafer 152 using a pick and place operation. The electrical components 154a-154b are contacted with the conductive layer 140 and reflowed to make mechanical and electrical connections with the raised base wafer 152; Figure 3b The electrical components 154a-154b are shown bonded to the conductive layer 140 of the raised base wafer 152; Figure 3c 1 is a top view of electrical components 154a-154b, such as CoW 170, bonded to conductive layer 140 of bumped substrate wafer 152. Bumped substrate wafer 152 may be cleaned and subjected to automated optical inspection (AOI).

[0030] exist Figure 3d In the embodiment of the present invention, an underfill material 160 is deposited around and below the electrical components 154a-154b. The underfill material 160 may be an epoxy resin. Figure 3e 1 is a top view of an underfill material 160 deposited around and below the electrical components 154a-154b. The back surface 128 of the electrical components 154a-154b may include components of a MEMS device, such as Figure 1b It is important that the underfill material 160 does not creep onto the back surface 128. Underfill material 160 that creeps onto the back surface 128 may be considered a cosmetic defect. In addition, the underfill material 160 may cover the laser marked area on the back surface 128.

[0031] like Figure 1f-1hAs described above, the polished back surface 128 prevents the underfill material 160 from progressing or creeping onto the polished back surface 128. With the polished back surface 128, the underfill material 160 does not extend beyond the edge or boundary 162. The polished back surface 128 inhibits creeping or progressing of the underfill material 160 over the back surface of the semiconductor die. The back surface 128 of the electrical components 154a-154b, due to its smooth, mirror-like polish, remains free of contamination and other defects from potential creep of the underfill material 160. The underfill material 160 is cured, and the raised base wafer 152 is subjected to AOI.

[0032] exist Figure 3f In the embodiment, CoW 170 is singulated through substrate 152 into individual semiconductor packages 174 using a saw blade or laser cutting tool 172. Individual semiconductor packages 174 may be inspected and electrically tested to be identified as KGD / KGU after singulation.

[0033] Figure 4 The diagram is similar to Figure 3d 1, wherein interconnect structure 178 is formed over conductive layer 140. Polished back surface 128 inhibits underfill material 160 from creeping or advancing over the back surface of the semiconductor die to avoid accumulation of underfill material on the back surface, which would interfere with contact between interconnect structure 178 and other external devices. Underfill material 160 should not be higher than the top of interconnect structure 178.

[0034] Figure 5a A cross-sectional view of a package-level interconnect substrate 180 including a conductive layer 182 and an insulating layer 184 is shown. The conductive layer 182 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag or other suitable conductive materials. The conductive layer 182 may be formed using PVD, CVD, electrolytic plating, chemical plating processes or other suitable metal deposition processes. The conductive layer 182 provides horizontal electrical interconnections across the substrate 180 and vertical electrical interconnections between the top surface 186 and the bottom surface 188 of the substrate 180. Depending on the design and function of the semiconductor die 104 and other electrical components, portions of the conductive layer 182 may be electrically shared or electrically isolated. The insulating layer 184 may include one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, solder resist, polyimide, BCB, PBO, and other materials having similar insulating and structural properties. The insulating layer 184 may be formed using PVD, CVD, printing, lamination, spin coating, spray coating, sintering, or thermal oxidation. Insulating layer 184 provides isolation between conductive layers 182. There may be multiple conductive layers like 182 separated by multiple insulating layers like 184.

[0035] exist Figure 5b In, similar to Figure 3a-3b, semiconductor package 174 is mounted to substrate 180 using a pick and place operation. Conductive bump material is deposited over conductive layer 182 on surface 188 using evaporation, electrolytic plating, chemical plating, ball drop or screen printing processes. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder and combinations thereof, as well as an optional flux solution. For example, the bump material can be eutectic Sn / Pb, high lead solder or lead-free solder. The bump material is bonded to conductive layer 182 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form a ball or bump 190. In another embodiment, bump 190 is formed on a UBM having a wetting layer, a barrier layer and an adhesive layer. Bump 190 can also be compression bonded or thermocompression bonded to conductive layer 182. Bump 190 represents a type of interconnect structure that can be formed over conductive layer 182. The interconnect structure may also use conductive paste, stud bumps, micro bumps or other electrical interconnects.

[0036] The combination of semiconductor package 174 and package-level substrate 180 constitutes semiconductor package 192. Figure 1f-1h As described above, polishing the back surface 128 prevents the underfill material 160 from progressing or creeping onto the polished back surface 128. With the polished back surface 128, the underfill material 160 does not extend beyond the edge or boundary 162. The polished back surface 128 inhibits creeping or progressing of the underfill material over the back surface of the semiconductor die. The back surface 128 of the electrical components 154a-154b, due to its smooth, mirror-like polish, remains free of contamination and other defects from potential creeping of the underfill material 160.

[0037] Figure 6 Electrical device 400 is shown having a chip carrier substrate or PCB 402 with a plurality of semiconductor packages disposed on a surface of PCB 402, including semiconductor packages 174 and 192. Electrical device 400 may have one type of semiconductor package, or multiple types of semiconductor packages, depending on the application.

[0038] The electrical device 400 may be a stand-alone system that uses a semiconductor package to perform one or more electrical functions. Alternatively, the electrical device 400 may be a subcomponent of a larger system. For example, the electrical device 400 may be a part of a tablet computer, a cellular phone, a digital camera, a communication system, or other electrical device. Alternatively, the electrical device 400 may be a graphics card, a network interface card, or other signal processing cards that may be inserted into a computer. The semiconductor package may include a microprocessor, a memory, an ASIC, a logic circuit, an analog circuit, an RF circuit, a discrete device, or other semiconductor die or electrical components. Miniaturization and weight reduction are essential for the product to be accepted by the market. The distance between semiconductor devices may be reduced to achieve higher density.

[0039] exist Figure 6 4, PCB 402 provides a common substrate for structural support and electrical interconnection of semiconductor packages disposed on the PCB. Conductive signal traces 404 are formed on the surface of PCB 402 or within its layers using evaporation, electrolytic plating, chemical plating, screen printing or other suitable metal deposition processes. Signal traces 404 provide electrical communication between each of the semiconductor packages, mounted components, and other external system components. Traces 404 also provide power and ground connections for each of the semiconductor packages.

[0040] In some embodiments, the semiconductor device has two packaging levels. The first level packaging is a technology for mechanically and electrically attaching a semiconductor die to an intermediate substrate. The second level packaging involves mechanically and electrically attaching an intermediate substrate to a PCB. In other embodiments, the semiconductor device may have a first level packaging, wherein the die is mechanically and electrically directly disposed on the PCB. For purposes of illustration, several types of first level packaging are shown on PCB 402, including bonding wire packaging 406 and flip chip 408. In addition, several types of second level packaging including ball grid array (BGA) 410, bump chip carrier (BCC) 412, land grid array (LGA) 416, multi-chip module (MCM) or SIP module 418, quad flat no-lead package (QFN) 420, quad flat package 422, embedded wafer level ball grid array (eWLB) 424 and wafer level chip size package (WLCSP) 426 are shown to be disposed on PCB 402. In one embodiment, the eWLB 424 is a fan-out wafer level package (Fo-WLP) and the WLCSP 426 is a fan-in wafer level package (Fi-WLP). Depending on the system requirements, any combination of semiconductor packages configured with any combination of first-level and second-level package types, as well as other electrical components, can be connected to the PCB 402. In some embodiments, the electrical device 400 includes a single attached semiconductor package, while other embodiments require multiple interconnected packages. By combining one or more semiconductor packages on a single substrate, manufacturers can incorporate prefabricated components into electrical devices and systems. Because semiconductor packages include complex functions, electrical devices can be manufactured using less expensive components and streamlined manufacturing processes. The resulting device is less likely to fail and is cheaper to manufacture, resulting in lower costs for consumers.

[0041] While one or more embodiments of the present invention have been described in detail, those skilled in the art will appreciate that modifications and adaptations may be made to those embodiments without departing from the scope of the invention as set forth in the appended claims.

Claims

1. A method for manufacturing a semiconductor device, comprising: providing a first substrate; polishing a surface of the first substrate to produce a polished surface; singulating the first substrate into a plurality of semiconductor dies; Provide inserts; disposing a semiconductor die over the interposer; and An underfill material is deposited around the semiconductor die, wherein the polishing surface inhibits progression of the underfill material onto a surface of a substrate. 2 . The method of claim 1 , further comprising grinding the surface of the substrate before polishing the surface of the substrate.

3. The method according to claim 1, wherein: Providing the insert comprises: providing a second substrate; and A conductive via is formed through the second substrate.

4. The method according to claim 3, wherein: Providing the insert also includes: forming a first insulating layer over the first surface of the second substrate; and A first conductive layer is formed over the first surface of the second substrate.

5. The method according to claim 4, wherein: Providing the insert also includes: forming a second insulating layer over a second surface of the second substrate opposite to the first surface of the second substrate; forming a second conductive layer over the second surface of the second substrate; and A bump is formed on the second conductive layer.

6. A method for manufacturing a semiconductor device, comprising: providing a first substrate; polishing a surface of the first substrate to produce a polished surface; singulating the first substrate into a plurality of semiconductor dies; and An underfill material is deposited around the semiconductor die, wherein the polishing surface inhibits progression of the underfill material onto a surface of a substrate.

7. The method of claim 6, further comprising grinding the surface of the substrate before polishing the surface of the substrate.

8. The method according to claim 6, further comprising: Provide inserts; and A semiconductor die is disposed over the interposer.

9. The method according to claim 8, wherein: Providing the insert comprises: providing a second substrate; and A conductive via is formed through the second substrate.

10. The method according to claim 9, wherein: Providing the insert also includes: forming a first insulating layer on the first surface of the second substrate; forming a first conductive layer on the first surface of the second substrate; forming a second insulating layer over a second surface of the second substrate opposite to the first surface of the second substrate; forming a second conductive layer over the second surface of the second substrate; and A bump is formed on the second conductive layer.

11. A semiconductor device comprising: A semiconductor die including a polished surface; an interposer, wherein the semiconductor die is disposed over the interposer; and An underfill material is deposited around the semiconductor die, wherein the polishing surface inhibits progression of the underfill material onto the polishing surface of the semiconductor die.

12. The semiconductor device according to claim 11, wherein The insert comprises: substrate; and A conductive via is formed through the substrate.

13. The semiconductor device according to claim 12, wherein: The insert also includes: forming a first insulating layer on the first surface of the substrate; forming a first conductive layer on the first surface of the substrate; forming a second insulating layer on a second surface of the second substrate opposite to the first surface of the second substrate; forming a second conductive layer over the second surface of the second substrate; and A bump is formed on the second conductive layer.

14. The semiconductor device of claim 11, wherein the semiconductor die has a thickness less than 120 microns. 15 . The semiconductor device of claim 11 , further comprising a packaging substrate, wherein the interposer and the semiconductor die are disposed over the packaging substrate.

Images