Semiconductor device and manufacturing method thereof
By adjusting the stress of the second silicon oxide layer in the semiconductor device and making it parallel to the sacrificial layer, the circuit failure problem caused by the stress mismatch of the cantilever beam structure is solved, and the yield of the device is improved.
Patent Information
- Application Number
- CN202510012964.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-03
- Publication Date
- 2025-04-11
AI Technical Summary
The cantilever beam structure in existing semiconductor devices collapses or lifts due to stress mismatch, which in turn leads to failure of the device circuit.
By forming a sacrificial layer and a functional layer on the semiconductor substrate, and forming a cantilever beam layer on the sacrificial layer, including a first silicon oxide layer, a titanium nitride layer and a second silicon oxide layer. During the formation of the second silicon oxide layer, the process parameters are adjusted to adjust its stress so that the upper surface of the second silicon oxide layer is parallel to the upper surface of the sacrificial layer, thereby removing the sacrificial layer to form a cavity.
By adjusting the stress of the second silicon oxide layer, the problem of stress mismatch in the cantilever beam layer is solved, the requirement of stress matching for each layer is reduced, the yield of semiconductor devices is improved, and the problem of circuit failure is reduced.
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Figure CN119797272A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof. Background Art
[0002] Micro-Electro-Mechanical System (MEMS) is formed by integrating microcircuits and micromachines on a chip using semiconductor manufacturing technology. It has the advantages of small size (usually millimeter or micron level), low power consumption, good durability and stable performance, making it widely used in fields such as sensors.
[0003] Among them, the cantilever beam structure is a widely used structure. In the related art, the cantilever beam structure adopts a multi-layer stacking structure. As a whole, the multi-layer structure has a collapse or warping phenomenon caused by stress mismatch, which further causes device circuit failure.
[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention
[0005] In view of the problems in the prior art, the purpose of the present invention is to provide a semiconductor device and a method for manufacturing the same, which overcomes the difficulties of the prior art and can solve the problem of circuit failure of semiconductor devices in related technologies.
[0006] A first aspect of the present disclosure provides a method for manufacturing a semiconductor device, comprising:
[0007] providing a semiconductor substrate;
[0008] forming a sacrificial layer and a functional layer located in a first region on the sacrificial layer on a semiconductor substrate;
[0009] A cantilever beam layer is formed in a second region on the sacrificial layer and on a sidewall of the sacrificial layer, wherein the cantilever beam layer includes a first silicon oxide layer, a titanium nitride layer and a second silicon oxide layer which are sequentially distributed from bottom to top, and a through hole is formed in the cantilever beam layer above the second region, wherein the through hole exposes a portion of the sacrificial layer below, wherein in the process of forming the second silicon oxide layer, a process parameter is adjusted to adjust the stress of the second silicon oxide layer so that an upper surface of the second silicon oxide layer above the second region is parallel to an upper surface of the sacrificial layer, and the second region is located on at least one side of the first region;
[0010] Through the through hole, the sacrificial layer is removed to form a cavity.
[0011] In an optional embodiment, during the process of forming the second silicon oxide layer, adjusting the process parameters includes:
[0012] A second silicon oxide layer is formed by chemical vapor deposition. During the deposition process, the film forming power and / or atmosphere ratio of the chemical vapor deposition equipment are adjusted. The film forming power and atmosphere ratio are both process parameters to adjust the stress of the cantilever beam layer so that the upper surface of the second silicon oxide layer above the second region is parallel to the upper surface of the sacrificial layer.
[0013] In an optional embodiment, the film forming power is 500w-1000w;
[0014] The atmosphere ratio is that the ratio of silane gas to oxygen is in the range of 1:1 to 1.1:1.
[0015] In an optional embodiment, forming a cantilever beam layer in the second region on the sacrificial layer and on the sidewall of the sacrificial layer comprises:
[0016] Before forming the functional layer located in the first region on the sacrificial layer, forming the first silicon oxide layer on the sacrificial layer and the semiconductor substrate, and forming the functional layer above the first silicon oxide layer portion in the first region on the sacrificial layer;
[0017] After forming the functional layer above the first silicon oxide layer portion in the first area on the sacrificial layer, the titanium nitride layer and the second silicon oxide layer located above the titanium nitride layer are formed, the titanium nitride layer covers the functional layer and the sacrificial layer, and the through hole is formed in the first silicon oxide layer, the titanium nitride layer and the second silicon oxide layer above the second area.
[0018] In an alternative embodiment, the functional layer is a heat-sensitive layer.
[0019] In an optional embodiment, at least one window is formed in the titanium nitride layer and the second silicon oxide layer on the functional layer, and the window exposes the functional layer.
[0020] In an optional embodiment, before forming the functional layer above the first silicon oxide layer portion in the first region on the sacrificial layer, the method for manufacturing the semiconductor device further includes:
[0021] Patterning the first silicon oxide layer to form a connection hole in the first silicon oxide layer, wherein the connection hole exposes a connection electrode on the semiconductor substrate;
[0022] The titanium nitride layer covers the functional layer and fills the connection hole to be electrically connected to the connection electrode.
[0023] In an optional embodiment, forming the titanium nitride layer and the second silicon oxide layer located above the titanium nitride layer includes:
[0024] before forming the second silicon oxide layer located above the titanium nitride layer, forming the hard mask layer on the titanium nitride layer;
[0025] Performing a first patterning on the hard mask layer, and etching the titanium nitride layer using the first patterned hard mask layer as a mask to form a first sub-through hole and a second sub-through hole, wherein the first sub-through hole is located in a portion of the titanium nitride layer above the functional layer, and the second sub-through hole is located in a portion of the titanium nitride layer above the second region;
[0026] forming a second silicon oxide layer on the hard mask layer after the first patterning, wherein the second silicon oxide layer also fills the first sub-through hole and the second sub-through hole;
[0027] The second silicon oxide layer portion in and above the first sub-through hole is removed to form the window; and the second silicon oxide layer portion in and above the second sub-through hole and the first silicon oxide layer portion below the second sub-through hole are removed to form the through hole.
[0028] In an optional embodiment, the material of the sacrificial layer is amorphous silicon or polycrystalline silicon, and the etching gas is a fluorine-containing gas.
[0029] In an alternative embodiment, the fluorine-containing gas is XeF2.
[0030] The disclosed embodiment also provides a semiconductor device, which is manufactured using the method for manufacturing the semiconductor device of the previous embodiment.
[0031] In the manufacturing method disclosed in the present invention, during the formation of the last second silicon oxide layer in the cantilever beam layer, the stress of the second silicon oxide layer is adjusted by adjusting the process parameters so that the second silicon oxide layer achieves stress matching, and finally the upper surface of the second silicon oxide layer located on the sacrificial layer is parallel to the upper surface of the sacrificial layer, thereby reducing the disadvantage of stress matching for each layer in the cantilever beam layer, so that the stress of the cantilever beam structure meets the functional requirements of the functional layer, improves the yield of the semiconductor device, and reduces the problem of circuit failure of the semiconductor device.
[0032] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS
[0033] Other features, objectives and advantages of the present invention will become more apparent from a reading of the detailed description of non-limiting embodiments made with reference to the following accompanying drawings.
[0034] Figure 1 A flow chart showing a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.
[0035] Figure 2-Figure 13 exhibit Figure 1 The structure diagram of the semiconductor device manufacturing method at various stages is shown.
[0036] Fig.14 Demonstration of use Figure 1 A cross-sectional view of another semiconductor device obtained by the manufacturing method of the semiconductor device shown. DETAILED DESCRIPTION
[0037] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the disclosure will be more comprehensive and complete and to fully convey the concepts of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
[0038] Figure 1 A flowchart showing a method for manufacturing a semiconductor device provided by an embodiment of the present disclosure is shown in FIG. Figure 1 As shown, the method for manufacturing the semiconductor device comprises the following steps:
[0039] Step 110: providing a semiconductor substrate;
[0040] Step 120: forming a sacrificial layer and a functional layer located in a first region on the sacrificial layer on the semiconductor substrate;
[0041] Step 130: forming a cantilever beam layer in a second region on the sacrificial layer and on a sidewall of the sacrificial layer, the cantilever beam layer comprising a first silicon oxide layer, a titanium nitride layer and a second silicon oxide layer sequentially distributed from bottom to top, a through hole being formed in the cantilever beam layer above the second region, the through hole exposing a portion of the sacrificial layer below, wherein in the process of forming the second silicon oxide layer, adjusting process parameters to adjust the stress of the second silicon oxide layer so that an upper surface of the second silicon oxide layer above the second region is parallel to an upper surface of the sacrificial layer, and the second region is located on at least one side of the first region;
[0042] Step 140: removing the sacrificial layer through the through hole to form a cavity.
[0043] In the manufacturing method disclosed in the present invention, during the formation of the last second silicon oxide layer in the cantilever beam layer, the stress of the second silicon oxide layer is adjusted by adjusting the process parameters so that the second silicon oxide layer achieves stress matching, and finally the upper surface of the second silicon oxide layer located on the sacrificial layer is parallel to the upper surface of the sacrificial layer, thereby reducing the disadvantage of stress matching for each layer in the cantilever beam layer, so that the stress of the cantilever beam structure meets the functional requirements of the functional layer, improves the yield of the semiconductor device, and reduces the problem of circuit failure of the semiconductor device.
[0044] Below, the method for manufacturing a semiconductor device provided by the embodiment of the present disclosure is described in detail in conjunction with the structure of the semiconductor device at each stage during the manufacturing process.
[0045] like Figure 2 As shown, a semiconductor substrate 1 is provided.
[0046] In the embodiment of the present disclosure, the semiconductor substrate 1 provides a process operation basis for subsequent processes.
[0047] Optionally, the semiconductor substrate 1 may be a third generation wide bandgap semiconductor material such as silicon carbide or gallium nitride. In other embodiments, the material of the semiconductor substrate 1 may also be other materials such as silicon, germanium, silicon germanium, gallium arsenide or indium gallium, and the semiconductor substrate 1 may also be other types of substrates such as a silicon substrate on an insulator or a germanium substrate on an insulator. The material of the semiconductor substrate 1 may be a material suitable for process requirements or easy to integrate.
[0048] Active devices (not shown) are formed in the semiconductor substrate 1 and are used to electrically connect with subsequent functional layers.
[0049] like Figure 2 As shown, the semiconductor substrate 1 includes a substrate body 11 and an interlayer dielectric layer 12 located above the substrate body 11, wherein active devices are formed in the substrate body 11 and connected through conductive plugs (not shown in the figure) in the interlayer dielectric layer 12.
[0050] like Figure 3 As shown, a sacrificial layer 2 is formed on a semiconductor substrate 1. The sacrificial layer 2 defines the position of the cavity later and will be removed later to form the cavity.
[0051] In an optional embodiment, the material of the sacrificial layer 2 is polysilicon or amorphous silicon or other materials, which are not limited here. According to the material of the sacrificial layer 2, a suitable method is selected to manufacture the sacrificial layer 2.
[0052] In one embodiment, a whole layer of sacrificial layer material is first formed on the semiconductor substrate 1, and then the sacrificial layer material is patterned to obtain the above-mentioned sacrificial layer 2. In a corresponding embodiment, multiple sacrificial layers 2 can be formed on the semiconductor substrate 1, and isolation holes formed by etching are formed between two adjacent sacrificial layers 2 to achieve mutual isolation.
[0053] like Figure 4 As shown, a first silicon oxide layer 31 is formed on the semiconductor substrate 1 and the sacrificial layer 2. The first silicon oxide layer 31 covers the semiconductor substrate 1 and the sacrificial layer 2. The first silicon oxide layer 31 is used as a bottom film of the subsequent cantilever beam layer on the one hand, and is used to isolate the functional layer from the sacrificial layer 2 on the other hand. For the cantilever beam layer and the sacrificial layer 2, the first silicon oxide layer 31 is made in the same process step, which can simplify the process steps and improve efficiency.
[0054] like Figure 5 As shown, the first silicon oxide layer 31 is patterned to form a connection hole 31 a in the first silicon oxide layer 31 , wherein the connection hole 31 a exposes a connection electrode (not shown in the figure) on the semiconductor substrate 1 .
[0055] In one embodiment, the connecting electrode is made in advance, for example, located in a dielectric layer on the semiconductor substrate 1, and the dielectric layer is used to achieve insulation isolation. The connecting electrode is used to connect active devices on or in the semiconductor substrate 1, and is later used to connect the functional layer. Please refer to the following content for details.
[0056] like Figure 6 As shown, a functional material layer 40 is deposited, and the functional material layer 40 covers the first silicon oxide layer 31 and fills the connection hole 31a (as shown in FIG. Figure 5 shown);
[0057] like Figure 7 As shown, the functional material layer 40 is patterned to form a functional layer 4 in the first region s1 on the sacrificial layer 2, and the functional layer 4 actually covers the first silicon oxide layer 31 above the first region s1. In this process, the functional material layer portion in the connection hole 31a and the functional material layer portion on the second region s2 on the sacrificial layer 2 are removed.
[0058] Depending on the type of semiconductor device to be formed, the functional layer 4 is made of a corresponding material. For example, if the semiconductor device to be formed is an uncooled infrared detector, the functional layer 4 is a thermosensitive layer whose resistance changes according to temperature, thereby being able to detect temperature.
[0059] The sacrificial layer 2 is divided into a first area s1 and a second area s2 located at at least one side of the first area s1 , wherein the first area s1 is a formation area of the functional layer 4 , and the second area s2 is a corresponding area for making a cantilever beam structure.
[0060] like Figure 8 As shown, a titanium nitride layer 32 and a hard mask layer 33 covering the titanium nitride layer 32 are formed, and the titanium nitride layer 32 covers the functional layer 4, the sacrificial layer 2 and the filling connection hole 31a (as shown in FIG. Figure 7 shown);
[0061] like Fig. 9 As shown, the hard mask layer 33 is patterned for the first time;
[0062] like Fig.10 As shown, the titanium nitride layer 32 is etched using the hard mask layer 33 after the first patterning as a mask to form a first sub-through hole 32a and a second sub-through hole 32b. The first sub-through hole 32a is located in the portion of the titanium nitride layer 32 above the functional layer 4, and the second sub-through hole 32b is located in the portion of the titanium nitride layer 32 above the second region s2.
[0063] In this embodiment, the material of the hard mask layer 33 is silicon nitride or the like. The hard mask layer 33 has a lower etching selectivity than the titanium nitride layer 32 , so as to effectively etch the titanium nitride layer 32 .
[0064] In this embodiment, the titanium nitride layer 32 serves as an electrical connection. The titanium nitride layer 32 contacts the functional layer 4 to form an electrical connection for transmitting the electrical signal of the functional layer 4.
[0065] like Fig.10 As shown, a plurality of first sub-through holes 32a and second sub-through holes 32b are formed, which correspond to the windows and through holes described below, respectively.
[0066] In this embodiment, the hard mask layer 33 after the first patterning does not need to be removed. In another embodiment, it can also be removed.
[0067] like Fig.11 As shown, a second silicon oxide layer 34 is formed on the hard mask layer 33 after the first patterning, and the second silicon oxide layer 34 also fills the first sub-through hole 32a and the second sub-through hole 32b (as shown in FIG. Fig.10 shown).
[0068] In the embodiment of the present disclosure, during the process of forming the second silicon oxide layer 34, the process parameters are adjusted to adjust the stress of the second silicon oxide layer 34 so that the upper surface of the second silicon oxide layer 34 above the second region s2 is parallel to the upper surface of the sacrificial layer 2, thereby solving the problem of warping and collapse of the cantilever beam layer surface caused by stress mismatch, ensuring good performance of the semiconductor device and avoiding device circuit failure.
[0069] In the embodiment of the present disclosure, chemical vapor deposition is used to form the second silicon oxide layer 34. During the deposition process, the film forming power and / or atmosphere ratio of the chemical vapor deposition equipment are adjusted. The film forming power and atmosphere ratio are both process parameters to adjust the stress of the cantilever beam layer so that the upper surface of the second silicon oxide layer 34 above the sacrificial layer 2 is parallel to the upper surface of the sacrificial layer 2. In this way, even after the sacrificial layer 2 is removed later, the upper surface of the second silicon oxide layer 34 above the cavity remains in its original state, for example, remains parallel to the upper surface of the semiconductor substrate 1.
[0070] In one embodiment, the film forming power affects the stress of the second silicon oxide layer 34. For example, when the film forming power is large, tensile stress is easily generated, and when the film forming power is small, compressive stress is easily generated. Therefore, by adjusting the film forming power, the tensile stress and / or compressive stress of the second silicon oxide layer 34 can be adjusted, and finally a stress matching state is obtained, solving the warping and collapse problems caused by the internal stress mismatch of the second silicon oxide layer 34.
[0071] In an optional manner, the film forming power is 500 W-1000 W. Therefore, a suitable film forming power can be selected within this range, and the second silicon oxide layer 34 with good morphology can be obtained within this range.
[0072] In another embodiment, the atmosphere ratio refers to the ratio between different gas sources introduced during the formation of the second silicon oxide layer 34. For example, the gas sources include silane (SiH4) gas and oxygen (O2) gas, and the atmosphere ratio is that the ratio of silane gas to oxygen is in the range of 1:1 to 1.1:1. Within this range, a second silicon oxide layer 34 with a good morphology can be obtained.
[0073] In the embodiment of the present disclosure, through experimental exploration, appropriate film forming power and atmosphere ratio can be set to obtain a second silicon oxide layer 34 with good stress matching, thereby obtaining a cantilever beam layer with good morphology.
[0074] like Fig.12 As shown, the first sub-through hole 32a (as shown in Fig.10 3a; and removing the second sub-through hole 32b (as shown in Fig.10 The second silicon oxide layer 34 portion in and above the through hole 32b and the first silicon oxide layer 31 portion below the second sub-through hole 32b are formed to form the through hole 3b.
[0075] In this embodiment, the window 3a exposes the functional layer 4, so that the functional layer 4 can receive external signals. For example, when the functional layer 4 is a heat-sensitive layer, its window 3a is used to receive external light signals.
[0076] In one embodiment, the first sub-through hole 32a (eg, Fig.10 3a; and removing the second sub-through hole 32b (as shown in Fig.10 The second silicon oxide layer 34 portion in and above the second sub-through hole 32b and the first silicon oxide layer 31 portion below the second sub-through hole 32b may specifically include:
[0077] A patterned photoresist layer is formed on the second silicon oxide layer 34, and the second silicon oxide layer 34 is partially etched using the patterned photoresist layer as a mask. After etching away the second silicon oxide layer 34 in the second sub-through hole 32b, the first silicon oxide layer 31 is continuously etched until the through hole 3b is formed.
[0078] In this embodiment, the through hole 3b and the window 3a are formed in the same process, which can improve the process efficiency. In another embodiment, they can also be formed in different processes.
[0079] In this embodiment, the through hole 3 b exposes the sacrificial layer 2 below.
[0080] like Fig.13 As shown, the sacrificial layer 2 (as shown in FIG. Fig.12 As shown), a cavity 2a is formed, thereby forming a cantilever beam structure 300. The cantilever beam structure 300 is a stacked structure composed of a first silicon oxide layer 31, a titanium nitride layer 32, a hard mask layer 33 and a second silicon oxide layer 34. The functional layer 4 and the cantilever beam structure 300 are in a suspended state, and the cantilever beam structure 300 is used to support the functional layer 4.
[0081] In one embodiment, the sacrificial layer 2 (eg, Fig.12 As shown), the cavity 2a is formed, which specifically includes the following steps: an etching gas is introduced into the etching chamber, and the etching gas etches the sacrificial layer 2 through the through hole 3b to form the cavity 2a.
[0082] In this process, a dry etching process is used to remove the sacrificial layer 2. The etching gas contacts the sacrificial layer 2 through the through hole 3b, and contacts the sacrificial layer 2, generates gaseous products and is exhausted.
[0083] In one embodiment, the material of the sacrificial layer 2 is polysilicon or amorphous silicon, and the etching gas is a fluorine-containing gas.
[0084] For example, the fluorine-containing gas is XeF2 or HF, which is introduced into the etching chamber, and the active substances in the generated plasma react chemically with the sacrificial layer 2 to form volatile compounds, which are then drawn out of the etching chamber.
[0085] like Fig.13 As shown, a semiconductor device is finally formed.
[0086] In another embodiment of the present disclosure, Fig.14 As shown, the final semiconductor device is a non-cooled infrared detector, in which at least one metal reflective layer 51 is formed on the upper surface of the interlayer dielectric layer 12, and the layers are isolated from each other by a PETEOS layer 52. The PETEOS layer 52 refers to a silicon oxide film grown by using TEOS as a raw material using PECVD (Plasma Enhanced Chemical Vapor Deposition).
[0087] Among them, the metal reflective layer 51 is located at the bottom of the cavity 2a, which reflects the light, so that the reflected light irradiates the functional layer 4 using the thermosensitive layer above, causing the temperature of the thermosensitive layer to change and finally convert it into a resistance change, causing the electrical signal to change.
[0088] Furthermore, a conductive layer 53 is formed between the interlayer dielectric layer 12 and the cantilever beam structure 300, and the conductive layer 53 is used to transmit electrical signals from the cantilever beam structure 300. For example, the titanium nitride layer 32 in the cantilever beam structure 300 is in electrical contact with the conductive layer 53 to transmit electrical signals.
[0089] The present disclosure also provides a semiconductor device using Figure 1 The method shown in the figure can be used to make it. Fig.13 and Fig.14 etc., which will not be described in detail here. Figure 1 The manufacturing method shown is used to manufacture the semiconductor device, so the semiconductor device has a good yield and a lower circuit failure problem.
[0090] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. The present disclosure is intended to cover any variations, uses or adaptations of the present disclosure, which follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The description and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.
Claims
1. A method for manufacturing a semiconductor device, characterized in that: include: providing a semiconductor substrate; forming a sacrificial layer and a functional layer located in a first region on the sacrificial layer on the semiconductor substrate; A cantilever beam layer is formed in a second region on the sacrificial layer and on a sidewall of the sacrificial layer, wherein the cantilever beam layer includes a first silicon oxide layer, a titanium nitride layer and a second silicon oxide layer which are sequentially distributed from bottom to top, and a through hole is formed in the cantilever beam layer above the second region, wherein the through hole exposes a portion of the sacrificial layer below, wherein in the process of forming the second silicon oxide layer, a process parameter is adjusted to adjust the stress of the second silicon oxide layer so that an upper surface of the second silicon oxide layer above the second region is parallel to an upper surface of the sacrificial layer, and the second region is located on at least one side of the first region; The sacrificial layer is removed through the through hole, thereby forming a cavity.
2. The method for manufacturing a semiconductor device according to claim 1, wherein: The step of adjusting process parameters during the process of forming the second silicon oxide layer includes: The second silicon oxide layer is formed by chemical vapor deposition. During the deposition process, the film forming power and / or atmosphere ratio of the chemical vapor deposition equipment are adjusted. The film forming power and the atmosphere ratio are both the process parameters to adjust the stress of the cantilever beam layer so that the upper surface of the second silicon oxide layer above the second region is parallel to the upper surface of the sacrificial layer.
3. The method for manufacturing a semiconductor device according to claim 2, wherein: The film forming power is 500w-1000w; The atmosphere ratio is that the ratio of silane gas to oxygen is in the range of 1:1 to 1.1:
1.
4. The method for manufacturing a semiconductor device according to claim 1, wherein: The forming of a cantilever beam layer in the second region on the sacrificial layer and on the sidewall of the sacrificial layer comprises: Before forming the functional layer located in the first region on the sacrificial layer, forming the first silicon oxide layer on the sacrificial layer and the semiconductor substrate, and forming the functional layer above the first silicon oxide layer portion in the first region on the sacrificial layer; After forming the functional layer above the first silicon oxide layer portion in the first area on the sacrificial layer, the titanium nitride layer and the second silicon oxide layer located above the titanium nitride layer are formed, the titanium nitride layer covers the functional layer and the sacrificial layer, and the through hole is formed in the first silicon oxide layer, the titanium nitride layer and the second silicon oxide layer above the second area.
5. The method for manufacturing a semiconductor device according to claim 4, characterized in that: The functional layer is a heat-sensitive layer.
6. The method for manufacturing a semiconductor device according to claim 5, characterized in that: At least one window is formed in the titanium nitride layer and the second silicon oxide layer on the functional layer, and the window exposes the functional layer.
7. The method for manufacturing a semiconductor device according to claim 6, wherein: Before forming the functional layer above the first silicon oxide layer portion in the first region on the sacrificial layer, the method for manufacturing the semiconductor device further includes: Patterning the first silicon oxide layer to form a connection hole in the first silicon oxide layer, wherein the connection hole exposes a connection electrode on the semiconductor substrate; The titanium nitride layer covers the functional layer and fills the connection hole to be electrically connected to the connection electrode.
8. The method for manufacturing a semiconductor device according to claim 6, wherein: The forming of the titanium nitride layer and the second silicon oxide layer located above the titanium nitride layer comprises: Before forming the second silicon oxide layer located above the titanium nitride layer, forming a hard mask layer on the titanium nitride layer; Performing a first patterning on the hard mask layer, and etching the titanium nitride layer using the first patterned hard mask layer as a mask to form a first sub-through hole and a second sub-through hole, wherein the first sub-through hole is located in a portion of the titanium nitride layer above the functional layer, and the second sub-through hole is located in a portion of the titanium nitride layer above the second region; forming a second silicon oxide layer on the hard mask layer after the first patterning, wherein the second silicon oxide layer also fills the first sub-through hole and the second sub-through hole; The second silicon oxide layer portion in and above the first sub-through hole is removed to form the window; and the second silicon oxide layer portion in and above the second sub-through hole and the first silicon oxide layer portion below the second sub-through hole are removed to form the through hole.
9. The method for manufacturing a semiconductor device according to claim 1, wherein: The step of removing the sacrificial layer through the through hole to form a cavity comprises: An etching gas is introduced into the etching chamber, so that the etching gas etches the sacrificial layer through the through hole to form the cavity.
10. The method for manufacturing a semiconductor device according to claim 9, characterized in that: The material of the sacrificial layer is amorphous silicon or polycrystalline silicon, and the etching gas is a fluorine-containing gas.
11. The method for manufacturing a semiconductor device according to claim 10, characterized in that: The fluorine-containing gas is XeF2.
12. A semiconductor device, characterized in that: The semiconductor device is manufactured using the method for manufacturing a semiconductor device according to any one of claims 1 to 11.