Wafer notch detection method, device, equipment and medium

Abstract

The invention provides a wafer notch detection method and device, equipment and a medium. The detection method comprises the following steps: acquiring a profile curve of a notch of a to-be-detected wafer; intersection points of straight lines where two bevel edges in the profile curve of the notch are located and the main surface profile line of the wafer in the profile curve are obtained; an auxiliary circle where an arc curve at the top end of the notch is located in the profile curve of the notch is obtained; determining values of evaluation parameters of the notch according to the straight line where the two bevel edges are located, the distance between the straight line where the two bevel edges are located and the intersection point of the main surface contour line of the wafer in the contour curve, the radius of the auxiliary circle and the endpoint of an arc curve at the top end of the notch; and detecting whether the profile morphology of the notch of the wafer to be detected is abnormal or not according to the value of the evaluation parameter of the notch and a set reference value.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor manufacturing technology, and in particular to a method, device, equipment and medium for detecting a wafer notch. Background Art

[0002] As substrates used in the manufacturing process of semiconductor devices, wafers made of semiconductors such as silicon wafers are widely used. Currently, silicon wafers used to manufacture semiconductor devices include polished wafers made by slicing single crystal ingots and performing grinding, polishing, cleaning and other processing processes, and epitaxial wafers with single crystal silicon epitaxial layers formed on the surface of polished wafers by chemical vapor deposition and other methods.

[0003] For the above two types of silicon wafers, the flatness and defects of their surfaces or edges are usually inspected. However, there is no relevant inspection solution for the notch of the wafer. Summary of the invention

[0004] The present disclosure provides a method, device, equipment and medium for detecting a wafer notch, which can detect the contour morphology of the notch.

[0005] The technical solution of the present disclosure is achieved as follows: In a first aspect, the present disclosure provides a method for detecting a wafer notch, the method comprising: Obtaining the contour curve of the notch of the wafer to be tested; Obtaining intersection points of two straight lines where two oblique sides in the contour curve of the notch are located and the contour line of the wafer main surface in the contour curve; Obtaining the auxiliary circle where the arc curve at the top of the notch is located in the contour curve of the notch; Determine the value of the evaluation parameter of the notch according to the straight lines where the two hypotenuses are located, the distances between the intersection points of the straight lines where the two hypotenuses are located and the wafer main surface contour line in the contour curve, the radius of the auxiliary circle and the endpoint of the arc curve at the top of the notch; Whether the notch profile of the wafer to be tested is abnormal is detected according to the value of the notch evaluation parameter and the set reference value.

[0006] In a second aspect, the present disclosure provides a wafer notch detection device, the detection device comprising: a first acquisition unit, a second acquisition unit, a third acquisition unit, a determination unit and a detection unit, wherein: The first acquisition unit is configured to acquire a contour curve of a notch of the wafer to be tested; The second acquisition unit is configured to acquire intersection points of two straight lines where two oblique sides in the contour curve of the notch are located and the contour line of the wafer main surface in the contour curve; The third acquisition unit is configured to acquire an auxiliary circle where the arc curve at the top of the notch is located in the contour curve of the notch; The determining unit is configured to determine the value of the evaluation parameter of the notch according to the straight lines where the two oblique sides are located, the distances between the intersection points of the straight lines where the two oblique sides are located and the wafer main surface contour line in the contour curve, the radius of the auxiliary circle, and the endpoint of the arc curve at the top of the notch; The detection unit is configured to detect whether the notch contour morphology of the wafer to be tested is abnormal according to the value of the notch evaluation parameter and the set reference value.

[0007] In a third aspect, the present disclosure provides a computing device, comprising: a processor and a memory; the processor is used to execute instructions stored in the memory to implement the wafer notch detection method as described in the first aspect.

[0008] In a fourth aspect, the present disclosure provides a computer storage medium, wherein the storage medium stores at least one instruction, and the at least one instruction is used to be executed by a processor to implement the wafer notch detection method as described in the first aspect.

[0009] The present disclosure provides a method, device, equipment and medium for detecting wafer notch; after obtaining the contour curve of the notch, the contour morphology of the notch is evaluated by using the straight lines where the two hypotenuses are located, the intersection points of the straight lines where the two hypotenuses are located and the contour lines of the wafer main surface in the contour curve, the auxiliary circle where the arc curve at the top of the notch is located and the end point of the arc curve at the top of the notch, so as to determine whether the notch meets the set contour morphology index. The technical solution of the present disclosure provides a means for detecting the contour morphology of the notch. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 A schematic flow chart of a wafer notch detection method provided in the present invention.

[0011] Figure 2 A schematic diagram of the complete outline of the outer periphery of a silicon wafer provided in the present invention.

[0012] Figure 3 A schematic diagram of the contour curve of the notch portion provided in the present invention.

[0013] Figure 4A schematic diagram of collecting a surface image of a notch provided in the present disclosure.

[0014] Figure 5 An image schematic diagram of the notch portion provided for the present disclosure.

[0015] Figure 6 Schematic diagram of standard parameters for evaluating notch profile morphology provided in the present disclosure.

[0016] Figure 7 A schematic diagram of obtaining evaluation parameters based on a notch contour curve provided in the present disclosure.

[0017] Figure 8 A schematic diagram of the composition of a wafer notch detection device provided in the present invention.

[0018] Fig. 9 A schematic diagram of the structure of a computing device provided by the present disclosure. DETAILED DESCRIPTION

[0019] The technical solutions in the present disclosure will be described clearly and completely below in conjunction with the accompanying drawings in the present disclosure.

[0020] Currently, a V-shaped notch is formed on the outer periphery of a silicon wafer to indicate a specific direction. For example, on a silicon wafer with a (100) crystal plane, the tip of the notch indicates <110> The notch is usually formed by the following process: grinding the outer periphery of a single crystal silicon ingot pulled by a CZ method, etc., adjusting the diameter of the single crystal silicon ingot to a specified value, and then, for example, moving a grindstone in the axial direction of the single crystal silicon ingot to form a V-shaped notch on the outer periphery of the single crystal silicon ingot.

[0021] The above-mentioned notch usually needs to be processed according to a set profile morphology index (for example, SEMI MF1-0305), but there is currently no solution for testing the processed notch.

[0022] Based on this, the present disclosure intends to analyze the notch profile of the wafer to be tested to obtain relevant morphological parameters to evaluate whether the notch meets the set profile morphology indicators (for example, the indicators shown in Fig. 5 of SEMI MF1-0305). Figure 1 , which shows a wafer notch detection method provided by the present disclosure, the detection method may include: S101: Obtaining a notch profile curve of a wafer to be tested.

[0023] Exemplarily, the contour curve of the notch refers to the contour curve of the notch portion in the complete contour of the periphery of the wafer to be tested. Figure 2 , Figure 2 The solid line in the figure schematically shows the complete outline of the outer periphery of the silicon wafer. Figure 2 It can be seen that the complete outline of the outer periphery of the silicon wafer can be approximately regarded as a circle except for the portion shown in the dotted box. Figure 2 The portion shown in the dotted box is the contour curve of the notch portion of the wafer to be tested. The enlarged schematic diagram of the contour curve of the notch portion is shown in FIG. Figure 3 As shown. Figure 3 In the embodiment, the contour curve of the notch portion is composed of at least three parts in a continuous manner, and the three parts include: wafer main surface contour lines 21 - 1 and 21 - 2 , bevel edges 22 - 1 and 22 - 2 , and an arc curve 23 at the top of the notch.

[0024] In some examples, the step S101 of obtaining the contour curve of the notch of the wafer to be tested includes: extracting the contour curve of the notch from the complete contour of the wafer to be tested. For example, the surface image of the wafer to be tested can be captured by an image acquisition device such as a CCD camera, and then the edge analysis of the surface image can be performed to obtain the complete contour of the periphery of the wafer to be tested, and finally the contour curve of the notch can be extracted from the complete contour. For another example, the complete contour of the wafer to be tested can be acquired by an instrument such as a 3D wafer profiler, a laser profiler, a wafer edge detection profiler, and then the contour curve of the notch can be extracted from the complete contour.

[0025] In some examples, it is also possible to only capture images of the notch portion of the surface of the wafer to be tested, and perform edge analysis on the captured image to obtain a contour curve of the notch. Specifically, the step S101 of obtaining the contour curve of the notch of the wafer to be tested includes: capturing a surface image of the wafer to be tested at the notch; and obtaining the contour curve of the notch of the wafer to be tested based on the surface image of the wafer to be tested at the notch.

[0026] For the above example, Figure 4As shown in the left half of the figure, two groups of four CCD cameras can be set up from the front (Front) to the back (Back) of the wafer to be tested to capture images of the notch part. In the first group of CCD cameras, Z1 is used to capture the image of the bevel (Bevel) of the outer periphery of the front of the wafer to be tested, and Z2 is used to capture the image of the top (Apex) of the outer periphery of the front of the wafer to be tested. In the second group of CCD cameras, Z4 is used to capture the image of the bevel (Bevel) of the top (Apex) of the outer periphery of the back of the wafer to be tested, and Z5 is used to capture the image of the bevel (Bevel) of the outer periphery of the back of the wafer to be tested. The detection area of ​​the above CCD cameras during shooting is centered on the Notch, and the range is 5.0mm×1.7mm. The field of view of the shooting is set to 2.4mm×1.8mm, and the detection accuracy is 1.15μm. The images captured by the above four CCD cameras are shown as follows: Figure 4 As shown in the images from top to bottom in the right half of the image. After obtaining these images, the contour curves of the notch corresponding to different shooting angles can be obtained by edge detection, and then the contour curves of the notch corresponding to these different shooting angles are merged to obtain the contour curve of the notch of the wafer to be tested, as shown in FIG. Figure 5 In the image of the notch portion shown, the contour curve of the portion may be a boundary curve between a gray area and a black area.

[0027] S102: Obtain intersection points of the straight lines where the two oblique sides in the contour curve of the notch are located and the contour line of the wafer main surface in the contour curve.

[0028] It should be noted that in the actual notch processing process, the bevel of the notch and the main surface contour of the wafer are connected by processing into an arc-shaped chamfer, that is, the main surface contour of the wafer and the bevel of the notch form an arc chamfer at the connection (such as Figure 5 ), will not Figure 3 As shown in , there is a more obvious angle.

[0029] In this disclosure, Figure 5 Taking the notch contour morphology obtained by actual processing as an example, the contour line of the main surface of the wafer and the hypotenuse of the notch form a chamfer of an arc at the connection. In this case, in some examples, the intersection of the straight lines where the two hypotenuses in the contour curve of the notch are located and the contour line of the main surface of the wafer in the contour curve obtained in step S102 includes: Extending two oblique sides of the contour curve of the notch respectively to obtain straight lines where the two oblique sides are located; Connecting the wafer main surface contour lines to form a main surface edge straight line; The intersection points of the straight lines where the two oblique edges are located and the straight line of the edge of the main surface are determined as the intersection points of the straight lines where the two oblique edges are located and the contour line of the main surface of the wafer.

[0030] S103: Obtaining the auxiliary circle where the arc curve at the top of the notch is located in the contour curve of the notch.

[0031] For example, after obtaining the contour curve of the notch, three or more non-collinear points can be selected on the arc curve at the top of the notch, and a perpendicular bisector can be determined for the line connecting every two points. The intersection of the two perpendicular bisectors is the center of the circle where the arc curve at the top of the notch is located. Based on the center of the circle and the arc curve at the top of the notch, the auxiliary circle where the arc curve at the top of the notch is located can be obtained.

[0032] Of course, after obtaining the contour curve of the notch and cutting out the arc curve at the top of the notch, the auxiliary circle can also be obtained by fitting multiple points on the arc curve at the top of the notch through the least square method. This disclosure will not elaborate on this.

[0033] S104: Determine the value of the notch evaluation parameter according to the straight lines where the two oblique edges are located, the intersection points of the straight lines where the two oblique edges are located and the wafer main surface contour line in the contour curve, the radius of the auxiliary circle and the endpoint of the arc curve at the notch top.

[0034] In this disclosure, taking SEMI MF1-0305 as an example, the morphology index of the notch can be evaluated by some standard parameters. Figure 3 Based on the notch profile curve shown, see Figure 6 These standard parameters include: notch opening width Vw, notch opening depth Vh, notch top arc curve radius Vr, notch opening angle , the distance P1 between the hypotenuse circumscribed circle O1 of the notch and the contour line of the main surface of the wafer, the distance P2 between the hypotenuse circumscribed circle of the notch and the top of the notch, and the arc radii VR1 and VR2 of the chamfer between the opening of the notch and the contour line of the main surface of the wafer respectively.

[0035] In the above standard parameters, Vh, Vw, Vr and It is convenient to detect the overall profile of the notch. Therefore, in this disclosure, the more critical evaluation parameters are Vh, Vw, Vr and Based on this, in some examples, the method further includes: Figure 6 The more critical evaluation parameters are selected from the standard parameters for evaluating notch profile morphology shown in .

[0036] In some examples, combined Figure 6 The standard parameters in the above evaluation parameters are shown as follows. In the above evaluation parameters, Vh can be obtained by the distance between the endpoint of the arc curve at the top of the notch and the contour line of the main surface of the wafer, Vw can be obtained by the distance between the two straight lines where the two hypotenuses in the contour curve of the notch are located and the intersection points of the contour line of the main surface of the wafer in the contour curve, Vr can be obtained by the radius of the auxiliary circle, It can be the included angle between the straight lines where the two hypotenuses in the contour curve of the notch are located.

[0037] S105: Detecting whether the notch profile of the wafer to be tested is abnormal according to the value of the notch evaluation parameter and the set reference value.

[0038] For example, the above four evaluation parameters each have a corresponding reference value, which is used to evaluate whether the contour of the notch is abnormal. The corresponding first reference value is the compliance value of the opening angle of the notch, which can be set to 90 degrees, and the tolerance allowed by the evaluation parameter is +5° and -1 degree. The second reference value corresponding to Vw is the compliance value of the opening width of the notch, which can be set to 3mm. The third reference value corresponding to Vr is the compliance value of the arc radius representing the top of the notch, which can be set to 0.9mm. The fourth reference value corresponding to Vh is the compliance value of the opening depth of the notch, which can be set to 1mm, and the tolerance allowed by the evaluation parameter is +0.25mm.

[0039] In some examples, by comparing the values ​​of the evaluation parameters obtained in step S104 with the corresponding reference values, when the comparison results are consistent or the difference is within the allowable tolerance range, it can be determined that the notch contour morphology of the wafer to be tested is normal; otherwise, it is determined that the notch contour morphology of the wafer to be tested is abnormal, and the notch needs to be reprocessed.

[0040] pass Figure 2 The technical solution shown, after obtaining the contour curve of the notch, uses the straight lines where the two hypotenuses are located, the intersection points of the straight lines where the two hypotenuses are located and the contour lines of the wafer main surface in the contour curve, the auxiliary circle where the arc curve at the top of the notch is located, and the endpoints of the arc curve at the top of the notch to evaluate the contour morphology of the notch, and then determine whether the notch meets the set contour morphology indicators. The technical solution disclosed in the present invention provides a means for detecting the contour morphology of the notch.

[0041] For the above technical solution, in order to facilitate the calculation of the value of the evaluation parameter of the notch, a coordinate system can be constructed to implement step S104. In some possible implementations, the value of the evaluation parameter of the notch is determined according to the straight lines where the two hypotenuses are located, the intersection points of the straight lines where the two hypotenuses are located and the contour lines of the main surface of the wafer in the contour curve, the radius of the auxiliary circle, and the endpoint of the arc curve at the top of the notch, including: A coordinate system is constructed with the intersection of the two hypotenuse lines as the origin; one of the coordinate axes in the coordinate system passes through the endpoint of the arc curve at the top of the notch; Under Coordinate System, perform the following steps: Get the angle between the two hypotenuse lines; Obtaining a first distance between intersection points according to coordinate values ​​of intersection points between the straight lines where the two hypotenuses are located and the wafer main surface contour line in the contour curve; Determine the radius of the auxiliary circle according to the coordinates of the center of the auxiliary circle and the coordinates of the endpoint of the arc curve at the top of the notch; A second distance between the endpoint of the arc curve at the notch top and the contour line of the wafer main surface is calculated according to the endpoint coordinates of the arc curve at the notch top.

[0042] For the above implementation, specifically, Figure 7 As shown, the straight lines L2 and L3 where the two hypotenuses in the contour curve of the notch are located intersect at point D1, and a plane rectangular coordinate system is constructed with point D1 as the origin, and one coordinate axis of the coordinate system (the Y axis is used as an example in this disclosure) passes through the end point D5 of the arc curve at the top of the notch. Based on the coordinate system constructed above, the angle between the straight lines where the two hypotenuses in the contour curve of the notch are located can be calculated, and this angle is the opening angle of the notch. . According to the intersection points of the two hypotenuse straight lines L2 and L3 in the contour curve of the notch and the wafer main surface contour line L1 in the contour curve as shown in D2 and D3 respectively, in the coordinate system constructed above, the first distance between D2 and D3 is calculated, which is the opening width Vw of the notch. In the coordinate system constructed above, the center C1 of the auxiliary circle where the arc curve at the top of the notch is located and the radius of the auxiliary circle can also be calculated. The radius of the auxiliary circle is the radius Vr of the arc curve at the top of the notch. In the coordinate system constructed above, the coordinates of the endpoint D5 of the arc curve at the top of the notch can be used to calculate the second distance between it and the wafer main surface contour line L1, which is the opening depth Vh of the notch.

[0043] Based on the above implementation, in some examples, detecting whether the notch profile of the wafer to be tested is abnormal according to the value of the notch evaluation parameter and the set reference value includes: Obtain a first difference between the angle between the straight lines where the two hypotenuses are located and a first reference value; Obtaining a second difference between the first distance and a second reference value; Obtaining a third difference between the radius of the auxiliary circle and a third reference value; obtaining a fourth difference between the second distance and a fourth reference value; When the first difference and the fourth difference are both less than or equal to the set tolerance, and the second difference and the third difference are 0, it is determined that there is no abnormality in the notch profile of the wafer to be tested; When at least one of the first difference and the fourth difference is greater than a set tolerance, or at least one of the second difference and the third difference is not 0, it is determined that the notch profile of the wafer to be tested is abnormal.

[0044] For the above example, it should be noted that, taking the standard SEMI MF1 as an example, the opening angle of the notch The notch opening depth is allowed to have tolerance, while the notch opening width and the arc radius of the notch top are not allowed to have tolerance. Based on this, if the angle between the straight lines where the two hypotenuses are located and the second distance are within the allowable tolerance range compared with the corresponding reference values, it means that the opening angle of the notch of the wafer to be tested is and the opening depth Vh meet the standard specifications. If the first distance and the auxiliary circle radius are equal to the corresponding reference values, it means that the opening width Vw of the notch and the arc curve radius Vr of the notch top meet the standard specifications. If the values ​​of the above evaluation parameters meet the specifications of the standard SEMI MF1, it can be determined that the notch profile of the wafer to be tested is normal. If the value of at least one of the above evaluation parameters does not meet the specifications of the standard SEMI MF1, it can be determined that the notch profile of the wafer to be tested is abnormal.

[0045] In the present disclosure, based on the detection means of the aforementioned technical solution, 20 wafers were tested for notch contour morphology, and the results obtained are shown in Table 1 below.

[0046]

[0047] Table 1 In the above Table 1, the units of Vh, Vw, and Vr are micrometers, The unit is degree.

[0048] It can be seen from Table 1 that the technical solution disclosed in the present invention can detect the more critical evaluation parameters of the contour morphology of the notch. Therefore, the detection result of the contour morphology of the notch is effective. In other words, the technical solution disclosed in the present invention provides a means for detecting the contour morphology of the notch.

[0049] Based on the same inventive concept as the above technical solution, see Figure 8 It shows a wafer notch detection device 80 provided by the present disclosure, the detection device 80 includes: a first acquisition unit 801, a second acquisition unit 802, a third acquisition unit 803, a determination unit 804 and a detection unit 805, wherein: The first acquisition unit 801 is configured to acquire a contour curve of a notch of the wafer to be tested; The second acquisition unit 802 is configured to acquire intersection points of two straight lines where two oblique sides in the contour curve of the notch are located and the contour line of the wafer main surface in the contour curve; The third acquisition unit 803 is configured to acquire the auxiliary circle where the arc curve at the top of the notch is located in the contour curve of the notch; The determining unit 804 is configured to determine the value of the evaluation parameter of the notch according to the straight lines where the two oblique edges are located, the distances between the intersection points of the straight lines where the two oblique edges are located and the wafer main surface contour line in the contour curve, the radius of the auxiliary circle, and the endpoint of the arc curve at the top of the notch; The detection unit 805 is configured to detect whether the notch contour morphology of the wafer to be tested is abnormal according to the value of the notch evaluation parameter and the set reference value.

[0050] In some examples, the second acquisition unit 802 is configured to: Extending two oblique sides in the contour curve of the notch respectively to obtain straight lines where the two oblique sides are located; Forming the main surface contour line of the wafer into a main surface edge straight line; The intersection points of the straight lines where the two oblique edges are located and the straight line of the edge of the main surface are determined as the intersection points of the straight lines where the two oblique edges are located and the contour line of the main surface of the wafer.

[0051] In some examples, the determining unit 804 is configured to: A coordinate system is constructed with the intersection of the two hypotenuse lines as the origin; a coordinate axis in the coordinate system passes through the endpoint of the arc curve at the top of the notch; In the coordinate system, perform the following steps: Obtaining the angle between the straight lines where the two hypotenuses are located; Obtaining a first distance between the intersection points according to the coordinate values ​​of the intersection points between the straight lines where the two hypotenuses are located and the wafer main surface contour line in the contour curve; Determine the radius of the auxiliary circle according to the coordinates of the center of the auxiliary circle and the coordinates of the endpoints of the arc curve at the top of the notch; A second distance between the endpoint of the arc curve at the notch top and the contour line of the wafer main surface is calculated according to the endpoint coordinates of the arc curve at the notch top.

[0052] In some examples, the detection unit 805 is configured to: Obtaining a first difference between an angle between the straight lines where the two hypotenuses are located and a first reference value; wherein the first reference value is a compliance value of the opening angle of the notch; Obtaining a second difference between the first distance and a second reference value; wherein the second reference value is a compliance value of the opening width of the notch; Obtain a third difference between the auxiliary circle radius and a third reference value; the third reference value is a compliance value of the arc radius of the top of the notch; Obtaining a fourth difference between the second distance and a fourth reference value; the fourth reference value is a compliance value of the opening depth of the notch; When the first difference and the fourth difference are both less than or equal to the set tolerance, and the second difference and the third difference are 0, it is determined that there is no abnormality in the notch profile of the wafer to be tested; When at least one of the first difference and the fourth difference is greater than a set tolerance, or when at least one of the second difference and the third difference is not 0, it is determined that the notch profile of the wafer to be tested is abnormal.

[0053] In some examples, the first reference value is 90 degrees; the second reference value is 3 mm, the third reference value is 0.9 mm, and the fourth reference value is 1 mm; accordingly, the tolerance corresponding to the first reference value is +5° and -1 degree; the tolerance corresponding to the fourth reference value is +0.25 mm.

[0054] In some examples, the first acquisition unit 801 is configured to: Collecting a surface image of the wafer to be tested at the notch; A contour curve of the notch of the wafer to be tested is obtained according to a surface image of the wafer to be tested at the notch.

[0055] In some examples, the determining unit 804 is further configured to: The evaluation parameters are selected from standard parameters for evaluating the notch profile morphology.

[0056] Please refer to Fig. 9, which shows a structural block diagram of a computing device provided by an exemplary embodiment of the present disclosure. In some examples, the computing device 90 may be at least one of a smart phone, a smart watch, a desktop computer, a laptop, a virtual reality terminal, an augmented reality terminal, a wireless terminal, and a laptop portable computer. The computing device 90 has a communication function and can access a wired network or a wireless network. The computing device 90 may generally refer to one of a plurality of terminals, and those skilled in the art may know that the number of the above terminals may be more or less. In some examples, the computing device 90 may receive data based on the wired network or wireless network to which it is connected. It can be understood that the computing device 90 undertakes the calculation and processing work of the technical solution of the present disclosure, and the present disclosure does not limit this.

[0057] like Fig. 9 As shown, the computing device in the present disclosure may include one or more of the following components: a processor 910 and a memory 920 .

[0058] Optionally, the processor 910 uses various interfaces and lines to connect various parts of the entire computing device, and executes various functions of the computing device and processes data by running or executing instructions, programs, code sets or instruction sets stored in the memory 920, and calling data stored in the memory 920. Optionally, the processor 910 can be implemented in at least one hardware form of digital signal processing (DSP), field-programmable gate array (FPGA), and programmable logic array (PLA). The processor 910 can integrate one or a combination of a central processing unit (CPU), a graphics processing unit (GPU), a neural network processor (NPU), and a baseband chip. Among them, the CPU mainly processes the operating system, user interface, and application programs; the GPU is responsible for rendering and drawing the content that needs to be displayed on the touch display; the NPU is used to implement artificial intelligence (AI) functions; and the baseband chip is used to process wireless communications. It is understandable that the above baseband chip may not be integrated into the processor 910, but may be implemented by a separate chip.

[0059] The memory 920 may include a random access memory (RAM) or a read-only memory (ROM). Optionally, the memory 920 includes a non-transitory computer-readable storage medium. The memory 920 may be used to store instructions, programs, codes, code sets, or instruction sets. The memory 920 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for at least one function (such as a touch function, a sound playback function, an image playback function, etc.), instructions for implementing the above various method embodiments, etc.; the data storage area may store data created according to the use of the computing device, etc.

[0060] In addition, those skilled in the art can understand that the structure of the computing device shown in the above drawings does not constitute a limitation on the computing device, and the computing device may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently. For example, the computing device also includes a display screen, a camera assembly, a microphone, a speaker, a radio frequency circuit, an input unit, a sensor (such as an acceleration sensor, an angular velocity sensor, a light sensor, etc.), an audio circuit, a WiFi module, a power supply, a Bluetooth module and other components, which will not be described in detail here.

[0061] The present disclosure also provides a computer-readable storage medium storing at least one instruction, wherein the at least one instruction is used to be executed by a processor to implement the wafer notch detection method as described in the above embodiments.

[0062] The present disclosure also provides a computer program product, which includes computer instructions, which are stored in a computer-readable storage medium; a processor of a computing device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computing device executes to implement the wafer notch detection method described in the above-mentioned embodiments.

[0063] Those skilled in the art should be aware that in one or more of the above examples, the functions described in the present disclosure can be implemented using hardware, software, firmware, or any combination thereof. When implemented using software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or codes on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any media that facilitates the transmission of computer programs from one place to another. Storage media can be any available media that can be accessed by a general or special-purpose computer.

[0064] It should be noted that the technical solutions described in the present disclosure can be combined arbitrarily without conflict.

[0065] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A method for detecting wafer notch, characterized in that: The detection method comprises: Obtaining the contour curve of the notch of the wafer to be tested; Obtaining intersection points of two straight lines where two oblique sides in the contour curve of the notch are located and the contour line of the wafer main surface in the contour curve; Obtaining the auxiliary circle where the arc curve at the top of the notch is located in the contour curve of the notch; Determine the value of the evaluation parameter of the notch according to the straight lines where the two hypotenuses are located, the distances between the intersection points of the straight lines where the two hypotenuses are located and the wafer main surface contour line in the contour curve, the radius of the auxiliary circle and the endpoint of the arc curve at the top of the notch; Whether the notch profile of the wafer to be tested is abnormal is detected according to the value of the notch evaluation parameter and the set reference value.

2. The detection method according to claim 1, characterized in that: The step of obtaining the intersection points of the straight lines where the two oblique sides in the contour curve of the notch are located and the contour line of the wafer main surface in the contour curve respectively includes: Extending two oblique sides in the contour curve of the notch respectively to obtain straight lines where the two oblique sides are located; Forming the main surface contour line of the wafer into a main surface edge straight line; The intersection points of the straight lines where the two oblique edges are located and the straight line of the edge of the main surface are determined as the intersection points of the straight lines where the two oblique edges are located and the contour line of the main surface of the wafer.

3. The detection method according to claim 1, characterized in that: The method of determining the value of the evaluation parameter of the notch according to the straight lines where the two oblique edges are located, the distances between the intersection points of the straight lines where the two oblique edges are located and the contour line of the wafer main surface in the contour curve, the radius of the auxiliary circle and the endpoint of the arc curve at the top of the notch comprises: A coordinate system is constructed with the intersection of the two hypotenuse lines as the origin; a coordinate axis in the coordinate system passes through the endpoint of the arc curve at the top of the notch; In the coordinate system, perform the following steps: Obtaining the angle between the straight lines where the two hypotenuses are located; Obtaining a first distance between the intersection points according to the coordinate values ​​of the intersection points between the straight lines where the two hypotenuses are located and the wafer main surface contour line in the contour curve; Determine the radius of the auxiliary circle according to the coordinates of the center of the auxiliary circle and the coordinates of the endpoints of the arc curve at the top of the notch; A second distance between the endpoint of the arc curve at the notch top and the contour line of the wafer main surface is calculated according to the endpoint coordinates of the arc curve at the notch top.

4. The method according to claim 3, characterized in that: The detecting whether the notch profile of the wafer to be tested is abnormal according to the value of the notch evaluation parameter and the set reference value includes: Obtaining a first difference between an angle between the straight lines where the two hypotenuses are located and a first reference value; wherein the first reference value is a compliance value of the opening angle of the notch; Obtaining a second difference between the first distance and a second reference value; wherein the second reference value is a compliance value of the opening width of the notch; Obtain a third difference between the auxiliary circle radius and a third reference value; the third reference value is a compliance value of the arc radius of the top of the notch; Obtaining a fourth difference between the second distance and a fourth reference value; the fourth reference value is a compliance value of the opening depth of the notch; When the first difference and the fourth difference are both less than or equal to the set tolerance, and the second difference and the third difference are 0, it is determined that there is no abnormality in the notch profile of the wafer to be tested; When at least one of the first difference and the fourth difference is greater than a set tolerance, or when at least one of the second difference and the third difference is not 0, it is determined that the notch profile of the wafer to be tested is abnormal.

5. The method according to claim 4, characterized in that The first reference value is 90 degrees; the second reference value is 3 mm, the third reference value is 0.9 mm, and the fourth reference value is 1 mm; accordingly, the tolerance corresponding to the first reference value is +5° and -1 degree; the tolerance corresponding to the fourth reference value is +0.25 mm.

6. The method according to claim 1, characterized in that The step of obtaining a notch profile curve of the wafer to be tested includes: Collecting a surface image of the wafer to be tested at the notch; A contour curve of the notch of the wafer to be tested is obtained according to a surface image of the wafer to be tested at the notch.

7. The method according to claim 1, characterized in that The method further comprises: The evaluation parameters are selected from standard parameters for evaluating the notch profile morphology.

8. A wafer notch detection device, characterized in that: The detection device comprises: a first acquisition unit, a second acquisition unit, a third acquisition unit, a determination unit and a detection unit, wherein: The first acquisition unit is configured to acquire a contour curve of a notch of the wafer to be tested; The second acquisition unit is configured to acquire intersection points of two straight lines where two oblique sides in the contour curve of the notch are located and the contour line of the wafer main surface in the contour curve; The third acquisition unit is configured to acquire an auxiliary circle where the arc curve at the top of the notch is located in the contour curve of the notch; The determining unit is configured to determine the value of the evaluation parameter of the notch according to the straight lines where the two oblique sides are located, the distances between the intersection points of the straight lines where the two oblique sides are located and the wafer main surface contour line in the contour curve, the radius of the auxiliary circle, and the endpoint of the arc curve at the top of the notch; The detection unit is configured to detect whether the notch contour morphology of the wafer to be tested is abnormal according to the value of the notch evaluation parameter and the set reference value.

9. A computing device, characterized in that The computing device comprises: a processor and a memory; the processor is used to execute instructions stored in the memory to implement the wafer notch detection method as described in any one of claims 1 to 7.

10. A computer storage medium, characterized in that: The storage medium stores at least one instruction, and the at least one instruction is used to be executed by a processor to implement the wafer notch detection method as described in any one of claims 1 to 7.

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