Method for eliminating parasitic capacitance influence in Crss measurement of power semiconductor device

Abstract

The invention discloses a method for eliminating parasitic capacitance influence in Crss measurement of a power semiconductor device, which comprises the following operation steps of: extending four terminals of an LCR meter by using a coaxial cable, respectively connecting one end of the coaxial cable to Hcur, Hpot, Lcur and Lpot, and connecting the other end of the coaxial cable to a PCB (Printed Circuit Board); reasonable PCB design is carried out on the output ends of the LCR and the SMU, the Hcur and the Hpot of the LCR are connected with the D end of the DUT, the Lcur and the Lpot are connected with the G end of the DUT, a shielding layer of a coaxial cable is used as an AC Guard wire to be connected to the S end of the DUT, a return path is provided for the current of Cds passing through the DUT, and meanwhile the wiring distance of the AC Guard on the PCB is reduced. According to the method for eliminating the parasitic capacitance influence in the Crss measurement of the power semiconductor device, transmission of AC Guard signals is achieved through the shielding layer of the coaxial cable, the length of an AC Guard wire is shortened as much as possible in the PCB design, and the Crss test accuracy in the static test of the power device can be effectively improved.

Description

Technical Field

[0001] The invention relates to the field of power semiconductor device testing, and in particular to a method for eliminating the influence of parasitic capacitance in Crss measurement of a power semiconductor device. Background Art

[0002] The method of eliminating the influence of parasitic capacitance in the Crss measurement of power semiconductor devices is a method for testing power semiconductor devices. The Crss test is a parameter in the static test of MOSFET (metal oxide semiconductor field effect transistor). In the MOSFET structure, Crss refers to the capacitance Cgd between the gate and the drain, also known as the feedback capacitance or reverse transfer capacitance. It has an important influence on the switching speed and power loss parameters of the MOSFET. Therefore, accurate measurement of the Crss parameter is very necessary for designing efficient and high-performance power semiconductor circuits. With the continuous development of science and technology, people have higher and higher requirements for the method of eliminating the influence of parasitic capacitance in the Crss measurement of power semiconductor devices.

[0003] Although the currently used Crss test method can achieve accurate measurement to a certain extent, the parasitic capacitance in the test loop will introduce a certain amount of measurement error, and the impact on the Crss test result cannot be ignored. Therefore, in order to improve the accuracy of the measurement, a method for eliminating the influence of parasitic capacitance in the Crss measurement of power semiconductor devices is provided to ensure that the measurement results of the Crss parameters are more accurate and reliable. To this end, we propose a method for eliminating the influence of parasitic capacitance in the Crss measurement of power semiconductor devices. Summary of the invention

[0004] Technical problem to be solved: In view of the deficiencies in the prior art, the present invention provides a method for eliminating the influence of parasitic capacitance in Crss measurement of power semiconductor devices. The shielding layer of the coaxial cable is used to realize the transmission of the AC Guard signal. By shortening the length of the AC Guard line as much as possible in the PCB design, the accuracy of the Crss test in the static test of the power device can be effectively improved, which can effectively solve the problems in the background technology.

[0005] Technical solution: To achieve the above purpose, the technical solution adopted by the present invention is: a method for eliminating the influence of parasitic capacitance in Crss measurement of power semiconductor devices, comprising the following steps:

[0006] S1: Use a coaxial cable to extend the four terminals of the LCR meter. Connect one end of the coaxial cable to Hcur, Hpot, Lcur and Lpot respectively, and the other end to the PCB board.

[0007] S2: Make reasonable PCB design for the output ends of LCR and SMU, connect Hcur and Hpot of LCR to D end of DUT, connect Lcur and Lpot to G end of DUT, connect the shielding layer of coaxial cable to S end of DUT as AC Guard line, provide return path for the current of Cds passing through DUT, reduce the wiring distance of AC Guard on PCB, minimize the impedance of AC Guard line in high-frequency circuit, eliminate the influence of parasitic capacitance on Crss test, connect HI end of SMU to D end of DUT, and connect LO end to S end of DUT;

[0008] S3: Insert the DUT into the socket, and insert the MOS tube of the semiconductor power device to be tested into the dedicated test socket on the PCB board, ensuring that the electrical connection between the MOS tube and the test system is correct, and prepare for the next Crss test;

[0009] S4: Start Crss test. The experimental environment required for leakage current test has been built. You can start Crss test of MOS tube. Before the test, you need to calibrate the LCR meter for open circuit and short circuit to eliminate the influence of parasitic parameters.

[0010] S5: Add high voltage to the D terminal of DUT, scan the Crss curve, adjust the Vds value, change the Crss test conditions, perform Cgd test on the MOS tube under different Vds, and thus generate the Crss test curve;

[0011] S6: The Crss test of DUT is completed. Through the reasonable design of AC Guard line, the influence of parasitic capacitance is eliminated.

[0012] As a preferred technical solution of the present application, it includes SMU, LCR, DUT, coaxial cable and parasitic capacitance, the DUT is provided with a device D terminal, a device G terminal and a device S terminal, the LCR is provided with an AC Guard line, the SMU is a high-voltage source meter, and provides a drain-source DC voltage Vds to the DUT, and the interface of the SMU includes a HI terminal and a LO terminal.

[0013] As a preferred technical solution of the present application, the HI end is the positive pole of the SMU, which outputs a high-voltage signal. An inductor is connected in series between the HI end and the D end of the DUT. The inductor exhibits a high-resistance characteristic under high-frequency conditions, which can effectively prevent the high-frequency AC signal of the LCR from being transmitted to the HI end of the SMU, thereby ensuring the accuracy and safety of the Crss test.

[0014] As a preferred technical solution of the present application, the LO terminal is the negative pole of the SMU, and the LO terminal is connected to the S terminal of the DUT and the AC Guard terminal of the LCR at the same time to provide a test loop for the Crss test.

[0015] As a preferred technical solution of the present application, the LCR is used to measure the value of Cgd, and the interface of the LCR includes Hcur, Hpot, Lcur, Lpot and AC Guard, wherein Hcur is a high-end current drive, Hpot is a high-end voltage detection, Lcur is a low-end current drive, and Lpot is a low-end voltage detection. The Hcur and Hpot are connected together after passing through a coaxial cable, and a series capacitor is added to the D end of the DUT. The Lcur and Lpot are connected together after passing through a coaxial cable and added to the G end of the DUT.

[0016] As a preferred technical solution of the present application, the Hpot and Lpot ports apply AC voltage signals to both ends of Cgd. These two ports can detect the actual voltage on Cgd to ensure the accuracy of the measurement.

[0017] As a preferred technical solution of the present application, the Hcur and Lcur ports are used to measure the current flow caused by the AC voltage signal.

[0018] As a preferred technical solution of the present application, the LCR uses the measured voltage and current data to calculate the impedance amplitude and phase angle of Cgd, thereby measuring and calculating the capacitance value of Cgd.

[0019] Beneficial effect: Compared with the prior art, the present invention provides a method for eliminating the influence of parasitic capacitance in Crss measurement of power semiconductor devices, which has the following beneficial effects: the method for eliminating the influence of parasitic capacitance in Crss measurement of power semiconductor devices utilizes the shielding layer of the coaxial cable to realize the transmission of the AC Guard signal, and shortens the length of the AC Guard line as much as possible in the PCB design, so as to effectively improve the accuracy of the Crss test in the static test of the power device; the method is simple and easy to implement, and can realize high-precision Crss test with the reasonable design of the coaxial cable and PCB, which reduces the difficulty of operation, reduces the additional equipment investment and maintenance cost, and improves the economy of the test; the method is not only suitable for Crss test of semiconductor power devices, but can also be extended to other electronic testing and measurement fields to improve the performance and reliability of electronic systems. The whole method for eliminating the influence of parasitic capacitance in Crss measurement of power semiconductor devices has a simple structure, is easy to operate, and has a better effect than the traditional method. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 The present invention is a schematic structural diagram of a method for eliminating the influence of parasitic capacitance in Crss measurement of a power semiconductor device.

[0021] Figure 2The present invention is a circuit diagram of a method for eliminating the influence of parasitic capacitance in Crss measurement of a power semiconductor device.

[0022] Figure 3 The present invention is a flow chart of a method for eliminating the influence of parasitic capacitance in Crss measurement of a power semiconductor device.

[0023] In the figure: 1. SMU; 2. LCR; 3. DUT; 4. Coaxial cable; 5. Parasitic capacitance; 6. Device D terminal; 7. Device G terminal; 8. ACGuard line; 9. Device S terminal. DETAILED DESCRIPTION

[0024] The technical scheme of the present invention will be clearly and completely described below in conjunction with the accompanying drawings and specific embodiments, but it will be understood by those skilled in the art that the following described embodiments are part of embodiments of the present invention, rather than all embodiments, and are only used to illustrate the present invention, and should not be considered as limiting the scope of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative work are within the scope of protection of the present invention. If specific conditions are not specified in the embodiments, they are carried out according to normal conditions or conditions recommended by the manufacturer. If the manufacturer is not specified in the reagents or instruments used, they are all conventional products that can be purchased commercially.

[0025] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0026] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0027] like Figure 1-3 As shown, a method for eliminating the influence of parasitic capacitance in Crss measurement of a power semiconductor device includes the following steps:

[0028] S1: Use a coaxial cable to extend the four terminals of the LCR meter. Connect one end of the coaxial cable to Hcur, Hpot, Lcur and Lpot respectively, and the other end to the PCB board.

[0029] S2: Make reasonable PCB design for the output ends of LCR and SMU, connect Hcur and Hpot of LCR to D end of DUT, connect Lcur and Lpot to G end of DUT, connect the shielding layer of coaxial cable to S end of DUT as AC Guard line, provide return path for the current of Cds passing through DUT, reduce the wiring distance of AC Guard on PCB, minimize the impedance of AC Guard line in high-frequency circuit, eliminate the influence of parasitic capacitance on Crss test, connect HI end of SMU to D end of DUT, and connect LO end to S end of DUT;

[0030] S3: Insert the DUT into the socket, and insert the MOS tube of the semiconductor power device to be tested into the dedicated test socket on the PCB board, ensuring that the electrical connection between the MOS tube and the test system is correct, and prepare for the next Crss test;

[0031] S4: Start Crss test. The experimental environment required for leakage current test has been built. You can start Crss test of MOS tube. Before the test, you need to calibrate the LCR meter for open circuit and short circuit to eliminate the influence of parasitic parameters.

[0032] S5: Add high voltage to the D terminal of DUT, scan the Crss curve, adjust the Vds value, change the Crss test conditions, perform Cgd test on the MOS tube under different Vds, and thus generate the Crss test curve;

[0033] S6: The Crss test of DUT is completed. Through the reasonable design of AC Guard line, the influence of parasitic capacitance is eliminated.

[0034] Furthermore, it includes SMU1, LCR2, DUT3, coaxial cable 4 and parasitic capacitor 5. DUT3 is provided with device D terminal 6, device G terminal 7 and device S terminal 9. LCR2 is provided with AC Guard line 8. SMU1 is a high-voltage source meter, which provides drain-source DC voltage Vds to DUT3. The interface of SMU1 includes HI terminal and LO terminal.

[0035] Furthermore, the HI terminal is the positive pole of SMU1, which outputs a high-voltage signal. An inductor is connected in series between the HI terminal and the D terminal of DUT3. The inductor exhibits a high-resistance characteristic under high-frequency conditions, which can effectively prevent the high-frequency AC signal of LCR2 from being transmitted to the HI terminal of SMU, thereby ensuring the accuracy and safety of the Crss test.

[0036] Furthermore, the LO terminal is the negative pole of SMU1, and the LO terminal is connected to the S terminal of DUT3 and the AC Guard terminal of LCR2 at the same time to provide a test loop for the Crss test.

[0037] Furthermore, LCR2 is used to measure the value of Cgd. The interfaces of LCR2 include Hcur, Hpot, Lcur, Lpot and ACGuard, where Hcur is high-end current drive, Hpot is high-end voltage detection, Lcur is low-end current drive, and Lpot is low-end voltage detection. Hcur and Hpot are connected together through a coaxial cable, and a series capacitor is added to the D end of DUT3. Lcur and Lpot are connected together through a coaxial cable and added to the G end of DUT3.

[0038] Furthermore, the Hpot and Lpot ports apply AC voltage signals to both ends of Cgd. These two ports can detect the actual voltage on Cgd to ensure the accuracy of the measurement.

[0039] Furthermore, the Hcur and Lcur ports are used to measure the current flow caused by the AC voltage signal.

[0040] Furthermore, LCR uses the measured voltage and current data to calculate the impedance amplitude and phase angle of Cgd, thereby measuring and calculating the capacitance value of Cgd.

[0041] Example:

[0042] Figure 1 This is a method for eliminating the influence of parasitic capacitance in Crss measurement of power semiconductor devices. The structure diagram includes 1SMU, LCR, DUT (semiconductor power device under test), coaxial cable, parasitic capacitance, equivalent resistance and inductance.

[0043] SMU is a high voltage source meter that provides a drain-source DC voltage Vds to the DUT. The SMU interface includes the HI terminal and the LO terminal;

[0044] The HI terminal is the positive pole of the SMU and outputs a high voltage signal. An inductor is connected in series between the HI terminal and the D terminal of the DUT. The inductor exhibits high resistance characteristics under high frequency conditions, which can effectively prevent the high frequency AC signal of the LCR from being transmitted to the HI terminal of the SMU, ensuring the accuracy and safety of the Crss test;

[0045] The LO terminal is the negative pole of the SMU. The LO terminal is connected to the S terminal of the DUT and the AC Guard terminal of the LCR at the same time to provide a test loop for the Crss test.

[0046] LCR is used to measure the value of Cgd. The LCR interface includes Hcur (high-end current drive), Hpot (high-end voltage detection), Lcur (low-end current drive), Lpot (low-end voltage detection) and AC Guard. Hcur and Hpot are connected together through a coaxial cable and added to the D end of the DUT with a series capacitor; Lcur and Lpot are connected together through a coaxial cable and added to the G end of the DUT.

[0047] The Hpot and Lpot ports apply AC voltage signals to both ends of Cgd. These two ports can detect the actual voltage on Cgd to ensure the accuracy of the measurement;

[0048] The Hcur and Lcur ports are used to measure the current flow caused by the AC voltage signal;

[0049] The LCR meter uses the voltage and current data measured above to measure and calculate the capacitance value of Cgd by calculating the impedance amplitude and phase angle of Cgd;

[0050] The capacitor blocks direct current and allows alternating current to pass, preventing the high voltage signal of the SMU from affecting the LCR.

[0051] AC Guard is connected to the S port of the DUT;

[0052] During the Crss test, LCR provides an AC high level at the D terminal of the DUT. Part of the current flows through Cgd and returns to the LCR through the Lcur terminal, and part of the current flows through Cds and returns to the LCR through the AC Guard port. This part of the current will not participate in the calculation of the Cgd capacitance. Ideally, the AC signal on Cds will flow back to the AC Guard smoothly without interfering with the LCR meter's measurement of Cgd. However, at high frequencies, the impedance of the AC Guard line itself will hinder the AC signal, and the parasitic capacitance between the G pole of the DUT and the AC Guard will provide an additional loop for the AC signal, resulting in the AC signal that should have been completely returned to the AC Guard. There is a part of the AC signal that forms a loop through this parasitic capacitance path, which ultimately increases the current value of the measured Cgd, and the capacitance value calculated by the LCR meter is higher than the actual value. Therefore, a reasonable design of the AC Guard line is crucial to improving the accuracy of the Crss measurement. It can reduce the impact of parasitic capacitance and ensure that the AC signal is hindered as little as possible, thereby obtaining a capacitance measurement result that is closer to the actual value.

[0053] The three pins of DUT (semiconductor power device under test) are D terminal (drain), G terminal (gate), and S terminal (source).

[0054] The D-terminal series DC blocking capacitor is connected to the H pot and H cur terminals of the LCR, and the series AC blocking inductor is connected to the HI terminal of the SMU;

[0055] The G end is connected to the L pot end and the L cur end of the LCR;

[0056] The S terminal is connected to the LO terminal of the SMU and the AC Guard of the LCR;

[0057] SMU applies high voltage Vds between the D and S terminals of the DUT, connects the Hcur and Hpot of the LCR to the D terminal of the DUT, connects the Lcur and Lpot to the G terminal of the DUT, and the test current flows from the D terminal of the DUT to the G terminal, thereby calculating the Cgd capacitance value of the DUT.

[0058] After the coaxial cable extends the four terminals Hcur, Hpot, Lcur and Lpot, Hcur is connected with Hpot, and Lcur is connected with Lpot. The shielding layer of the coaxial cable is used to transmit the AC Guard signal.

[0059] The coaxial cable consists of a center conductor, an insulation layer, a shielding layer, and an outer sheath. The center conductor of the coaxial cable is used to transmit the signal of the LCR four-terminal, and the shielding layer is used to transmit the AC Guard signal. With the shielding layer of the coaxial cable as the ACGuard of the LCR, the impedance of the AC Guard can be greatly reduced.

[0060] Parasitic capacitance, equivalent resistance and inductance are parasitic parameters on the AC Guard line at high frequencies.

[0061] Parasitic capacitance refers to the parasitic capacitance existing on the line from the G terminal of the DUT to the AC Guard;

[0062] The equivalent resistance and inductance refer to the equivalent values ​​on the AC Guard line of the LCR under high frequency test conditions;

[0063] On the one hand, due to the equivalent resistance of the AC Guard line that does not change with frequency and the equivalent inductance that increases with frequency, the impedance of the line increases at high frequencies, and the blocking effect on the AC signal also increases, resulting in the blocking of the AC signal flowing through Cds and returning to the AC Guard line; on the other hand, due to the parasitic capacitance between the G terminal and the AC Guard, an AC loop to the G terminal of the DUT is provided for the current flowing through Cds, resulting in an increase in the current measured at the L cur terminal of the LCR. According to the capacitance calculation formula, this additional current will cause the tested capacitance value to be too large. Therefore, in order to make the current flowing through Cds flow back to the AC Guard terminal completely and ensure that the measurement of Cgd is not affected, the shielding layer of the coaxial cable can be used as ACGuard, and the length of the AC Guard line can be shortened in the PCB design to eliminate the influence of parasitic capacitance, thereby improving the accuracy of Crss measurement and obtaining a capacitance value closer to the actual value.

[0064] Figure 2 It is a method for eliminating the influence of parasitic capacitance in Crss measurement of power semiconductor devices;

[0065] 6 is the D terminal of DUT, which is connected to Hcur and Hpot of LCR and HI terminal of SMU;

[0066] 7 is the G terminal of DUT, which is connected to Lcur and Lpot of LCR;

[0067] 8 is the AC Guard line of LCR, which is connected to the S terminal through a relay during crss testing;

[0068] 9 is the S terminal of DUT, which is connected to the LO terminal of SMU and the AC Guard line of LCR;

[0069] In this method, the shielding layer of the coaxial cable is used as the AC Guard. At the same time, the length of the AC Guard line is shortened as much as possible during PCB line design to reduce the impedance of the line, thereby eliminating the influence of parasitic capacitance on the AC Guard current, ensuring that the current flowing through Cds can completely flow back to the AC Guard end of the LCR through the AC Guard line, reducing the influence on the Cgd measurement loop, and improving the accuracy of Crss measurement.

[0070] Figure 3 A flow chart of a method for eliminating the influence of parasitic capacitance in Crss measurement of power semiconductor devices;

[0071] S1 uses a coaxial cable to extend the four terminals of the LCR meter, which means connecting one end of the coaxial cable to Hcur, Hpot, Lcur and Lpot respectively, and the other end to the PCB board.

[0072] S2 Reasonable PCB design for the output of LCR and SMU means connecting the Hcur and Hpot of LCR to the D end of DUT; connecting Lcur and Lpot to the G end of DUT; connecting the shielding layer of coaxial cable to the S end of DUT as AC Guard line, providing a return path for the current of Cds passing through DUT, and reducing the wiring distance of AC Guard on PCB, minimizing the impedance of ACGuard line in high-frequency circuit, and eliminating the influence of parasitic capacitance on Crss test. The HI end of SMU is connected to the D end of DUT, and the LO end is connected to the S end of DUT.

[0073] S3 inserts the DUT into the socket (test socket), which is to insert the MOS tube of the semiconductor power device to be tested into the special test socket on the PCB board to ensure that the electrical connection between the MOS tube and the test system is correct, so as to prepare for the subsequent Crss test;

[0074] S4 starts the Crss test, which means that the experimental environment required for the leakage current test has been built, and the Crss test of the MOS tube can be started. Before the test, the LCR meter needs to be calibrated for open circuit and short circuit to eliminate the influence of parasitic parameters.

[0075] S5 applies high voltage to the D terminal of DUT. Scanning the Crss curve means adjusting the size of Vds, changing the Crss test conditions, and performing Cgd tests on MOS tubes under different Vds, thereby generating a Crss test curve.

[0076] The Crss test of S6 DUT is completed. Through the reasonable design of AC Guard line, the influence of parasitic capacitance is eliminated.

[0077] It should be noted that, in this article, relational terms such as first and second (number one, number two), etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "including one..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0078] The above shows and describes the basic principles and main features of the present invention and the advantages of the present invention. It should be understood by those skilled in the art that the present invention is not limited by the above embodiments, and the above embodiments and descriptions are only for explaining the principles of the present invention. Without departing from the spirit and scope of the present invention, the present invention may have various changes and improvements, and these changes and improvements all fall within the scope of the present invention to be protected.

Claims

1. A method for eliminating the influence of parasitic capacitance in Crss measurement of power semiconductor devices, characterized in that: The steps include: S1: Use a coaxial cable to extend the four terminals of the LCR meter. Connect one end of the coaxial cable to Hcur, Hpot, Lcur and Lpot respectively, and the other end to the PCB board. S2: Make reasonable PCB design for the output ends of LCR and SMU, connect Hcur and Hpot of LCR to D end of DUT, connect Lcur and Lpot to G end of DUT, connect the shielding layer of coaxial cable to S end of DUT as AC Guard line, provide return path for the current of Cds passing through DUT, reduce the wiring distance of AC Guard on PCB, minimize the impedance of AC Guard line in high-frequency circuit, eliminate the influence of parasitic capacitance on Crss test, connect HI end of SMU to D end of DUT, connect LO end to S end of DUT, LCR is inductance, resistance and capacitance tester, SMU is signal source measurement unit, DUT is semiconductor power device under test; S3: Insert the DUT into the socket, and insert the MOS tube of the semiconductor power device to be tested into the dedicated test socket on the PCB board, ensuring that the electrical connection between the MOS tube and the test system is correct, and prepare for the next Crss test; S4: Start Crss test. The experimental environment required for leakage current test has been built. You can start Crss test of MOS tube. Before the test, you need to calibrate the LCR meter for open circuit and short circuit to eliminate the influence of parasitic parameters. S5: Add high voltage to the D terminal of DUT, scan the Crss curve, adjust the Vds value, change the Crss test conditions, perform Cgd test on the MOS tube under different Vds, and thus generate the Crss test curve; S6: The Crss test of DUT is completed. Through the reasonable design of AC Guard line, the influence of parasitic capacitance is eliminated.

2. A method for eliminating the influence of parasitic capacitance in Crss measurement of power semiconductor devices according to claim 1, characterized in that: The invention comprises an SMU (1), an LCR (2), a DUT (3), a coaxial cable (4) and a parasitic capacitor (5); the DUT (3) is provided with a device D terminal (6), a device G terminal (7) and a device S terminal (9); the LCR (2) is provided with an AC Guard line (8); the SMU (1) is a high-voltage source meter, which provides a drain-source DC voltage Vds to the DUT (3); and the interface of the SMU (1) comprises a HI terminal and a LO terminal.

3. The method for eliminating the influence of parasitic capacitance in Crss measurement of power semiconductor devices according to claim 2, characterized in that: The HI terminal is the positive electrode of the SMU (1) and outputs a high voltage signal. An inductor is connected in series between the HI terminal and the D terminal of the DUT (3). The inductor exhibits a high impedance characteristic under high frequency conditions and can effectively prevent the high frequency AC signal of the LCR (2) from being transmitted to the HI terminal of the SMU, thereby ensuring the accuracy and safety of the Crss test.

4. The method for eliminating the influence of parasitic capacitance in Crss measurement of power semiconductor devices according to claim 2, characterized in that: The LO terminal is the negative pole of the SMU (1), and is connected to the S terminal of the DUT (3) and the ACGuard terminal of the LCR (2) to provide a test loop for the Crss test.

5. The method for eliminating the influence of parasitic capacitance in Crss measurement of power semiconductor devices according to claim 2, characterized in that: The LCR (2) is used to measure the value of Cgd. The interface of the LCR (2) includes Hcur, Hpot, Lcur, Lpot and AC Guard, wherein Hcur is a high-end current drive, Hpot is a high-end voltage detection, Lcur is a low-end current drive, and Lpot is a low-end voltage detection. The Hcur and Hpot are connected together through a coaxial cable and connected in series with a capacitor to the D end of the DUT (3). The Lcur and Lpot are connected together through a coaxial cable and added to the G end of the DUT (3).

6. A method for eliminating the influence of parasitic capacitance in Crss measurement of power semiconductor devices according to claim 5, characterized in that: The Hpot and Lpot ports apply an AC voltage signal to both ends of Cgd. These two ports can detect the actual voltage on Cgd to ensure the accuracy of the measurement.

7. The method for eliminating the influence of parasitic capacitance in Crss measurement of power semiconductor devices according to claim 5, characterized in that: The Hcur and Lcur ports are used to measure the current flow caused by the AC voltage signal.

8. The method for eliminating the influence of parasitic capacitance in Crss measurement of power semiconductor devices according to claim 2, characterized in that: The LCR uses the measured voltage and current data to calculate the impedance amplitude and phase angle of Cgd, thereby measuring and calculating the capacitance value of Cgd.

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