Switching matrix test system and method based on interconnection resource linear vectorization

Abstract

The invention relates to the technical field of chip automatic testing, in particular to a switch matrix testing system and method based on interconnection resource linear vectorization, and the system comprises a netlist hunting script module, a code stream generation module and a switch matrix testing module. The netlist hunting script module comprises a parameter file set, a netlist framework construction service and an automatic hunting service; the netlist hunting script module is used for constructing an initial netlist by utilizing the netlist framework construction service according to the parameter file set, and performing automatic hunting operation on the initial netlist by utilizing the automatic hunting service according to the parameter file set to obtain a layout change netlist; the code stream generation module is used for converting the layout change netlist into a code stream; and the switch matrix test module is used for performing switch matrix test on the code stream to obtain a test result. According to the invention, the efficiency of interconnection resource testing and the efficiency of failure positioning can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of chip automated testing, and in particular to a switch matrix testing system and method based on interconnection resource linear vectorization. Background Art

[0002] The purpose of the test is to screen out problematic chips and debug chip design problems. Interconnection resources are the hub of FPGA logic signal transmission. The number of lines and configuration bits is huge, the probability of production problems is greater, and test coverage and debugging are more difficult.

[0003] Today's test methods often have some limitations, such as manual wiring, which is time-consuming and labor-intensive, poor portability, difficult test case development, and difficult to ensure test case quality. If a signal is used to connect various line types, although the test vectors can be reduced, it is very difficult to debug failed chip problems or design problems.

[0004] Currently, FPGAs are getting larger and larger, and the number of resources is increasing. Traditional testing methods cannot meet the technical personnel's needs for automation and customization of test case development. Summary of the invention

[0005] The present invention provides a switch matrix test system based on interconnection resource linear vectorization, the main purpose of which is to improve the efficiency of interconnection resource testing and the efficiency of failure location.

[0006] To achieve the above object, the present invention provides a switch matrix test system based on interconnection resource linear vectorization, the system comprising a netlist line search script module, a bit stream generation module and a switch matrix test module; The netlist line-finding script module includes a parameter file set, a netlist framework building service, and an automatic line-finding service; The netlist search script module is used to use the netlist framework construction service to build an initial netlist according to the parameter file set, and use the automatic search service to perform an automatic search operation on the initial netlist according to the parameter file set to obtain a layout change netlist; The code stream generation module is used to convert the layout change netlist into a code stream; The switch matrix test module is used to perform a switch matrix test on the code stream to obtain a test result.

[0007] In addition, the parameter file set includes device architecture parameters, SM architecture parameters, node parameters, fan-shaped driver file parameters, rtg library files, vector rule parameters, design guidance and test constraint parameters, and a test vector list; The node parameters include fixed node parameters, split node parameters, starting node parameters of the network to be tested, and starting node parameters of the auxiliary test network; The SM in the SM architecture parameter represents a switch matrix.

[0008] In addition, the use of the netlist framework construction service to construct an initial netlist according to the parameter file set includes: Using the netlist framework to build a service, calling the device architecture parameters, SM architecture parameters, node parameters and test vector list in the parameter file set; An initial netlist is constructed according to the device architecture parameters, SM architecture parameters, node parameters and test vector list.

[0009] In addition, constructing an initial netlist according to the device architecture parameters, SM architecture parameters, node parameters and test vector list includes: The device architecture parameters and SM architecture parameters are used to configure a preset header file to obtain an initial netlist framework, wherein the initial netlist framework includes a signal splitting area, a routing area to be tested, and a signal merging area; The fixed node parameters are used to construct the input pins of the signal splitting area and the output pins of the signal merging area; The split node parameter is used to split the input signal entering from the input pin into four signals, and the four signals are used to perform line coverage on the output pin; The starting node parameter of the line network to be tested is used to connect the lines between the interconnected resources in the routing area to be tested to obtain the interconnected resource network; The auxiliary test line network starting node parameter is used to perform a line supplement operation based on boundary bypass connection on the interconnected resource network to obtain an enhanced interconnected resource network; The test vector list is used to input the enhanced interconnection resource network to obtain an initial netlist signal; The initial netlist signal is output in a logical configuration form to obtain an initial netlist.

[0010] In addition, the automatic line search service is used to perform an automatic line search operation on the initial netlist according to the parameter file set to obtain a layout change netlist, including: Using the automatic line search service, calling the device architecture parameters, SM architecture parameters, fan-shaped driver file parameters, rtg library files, vector rule parameters, and design guidance and test constraint parameters in the parameter file set; By using the pre-built automatic routing logic, the initial netlist is automatically routed according to the device architecture parameters, SM architecture parameters, fan-shaped driver file parameters, rtg library files, vector rule parameters, and design guidance and test constraint parameters to obtain a layout change netlist.

[0011] In addition, the process of obtaining the layout change netlist includes: The automatic path finding logic is used to iteratively search for each routing channel line in the initial netlist according to the device architecture parameters, SM architecture parameters, vector rule parameters, design guidance and test constraint parameters to obtain a layout change netlist; The device architecture parameters and SM architecture parameters are used as the physical constraints and resource navigation basis for generating each routing channel line; The rtg library file is used to provide all rtg information in the coordinate resources of all SMs in the initial netlist, wherein the rtg information includes a signal input point and a signal output point, which is a signal transmission unit controlled by a switch inside the SM; The sector drive file parameters are used to convert the logic signal input from the signal input point into a hash form signal when passing through the SM and output it from the signal output point to obtain a hash text signal; The vector rule parameter is used to map the line type of each routing channel line in the initial netlist from a preset direction+span number+serial number form to a preset plane rectangular coordinate system operation function form; The design guidance file in the design guidance and test constraint parameters is used to specify the priority and path constraints of each preset test line type in the initial netlist; The test constraint parameters in the design guidance and test constraint parameters are used to statically constrain the coordinate resources of the SM to be tested and dynamically constrain the rtg range of the initial netlist.

[0012] In addition, the automatic path finding logic includes: Extracting the starting point-end point routing vector information of the current routing channel line in the initial netlist according to the device architecture parameters, SM architecture parameters, fan-shaped driver file parameters and rtg library files; Obtaining initialization parameter i, obtaining the coordinates of the routing channel line constrained for the i-th time, obtaining the coordinates of the target routing channel line, and obtaining the distance information of the target routing coordinates from the starting point-end point routing vector information; According to the i-th route starting point, all the i-th route ending points are randomly generated; According to the vector rule parameters, the distance information between the routing starting point and each routing end point is calculated, and the target routing end point of the target routing channel line coordinate is preferably obtained, and the next routing channel line coordinate corresponding to the target routing end point is calculated; Determining whether the next routing channel line coordinates conform to the constraint area in the design guidance and test constraint parameters; When the constraint area is exceeded, return to the step of preferentially obtaining the target routing end point of the target routing channel line coordinates, and calculating the next routing channel line coordinates corresponding to the target routing end point, to obtain an updated target routing end point and an updated next routing channel line coordinates; When the constraint area is not exceeded, the next routing channel line coordinates are placed in a preset cache area, and the last level routing channel line coordinates in the cache area are extracted; Determine whether the last level routing channel line coordinates effectively connect the starting point and the ending point; When the last level routing channel line coordinates effectively connect the starting point and the ending point, an automatic path finding is completed; When the last level of routing channel line coordinates do not effectively connect the starting point and the ending point, the value i is multiplied to obtain an updated i, and the operation step of obtaining the routing channel line coordinates constrained for the i-th time is returned to the above.

[0013] In addition, the switch matrix test module includes design test conditions, simulation services, operation test conditions and dichotomy judgment conditions: The design test condition is used to determine whether the code stream has a design rule problem; The simulation service is used to perform full chip simulation on the bit stream to obtain board-level test results; The running test condition is used to test whether the board-level test result passes; The binary search condition is used to test whether the code stream needs to design a debug vector through the binary search method.

[0014] In addition, the rtg library file includes: Extract FPGA software architecture parameters from the pre-built architecture information process file to obtain basic architecture information; Using the pre-built genhcelldb.pl tool, extract all SM resource coordinates from the infrastructure information to obtain an SM coordinate file; Generate a routing file of the SM coordinate file using the pre-built getrtgs.pl tool to obtain an SM routing file; The SM coordinate file and the SM routing file are merged to obtain a routing library file, and rtg information is extracted from the routing library file to obtain a rtg library file.

[0015] To achieve the above object, the present invention further provides a switch matrix testing method based on interconnection resource linear vectoring, the method comprising: Using a pre-built netlist framework building service, building an initial netlist according to a pre-built parameter file set, and using a pre-built automatic line search service, performing an automatic line search operation on the initial netlist according to the parameter file set to obtain a layout change netlist; Converting the layout change netlist into a code stream; A switch matrix test is performed on the code stream to obtain a test result.

[0016] The present invention solves the problem described in the background technology. The present invention realizes the test automation process by means of a netlist search script module, a code stream generation module and a switch matrix test module. The netlist search script module can use a linear vectorization method to physically arrange the resources to be tested and related resources. The code stream generation module is used to generate a code stream from the physical arrangement result. The switch matrix test module is used to use the code stream to perform failure analysis on the FPGA chip, thereby mass production testing. Therefore, the present invention can improve the efficiency of interconnection resource testing and the efficiency of failure location. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A schematic diagram of the structure of a switch matrix test system based on interconnection resource linear vectoring provided by an embodiment of the present invention; Figure 2 A thumbnail diagram of the SM structure architecture in a switch matrix test system based on interconnection resource linear vectorization provided in an embodiment of the present invention; Figure 3 A schematic diagram of netlist construction in a switch matrix test system based on interconnection resource linear vectorization provided in an embodiment of the present invention; Figure 4 A schematic diagram of automatic line search logic in a switch matrix test system based on interconnection resource linear vectorization provided by an embodiment of the present invention; Figure 5 A schematic flow chart of a switch matrix testing method based on interconnection resource linear vectoring provided in one embodiment of the present invention.

[0018] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0019] In order to make the purpose, technical solution and advantages of the present application more obvious, the exemplary embodiments according to the present application will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application, and it should be understood that the present application is not limited to the exemplary embodiments described here.

[0020] Terminology explanation: Switch Marix: A switch matrix connecting modules, which is composed of various muxes of different sizes, abbreviated as SM.

[0021] Interconnection resources: Interconnection resources refer to the connection resources between SMs or between SMs and adjacent functional modules, as well as the SM itself as a switch matrix.

[0022] Line vectorization: The process of mapping a line type in the form of direction + span number + sequence number to a plane rectangular coordinate.

[0023] HCDL language: a language for describing the underlying netlist of a chip, which can be roughly classified into the elements of design, module, net, rtg, inst, cfg, inpin, and outpin.

[0024] FPGA_Sculptor: A back-end design tool for FPGA that can generate code streams by directly modifying the netlist after pr, skipping the previous synthesis compilation process.

[0025] ATE: (Auto Test Equipment), automated test equipment used for automated testing of electronic components, circuit boards, chips or larger systems.

[0026] Routing gate: A route in SM where the start and end points are controlled by switches, abbreviated as rtg.

[0027] srcp: The end point of a rtg route and the starting point of a line.

[0028] sikp: The starting point of an rtg route and the end point of a line.

[0029] fullchip_sim: full chip functional simulation.

[0030] Junction: The RTG hub for interconnected resources.

[0031] An embodiment of the present application relates to a switch matrix test system based on interconnection resource linear vectorization, such as Figure 1 As shown, it mainly includes a netlist search script module, a bit stream generation module and a switch matrix test module; The netlist line-finding script module includes a parameter file set, a netlist framework building service, and an automatic line-finding service; The netlist search script module is used to use the netlist framework construction service to build an initial netlist according to the parameter file set, and use the automatic search service to perform an automatic search operation on the initial netlist according to the parameter file set to obtain a layout change netlist; The code stream generation module is used to convert the layout change netlist into a code stream; The switch matrix test module is used to perform a switch matrix test on the code stream to obtain a test result.

[0032] The netlist framework construction service is a script service for constructing a netlist. The automatic line search service is a script service for traversing paths in a netlist.

[0033] The code stream generation module is constructed by FPGA_Sculptor tool. The switch matrix test module is constructed by automated test equipment.

[0034] For details, refer to Figure 1 As shown, in the embodiment of the present invention, the parameter file set includes device architecture parameters, SM architecture parameters, node parameters, fan-shaped driver file parameters, rtg library files, vector rule parameters, design guidance and test constraint parameters, and a test vector list; The node parameters include fixed node parameters, split node parameters, starting node parameters of the network to be tested, and starting node parameters of the auxiliary test network; The SM in the SM architecture parameter represents a switch matrix.

[0035] The device architecture parameters refer to a set of parameters that describe the overall hardware architecture of the FPGA device. The SM architecture parameters refer to configuration parameters that describe the switch matrix (SM) inside the FPGA.

[0036] Among them, the fixed node parameters in the node parameters are used to fix the connection of non-programmable nodes. The split node parameters are used for nodes that can be divided into multiple sub-paths. The starting node parameters of the line network to be tested are used to describe the starting point of the test target line network. The starting node parameters of the auxiliary test line network are used to describe the starting point of the auxiliary test path.

[0037] The rtg library file refers to a database containing the topological structure of all routing resources of the FPGA, switch matrix (SM) routing rules and resource coordinates.

[0038] The fan-shaped drive file parameters are used to describe the signal parameters for driving multiple parallel nodes.

[0039] The vector rule parameters refer to a set of rules required for generating a test vector.

[0040] The design guidance parameters refer to a set of rules that guide layout and routing tools to optimize the design.

[0041] The test constraint parameters refer to the boundary conditions that limit the test process.

[0042] The test vector list refers to a set of input signal sequences used to simulate the functions or fault scenarios of FPGA design.

[0043] Specifically, in the embodiment of the present invention, the device architecture parameters include: device name, unpackaged IO, FPGA chip internal resource coordinate boundaries including IO, CLE, SM and ROW_NUM ("row" number), COL_NUM ("column" number).

[0044] Specifically, in the embodiments of the present invention, reference Figure 2 As shown, the SM architecture parameters include: ROW information and its mapping relationship with the Y coordinate, COL information and its mapping relationship with the X coordinate, boundary information of the X and Y coordinates, a boundary SM resource coordinate set {XxYx…XmYn}, a coordinate elimination set occupied by digital modules such as xxx and yyy, and boundary coordinate information of the position occupied by the digital module.

[0045] Specifically, in the embodiment of the present invention, the fixed node parameters in the node parameters include the fixed module INST and the fixed wire net NET. The meaning of fixed means that, for example, the IO module (IO BUFFER), IOL module (IO LOGIC), and CLE module (programmable logic module) are used as auxiliary test modules in the design to be tested, and their internal parameters can be defined in a unified manner by entering the reference module INST and the fixed wire net NET, without having to change them multiple times according to the changes in the case, and their position coordinates and BLOCK names change with the case.

[0046] Specifically, in the embodiment of the present invention, the split node parameter is the splitting form of the input signal, for example, one input signal is split into four signals.

[0047] Specifically, in the embodiment of the present invention, the rtg library file contains information of all rtgs in all SM coordinate resources. The actual circuit does not use all of them, and adopts an external floating (suspended, not connected) mode. Therefore, the test of the present invention does not need to pay attention to this part of the suspended pins.

[0048] Specifically, in the embodiment of the present invention, the fan-shaped drive file parameters need to be separated from the rtg database file, and the fan-shaped drive file parameters focus on the vector nature of the internal sikp of all SM resources, that is, a one-input and multiple-output fan-shaped drive structure.

[0049] Specifically, in the embodiment of the present invention, the vector rule file needs to be independently constructed, mainly focusing on the determined output end srcp, such as input from port 1 and output from port 2. This fixed route is completed by the present invention using vectorized rules with the help of a scripting language, so that it can be directly called as a function.

[0050] Specifically, in the embodiment of the present invention, the design test vector in the design guidance and test constraint parameters needs to guide the constrained SIKP pointing randomness and specify the high priority line type.

[0051] 1) Assuming that the current routing does not require human guidance, the RTG of the entire route from A to B needs to be implemented using automatic routing logic. When routing, there will be multiple RTGs to choose from at each junction, and the optimal path needs to be selected through constraints and iterative routing to reach the end point.

[0052] 2) Assume that the current wiring requires manual guidance, the test line type is RRk, and the route is written to RRiSRCj at the SM_L_XxYy coordinate position. After the vector rule is calculated, the next level of sikp is RRqSIKp of SM_L_XmYn. At this position, Sikp will export its own fan-shaped drive structure file. Through the randomization function in the script and the path convergence principle, all rtgs are sorted. At this time, the program will rank this line type to the highest priority according to the manually entered line type RRk.

[0053] 3) Several basic principles followed by automatic routing, these routing principles are only used for testing. Automatic routing has something in common with the Router (routing tool) in EDA (electronic design automation), but it is not the same as the Router in EDA: Routing principle 1: Path convergence and approximation principle. Routing always points to or approaches the end point, and a small number of incremental line segments in the middle can be ignored.

[0054] Wiring principle 2: long plus short, long in the middle and short at both ends. Use long jumpers when the plane space is large, otherwise use short jumpers.

[0055] Wiring principle 3: No repeated wiring principle. SMs with the same coordinates should not repeatedly drive the same srcp in the same period or in different periods.

[0056] Routing method 4: Pre-routing mechanism, routing calls two functions, one is the front-end wire router, and the other is the feedback adjustment router. Correct routing is performed through the front-end plus feedback mechanism.

[0057] Specifically, in the embodiment of the present invention, the test constraint parameters in the design guidance and test constraint parameters include the SM constraints of the source data channel splitting and each splitting route, the SM constraints of the channel to be tested and the SM constraints of the auxiliary test channel. The content of the test constraint parameters needs to be written into the script.

[0058] 1) Static constraints: refers to the constraint area is a fixed resource coordinate, which can be considered as the SM constraint of the line to be tested. Once the test line type is selected, the constraints of this part can be constrained: 2) Dynamic constraint: refers to a constraint method in which the constraint area gradually narrows the search range as the search route changes. It can be considered that it is basically applicable to the SM constraint where the split route is located and the SM constraint where the auxiliary test line is located.

[0059] 3) In addition to the coordinate range, the constraints also include routing constraints, that is, optimizing the rtg range.

[0060] For details, refer to Figure 3 As shown, in the embodiment of the present invention, the use of the netlist framework to build a service and build an initial netlist according to the parameter file set includes: Using the netlist framework to build a service, calling the device architecture parameters, SM architecture parameters, node parameters and test vector list in the parameter file set; An initial netlist is constructed according to the device architecture parameters, SM architecture parameters, node parameters and test vector list.

[0061] In detail, in an embodiment of the present invention, constructing an initial netlist according to the device architecture parameters, SM architecture parameters, node parameters and test vector list includes: The device architecture parameters and SM architecture parameters are used to configure a preset header file to obtain an initial netlist framework, wherein the initial netlist framework includes a signal splitting area, a routing area to be tested, and a signal merging area; The fixed node parameters are used to construct the input pins of the signal splitting area and the output pins of the signal merging area; The split node parameter is used to split the input signal entering from the input pin into four signals, and the four signals are used to perform line coverage on the output pin; The starting node parameter of the line network to be tested is used to connect the lines between the interconnected resources in the routing area to be tested to obtain the interconnected resource network; The auxiliary test line network starting node parameter is used to perform a line supplement operation based on boundary bypass connection on the interconnected resource network to obtain an enhanced interconnected resource network; The test vector list is used to input the enhanced interconnection resource network to obtain an initial netlist signal; The initial netlist signal is output in a logical configuration form to obtain an initial netlist.

[0062] The header file includes the necessary information for netlist construction: design "case.hcdl" deviceversion.

[0063] The input pin and the output pin are transmission endpoints of the signal.

[0064] The interconnected resource network refers to a network formed by connecting various interconnected resources.

[0065] The line supplement operation refers to adding a connection mode caused by the boundary on the basis of the interconnected resource network. The enhanced interconnected resource network is an interconnected resource network with boundary connection.

[0066] Specifically, in the embodiments of the present invention, reference Figure 3 Take the test vector generation of the test sieve as an example: First, the first section contains the design header file.

[0067] The second part is the input and output pins and line network information, called fixed connection INST / NET, such as Figure 3 As shown in ① and ⑥, data_src is used as the data input pin, row0_result and others are used as output pins, and the output signal can be logically used to finally output a flag signal.

[0068] The third part is the input signal source splitting information, such as Figure 3 The input signal shown in ② is split into four signals, each of which enters a row of the chip to cover the channel.

[0069] The fourth part is the starting node parameters of the line network to be tested, such as Figure 3 As shown in ③, each dut is an interconnection resource to be tested, and a data line runs through all interconnection resources of a certain line type in the current row.

[0070] The fifth part is the auxiliary test line network starting node parameters, such as Figure 3 As shown in ④, the light-colored signal line needs to go back to the next row or column of interconnection resources after reaching the boundary, mainly the reflection lines of various boundaries and the boundaries of digital modules in the chip. In addition, it should be noted that the initial parameters of the fixed part need to be replaced with the test vector design parameters, such as the BLOCK coordinates of the IO, the level standard, the slew rate, etc. Then it is presented through the logic configuration method, such as Figure 3 In step ⑤, the initial netlist is obtained.

[0071] In addition, the test vector generation for tracking failure points is basically similar to the above content, such as Figure 3 As shown in ⑥, the entire long chain rtg is divided into segmented signal outputs by inserting multiple IO nodes, and the results of the output IO are detected, which will not be repeated here.

[0072] The present invention completes the construction of the initial netlist through the above process, and then can start automatic path finding for the netlist.

[0073] In detail, in an embodiment of the present invention, the automatic line search service is used to perform an automatic line search operation on the initial netlist according to the parameter file set to obtain a layout change netlist, including: Using the automatic line search service, calling the device architecture parameters, SM architecture parameters, fan-shaped driver file parameters, rtg library files, vector rule parameters, and design guidance and test constraint parameters in the parameter file set; By using the pre-built automatic routing logic, the initial netlist is automatically routed according to the device architecture parameters, SM architecture parameters, fan-shaped driver file parameters, rtg library files, vector rule parameters, and design guidance and test constraint parameters to obtain a layout change netlist.

[0074] In detail, in the embodiment of the present invention, the process of obtaining the layout change netlist includes: The automatic path finding logic is used to iteratively search for each routing channel line in the initial netlist according to the device architecture parameters, SM architecture parameters, vector rule parameters, design guidance and test constraint parameters to obtain a layout change netlist; The device architecture parameters and SM architecture parameters are used as the physical constraints and resource navigation basis for generating each routing channel line; The rtg library file is used to provide all rtg information in the coordinate resources of all SMs in the initial netlist, wherein the rtg information includes a signal input point and a signal output point, which is a signal transmission unit controlled by a switch inside the SM; The sector drive file parameters are used to convert the logic signal input from the signal input point into a hash form signal when passing through the SM and output it from the signal output point to obtain a hash text signal; The vector rule parameter is used to map the line type of each routing channel line in the initial netlist from a preset direction+span number+serial number form to a preset plane rectangular coordinate system operation function form; The design guidance file in the design guidance and test constraint parameters is used to specify the priority and path constraints of each preset test line type in the initial netlist; The test constraint parameters in the design guidance and test constraint parameters are used to statically constrain the coordinate resources of the SM to be tested and dynamically constrain the rtg range of the initial netlist.

[0075] The routing channel line refers to a path for signal transmission.

[0076] Specifically, in an embodiment of the present invention, the same parameter plays different roles in different steps. In the process of obtaining the layout change netlist, the present invention uses the device architecture parameters and SM architecture parameters as the physical constraints and resource navigation basis for the generation of each routing channel line. The rtg library file is used as data to provide all rtg information in the coordinate resources of all SMs in the initial netlist. The fan-shaped drive file parameters are used as a conversion tool to convert logical signals into signals in hash form. The vector rule parameters are used as a tool to convert the data type [direction + span number + sequence number] into a plane rectangular coordinate system operation function form. The design guidance and test constraint parameters are used as artificial experience for interference and constraints.

[0077] In detail, in the embodiment of the present invention, the automatic path finding logic includes: Extracting the starting point-end point routing vector information of the current routing channel line in the initial netlist according to the device architecture parameters, SM architecture parameters, fan-shaped driver file parameters and rtg library files; Obtaining initialization parameter i, obtaining the coordinates of the routing channel line constrained for the i-th time, obtaining the coordinates of the target routing channel line, and obtaining the distance information of the target routing coordinates from the starting point-end point routing vector information; According to the i-th route starting point, all the i-th route ending points are randomly generated; According to the vector rule parameters, the distance information between the routing starting point and each routing end point is calculated, and the target routing end point of the target routing channel line coordinate is preferably obtained, and the next routing channel line coordinate corresponding to the target routing end point is calculated; Determining whether the next routing channel line coordinates conform to the constraint area in the design guidance and test constraint parameters; When the constraint area is exceeded, return to the step of preferentially obtaining the target routing end point of the target routing channel line coordinates, and calculating the next routing channel line coordinates corresponding to the target routing end point, to obtain an updated target routing end point and an updated next routing channel line coordinates; When the constraint area is not exceeded, the next routing channel line coordinates are placed in a preset cache area, and the last level routing channel line coordinates in the cache area are extracted; Determine whether the last level routing channel line coordinates effectively connect the starting point and the ending point; When the last level routing channel line coordinates effectively connect the starting point and the ending point, an automatic path finding is completed; When the last level of routing channel line coordinates do not effectively connect the starting point and the ending point, the value i is multiplied to obtain an updated i, and the operation step of obtaining the i-th routing channel line coordinates is returned to the above.

[0078] The starting point-ending point routing vector information includes the position coordinates of the two SMs and the connection path between the two SMs.

[0079] The initialization parameter i is a preset dynamically changing parameter.

[0080] Among them, the distance information is the distance between the scrp of the current rtg and the sikp of the destination rtg in the target routing coordinates.

[0081] Specifically, in the embodiment of the present invention, it is necessary to adjust the device architecture parameters, SM architecture parameters, fan-shaped driver file parameters and rtg library files to realize automatic routing. The automatic routing logic adopts an iterative routing search method, with the help of linear vectorization calculation functions and sikp pointing randomization, and automatic routing is performed under the cooperation of constraint rules and wiring rules.

[0082] In detail, in the embodiment of the present invention, the switch matrix test module includes design test conditions, simulation services and operation test conditions and dichotomy judgment conditions: The design test condition is used to determine whether the code stream has a design rule problem; The simulation service is used to perform full chip simulation on the bit stream to obtain board-level test results; The running test condition is used to test whether the board-level test result passes; The binary search condition is used to test whether the code stream needs to design a debug vector through the binary search method.

[0083] The binary judgment is used to generate the test vectors required for debugging.

[0084] Specifically, in the embodiment of the present invention, the code stream and the corresponding excitation signal and golden signal are used to perform failure analysis on the FPGA chip, so as to realize mass production testing.

[0085] Specifically, the present invention uses linear vectorization, design guidance rules, automatic line search logic and test area constraints to automatically generate vectors. At the beginning of the design, the device type, test linear type, test input port, test output port and debug port are determined. The automated script generates a netlist file based on the input parameters, and further generates a code stream and an ATE vector file. If there is a failed chip, the designer can customize the binary series in the script and generate multiple vector files of the same linear type to approximate the failure position. The specific code stream test process is a common test process, and the present invention will not be repeated here.

[0086] In detail, in the embodiment of the present invention, the rtg library file includes: Extract FPGA software architecture parameters from the pre-built architecture information process file to obtain basic architecture information; Using the pre-built genhcelldb.pl tool, extract all SM resource coordinates from the infrastructure information to obtain an SM coordinate file; Generate a routing file of the SM coordinate file using the pre-built getrtgs.pl tool to obtain an SM routing file; The SM coordinate file and the SM routing file are merged to obtain a routing library file, and rtg information is extracted from the routing library file to obtain a rtg library file.

[0087] The architecture information process file is an original data file provided by an FPGA manufacturer or design tool, and contains the underlying parameters of the device hardware architecture. The basic architecture information is a set of FPGA software-level architecture parameters extracted from the architecture information process file.

[0088] The genhcelldb.pl is a pre-built automation script for extracting SM resource coordinates from infrastructure information. The SM coordinate file is a file that records the physical locations of all switch matrices (SM) in the FPGA device.

[0089] The getrtgs.pl is a pre-built automation script for generating a routing rule file based on the SM coordinate file. The SM routing file is a file that describes the signal path rules within and across a switch matrix (SM).

[0090] The routing library file is a unified database file after merging the SM coordinate file and the SM routing file. The rtg library file is a final routing resource graph (rtg) database extracted from the routing library file.

[0091] Specifically, in an embodiment of the present invention, the rtg library file contains a database of multiple coordinates, and the databases of multiple coordinates are merged into the same library file. The architecture information process file is an fpga software architecture parameter file, which contains IO information, interconnection information, various cell (fpga software level minimum unit) configuration information, etc. The SM coordinates are all SM resource coordinates of the device extracted from the architecture information, and then the SM routing file is generated, and finally all rtg information is extracted from the routing library.

[0092] In summary, this solution is highly operable, portable, and flexible in application. It can achieve customized test coverage of FPGA chip interconnection resources and improve the efficiency of interconnection resource testing and failure location.

[0093] The present invention solves the problem described in the background technology. The present invention realizes the test automation process by means of a netlist search script module, a code stream generation module and a switch matrix test module. The netlist search script module can use a linear vectorization method to physically arrange the resources to be tested and related resources. The code stream generation module is used to generate a code stream from the physical arrangement result. The switch matrix test module is used to use the code stream to perform failure analysis on the FPGA chip, thereby mass production testing. Therefore, the present invention can improve the efficiency of interconnection resource testing and the efficiency of failure location.

[0094] Further, see Figure 5 As shown, the embodiment of the present invention also provides a method for utilizing Figure 1 The control method performed by the switch matrix test system based on interconnection resource linear vectoring includes: Using a pre-built netlist framework building service, building an initial netlist according to a pre-built parameter file set, and using a pre-built automatic line search service, performing an automatic line search operation on the initial netlist according to the parameter file set to obtain a layout change netlist; Converting the layout change netlist into a code stream; A switch matrix test is performed on the code stream to obtain a test result.

[0095] The netlist framework construction service is a service for constructing a netlist. The automatic line search service is a service for traversing paths in a netlist.

[0096] In the embodiment of the present invention, the parameter file set includes device architecture parameters, SM architecture parameters, node parameters, fan-shaped driver file parameters, rtg library files, vector rule parameters, design guidance and test constraint parameters, and a test vector list; The node parameters include fixed node parameters, split node parameters, starting node parameters of the network to be tested, and starting node parameters of the auxiliary test network; The SM in the SM architecture parameter represents a switch matrix.

[0097] The device architecture parameters refer to a set of parameters that describe the overall hardware architecture of the FPGA device. The SM architecture parameters refer to configuration parameters that describe the switch matrix (SM) inside the FPGA.

[0098] Among them, the fixed node parameters in the node parameters are used to fix the connection of non-programmable nodes. The split node parameters are used for nodes that can be divided into multiple sub-paths. The starting node parameters of the line network to be tested are used to describe the starting point of the test target line network. The starting node parameters of the auxiliary test line network are used to describe the starting point of the auxiliary test path.

[0099] The rtg library file refers to a database containing the topological structure of all routing resources of the FPGA, switch matrix (SM) routing rules and resource coordinates.

[0100] The fan-shaped drive file parameters are used to describe the signal parameters for driving multiple parallel nodes.

[0101] The vector rule parameters refer to a set of rules required for generating a test vector.

[0102] The design guidance parameters refer to a set of rules that guide layout and routing tools to optimize the design.

[0103] The test constraint parameters refer to the boundary conditions that limit the test process.

[0104] The test vector list refers to a set of input signal sequences used to simulate the functions or fault scenarios of FPGA design.

[0105] Specifically, the present invention uses HCDL language, FPGA_Sculptor, and scripts to build a netlist framework construction service, the automatic line search service, stream code generation, and switch matrix test service, and uses a linear vectorization method to place and route the resources to be tested and related resources and generate a code stream. This code stream and the corresponding stimulus signal and golden signal are used to perform failure analysis and mass production testing on FPGA chips.

[0106] It is obvious to those skilled in the art that the present invention is not limited to the details of the above exemplary embodiments, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0107] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the spirit and scope of the technical solution of the present invention.

Claims

1. A switch matrix test system based on interconnection resource linear vectorization, characterized in that: The system includes a netlist search script module, a code stream generation module and a switch matrix test module; The netlist line-finding script module includes a parameter file set, a netlist framework building service, and an automatic line-finding service; The netlist search script module is used to use the netlist framework construction service to build an initial netlist according to the parameter file set, and use the automatic search service to perform an automatic search operation on the initial netlist according to the parameter file set to obtain a layout change netlist; The code stream generation module is used to convert the layout change netlist into a code stream; The switch matrix test module is used to perform a switch matrix test on the code stream to obtain a test result.

2. The switch matrix test system based on interconnection resource linear vectoring according to claim 1, characterized in that: The parameter file set includes device architecture parameters, SM architecture parameters, node parameters, fan-shaped driver file parameters, rtg library files, vector rule parameters, design guidance and test constraint parameters, and a test vector list; The node parameters include fixed node parameters, split node parameters, starting node parameters of the network to be tested, and starting node parameters of the auxiliary test network; The SM in the SM architecture parameter represents a switch matrix.

3. The switch matrix test system based on interconnection resource linear vectoring as claimed in claim 2, characterized in that: The using the netlist framework construction service to construct an initial netlist according to the parameter file set includes: Using the netlist framework to build a service, calling the device architecture parameters, SM architecture parameters, node parameters and test vector list in the parameter file set; An initial netlist is constructed according to the device architecture parameters, SM architecture parameters, node parameters and test vector list.

4. The switch matrix test system based on interconnection resource linear vectoring as claimed in claim 3, characterized in that: The initial netlist is constructed according to the device architecture parameters, SM architecture parameters, node parameters and test vector list, including: The device architecture parameters and SM architecture parameters are used to configure a preset header file to obtain an initial netlist framework, wherein the initial netlist framework includes a signal splitting area, a routing area to be tested, and a signal merging area; The fixed node parameters are used to construct the input pins of the signal splitting area and the output pins of the signal merging area; The split node parameter is used to split the input signal entering from the input pin into four signals, and the four signals are used to perform line coverage on the output pin; The starting node parameter of the line network to be tested is used to connect the lines between the interconnected resources in the routing area to be tested to obtain the interconnected resource network; The auxiliary test line network starting node parameter is used to perform a line supplement operation based on boundary bypass connection on the interconnected resource network to obtain an enhanced interconnected resource network; The test vector list is used to input the enhanced interconnection resource network to obtain an initial netlist signal; The initial netlist signal is output in a logical configuration form to obtain an initial netlist.

5. The switch matrix test system based on interconnection resource linear vectoring according to claim 4, characterized in that: The method of using the automatic line search service to perform an automatic line search operation on the initial netlist according to the parameter file set to obtain a layout change netlist includes: Using the automatic line search service, calling the device architecture parameters, SM architecture parameters, fan-shaped driver file parameters, rtg library files, vector rule parameters, and design guidance and test constraint parameters in the parameter file set; By using the pre-built automatic routing logic, the initial netlist is automatically routed according to the device architecture parameters, SM architecture parameters, fan-shaped driver file parameters, rtg library files, vector rule parameters, and design guidance and test constraint parameters to obtain a layout change netlist.

6. The switch matrix test system based on interconnection resource linear vectoring according to claim 5, characterized in that: The process of obtaining the layout change netlist includes: The automatic path finding logic is used to iteratively search for each routing channel line in the initial netlist according to the device architecture parameters, SM architecture parameters, vector rule parameters, design guidance and test constraint parameters to obtain a layout change netlist; The device architecture parameters and SM architecture parameters are used as the physical constraints and resource navigation basis for generating each routing channel line; The rtg library file is used to provide all rtg information in the coordinate resources of all SMs in the initial netlist, wherein the rtg information includes a signal input point and a signal output point, which is a signal transmission unit controlled by a switch inside the SM; The sector drive file parameters are used to convert the logic signal input from the signal input point into a hash form signal when passing through the SM and output it from the signal output point to obtain a hash text signal; The vector rule parameter is used to map the line type of each routing channel line in the initial netlist from a preset direction+span number+serial number form to a preset plane rectangular coordinate system operation function form; The design guidance file in the design guidance and test constraint parameters is used to specify the priority and path constraints of each preset test line type in the initial netlist; The test constraint parameters in the design guidance and test constraint parameters are used to statically constrain the coordinate resources of the SM to be tested and dynamically constrain the rtg range of the initial netlist.

7. The switch matrix test system based on interconnection resource linear vectoring according to claim 6, characterized in that: The automatic path-finding logic comprises: Extracting the starting point-end point routing vector information of the current routing channel line in the initial netlist according to the device architecture parameters, SM architecture parameters, fan-shaped driver file parameters and rtg library files; Obtaining initialization parameter i, obtaining the coordinates of the routing channel line constrained for the i-th time, obtaining the coordinates of the target routing channel line, and obtaining the distance information of the target routing coordinates from the starting point-end point routing vector information; According to the i-th route starting point, all the i-th route ending points are randomly generated; According to the vector rule parameters, the distance information between the routing starting point and each routing end point is calculated, and the target routing end point of the target routing channel line coordinate is preferably obtained, and the next routing channel line coordinate corresponding to the target routing end point is calculated; Determining whether the next routing channel line coordinates conform to the constraint area in the design guidance and test constraint parameters; When the constraint area is exceeded, return to the step of preferentially obtaining the target routing end point of the target routing channel line coordinates, and calculating the next routing channel line coordinates corresponding to the target routing end point, to obtain an updated target routing end point and an updated next routing channel line coordinates; When the constraint area is not exceeded, the next routing channel line coordinates are placed in a preset cache area, and the last level routing channel line coordinates in the cache area are extracted; Determine whether the last level routing channel line coordinates effectively connect the starting point and the ending point; When the last level routing channel line coordinates effectively connect the starting point and the ending point, an automatic path finding is completed; When the last level of routing channel line coordinates do not effectively connect the starting point and the ending point, the value i is multiplied to obtain an updated i, and the operation step of obtaining the i-th routing channel line coordinates is returned to the above.

8. The switch matrix test system based on interconnection resource linear vectoring according to claim 7, characterized in that: The switch matrix test module includes design test conditions, simulation services, operation test conditions and dichotomy judgment conditions: The design test condition is used to determine whether the code stream has a design rule problem; The simulation service is used to perform full chip simulation on the bit stream to obtain board-level test results; The running test condition is used to test whether the board-level test result passes; The binary search condition is used to test whether the code stream needs to design a debug vector through the binary search method.

9. The switch matrix test system based on interconnection resource linear vectoring according to claim 8, characterized in that: The rtg library file includes: Extract FPGA software architecture parameters from the pre-built architecture information process file to obtain basic architecture information; Using the pre-built genhcelldb.pl tool, extract all SM resource coordinates from the infrastructure information to obtain an SM coordinate file; Generate a routing file of the SM coordinate file using the pre-built getrtgs.pl tool to obtain an SM routing file; The SM coordinate file and the SM routing file are merged to obtain a routing library file, and rtg information is extracted from the routing library file to obtain a rtg library file.

10. A switch matrix testing method based on interconnection resource linear vectoring, characterized in that: The method comprises: Using a pre-built netlist framework building service, building an initial netlist according to a pre-built parameter file set, and using a pre-built automatic line search service, performing an automatic line search operation on the initial netlist according to the parameter file set to obtain a layout change netlist; Converting the layout change netlist into a code stream; A switch matrix test is performed on the code stream to obtain a test result.

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