Switch Matrix Test System and Method Based on Linear Vectorization of Internet Resources

Abstract

The present invention relates to the technical field of chip automated testing, and provides a switch matrix testing system and method based on the linear vectorization of interconnection resources. The system includes a netlist line search script module, a bitstream generation module, and a switch matrix testing module. The netlist line search script module includes a parameter file set, a netlist framework construction service, and an automatic line search service. The netlist line search script module is used to construct an initial netlist according to the parameter file set by using the netlist framework construction service, and perform an automatic line search operation on the initial netlist according to the parameter file set by using the automatic line search service to obtain a layout change netlist. The bitstream generation module is used to convert the layout change netlist into a bitstream. The switch matrix testing module is used to perform a switch matrix test on the bitstream to obtain a test result. The present invention can improve the efficiency of interconnection resource testing and the efficiency of failure location.

Description

Technical Field

[0001] The present invention relates to the technical field of chip automated testing, and particularly to a switch matrix testing system and method based on the linear vectorization of interconnection resources. Background Art

[0002] The purpose of testing is to screen out defective chips and debug chip design problems. Interconnection resources are the hubs for FPGA logic signal transmission, with a large number of wire tracks and configuration bits, and a higher probability of problems in production and manufacturing. Testing coverage and debugging are relatively difficult.

[0003] Current testing methods often have some limitations. For example, manual wiring is used in testing, which is time-consuming and laborious, has poor portability, is difficult to develop test cases, and it is difficult to guarantee the quality of test cases. If a single signal is used to connect various linear types, although the test vectors can be reduced, it is very difficult to debug defective chips or design problems.

[0004] Currently, the scale of FPGAs is getting larger and the number of resources is increasing. Traditional testing methods cannot meet the needs of technicians for the automation and customization of test case development. Summary of the Invention

[0005] The present invention provides a switch matrix testing system based on the linear vectorization of interconnection resources, and its main purpose is to improve the efficiency of interconnection resource testing and the efficiency of failure location.

[0006] To achieve the above object, a switch matrix testing system based on the linear vectorization of interconnection resources provided by the present invention includes a netlist routing script module, a bitstream generation module, and a switch matrix testing module;

[0007] The netlist routing script module includes a parameter file set, a netlist framework construction service, and an automatic routing service;

[0008] The netlist routing script module is used to construct an initial netlist according to the parameter file set by using the netlist framework construction service, and perform an automatic routing operation on the initial netlist according to the parameter file set by using the automatic routing service to obtain a layout change netlist;

[0009] The bitstream generation module is used to convert the layout change netlist into a bitstream;

[0010] The switch matrix testing module is used to perform switch matrix testing on the bitstream to obtain a test result.

[0011] In addition, the parameter file set includes device architecture parameters, SM architecture parameters, node parameters, fanout driver file parameters, rtg library files, vector rule parameters, design guidelines and test constraint parameters, and a test vector list;

[0012] Among them, the node parameters include fixed connection node parameters, split node parameters, starting node parameters of the netlist to be tested, and starting node parameters of the auxiliary test netlist;

[0013] Among them, SM in the SM architecture parameters represents a switch matrix.

[0014] In addition, the service for constructing using the netlist framework constructs an initial netlist according to the parameter file set, including:

[0015] The service for constructing using the netlist framework calls the device architecture parameters, SM architecture parameters, node parameters, and test vector list in the parameter file set;

[0016] An initial netlist is constructed according to the device architecture parameters, SM architecture parameters, node parameters, and test vector list.

[0017] In addition, constructing the initial netlist according to the device architecture parameters, SM architecture parameters, node parameters, and test vector list includes:

[0018] The device architecture parameters and SM architecture parameters are used to configure a preset header file to obtain an initial netlist framework, where the initial netlist framework includes a signal splitting area, a routing area to be tested, and a signal merging area;

[0019] The fixed connection node parameters are used to construct the input pins of the signal splitting area and the output pins of the signal merging area;

[0020] The split node parameters are used to split the input signal entering from the input pins into 4 paths of signals, and the 4 paths of signals are used to cover the lanes of the output pins;

[0021] The starting node parameters of the netlist to be tested are used to connect the through-lines between the various interconnection resources in the routing area to be tested to obtain an interconnection resource network;

[0022] The starting node parameters of the auxiliary test netlist are used to perform a through-line supplement operation on the interconnection resource network based on boundary bypass connection to obtain an enhanced interconnection resource network;

[0023] The test vector list is used to input to the enhanced interconnection resource network to obtain an initial netlist signal;

[0024] The initial netlist signal is output in a logical configuration form to obtain an initial netlist.

[0025] In addition, the automatic routing operation is performed on the initial netlist according to the parameter file set by using the automatic routing service, and a layout change netlist is obtained, including:

[0026] The device architecture parameters, SM architecture parameters, fanout driver file parameters, rtg library file, vector rule parameters, and design guidance and test constraint parameters in the parameter file set are called by using the automatic routing service;

[0027] An automatic routing operation is performed on the initial netlist according to the device architecture parameters, SM architecture parameters, fanout driver file parameters, rtg library file, vector rule parameters, and design guidance and test constraint parameters by using a pre-built automatic routing logic, and a layout change netlist is obtained.

[0028] In addition, during the process of obtaining the layout change netlist, it includes:

[0029] The automatic routing logic is used to iteratively search for each routing channel line in the initial netlist according to the device architecture parameters, SM architecture parameters, vector rule parameters, design guidance and test constraint parameters, and obtain a layout change netlist;

[0030] The device architecture parameters and SM architecture parameters are used as the physical constraints and resource navigation basis for generating each routing channel line;

[0031] The rtg library file is used to provide all rtg information within the coordinate resources of all SMs in the initial netlist, where the rtg information includes signal input points and signal output points, and is a signal transmission unit controlled by switches inside the SM;

[0032] The fanout driver file parameters are used to convert the logic signal input from the signal input point into a signal in hash form and output it from the signal output point when passing through the SM, obtaining a hash text signal;

[0033] The vector rule parameters are used to map the line type of each routing channel line in the initial netlist from the form of preset direction + number of crossings + serial number to the form of a preset plane rectangular coordinate system operation function;

[0034] The design guidance file in the design guidance and test constraint parameters is used to specify the priority and path constraints of each preset test line type in the initial netlist;

[0035] The test constraint parameters in the design guidance and test constraint parameters are used to statically constrain the coordinate resources of the SMs to be tested and dynamically constrain the rtg range of the initial netlist.

[0036] In addition, the automatic routing logic includes:

[0037] Extract the start - end routing vector information of the current routing channel line in the initial netlist according to the device architecture parameters, SM architecture parameters, sector drive file parameters, and rtg library file;

[0038] Obtain the initialization parameter i, obtain the coordinates of the routing channel line for the i - th constraint, obtain the target routing channel line coordinates, and obtain the distance information of the target routing coordinates from the start - end routing vector information;

[0039] Randomly generate all the routing end points for the i - th time according to the routing start point for the i - th time;

[0040] According to the vector rule parameters, calculate the distance information between the routing start point and each routing end point, preferably obtain the target routing end point of the target routing channel line coordinates, and calculate the coordinates of the next routing channel line corresponding to the target routing end point;

[0041] Judge whether the coordinates of the next routing channel line conform to the constraint area in the design guidance and test constraint parameters;

[0042] When exceeding the constraint area, return to the step of preferably obtaining the target routing end point of the target routing channel line coordinates and calculating the coordinates of the next routing channel line corresponding to the target routing end point, to obtain the updated target routing end point and the updated coordinates of the next routing channel line;

[0043] When not exceeding the constraint area, place the coordinates of the next routing channel line in a preset cache area, and extract the coordinates of the last - level routing channel line in the cache area;

[0044] Judge whether the coordinates of the last - level routing channel line are effectively connected to the start point and the end point;

[0045] When the coordinates of the last - level routing channel line are effectively connected to the start point and the end point, complete one - time automatic path finding;

[0046] When the coordinates of the last - level routing channel line are not effectively connected to the start point and the end point, increase the value of i by a multiple, obtain the updated i, and return to the above operation step of obtaining the coordinates of the routing channel line for the i - th constraint.

[0047] In addition, the switch matrix test module includes design test conditions, simulation services, running test conditions, and dichotomy judgment conditions:

[0048] The design test conditions are used to judge whether there are design rule problems in the bitstream;

[0049] The simulation service is used to perform full-chip simulation on the bitstream to obtain board-level test results;

[0050] The operating test conditions are used to test whether the board-level test results pass;

[0051] The dichotomy judgment condition is used to test whether the bitstream needs to design debug vectors through dichotomy.

[0052] In addition, the rtg library file includes:

[0053] Extract FPGA software architecture parameters from a pre-built architecture information process file to obtain basic architecture information;

[0054] Use a pre-built genhcelldb.pl tool to extract all SM resource coordinates from the basic architecture information to obtain an SM coordinate file;

[0055] Use a pre-built getrtgs.pl tool to generate a routing file for the SM coordinate file to obtain an SM routing file;

[0056] Merge the SM coordinate file and the SM routing file to obtain a routing library file, and extract rtg information from the routing library file to obtain an rtg library file.

[0057] To achieve the above object, the present invention also provides a switch matrix test method based on the linear vectorization of interconnection resources. The method includes:

[0058] Use a pre-built netlist framework construction service to construct an initial netlist according to a pre-built parameter file set, and use a pre-built automatic wiring service to perform automatic wiring operations on the initial netlist according to the parameter file set to obtain a layout change netlist;

[0059] Convert the layout change netlist into a bitstream;

[0060] Perform switch matrix testing on the bitstream to obtain test results.

[0061] To solve the problems described in the background art, the present invention realizes the test automation process with the help of a netlist wiring script module, a bitstream generation module, and a switch matrix test module. Among them, the netlist wiring script module can use the linear vectorization method to physically arrange the resources to be tested and related resources. The bitstream generation module is used to generate a bitstream from the physical arrangement results; the switch matrix test module is used to perform failure analysis on the FPGA chip using the bitstream, so as to perform mass production testing. Therefore, the present invention can improve the efficiency of interconnection resource testing and the efficiency of failure location. Description of the Drawings

[0062] Figure 1 Schematic diagram of the switch matrix test system based on the linear vectorization of interconnected resources provided by an embodiment of the present invention;

[0063] Figure 2 Thumbnail of the SM structure architecture in the switch matrix test system based on the linear vectorization of interconnected resources provided by an embodiment of the present invention;

[0064] Figure 3 Schematic diagram of netlist construction in the switch matrix test system based on the linear vectorization of interconnected resources provided by an embodiment of the present invention;

[0065] Figure 4 Schematic diagram of the automatic line search logic in the switch matrix test system based on the linear vectorization of interconnected resources provided by an embodiment of the present invention;

[0066] Figure 5 Schematic flow chart of the switch matrix test method based on the linear vectorization of interconnected resources provided by an embodiment of the present invention.

[0067] The realization of the object of the present invention, functional features and advantages will be further described with reference to the embodiments and the accompanying drawings. Detailed implementation manners

[0068] In order to make the object, technical solution and advantages of the present application more obvious, exemplary embodiments according to the present application will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. It should be understood that the present application is not limited by the exemplary embodiments described herein.

[0069] Term explanation:

[0070] Switch Marix: The switch matrix that connects between modules, which is internally composed of various muxes of different sizes, abbreviated as SM.

[0071] Interconnected resources: Interconnected resources refer to the wiring resources between SMs or between an SM and adjacent functional modules, and the SM itself as a switch matrix.

[0072] Linear vectorization: The process of mapping the linear type in the form of direction + number of spans + serial number to the plane rectangular coordinate.

[0073] HCDL language: A language for describing the chip's underlying netlist, which can be roughly classified into elements such as design, module, net, rtg, inst, cfg, inpin, and outpin.

[0074] FPGA_Sculptor: A backend design tool for FPGA that can generate bitstreams by directly modifying the post-placement and routing netlist, skipping the previous synthesis and compilation processes.

[0075] ATE: (Auto Test Equipment), automated test equipment used for the automated testing of electronic components, circuit boards, chips, or larger systems.

[0076] routing gate: A section of routing in the SM controlled by switches for starting and ending connections, abbreviated as rtg.

[0077] srcp: The end point of a section of rtg routing and also the starting point of a section of wire track.

[0078] sikp: The starting point of a section of rtg routing and also the ending point of a section of wire track.

[0079] fullchip_sim: Full-chip functional simulation.

[0080] Junction: The rtg hub point of the interconnect resources.

[0081] One embodiment of this application relates to a switch matrix test system based on the linear vectorization of interconnect resources, as Figure 1 shown, mainly including a netlist wire tracing script module, a bitstream generation module, and a switch matrix test module;

[0082] The netlist wire tracing script module includes a parameter file set, a netlist framework construction service, and an automatic wire tracing service;

[0083] The netlist wire tracing script module is used to construct an initial netlist according to the parameter file set by using the netlist framework construction service, and perform an automatic wire tracing operation on the initial netlist according to the parameter file set by using the automatic wire tracing service to obtain a layout change netlist;

[0084] The bitstream generation module is used to transform the layout change netlist into a bitstream;

[0085] The switch matrix test module is used to perform switch matrix testing on the bitstream to obtain a test result.

[0086] Among them, the netlist framework construction service is a script service for constructing a netlist. The automatic wire tracing service is a script service for traversing the paths in the netlist.

[0087] Among them, the bitstream generation module is constructed by the FPGA_Sculptor tool. The switch matrix test module is constructed by the automated test equipment.

[0088] Specifically, referring to Figure 1 As shown, in the embodiment of the present invention, the parameter file set includes device architecture parameters, SM architecture parameters, node parameters, fanout drive file parameters, rtg library files, vector rule parameters, design guidelines and test constraint parameters, and a test vector list;

[0089] Among them, the node parameters include fixed connection node parameters, split node parameters, starting node parameters of the net to be tested, and starting node parameters of the auxiliary test net;

[0090] Among them, SM in the SM architecture parameters represents the switch matrix.

[0091] Among them, the device architecture parameters refer to a set of parameters describing the overall hardware architecture of the FPGA device. The SM architecture parameters refer to the configuration parameters describing the internal switch matrix (SM) of the FPGA.

[0092] Among them, the fixed connection node parameters in the node parameters are used to fixedly connect non-programmable nodes. The split node parameters are used for nodes that can be divided into multiple sub-paths. The starting node parameters of the net to be tested are used to describe the starting point of the test target net. The starting node parameters of the auxiliary test net are used to describe the starting point of the auxiliary test path.

[0093] Among them, the rtg library file refers to a database containing the topological structure of all routing resources of the FPGA, the routing rules of the switch matrix (SM), and resource coordinates.

[0094] Among them, the fanout drive file parameters are used to describe the signal parameters for driving multiple parallel nodes.

[0095] Among them, the vector rule parameters refer to a set of rules required for test vector generation.

[0096] Among them, the design guideline parameters refer to a set of rules for guiding the placement and routing tool to optimize the design.

[0097] Among them, the test constraint parameters refer to the boundary conditions that limit the test process.

[0098] Among them, the test vector list refers to a set of input signal sequences used to simulate the functions or fault scenarios of the FPGA design.

[0099] Specifically, in the embodiment of the present invention, the device architecture parameters include: device name, unencapsulated IOs, the internal resource coordinate boundaries of the FPGA chip including IOs, CLEs, SMs, and the ROW_NUM (sequence number of "row") and COL_NUM (sequence number of "column").

[0100] Specifically, in the embodiment of the present invention, referring to Figure 2As shown, the SM architecture parameters include: the ROW information and its mapping relationship with the Y coordinate, the COL information and its mapping relationship with the X coordinate, the boundary information of the X and Y coordinates, the set of boundary SM resource coordinates {XxYx…XmYn}, the set of coordinates excluded by digital modules such as xxx and yyy, and the boundary coordinate information of the occupied positions of digital modules.

[0101] Specifically, in the embodiments of the present invention, the fixed connection node parameters in the node parameters include the fixed connection module INST and the fixed connection netlist NET. Here, the meaning of "fixed connection" is that, for example, IO modules (IO BUFFER), IOL modules (IO LOGIC), and CLE modules (programmable logic modules) are used as auxiliary test modules in the design under test. The parameters inside them can be defined in the unified way of inputting parameters to the module INST and the fixed connection netlist NET, without the need to be modified multiple times according to the changes of cases. However, their position coordinates and BLOCK names change with the cases.

[0102] Specifically, in the embodiments of the present invention, the split node parameters are the split forms of input signals. For example, an input signal is split into 4 signals.

[0103] Specifically, in the embodiments of the present invention, the rtg library file contains the information of all rtgs within all SM coordinate resources. In the actual circuit, not all of them are used, and an external floating (hanging, not connected) method is adopted. Therefore, in the test of the present invention, there is no need to pay attention to these floating pins.

[0104] Specifically, in the embodiments of the present invention, the sector drive file parameters need to be separated from the rtg database file. The sector drive file parameters focus on the vector nature of sikp within all SM resources, that is, the one-in-many-out sector drive structure.

[0105] Specifically, in the embodiments of the present invention, the vector rule file needs to be independently constructed, mainly focusing on the determined output end srcp. For example, for the fixed routing from port 1 input to port 2 output, the present invention uses the vectorization rule to complete it with the help of a scripting language, so that it can be directly called as a function.

[0106] Specifically, in the embodiments of the present invention, the design test vectors in the design guidance and test constraint parameters need to guide the constrainable sikp to point to randomness and the specified high-priority line type.

[0107] 1) Assume that the current routing does not require manual guidance. Then, the rtg for the entire routing from A to B needs to be implemented using automatic route finding logic. When routing, there will be multiple rtgs available when reaching each junction, and an optimal path needs to be selected through constraint and iterative route finding to reach the end point.

[0108] 2) Assume that the current wiring requires manual guidance. The test wire type is RRk. When routing at the SM_L_XxYy coordinate position, it is written to RRiSRCj. After vector rule calculation, the next-level sikp is RRqSIKp at SM_L_XmYn. At this position, Sikp will export its own fan-shaped drive structure file. Through the randomization function and path convergence principle in the script, by sorting all rtgs, the program will rank this wire type with the highest priority according to the manually input wire type RRk.

[0109] 3) Several basic principles followed by automatic wire tracing. These wiring principles are only used for testing. Automatic wire tracing has something in common with the Router (wiring tool) in EDA (Electronic Design Automation), but is not equivalent to the Router in EDA:

[0110] Wiring Principle 1: Path convergence and approximation principle. The wiring always points to or approaches the end point, and a small number of incremental line segments in the middle can be ignored.

[0111] Wiring Principle 2: Long plus short, long in the middle and short at both ends principle. Use long jumpers when the planar space is large, otherwise use short jumpers.

[0112] Wiring Principle 3: Non-repetitive wiring principle. For the SM at the same coordinate, do not drive the same srcp repeatedly in the same period or different periods.

[0113] Wiring Method 4: Pre-wiring mechanism. The wiring calls two functions, one is the leading wire router, and the other is the feedback adjustment router. Correct wiring is carried out through the leading plus feedback mechanism.

[0114] Specifically, in the embodiment of the present invention, the test constraint parameters in the design guidance and test constraint parameters include source data lane splitting and the SM constraints where each split route is located, the SM constraint where the to-be-tested lane is located, and the SM constraint where the auxiliary test lane is located. The content of the test constraint parameters needs to be written into the script.

[0115] 1) Static constraint: It means that the constraint area is the fixed resource coordinate, which can be considered as the SM constraint where the to-be-tested lane is located. Once the test wire type is selected, the constraint of this part of the content can be carried out:

[0116] 2) Dynamic constraint: It means a constraint method in which the constraint area gradually reduces the wire tracing range as the wire tracing route changes. It can be considered that it is basically applicable to the SM constraints where the split routes are located and the SM constraints where the auxiliary test lanes are located.

[0117] 3) The content of the constraint includes not only the coordinate range but also the constraint of the route, that is, optimizing the rtg range.

[0118] Specifically, refer to Figure 3As shown in the figure, in the embodiment of the present invention, the service for constructing the netlist framework constructs an initial netlist according to the parameter file set, including:

[0119] The service for constructing the netlist framework calls the device architecture parameters, SM architecture parameters, node parameters, and test vector list in the parameter file set;

[0120] An initial netlist is constructed according to the device architecture parameters, SM architecture parameters, node parameters, and test vector list.

[0121] Specifically, in the embodiment of the present invention, the construction of the initial netlist according to the device architecture parameters, SM architecture parameters, node parameters, and test vector list includes:

[0122] The device architecture parameters and SM architecture parameters are used to configure a preset header file to obtain an initial netlist framework, where the initial netlist framework includes a signal splitting area, a routing area to be tested, and a signal merging area;

[0123] The fixed connection node parameters are used to construct the input pins of the signal splitting area and the output pins of the signal merging area;

[0124] The splitting node parameters are used to split the input signal entering from the input pins into 4 paths of signals, and the 4 paths of signals are used to cover the lanes of the output pins;

[0125] The starting node parameters of the wire net to be tested are used to connect the through wires between the various interconnection resources in the routing area to be tested to obtain an interconnection resource network;

[0126] The starting node parameters of the auxiliary test wire net are used to perform a through wire supplement operation on the interconnection resource network based on boundary bypass connection to obtain an enhanced interconnection resource network;

[0127] The test vector list is used to input into the enhanced interconnection resource network to obtain an initial netlist signal;

[0128] The initial netlist signal is output in a logical configuration form to obtain an initial netlist.

[0129] Among them, the header file includes the necessary information for netlist construction: design “case.hcdl” deviceversion.

[0130] Among them, the input pins and output pins are the transmission endpoints of the signal.

[0131] Among them, the interconnection resource network refers to a network formed by connecting various interconnection resources.

[0132] Among them, the through-line supplement operation refers to adding, on the basis of the interconnected resource network, the connection methods caused by the boundaries. The enhanced interconnected resource network is a boundary-connected interconnected resource network.

[0133] Specifically, in the embodiments of the present invention, referring to Figure 3 Taking the generation of test vectors for a test sieve as an example:

[0134] First, the first part includes a design header file.

[0135] The second part is the input, output pin and wire network information, which is called the fixed INST / NET. As shown in Figure 3 ① and ⑥ in it, data_src is used as the input pin of the data, row0_result, etc. are used as the output pins, and the output signal can perform logic to finally output a flag signal.

[0136] The third part is the input signal source splitting information. As shown in Figure 3 ② in it, the input signal is split into four signals, and each signal enters a row of the chip to cover the wire track.

[0137] The fourth part is the starting node parameters of the wire network to be tested. As shown in Figure 3 ③ in it, each dut is an interconnected resource to be tested, and all the interconnected resources of a certain wire type in the current row are penetrated through a data line.

[0138] The fifth part is the starting node parameters of the auxiliary test wire network. As shown in Figure 3 ④ in it, after the light-colored signal line reaches the boundary, it needs to loop back and enter the interconnected resources of the next row or the next column, mainly various boundary reflection lines and the boundaries of digital modules in the chip. In addition, it should be noted that the initial parameters in the fixed part need to be replaced with the test vector design parameters, and the initial parameters such as the BLOCK coordinates of the IO, the level standard, the slew rate, etc. Then it is presented through the configuration method of logic. As shown in Figure 3 ⑤ in it, the initial netlist is obtained.

[0139] In addition, the generation of test vectors for tracing failure points is basically similar to the above content. As shown in Figure 3 ⑥ in it, the entire long chain rtg is divided into segmented signal outputs by inserting multiple IO nodes, and the results of the output IO are detected, which will not be elaborated here.

[0140] Through the above process, the present invention completes the construction of the initial netlist, and then can start the automatic routing of the netlist.

[0141] Specifically, in the embodiments of the present invention, using the automatic routing service, according to the parameter file set, performing an automatic routing operation on the initial netlist to obtain a layout change netlist, including:

[0142] Using the automatic route finding service, call the device architecture parameters, SM architecture parameters, fan drive file parameters, rtg library file, vector rule parameters, and design guidance and test constraint parameters in the parameter file set;

[0143] Using the pre-built automatic routing logic, perform automatic route finding operations on the initial netlist according to the device architecture parameters, SM architecture parameters, fan drive file parameters, rtg library file, vector rule parameters, and design guidance and test constraint parameters to obtain a layout change netlist.

[0144] Specifically, in the embodiment of the present invention, in the process of obtaining the layout change netlist, it includes:

[0145] The automatic routing logic is used to iteratively find each routing channel line in the initial netlist according to the device architecture parameters, SM architecture parameters, vector rule parameters, design guidance and test constraint parameters to obtain a layout change netlist;

[0146] The device architecture parameters and SM architecture parameters are used as the physical constraints and resource navigation basis for generating each routing channel line;

[0147] The rtg library file is used to provide all rtg information within the coordinate resources of all SMs in the initial netlist, where the rtg information includes signal input points and signal output points, and is a signal transmission unit controlled by switches inside the SM;

[0148] The fan drive file parameters are used to convert the logic signal input from the signal input point into a signal in hash form and output it from the signal output point when passing through the SM to obtain a hash text signal;

[0149] The vector rule parameters are used to map the line type of each routing channel line in the initial netlist from the form of preset direction + number of crossings + serial number to the form of a preset plane rectangular coordinate system operation function;

[0150] The design guidance file in the design guidance and test constraint parameters is used to specify the priority and path constraints of each preset test line type in the initial netlist;

[0151] The test constraint parameters in the design guidance and test constraint parameters are used to statically constrain the coordinate resources of the SM to be tested and dynamically constrain the rtg range of the initial netlist.

[0152] Among them, the routing channel line refers to the path of signal transmission.

[0153] Specifically, in the embodiments of the present invention, the roles played by the same parameter in different steps are different. In the process of obtaining the layout change netlist, the present invention uses the device architecture parameters and SM architecture parameters as the physical constraints and resource navigation basis for generating each routing channel line. The rtg library file is used as the data providing all rtg information within the coordinate resources of all SMs in the initial netlist. The fanout driver file parameters are used as a conversion tool for converting logical signals into hash-form signals. The vector rule parameters are used as a tool for converting the data type [direction + number of crossings + sequence number] into the form of a plane rectangular coordinate system operation function. The design guidance and test constraint parameters are used to interfere with and constrain based on human experience.

[0154] Specifically, in the embodiments of the present invention, the automatic routing logic includes:

[0155] According to the device architecture parameters, SM architecture parameters, fanout driver file parameters, and rtg library file, extract the start point - end point routing vector information of the current routing channel line in the initial netlist;

[0156] Obtain the initialization parameter i, obtain the coordinates of the routing channel line for the i-th constraint, obtain the target routing channel line coordinates, and obtain the distance information of the target routing coordinates from the start point - end point routing vector information;

[0157] According to the routing start point for the i-th time, randomly generate all routing end points for the i-th time;

[0158] According to the vector rule parameters, calculate the distance information between the routing start point and each routing end point, preferably obtain the target routing end point of the target routing channel line coordinates, and calculate the coordinates of the next routing channel line corresponding to the target routing end point;

[0159] Judge whether the coordinates of the next routing channel line conform to the constraint area in the design guidance and test constraint parameters;

[0160] When exceeding the constraint area, return to the step of preferably obtaining the target routing end point of the target routing channel line coordinates and calculating the coordinates of the next routing channel line corresponding to the target routing end point, to obtain the updated target routing end point and the updated coordinates of the next routing channel line;

[0161] When not exceeding the constraint area, place the coordinates of the next routing channel line in a preset cache area, and extract the coordinates of the last-level routing channel line in the cache area;

[0162] Judge whether the coordinates of the last-level routing channel line are effectively connected to the start point and the end point;

[0163] When the coordinates of the last-level routing channel line are effectively connected to the starting point and the ending point, an automatic routing is completed;

[0164] When the coordinates of the last-level routing channel line do not effectively connect the starting point and the ending point, the value of i is increased by a multiple to obtain an updated i, and it returns to the above operation step of obtaining the coordinates of the routing channel line for the i-th time.

[0165] Among them, the starting point - ending point routing vector information includes the position coordinates of two SMs and the connection path between the two SMs.

[0166] Among them, the initialization parameter i is a preset dynamically changing parameter.

[0167] Among them, the distance information is the distance between the scrp of the current rtg and the sikp of the end rtg in the target routing coordinates.

[0168] Specifically, in the embodiments of the present invention, it is necessary to mobilize device architecture parameters, SM architecture parameters, sector drive file parameters, and rtg library files to achieve automatic routing. Among them, the automatic routing logic adopts an iterative method to find the route, with the help of a line vectorization calculation function and randomization of the sikp pointer, and automatic routing is carried out under the cooperation of constraint rules and routing rules.

[0169] In detail, in the embodiments of the present invention, the switch matrix test module includes designing test conditions, simulation services, running test conditions, and bisection judgment conditions:

[0170] The designed test conditions are used to determine whether there are design rule problems in the bitstream;

[0171] The simulation service is used to perform full-chip simulation on the bitstream to obtain board-level test results;

[0172] The running test conditions are used to test whether the board-level test results pass;

[0173] The bisection judgment condition is used to test whether the bitstream needs to design a debug vector through bisection.

[0174] Among them, the bisection judgment is used to generate test vectors required for debugging.

[0175] Specifically, in the embodiments of the present invention, using this bitstream and the corresponding excitation signal and golden signal to perform failure analysis on the FPGA chip can achieve mass production testing.

[0176] Specifically, the present invention uses linear vectorization, designs guiding rules, automatic line-following logic, and test area constraints to automate the generation of vectors. At the beginning of the design, the device type, test line type, test input ports, test output ports, and debug ports are determined. The automation script generates a netlist file based on the input parameters, and then further generates a bitstream and an ATE vector file. If there are defective chips, the designer can customize the bisection series in the script to generate multiple vector files of the same line type to approximate and locate the defective position. The specific bitstream test process is a common test process, which will not be elaborated here in the present invention.

[0177] Specifically, in the embodiments of the present invention, the rtg library file includes:

[0178] Extract FPGA software architecture parameters from the pre-built architecture information process file to obtain basic architecture information;

[0179] Use the pre-built genhcelldb.pl tool to extract all SM resource coordinates from the basic architecture information to obtain an SM coordinate file;

[0180] Use the pre-built getrtgs.pl tool to generate a routing file for the SM coordinate file to obtain an SM routing file;

[0181] Merge the SM coordinate file and the SM routing file to obtain a routing library file, and extract rtg information from the routing library file to obtain an rtg library file.

[0182] Among them, the architecture information process file is an original data file provided by the FPGA manufacturer or design tool, and contains the underlying parameters of the device hardware architecture. The basic architecture information is a set of FPGA software-level architecture parameters extracted from the architecture information process file.

[0183] Among them, the genhcelldb.pl is a pre-built automation script for extracting SM resource coordinates from the basic architecture information. The SM coordinate file is a file recording the physical positions of all switch matrices (SMs) in the FPGA device.

[0184] Among them, the getrtgs.pl is a pre-built automation script for generating a routing rule file based on the SM coordinate file. The SM routing file is a file describing the signal path rules inside and across the switch matrix (SM).

[0185] Among them, the routing library file is a unified database file after merging the SM coordinate file and the SM routing file. The rtg library file is the final routing resource graph (rtg) database extracted from the routing library file.

[0186] Specifically, in the embodiment of the present invention, the rtg library file contains databases of multiple coordinates, and the databases of multiple coordinates are merged into the same library file. The architecture information process file is an fpga software architecture parameter file, which includes IO information, interconnection information, configuration information of various cells (the smallest unit of the fpga software level), etc. The SM coordinates are all the SM resource coordinates of the device extracted from the architecture information, and then the routing file of the SM is generated. Finally, all rtg information is extracted from the routing library.

[0187] In summary, the present solution has strong operability, strong portability, and is relatively flexible in application. It can achieve customized test coverage of the interconnection resources of the FPGA chip, and improve the efficiency of interconnection resource testing and the efficiency of failure location.

[0188] To solve the problems described in the background art, the present invention realizes the test automation process with the help of a netlist routing script module, a bitstream generation module, and a switch matrix test module. Among them, the netlist routing script module can use the vectorization method of line type to physically arrange the resources to be tested and related resources. The bitstream generation module is used to generate a bitstream from the physical arrangement result. The switch matrix test module is used to perform failure analysis on the FPGA chip using the bitstream, so as to perform mass production testing. Therefore, the present invention can improve the efficiency of interconnection resource testing and the efficiency of failure location.

[0189] Further, referring to Figure 5 as shown, the embodiment of the present invention also provides a control method executed by a switch matrix test system based on the vectorization of the interconnection resource line type shown in Figure 1 as shown, including:

[0190] Construct a service using a pre-built netlist framework, construct an initial netlist according to a pre-built set of parameter files, and use a pre-built automatic routing service to perform an automatic routing operation on the initial netlist according to the set of parameter files to obtain a layout change netlist;

[0191] Convert the layout change netlist into a bitstream;

[0192] Perform a switch matrix test on the bitstream to obtain a test result.

[0193] Among them, the netlist framework construction service is a service for constructing a netlist. The automatic routing service is a service for traversing the paths in the netlist.

[0194] In the embodiments of the present invention, the parameter file set includes device architecture parameters, SM architecture parameters, node parameters, fanout driver file parameters, an rtg library file, vector rule parameters, design guidance and test constraint parameters, and a test vector list;

[0195] Among them, the node parameters include fixed connection node parameters, split node parameters, starting node parameters of the net to be tested, and starting node parameters of the auxiliary test net;

[0196] Among them, SM in the SM architecture parameters represents a switch matrix.

[0197] Among them, the device architecture parameters refer to a set of parameters describing the overall hardware architecture of the FPGA device. The SM architecture parameters refer to the configuration parameters describing the internal switch matrix (SM) of the FPGA.

[0198] Among them, the fixed connection node parameters in the node parameters are used to fixedly connect non-programmable nodes. The split node parameters are used for nodes that can be divided into multiple sub-paths. The starting node parameters of the net to be tested are used to describe the starting point of the test target net. The starting node parameters of the auxiliary test net are used to describe the starting point of the auxiliary test path.

[0199] Among them, the rtg library file refers to a database containing the topological structure of all routing resources of the FPGA, the routing rules of the switch matrix (SM), and resource coordinates.

[0200] Among them, the fanout driver file parameters are used to describe the signal parameters for driving multiple parallel nodes.

[0201] Among them, the vector rule parameters refer to a set of rules required for test vector generation.

[0202] Among them, the design guidance parameters refer to a set of rules for guiding the placement and routing tool to optimize the design.

[0203] Among them, the test constraint parameters refer to the boundary conditions that limit the test process.

[0204] Among them, the test vector list refers to a set of input signal sequences used to simulate the functions or fault scenarios of the FPGA design.

[0205] Specifically, the present invention constructs a netlist framework construction service, the automatic wire tracing service, bitstream generation, and switch matrix test service with the help of the HCDL language, FPGA_Sculptor, and scripts, uses a linear vectorization method to perform place & route on the resources to be tested and related resources and generate a bitstream. The FPGA chip is subjected to failure analysis and mass production testing using this bitstream and the corresponding excitation signal and golden signal.

[0206] For those skilled in the art, it is obvious that the present invention is not limited to the details of the above-mentioned exemplary embodiments, and the present invention can be implemented in other specific forms without departing from the spirit or basic characteristics of the present invention.

[0207] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. A switch matrix test system based on the linear vectorization of interconnected resources, characterized in that The system includes a netlist routing script module, a bitstream generation module, and a switch matrix test module; The netlist routing script module includes a parameter file set, a netlist framework construction service, and an automatic routing service. Among them, the parameter file set includes device architecture parameters, SM architecture parameters, node parameters, fanout driver file parameters, an rtg library file, vector rule parameters, design guidance and test constraint parameters, and a test vector list; Among them, the node parameters include fixed connection node parameters, split node parameters, starting node parameters of the netlist to be tested, and starting node parameters of the auxiliary test netlist; Among them, SM in the SM architecture parameters represents a switch matrix; The netlist routing script module is used to construct an initial netlist according to the parameter file set by using the netlist framework construction service, and call the device architecture parameters, SM architecture parameters, fanout driver file parameters, rtg library file, vector rule parameters, and design guidance and test constraint parameters in the parameter file set by using the automatic routing service; Perform an automatic routing operation on the initial netlist according to the device architecture parameters, SM architecture parameters, fanout driver file parameters, rtg library file, vector rule parameters, and design guidance and test constraint parameters by using pre-built automatic routing logic to obtain a layout change netlist; Among them, the automatic routing logic is used to iteratively search for each routing channel line in the initial netlist according to the device architecture parameters, SM architecture parameters, vector rule parameters, and design guidance and test constraint parameters to obtain a layout change netlist; The device architecture parameters and SM architecture parameters are used as the physical constraints and resource navigation basis for generating each routing channel line; The rtg library file is used to provide all rtg information within the coordinate resources of all SMs in the initial netlist. Among them, the rtg information includes signal input points and signal output points, which are signal transmission units controlled by switches inside the SM; The fanout driver file parameters are used to convert the logic signal input from the signal input point into a signal in hash form and output it from the signal output point when passing through the SM to obtain a hash text signal; The vector rule parameters are used to map the line type of each routing channel line in the initial netlist from the form of preset direction + number of crossings + serial number to the form of a preset plane rectangular coordinate system operation function; The design guidance file in the design guidance and test constraint parameters is used to specify the priority and path constraints of each preset test line type in the initial netlist; The test constraint parameters in the design guidance and test constraint parameters are used to statically constrain the coordinate resources of the SM to be tested and dynamically constrain the rtg range of the initial netlist; The bitstream generation module is used to convert the layout change netlist into a bitstream; The switch matrix test module is used to perform a switch matrix test on the bitstream to obtain a test result.

2. The switch matrix test system based on the line vectorization of interconnected resources as described in claim 1, characterized in that, The step of constructing an initial netlist according to the parameter file set by using the netlist framework construction service includes: Using the netlist framework construction service, call the device architecture parameters, SM architecture parameters, node parameters, and test vector list in the parameter file set; Construct an initial netlist according to the device architecture parameters, SM architecture parameters, node parameters, and test vector list.

3. The switch matrix test system based on the linear vectorization of interconnected resources according to claim 2, characterized in that, The constructing of the initial netlist according to the device architecture parameters, SM architecture parameters, node parameters, and test vector list includes: The device architecture parameters and SM architecture parameters are used to configure a preset header file to obtain an initial netlist framework, where the initial netlist framework includes a signal splitting area, a routing area to be tested, and a signal merging area; The fixed connection node parameters are used to construct the input pins of the signal splitting area and the output pins of the signal merging area; The splitting node parameters are used to split the input signal entering from the input pins into 4 signals, and the 4 signals are used to cover the lanes of the output pins; The starting node parameters of the netlist to be tested are used to connect the through-lines between the various interconnection resources in the routing area to be tested to obtain an interconnection resource network; The starting node parameters of the auxiliary test netlist are used to perform a through-line supplement operation on the interconnection resource network based on boundary detour connection to obtain an enhanced interconnection resource network; The test vector list is used to input the enhanced interconnection resource network to obtain an initial netlist signal; Output the initial netlist signal in a logical configuration form to obtain an initial netlist.

4. The switch matrix test system based on the line vectorization of interconnected resources as described in claim 3, characterized in that, The automatic routing logic includes: According to the device architecture parameters, SM architecture parameters, fanout driver file parameters, and rtg library file, extract the start point - end point routing vector information of the current routing channel line in the initial netlist; Obtain the initialization parameter i, obtain the coordinates of the routing channel line for the i-th constraint to obtain the target routing channel line coordinates, and obtain the distance information of the target routing coordinates from the start point - end point routing vector information; Randomly generate all the routing end points for the i-th time according to the i-th routing start point; According to the vector rule parameters, calculate the distance information between the routing start point and each routing end point, preferably obtain the target routing end point of the target routing channel line coordinates, and calculate the coordinates of the next routing channel line corresponding to the target routing end point; Judge whether the next routing channel line coordinates conform to the constraint area in the design guidance and test constraint parameters; When exceeding the constraint area, return to the step of preferably obtaining the target routing end point of the target routing channel line coordinates and calculating the coordinates of the next routing channel line corresponding to the target routing end point to obtain the updated target routing end point and the updated coordinates of the next routing channel line; When not exceeding the constraint area, place the next routing channel line coordinates in a preset cache area, and extract the coordinates of the last-level routing channel line in the cache area; Judge whether the coordinates of the last-level routing channel line effectively connect the start point and the end point; When the coordinates of the last-level routing channel line effectively connect the start point and the end point, complete one automatic routing; When the coordinates of the last - level routing channel line do not effectively connect the starting point and the ending point, multiply the value of i by a multiple to obtain an updated i, and return to the operation step of obtaining the coordinates of the routing channel line for the i - th time of constraint.

5. The switch matrix test system based on the linear vectorization of interconnected resources as described in claim 4, characterized in that, The switch matrix test module includes designing test conditions, simulation services, running test conditions, and dichotomy judgment conditions: The designed test conditions are used to determine whether there are design rule problems in the bitstream. The simulation service is used to perform full - chip simulation on the bitstream to obtain board - level test results. The running test conditions are used to test whether the board - level test results pass. The dichotomy judgment conditions are used to test whether the bitstream needs to design debug vectors through dichotomy.

6. The switch matrix test system based on the linear vectorization of interconnected resources as claimed in claim 5, wherein The rtg library file includes: Extract FPGA software architecture parameters from a pre - constructed architecture information process file to obtain basic architecture information. Use a pre - constructed genhcelldb.pl tool to extract all SM resource coordinates from the basic architecture information to obtain an SM coordinate file. Use a pre - constructed getrtgs.pl tool to generate a routing file for the SM coordinate file to obtain an SM routing file. Merge the SM coordinate file and the SM routing file to obtain a routing library file, and extract rtg information from the routing library file to obtain an rtg library file.

7. A switching matrix testing method based on the linear vectorization of interconnected resources, which is used to control the switching matrix testing system based on the linear vectorization of interconnected resources described in claim 1, characterized in that, The method includes: Use a pre - constructed netlist framework construction service to construct an initial netlist according to a pre - constructed set of parameter files, and use a pre - constructed automatic wire - tracing service to perform automatic wire - tracing operations on the initial netlist according to the set of parameter files to obtain a layout - changed netlist. Convert the layout - changed netlist into a bitstream. Perform switch matrix testing on the bitstream to obtain test results.

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